Diode with intrinsic epitaxial layer

Abstract

The invention relates to a diode with an intrinsic epitaxial layer. An electronic device (100) includes: an n-type substrate (113) having a first n-type dopant concentration; an intrinsic epitaxial layer (114) on the n-type substrate (113) and having a second n-type dopant concentration that is less than the first n-type dopant concentration; an n-type epitaxial layer (115) on the intrinsic epitaxial layer (114) and having a third n-type dopant concentration greater than the second n-type dopant concentration; and a p-type epitaxial layer (116) on the n-type epitaxial layer (115). A method includes growing an intrinsic epitaxial layer (114) having a second n-type dopant concentration on an n-type substrate (113) having a higher first n-type dopant concentration; growing an n-type epitaxial layer (115) having a third n-type dopant concentration on the intrinsic epitaxial layer (114), the third n-type dopant concentration being greater than the second n-type dopant concentration; and growing a p-type epitaxial layer (116) on the n-type epitaxial layer (115).

Description

Technical Field

[0001] This application generally relates to semiconductors and, more particularly, to diodes having an intrinsic epitaxial layer. Background Art

[0002] An electrostatic discharge (ESD) protection circuit allows a protected circuit, which is capable of providing protection by conducting a high current in response to an ESD event, to operate normally. A vertical diode can be used in an integrated bipolar structure of an epitaxial layer for low-capacitance reverse biasing during normal circuit operation and for preventing snapback during an ESD event. However, the outward diffusion of substrate dopants into the epitaxial layer increases the dopant concentration of the epitaxial layer, which changes the breakdown voltage rating of the ESD protection circuit. The rotation or spin of the wafer during the formation of the epitaxial layer may cause the increase in the epitaxial layer concentration due to the outward diffusion of substrate dopants to be more pronounced at the wafer edge than at the center. The diode p-n junction breakdown voltage rating of the ESD protection circuit is affected by the junction depletion layer width and the dopant concentration of the epitaxial layer. The spatial variation of the dopant concentration within the wafer may reduce the production yield, where the breakdown voltage performance of the die area near the wafer edge is worse than that of the die area near the wafer center. Summary of the Invention

[0003] In one aspect, an electronic device includes: an n-type substrate having a first n-type dopant concentration; an intrinsic epitaxial layer located on the n-type substrate and having a second n-type dopant concentration less than the first n-type dopant concentration; an n-type epitaxial layer located on the intrinsic epitaxial layer and having a third n-type dopant concentration greater than the second n-type dopant concentration; and a p-type epitaxial layer located above the n-type epitaxial layer.

[0004] In another aspect, an electronic device includes a protected circuit coupled to a terminal and an electrostatic discharge (ESD) protection circuit coupled to the terminal, where the protection circuit includes first and second stacks. The first stack includes a first portion of an n-type substrate, a first portion of an intrinsic epitaxial layer on the first portion of the n-type substrate, a first portion of an n-type epitaxial layer on the first portion of the intrinsic epitaxial layer, a first portion of a p-type epitaxial layer on the first portion of the n-type epitaxial layer, an n-type region in a portion of the first portion of the p-type epitaxial layer and spaced apart from the first portion of the n-type epitaxial layer to form a cathode of a first diode, a p-type region in a portion of the n-type epitaxial layer and spaced apart from the n-type substrate, and a junction forming a p-n junction of a Zener diode between the p-type region and a portion of the n-type epitaxial layer. The second stack is spaced apart from the first stack and includes a second portion of the n-type substrate, a second portion of the intrinsic epitaxial layer on the second portion of the n-type substrate, a second portion of the n-type epitaxial layer on the second portion of the intrinsic epitaxial layer, a second portion of the p-type epitaxial layer on the second portion of the n-type epitaxial layer, a p-type region in the second portion of the p-type epitaxial layer and spaced apart from the second portion of the n-type epitaxial layer, and a junction forming a p-n junction of a second diode between the second portion of the p-type epitaxial layer and the second portion of the n-type epitaxial layer.

[0005] In another aspect, a method includes: growing an intrinsic epitaxial layer having a second n-type dopant concentration on an n-type substrate of a wafer, the n-type substrate having a first n-type dopant concentration greater than the second n-type dopant concentration; growing an n-type epitaxial layer having a third n-type dopant concentration on the intrinsic epitaxial layer, the third n-type dopant concentration being greater than the second n-type dopant concentration; and growing a p-type epitaxial layer on the n-type epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a top perspective view of an electronic device having a semiconductor die with an ESD protection circuit.

[0007] Figure 1A is a partial cross-sectional side view of a diode in an epitaxial layer stack on a substrate.

[0008] Figure 1B is Figure 1 a simplified schematic diagram of the electronic device of

[0009] Figure 1C is a partial cross-sectional side view of an example implementation of an ESD protection circuit.

[0010] Figure 2It is a flowchart of a method for manufacturing an electronic device.

[0011] Figure 2A It is Figure 2 a flowchart of an example pre-cleaning process in an embodiment of the method.

[0012] Figures 3 - 15 It is according to Figure 2 and 2A a partial cross-sectional side view of a wafer undergoing a manufacturing process according to the method.

[0013] Figure 16 It is a graph showing the variation of the temperature of an example intrinsic layer deposition over time.

[0014] Figure 17 It is a graph showing the variation of current with voltage in an embodiment of an ESD protection circuit.

[0015] Figure 18 It is a graph showing the variation of bipolar holding voltage with distance.

[0016] Figure 19 It shows a cumulative probability curve graph of the bipolar holding voltage. Detailed Description

[0017] In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. Additionally, the term "couple / couples" encompasses indirect or direct electrical connection or mechanical connection or a combination thereof. For example, if a first device is coupled to or coupled with a second device, the connection can be by direct electrical connection or by indirect electrical connection via one or more intervening devices and connections. The following describes one or more operating characteristics of various circuits, systems, and / or components in the context of their functions, which in some cases are caused by the configuration and / or interconnection of various structures when the circuits are powered and operating. In the following discussion and claims, the terms "including / includes", "having / has", "with" or their variants are intended to be inclusive in a manner similar to the term "comprising" and should thus be interpreted to mean "including but not limited to".

[0018] Unless otherwise specified, "about", "substantially", or "essentially" in front of a value means + / - 10% of the stated value. The following describes one or more operating characteristics of various circuits, systems, and / or components in the context of their functions, which in some cases are caused by the configuration and / or interconnection of various structures when the circuit is powered and operating. For ease of description in conjunction with specific figures, one or more structures, features, aspects, components, etc. may be referred to herein as first, second, third, etc., such as first and second terminals, first, second, and third wells, etc., where these should not be construed as limitations on the claims. The various disclosed structures and methods of the present disclosure can be beneficially applied to the manufacture of electronic devices such as integrated circuits. Although it may be desirable for such examples to provide various improvements, the present disclosure does not require specific results unless explicitly recited in the specific claims.

[0019] First referring to Figures 1 - 1C , Figure 1 FIG. shows an electronic device 100, such as an integrated circuit having a semiconductor die 110 that includes an ESD protection circuit 111, Figure 1A FIG. shows a diode D in an epitaxial layer stack on a substrate of the semiconductor die 110, Figure 1B FIG. shows a schematic diagram of one embodiment of the electronic device 100, and Figure 1C FIG. shows an example embodiment of the ESD protection circuit 111. In one example, the electronic device 100 includes a protected circuit or component 112 ( Figure 1 and 1B ), such as formed in the same semiconductor die 110 that has the ESD protection circuit 111.

[0020] In another embodiment, the protection circuit 111 may be encapsulated in the corresponding packaged electronic device 100, for example, to protect a separate electronic device (e.g., another integrated circuit) from ESD events in a system such as a printed circuit board (not shown). In another example, the protection circuit 111 is included in the semiconductor die 110, and the protected circuit 112 is formed in a second semiconductor die (not shown), and the first and second semiconductor dies are packaged together in a common electronic device, which can be mounted on a host circuit board (not shown).

[0021] Figure 1 , 1A and 1C show the example flat-packaged electronic device 100 and the semiconductor die 110 in an example three-dimensional space, the example three-dimensional space having a first direction X, a second direction Y that is perpendicular (orthogonal) to the first direction X, and a third direction Z that is perpendicular (orthogonal) to the first direction X and the second direction Y ( Figure 1 ). Structures or features along any two of these directions are orthogonal to each other. As Figure 1As shown, the electronic device 100 has opposite first and second sides 101 and 102 (e.g., bottom side and top side), which are spaced apart from each other along a third direction Z at the shown positions. The electronic device 100 also has: opposite third and fourth sides 103 and 104 (e.g., lateral sides), which are spaced apart from each other along a first direction X; and opposite fifth and sixth sides 105 and 106, which are spaced apart from each other along a second direction Y at the shown positions.

[0022] In the shown example, the electronic device 100 has conductive leads or terminals 107 along four lateral sides 103 - 106, which are exposed along the bottom first side 101 and along the corresponding ones of the lateral sides 103 - 106 of the molded or ceramic package structure 108. In different embodiments, the ESD protection circuit 111 can be encapsulated in different types or forms of packages using suitable conductive leads, which allow the packaged electronic device to be soldered to a host circuit board or mounted in a socket (not shown) of a host system.

[0023] The shown example provides a p - n junction within the electronic device, e.g., using one or more diodes that form a p - n junction of epitaxial silicon or other semiconductor material formed (e.g., grown) above a semiconductor substrate. In one example, the junction and diodes can be integrated into an ESD protection circuit system within a common semiconductor die having a protected circuit and / or into a dedicated ESD protection device that can be mounted on a circuit board very close to a protected device such as an integrated circuit.

[0024] Figure 1A Shown is an example diode D having a p - n junction formed in a stack including one or more epitaxial silicon layers above a silicon substrate. In other examples, the various layers can use different types of semiconductor materials, such as gallium arsenide, etc. The shown portion of the semiconductor die 110 has a doped silicon substrate 113 (labeled "N+ substrate") doped with an n - type dopant, e.g., phosphorus, arsenic, etc., and the n - type substrate 113 has a first n - type dopant concentration. In some examples, the first n - type dopant concentration of the substrate 113 can be greater than 1×10 18 cm -3 ; and in some examples, the first concentration can exceed 5×10 19 cm -3 . In these or other examples, the n - type substrate 113 can have a resistance range of approximately 0.0011 to 0.0013 ohm - centimeters. An intrinsic epitaxial silicon layer 114 having a second n - type dopant concentration extends on the top side of the substrate 113, and at Figure 1Ais labeled as "intrinsic EPI". The second n-type dopant concentration of the intrinsic epitaxial silicon layer 114 is less than the first n-type dopant concentration of the n-type substrate 113. In some examples, the second n-type dopant concentration of the intrinsic epitaxial silicon layer 114 can be less than 1×10 14 cm -3 ; and in some examples, it can be less than 1×10 13 cm -3 .

[0025] Figure 1A The stack in also includes an n-type epitaxial layer 115 located on the intrinsic epitaxial layer 114, which can also be referred to as the device epitaxial film. The n-type epitaxial layer 115 has a third n-type dopant concentration greater than the second n-type dopant concentration. In some examples, the third n-type dopant concentration of the n-type epitaxial layer 115 can be between 1×10 15 cm -3 and 1×10 17 cm -3 . In these or other examples, the n-type epitaxial layer 115 can have a resistance range of approximately 0.70 to 0.80 ohm-cm. The p-type epitaxial silicon layer 116 extends over the n-type epitaxial layer 115 and contains p-type dopants (e.g., boron, etc.). In another example, a p-type buried layer (e.g., PBL, not shown) extends in the upper portion of the n-type epitaxial layer 115 and into the lower portion of the p-type epitaxial silicon layer 116. The shown stack portion provides the p-n junction of the diode D schematically shown in Figure 1A .

[0026] The shown stack structure advantageously includes the intrinsic epitaxial layer 114 formed by a separate deposition process to mitigate the diffusion of n-type dopants from the substrate 113 into the n-type epitaxial layer 115 during the epitaxial layer formation process. This provides a benefit compared to directly forming (e.g., growing) the n-type epitaxial layer 115 on the top side of the n-type substrate 113. In particular, the former method results in the outward diffusion of n-type dopants from the substrate 113 into the n-type epitaxial layer 115, while the n-type dopant concentration in the n-type epitaxial layer 115 has a spatial variation, which may lead to a reduction in production yield compared to the breakdown voltage variation in the die area between the center and the edge of the wafer due to wafer rotation during the epitaxial layer formation process.

[0027] In one example, the intrinsic epitaxial layer 114 includes a non-zero n-type dopant concentration, e.g., due to some diffusion of n-type dopants from the substrate 113 into the intrinsic epitaxial layer 114 during formation of the intrinsic epitaxial layer 114 by epitaxial growth or deposition and associated processing. In one example, the intrinsic epitaxial layer 114 has a first thickness T1 of 0.1 μm or more. In this or another example, the thickness T1 of the intrinsic epitaxial layer 114 is 1.5 μm or less. In these or other examples, the n-type epitaxial layer 115 has a second thickness T2, and the second thickness T2 is greater than the first thickness T1. Regarding the p-n junction of the diode D, the final n-type epitaxial film thickness includes the thickness T1 of the intrinsic epitaxial film layer 114 and the thickness T2 of the n-type epitaxial layer.

[0028] Figure 1B FIG. shows an example circuit configuration of an ESD protection circuit 111 for protecting a protected circuit or component 112 from adverse effects associated with an ESD event. In this example, the electronic device 100 includes a protected circuit or component 112 and a reference voltage (e.g., GND), and the protected circuit or component is connected between a protected pad 107 (e.g., an IC terminal, pin, pad, etc.) and an associated protected internal node 117. The protected pad 107 has a voltage labeled "PAD" in Figure 1B FIG. The electronic device 100 also includes a power pad 107 (e.g., for receiving a supply voltage VDD) and an internal node 118 that connects the supply voltage from the power pad 107 to the protected circuit or component 112.

[0029] In this example, the protected circuit or component 112 is connected between the protected pad 107 (e.g., the protected node 117) and the reference node 119 (GND). The ESD protection circuit 111 is connected in parallel with the protected circuit or component 112. In this example, the electronic device 100 is an integrated circuit electronic device 100 in which the protected circuit or component 112 is connected to an externally accessible terminal or pad 107, and the ESD protection circuit 111 is electrically connected to the externally accessible terminal or pad 107 of the IC 100.

[0030] For example, when the protected pad is soldered to the host printed circuit board (PCB) or otherwise subjected to hot plug surges, switching noise, or other transient voltage conditions, the ESD protection circuit 111 protects the circuit or component 112 from ESD events associated with the externally accessible conductive pad structure 107. During steady state operation, when a supply voltage is provided to the VDD pad 107, a voltage level at the protected pad 107 that is below the breakdown voltage rating of the ESD protection circuit 111 does not trigger conduction of the ESD protection circuit 111, and the protected circuit or component 112 operates in a normal designed manner. In one example, a vertical stack structure of one or more protection diodes of the ESD protection circuit 111 (e.g., as referenced Figure 1A and 1C described) can help provide a low capacitance to the protected node or pad 107 to facilitate the desired operation of the protected circuit or component 112.

[0031] If an ESD event occurs at the protected pad 107, then the associated protected node voltage VPROT rapidly rises, e.g., with a fast rise time in a high voltage human body model (HBM) ESD test event. The rapid voltage rise causes a voltage breakdown within the ESD protection circuit 111, which conducts the ESD event current through the ESD protection circuit 111 to mitigate or avoid excessive current flow in the protected circuit or component 112.

[0032] Figure 1C An example implementation of the ESD protection circuit 111 is shown for a semiconductor die 110 that includes a first stack S1 and a second stack S2. In this example, stacks S1 and S2 include example portions of a substrate 113 and epitaxial layers 114 - 116, as described above in connection with Figure 1A described. The first stack S1 includes a first portion of an n-type substrate 113, a first portion of an intrinsic epitaxial layer 114 on the first portion of the n-type substrate 113, a first portion of an n-type epitaxial layer 115 on the first portion of the intrinsic epitaxial layer 114, and a first portion of a p-type epitaxial layer 116 on the first portion of the n-type epitaxial layer 115.

[0033] Additionally, the first stack S1 includes n-type regions 124, 126 in an upper portion of a first portion of the p-type epitaxial layer 116. In one example, the n-type regions include a diffused n-type region 124 and an n-type source / drain (NSD) implant region 126 within the diffused n-type region 126. The n-type regions 124, 126 are spaced apart (e.g., above) from a first portion of the n-type epitaxial layer 115 to form a cathode of a first diode D1. In this example, anodes of the first diode D1 and the Zener diode Z1 are connected together and form a diode circuit having a thyristor structure that can be triggered by an ESD event to conduct current when a protected node voltage (e.g., Figure 1B VPROT in) exceeds a first trigger voltage that is higher than a normal operating voltage of the protected circuit or component 112 during an ESD event.

[0034] Figure 1C A second stack S2 in is laterally spaced apart from the first stack S1 (e.g., along a first direction X). In this example, the second stack S2 includes a second portion of the n-type substrate 113, a second portion of the intrinsic epitaxial layer 114 on the second portion of the n-type substrate 113, a second portion of the n-type epitaxial layer 115 on the second portion of the intrinsic epitaxial layer 114, and a second portion of the p-type epitaxial layer 116 on the second portion of the n-type epitaxial layer 115. Additionally, the second stack S2 includes a p-type region 128, e.g., a p-type source / drain implant region (PSD) in the second portion of the p-type epitaxial layer 116. The p-type region 128 is spaced apart (e.g., above) from the second portion of the n-type epitaxial layer 115 along a third direction Z. A junction between the second portion of the p-type epitaxial layer 116 and the second portion of the n-type epitaxial layer 115 forms a p-n junction of a second diode D2 schematically shown in FIG. 1C.

[0035] In Figure 1C example, the semiconductor die 110 of the electronic device 100 also includes a p-doped region 121 along a portion of a top side of the p-type epitaxial layer 116. Additionally, in this example, the electronic device 100 also includes one or more instances of deep trench isolation structures 122, 123 that extend along a third direction Z through the intrinsic epitaxial layer 114, the n-type epitaxial layer 115, and the p-type epitaxial layer 116 and into the n-type substrate 113 and separate the first stack S1 and the second stack S2. In one example, each instance of the deep trench isolation structure includes an oxide or other suitable trench wall liner 122 and doped polysilicon 123 encapsulated by the liner 122. Figure 1C The cross-sectional view shown includes two deep trench structures extending between the first stack S1 and the second stack S2, e.g., they correspond to sidewalls of first and second deep trench ring or box structures that laterally surround the first stack S1 and the second stack S2, respectively.

[0036] In the illustrated example, a p-type region 120 (e.g., PBL) extends laterally within an exemplary first deep trench ring or box structure 122, 123 that circumscribes the first stack S1. Additionally, the region that is laterally between the first deep trench structure 122 and the second deep trench structure 123 (e.g., the region between the first stack S1 and the second stack S2) includes a p-type region, such as is created by implantation of the PBL p-type region 120 prior to formation of the deep trench structures during fabrication, but this is not required for all possible embodiments.

[0037] In this example, the semiconductor die 110 further includes metallization structures 131, 133 that couple the cathode of the first diode D1 to the anode of the second diode D2 to form an electrostatic discharge (ESD) protection circuit 111. In this example, the metallization structures include: a first or pre-metal dielectric (PMD) layer 130 in which tungsten metal contacts 131 are formed to make connections to the n-type regions 124, 126 and the p-type region 128; and a first interlevel or interlayer dielectric (ILD) layer 132 in which conductive metal traces or via features 133 are electrically connected to the illustrated tungsten contacts 131 to electrically couple the cathode of the first diode D1 to the anode of the second diode D2. The cathode of the Zener diode Z1 and the second diode D2 are connected to a backside metal structure 140 through the substrate 113, e.g., to provide a conduction path for ESD event current.

[0038] Figure 2 and 2A An exemplary process or method 200 for manufacturing an electronic device is illustrated. More specifically, Figure 2A illustrates Figure 2 an exemplary pre-clean process (e.g., at 204, 214) in an embodiment of the method. Figures 3 - 15 The above-described semiconductor die 110 fabricated in accordance with the method 200 is illustrated. In the illustrated example, the above-described first stack S1 and second stack S2 are formed in parallel by various deposition and implantation processes.

[0039] Method 200 begins at Figure 2 201: An intrinsic epitaxial layer 114 is formed (e.g., grown) on an initial n-type substrate 113. Figures 3 - 6 illustrates Figure 2 an example of forming an intrinsic epitaxial layer on an initial semiconductor wafer (or semiconductor substrate) 301 at 201. The wafer 301 can be any suitable semiconductor substrate, such as a silicon wafer or a wafer of another type of semiconductor material. In this example, the substrate 301 includes an n-type dopant (e.g., labeled "N+"), such as phosphorus. At Figure 2 202 in Figure 3The wafer loading process 300 shown loads the wafer 301 into an epitaxial deposition processing chamber (not shown), and rotates the loaded wafer while purging the processing chamber, and the chamber temperature increases.

[0040] At Figure 2 204 in, a pre-cleaning process is performed at a first temperature. Figures 4 - 4B An example is shown where a pre-cleaning process 400 is performed to clean the wafer surface before forming an intrinsic epitaxial silicon layer. Figure 2A An example is shown of a pre-cleaning process performed at Figure 2 204 in. In this example, in Figure 2A , a first hydrogen bake process is performed at 231, followed by wafer etching at 232 and a second hydrogen bake process at 233. Figure 4 An example is shown where a first hydrogen bake process 401 (e.g., at Figure 16 231 in) is performed in a hydrogen environment (e.g., H2) at a first temperature (e.g., labeled "TEMP1" in Figure 2A ) while the wafer 301 is rotating. In some examples, the loading temperature at which the wafer is loaded into the chamber is approximately 850 °C, the first temperature (e.g., TEMP 1) of the first hydrogen bake process 401 before etching is stabilized at 1150 °C, and the processing chamber is controlled to increase the temperature from the loading (e.g., approximately 850 °C) to the pre-etch first temperature of approximately 1150 °C. The range is 850 °C to 1150 °C. Then, by performing Figure 4A the etching process 402 in (e.g., Figure 2A 232 in), the top side of the wafer is chemically etched. In some examples, the etching process 402 includes pre-cleaning conditions where the temperature is approximately 1150 °C at atmospheric pressure, the processing time is approximately 30 seconds, and approximately 0.1 μm of silicon is etched using H2 and HCl gases. In Figure 4B , a second hydrogen bake process 403 (e.g., Figure 2A 233 in) is performed. In some examples, during the second hydrogen bake process 403, the temperature is reduced from approximately 1150 °C to approximately 1050 °C.

[0041] Method 200 proceeds to Figure 2 206 of: growing an intrinsic epitaxial layer 114 on the cleaned top side of the wafer 301. Figure 5 An example is shown where an epitaxial growth process 500 for forming (e.g., growing) an intrinsic epitaxial layer 114 is performed. In one example, the epitaxial growth process 500 (e.g., at Figure 16 ) is performed at a second temperature less than the first temperature TEMP1 (e.g., labeled "TEMP2" in Figure 2at 206). In some examples, the second temperature (TEMP2) is an epitaxial film deposition temperature of approximately 1050 °C (e.g., + / - 10 °C). In one embodiment, an n-type dopant (e.g., phosphorus) can diffuse from the substrate 113 into the intrinsic epitaxial layer 114, and the final intrinsic epitaxial layer 114 contains at least some of the diffused n-type dopant. In the example shown, the intrinsic epitaxial layer 114 is grown with a starting thickness 501, as Figure 5 shown, the starting thickness is greater than the target first thickness T1 because a subsequent pre-clean etch process (e.g., at Figure 2 214) will reduce the thickness to the desired target first thickness T1.

[0042] In one example, method 200 proceeds to form an n-type epitaxial layer 115 at 211. In the example shown, method 200 includes unloading the wafer 301 from the processing chamber at 208 after growing the intrinsic epitaxial layer 114 at 206. Figure 6 shows an example where an unloading process 600 of removing the wafer 301 from the processing chamber is performed before forming the n-type epitaxial layer at 211. In one embodiment, after unloading the wafer at 208, the processing chamber can be evacuated and / or cleaned, e.g., by purging to remove the remaining n-type dopant in the processing chamber.

[0043] Method 200 proceeds to Figure 2 211: grow an n-type epitaxial layer 115 with a third n-type dopant concentration on the intrinsic epitaxial layer 114. In one example, the process at 211 is similar to the process at 201, but with an n-type dopant added during the epitaxial layer formation at 216. In this example, method 200 includes Figure 2 a wafer reload at 212. Figure 7 shows an example where a wafer load (e.g., reload) process 700 of loading the wafer 301 into the processing chamber is performed.

[0044] Method 200 continues at Figure 2 214 after reloading the wafer 301 into the processing chamber, where another pre-clean operation is performed at a first temperature (e.g., TEMP1). Figures 8 - 8B shows an example where a pre-clean process 800 is performed to clean the wafer surface before forming the n-type epitaxial layer 115. Figure 2A shows Figure 2 an example pre-clean process performed at 214. In this example, in Figure 2A , a first hydrogen bake process is performed at 231, followed by a wafer etch at 232 and a second hydrogen bake process at 233. Figure 8Shows an example where a first hydrogen baking process 801 (e.g., 231 in Figure 16 below) is performed in a hydrogen environment (e.g., H2) at a first temperature (e.g., labeled "TEMP1" in Figure 2A below), while the wafer 301 is rotating. Then, by performing the etching process 802 (e.g., 232 in Figure 8A below), the top side of the wafer is chemically etched. As a result of the etching process 802, the thickness 501 is reduced to T1. In Figure 2A below, a second hydrogen baking process 803 (e.g., 233 in Figure 8B below) is performed. Figure 2A below).

[0045] Method 200 proceeds to Figure 2 216 in Figure 9 below: An n-type epitaxial layer 115 is grown on the cleaned top side of the intrinsic epitaxial layer 114. Figure 16 Shows an example where an epitaxial growth process 900 of forming (e.g., growing) an n-type epitaxial layer 115 on the intrinsic epitaxial layer 114 is performed. In one example, the epitaxial growth process 900 (e.g., at 216 in Figure 2 below) is performed at a second temperature lower than the first temperature TEMP1 (e.g., labeled "TEMP2" in Figure 10 below). In one example, the epitaxial growth process 900 is performed in an environment containing an n-type dopant (e.g., phosphorus, arsenic, etc.), and the n-type epitaxial layer 115 formed at 216 contains a third n-type dopant concentration. Then, the wafer 301 is unloaded at 218, where

[0046] Shows an example where an unloading process 1000 of unloading the wafer 301 from the epitaxial deposition processing chamber is performed. Figure 2 Method 200 proceeds to Figure 11 220 in Figure 11 below: A p-type dopant is implanted to form a p-type region 120 (e.g., a buried layer).

[0047] Shows an example where an implantation process 1100 is performed using an implantation mask 1101 that exposes the intended p-type implantation region 120. The implantation process 1100 implants a p-type dopant (e.g., boron, etc.) into the exposed upper portion of the n-type epitaxial layer 115 to form a p-type region 120 (e.g., labeled "PBL" in Figure 2 below) that is spaced apart (e.g., above) from the n-type substrate 113 in a first portion of the n-type epitaxial layer 115. Figure 12An example is shown where another epitaxial growth deposition process 1200 of forming a p-type epitaxial layer 116 on an n-type epitaxial layer 115 is performed. As Figure 12 seen, in one example, dopants from the p-type region 120 diffuse upward into the lower portion of the epitaxially grown p-type epitaxial layer 116.

[0048] At Figure 2 224 and 226 in, method 200 proceeds to source-drain implantation, including n-type source-drain (NSD) implantation at 224. Figure 13 An example is shown where an implantation process 1300 is performed using a mask 1301. The implantation process 1300 implants n-type dopants (e.g., phosphorus) along the top side of the p-type epitaxial layer 116 into the exposed region 126 to form an n-type region 126, followed by annealing to diffuse the n-type dopants to form a diffused n-type region 124. The n-type regions 124, 126 are spaced apart (e.g., above) from a first portion of the n-type epitaxial layer 115 and also above a portion of the p-type region 120, as Figure 13 shown.

[0049] At 226, method 200 proceeds in Figure 2 to p-type source-drain (PSD) implantation. Figure 14 An example is shown where an implantation process 1400 is performed using a mask 1401, i.e., implanting p-type dopants (e.g., boron) in a second portion of the p-type epitaxial layer 116 to form a p-type region 128 spaced apart (e.g., above) from a second portion of the n-type epitaxial layer 115.

[0050] Example method 200 proceeds to 228: etching one or more trenches, e.g., to form four lateral deep trench isolation structures as described in reference Figure 1C . Figure 15 An example is shown where an etching process 1500 is performed using an etching mask 1501, i.e., forming a trench 1502 between the first stack S1 and the second stack S2. The trench 1502 extends through the intrinsic epitaxial layer 114, the n-type epitaxial layer 115, and the p-type epitaxial layer 116 and into the n-type substrate 113, as Figure 15 shown. Other wafer-level processing and packaging steps may be performed to complete the packaged electronic device 100 (not shown in Figure 2 ).

[0051] Figure 16 is a graph of the temperature of an example intrinsic layer deposition versus time. That is, Figure 16 FIG. 1600 with a curve 1601 is shown, showing the wafer temperature versus time, e.g., forming the intrinsic epitaxial layer 114 at 201 above, and in one example, at Figure 2 226 in Figure 2Similar processing can be used at 211 in [text not provided] to form the n-type epitaxial layer 115. In FIG. 1600, the wafer 301 is loaded at time T1, and while the wafer 301 is rotating, the temperature is increased from T1 to a first temperature TEMP1 at time T2. From time T2 to time T3, a first hydrogen bake process is performed (e.g., at 231 in [text not provided]), and a pre-clean etch is performed from T3 to time T4 in [text not provided] (e.g., 232 in [text not provided]). In [text not provided], a second hydrogen bake process is performed from T4 to time T5 (e.g., 233 in [text not provided]), followed by a pre-deposition process from T5 to time T6 while the temperature is decreased to a second temperature TEMP2. An epitaxial deposition process is performed from T6 to time T7, and then the process chamber temperature is decreased before the wafer unloading process at time T8. Figure 2A in [text not provided] Figure 16 and a pre-clean etch is performed from T3 to time T4 in [text not provided] (e.g., Figure 2A 232 in [text not provided]). In Figure 16 [text not provided], a second hydrogen bake process is performed from T4 to time T5 (e.g., Figure 2A 233 in [text not provided]), followed by a pre-deposition process from T5 to time T6 while the temperature is decreased to a second temperature TEMP2. An epitaxial deposition process is performed from T6 to time T7, and then the process chamber temperature is decreased before the wafer unloading process at time T8.

[0052] Figure 17 FIG. [text not provided] is a graph of current versus voltage for an embodiment of the ESD protection circuit. That is, Figure 17 FIG. 1700 is shown having a curve 1701, showing the voltage-versus-current of an embodiment of the ESD protection circuit 111 (e.g., Figure 1C the triggerable bipolar transistor structures D1 and Z1 in [text not provided]). The ESD protection circuit 111 allows the protected circuit (e.g., the protected circuit 112 above) to operate normally at a protected node voltage VPROT below the trigger level of the ESD protection circuit 111, and the trigger level is shown as the "operating" range in FIG. 1700. Voltage breakdown can occur in the voltage range marked "voltage breakdown" above the breakdown voltage level VB. During an ESD event where the protected node voltage VPROT first triggers the voltage level VT1, the ESD protection circuit 111 conducts a small amount of current and then triggers snapback operation, where the bipolar structures D1, Z1 turn on to conduct an increasing current while the protected node voltage VPROT decreases to an initial holding voltage level VHOLD and then rises with a substantially linear slope corresponding to the impedance of the bipolar linear region marked "R". For example, this operation can successfully conduct the ESD event current through the first stack S1 to the substrate 113 and then to Figure 1C the metal structure 140 on the bottom side in [text not provided]. Figure 17 FIG. [text not provided] further shows a second trigger voltage level VT2, and if it is higher than VT2, the current may increase and may cause a thermal failure in the high-current region marked "thermal second breakdown region".

[0053] Figure 18 FIG. [text not provided] is a graph of bipolar holding voltage versus distance. That is, Figure 18 FIG. 1800 is shown, where the vertical axis represents the bipolar holding voltage, e.g., with reference to Figure 17The described VHOLD is set to be lower than the breakdown voltage rating VB of a given device design. The horizontal axis in FIG. 1800 represents the distance from the wafer edge ("WE") to the wafer center ("WC"). FIG. 1800 includes a first set of data points 1801 corresponding to a baseline ESD protection circuit without an intrinsic epitaxial layer, and a second set of data points 1803 corresponding to the above-described ESD protection circuit 111 in the semiconductor die 110 of the electronic device 100. As shown in the first data set 1801, some electronic devices, such as those closer to the lateral edge of the processed wafer, experience a hold voltage VHOLD that drops below the lower limit of the final test specification (e.g., labeled "specification lower limit") and thus experience the breakdown voltage rating, while in the data set 1803 from devices that include the intrinsic epitaxial layer 114, all devices have a bipolar hold voltage VHOLD that is above the upper specification limit and thus have a breakdown voltage rating VB. Thus, compared to the final breakdown voltage test, using the intrinsic epitaxial layer 1400 in the ESD protection circuit system significantly improves the manufacturing product yield.

[0054] Figure 19 A cumulative probability curve graph showing the bipolar hold voltage. That is, Figure 19 FIG. 1900 showing four cumulative probability curve graphs including the bipolar hold voltage (e.g., the VHOLD described in reference Figure 17 . The first curve 1901 corresponds to a baseline ESD protection circuit without an intrinsic epitaxial layer at the edge of the processed wafer. The second curve 1902 corresponds to a baseline ESD protection circuit without an intrinsic epitaxial layer at the center of the processed wafer. The third curve 1903 corresponds to an embodiment of the ESD protection circuit 111 with an intrinsic epitaxial layer 114 at the edge of the processed wafer. The fourth curve 1904 corresponds to an embodiment of the ESD protection circuit 111 with an intrinsic epitaxial layer 114 at the center of the processed wafer. As shown in FIG. 1900, the baseline ESD protection device (e.g., curve 1902) and the exemplary ESD protection circuit 111 formed with an intrinsic epitaxial layer 114 at the center of the processed wafer (e.g., curve 1904) are between the lower and upper specification limits within the acceptable breakdown voltage design range of VHOLD. As further shown by the comparison of the wafer edge curves 1901 and 1903 of the corresponding baseline and ESD protection circuit 111 with an intrinsic epitaxial layer 114, the baseline ESD protection device at the edge of the processed wafer has a significant lower specification limit problem in terms of breakdown voltage operation (e.g., VHOLD), while the ESD protection circuit 111 with an intrinsic epitaxial layer 114 at the wafer edge provides a significant improvement, and its performance is generally between the lower and upper specification limits within the acceptable breakdown voltage range of the bipolar hold voltage VHOLD.

[0055] Within the scope of the claims, modifications may be made in the described examples, and other embodiments are possible.

Claims

1. An electronic device, comprising: an n-type substrate having a first n-type dopant concentration; An intrinsic epitaxial layer, which is located on the n-type substrate and has a second n-type dopant concentration less than the first n-type dopant concentration. n-type dopant concentration; an n-type epitaxial layer on the intrinsic epitaxial layer and having a third n-type dopant concentration greater than the second n-type dopant concentration; and The p-type epitaxial layer is located on the n-type epitaxial layer. 2 . The electronic device according to claim 1 , wherein the intrinsic epitaxial layer has a thickness of 0.1 μm or more. 3 . The electronic device according to claim 2 , wherein the thickness of the intrinsic epitaxial layer is 1.5 μm or less. 4 . The electronic device of claim 1 , further comprising an n-type region located in a portion of the p-type epitaxial layer and spaced apart from the n-type epitaxial layer to form a cathode of a first diode. 5 . The electronic device of claim 4 , further comprising a p-type region located in a portion of the n-type epitaxial layer and spaced apart from the n-type substrate. 6 . The electronic device of claim 1 , further comprising a p-type region located in a portion of the p-type epitaxial layer and spaced apart from the n-type epitaxial layer.

7. The electronic device according to claim 6, further comprising: a first stack comprising a first portion of the n-type substrate, a first portion of the intrinsic epitaxial layer on the first portion of the n-type substrate, a first portion of the n-type epitaxial layer on the first portion of the intrinsic epitaxial layer, a first portion of the p-type epitaxial layer over the first portion of the n-type epitaxial layer, an n-type region in a portion of the first portion of the p-type epitaxial layer and spaced apart from the first portion of the n-type epitaxial layer to form a cathode of a first diode, a p-type region in a portion of the n-type epitaxial layer and spaced apart from the n-type substrate, and an intersection between the p-type region and a portion of the n-type epitaxial layer to form a pn junction of a Zener diode; as well as a second stack spaced apart from the first stack and comprising a second portion of the n-type substrate, a second portion of the intrinsic epitaxial layer on the second portion of the n-type substrate, a second portion of the n-type epitaxial layer on the second portion of the intrinsic epitaxial layer, a second portion of the p-type epitaxial layer on the second portion of the n-type epitaxial layer, a p-type region in the second portion of the p-type epitaxial layer and spaced apart from the second portion of the n-type epitaxial layer, and a junction between the second portion of the p-type epitaxial layer and the second portion of the n-type epitaxial layer forming a pn junction of a second diode.

8. The electronic device of claim 7, further comprising a deep trench isolation structure extending through the intrinsic epitaxial layer, the n-type epitaxial layer, and the p-type epitaxial layer and into the n-type substrate and separating the first and second stacks. 9 . The electronic device of claim 7 , further comprising a metallization structure coupling the cathode of the first diode to the anode of the second diode to form an electrostatic discharge (ESD) protection circuit.

10. The electronic device according to claim 1, wherein: The intrinsic epitaxial layer has a first thickness; and The n-type epitaxial layer has a second thickness greater than the first thickness.

11. An electronic device comprising: a protected circuit coupled to the terminal; as well as an electrostatic discharge protection circuit coupled to the terminal and comprising: a first stack comprising a first portion of an n-type substrate, a first portion of an intrinsic epitaxial layer on the first portion of the n-type substrate, a first portion of an n-type epitaxial layer on the first portion of the intrinsic epitaxial layer, a first portion of a p-type epitaxial layer over the first portion of the n-type epitaxial layer, an n-type region in a portion of the first portion of the p-type epitaxial layer and spaced apart from the first portion of the n-type epitaxial layer to form a cathode of a first diode, a p-type region in a portion of the n-type epitaxial layer and spaced apart from the n-type substrate, and an intersection between the p-type region and a portion of the n-type epitaxial layer to form a pn junction of a Zener diode; as well as a second stack spaced apart from the first stack and comprising a second portion of the n-type substrate, a second portion of the intrinsic epitaxial layer on the second portion of the n-type substrate, a second portion of the n-type epitaxial layer on the second portion of the intrinsic epitaxial layer, a second portion of the p-type epitaxial layer on the second portion of the n-type epitaxial layer, a p-type region in the second portion of the p-type epitaxial layer and spaced apart from the second portion of the n-type epitaxial layer, and a junction between the second portion of the p-type epitaxial layer and the second portion of the n-type epitaxial layer forming a pn junction of a second diode.

12. The electronic device according to claim 11, wherein: The n-type substrate has a first n-type dopant concentration; The intrinsic epitaxial layer has a second n-type dopant concentration that is less than the first n-type dopant concentration; and The n-type epitaxial layer has a third n-type dopant concentration greater than the second n-type dopant concentration.

13. The electronic device of claim 11, further comprising a deep trench isolation structure extending through the intrinsic epitaxial layer, the n-type epitaxial layer, and the p-type epitaxial layer and into the n-type substrate and separating the first and second stacks.

14. The electronic device of claim 11, further comprising a metallization structure coupling the cathode of a first diode to an anode of the second diode and the terminal.

15. A method comprising: growing an intrinsic epitaxial layer having a second n-type dopant concentration on an n-type substrate of a wafer, the n-type substrate having a first n-type dopant concentration greater than the second n-type dopant concentration; growing an n-type epitaxial layer having a third n-type dopant concentration on the intrinsic epitaxial layer, the third n-type dopant concentration being greater than the second n-type dopant concentration; and A p-type epitaxial layer is grown on the n-type epitaxial layer.

16. The method according to claim 15, further comprising: After growing the intrinsic epitaxial layer, unloading the wafer from a processing chamber; reloading the wafer into the processing chamber after unloading the wafer from the processing chamber; as well as After reloading the wafer into the processing chamber and before growing the n-type epitaxial layer, a pre-cleaning process is performed.

17. The method of claim 16, wherein: The pre-cleaning process is performed at a first temperature; and Growing the n-type epitaxial layer is performed at a second temperature that is less than the first temperature.

18. The method of claim 16, wherein the pre-cleaning process comprises: performing a first hydrogen baking process; After the first hydrogen baking process, performing an etching process of etching the intrinsic epitaxial layer; and After the etching process, a second hydrogen baking process is performed.

19. The method of claim 15, further comprising: forming a first stack comprising a first portion of the n-type substrate, a first portion of the intrinsic epitaxial layer on the first portion of the n-type substrate, a first portion of the n-type epitaxial layer on the first portion of the intrinsic epitaxial layer, and a first portion of the p-type epitaxial layer over the first portion of the n-type epitaxial layer; forming a second stack spaced apart from the first stack and comprising a second portion of the n-type substrate, a second portion of the intrinsic epitaxial layer on the second portion of the n-type substrate, a second portion of the n-type epitaxial layer on the second portion of the intrinsic epitaxial layer, and a second portion of the p-type epitaxial layer on the second portion of the n-type epitaxial layer; implanting an n-type dopant in a portion of the first portion of the p-type epitaxial layer to form an n-type region spaced apart from the first portion of the n-type epitaxial layer; implanting a p-type dopant in the second portion of the p-type epitaxial layer to form a p-type region spaced apart from the second portion of the n-type epitaxial layer; as well as A trench is etched between the first and second stacks, the trench extending through the intrinsic epitaxial layer, the n-type epitaxial layer, and the p-type epitaxial layer and into the n-type substrate. 20 . The method of claim 19 , further comprising implanting the p-type dopant in the first portion of the n-type epitaxial layer in a manner spaced apart from the n-type substrate before growing the p-type epitaxial layer.

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