Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductor chips. The semiconductor device comprises a collector region, a drift region, an emitter region and a gate region, the drift region is arranged on the collector region, the emitter region is arranged on the side, away from the collector region, of the drift region, and the gate region is arranged on the side, away from the collector region, of the drift region. The projection of the gate region on a first reference plane is not overlapped with the projection of the drift region on the first reference plane, the first reference plane is parallel to the thickness direction of the drift region, and the drift region comprises a first sub-drift region and a second sub-drift region which are stacked; the second sub-drift region is located on the side, away from the collector region, of the first sub-drift region, and the doping types of the first sub-drift region and the second sub-drift region are different.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor chips, and in particular, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As a composite power semiconductor device that combines the advantages of a metal-oxide-semiconductor field-effect transistor (MOSFET) with a high input impedance and a bipolar junction transistor (BJT) with a low on-state voltage drop, the insulated gate bipolar transistor (IGBT) occupies an important position in the fields of new energy power generation, electric vehicles, industrial frequency converters, and smart grids.

[0003] Planar IGBT devices have become one of the mainstream technical routes for medium and high voltage application scenarios due to their simple manufacturing process, strong reliability, and controllable cost. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, aiming to solve the problems of easy damage and poor reliability of the gate dielectric layer of the semiconductor device.

[0005] To achieve the above object, the embodiments of the present disclosure adopt the following technical solutions: On the one hand, a semiconductor device is provided, including a collector region, a drift region, an emitter region, and a gate region. The drift region is disposed above the collector region. The emitter region is disposed on a side of the drift region away from the collector region. The gate region is disposed on a side of the drift region away from the collector region, and a projection of the gate region on a first reference plane does not overlap with a projection of the drift region on the first reference plane, and the first reference plane is parallel to a thickness direction of the drift region. The drift region includes a first sub-drift region and a second sub-drift region stacked, the second sub-drift region is located on a side of the first sub-drift region away from the collector region, and doping types of the first sub-drift region and the second sub-drift region are different.

[0006] When the semiconductor device of the present invention operates in a breakdown voltage state, the voltage of the gate region is 0 potential or negative potential, the emitter region is at a low potential, and the collector region is at a high potential. At this time, the PN junction formed by the second sub-drift region and the first sub-drift region is in a reverse bias state, and will bear part of the electric field, thereby reducing the peak value of the electric field at the gate oxide, making the electric field distribution in the device more uniform, which is beneficial to improving the breakdown voltage of the semiconductor device, and improving the expected life and reliability of the semiconductor device.

[0007] In addition, the improvement of the electric field distribution can make the temperature distribution more uniform, avoid surface overheating of the semiconductor device due to too high surface electric field, and further improve the expected life and reliability of the semiconductor device.

[0008] In a feasible embodiment, the semiconductor device further includes a carrier storage layer located between the second sub-drift region and the emitter region, and the doping types of the carrier storage layer and the second sub-drift region are different.

[0009] When the semiconductor device of the present invention operates in the on state, the voltage of the gate region is greater than the threshold voltage, the emitter region is at a low potential, and the collector region is at a high potential. The holes injected from the collector region are partially blocked by the carrier storage layer when diffusing in the drift region, forming local hole accumulation, significantly increasing the carrier concentration in the drift region, and thus reducing the on-resistance.

[0010] In a feasible embodiment, the emitter region includes a first emitter region and a second emitter region respectively located on both sides of the gate region, and the arrangement direction of the first emitter region and the second emitter region is the first direction. The carrier storage layer includes a first sub-carrier storage layer and a second sub-carrier storage layer. The first sub-carrier storage layer is located between the first emitter region and the second sub-drift region. The second sub-carrier storage layer is located between the second emitter region and the second sub-drift region.

[0011] In a feasible embodiment, along the first direction, there is a gap between the first sub-carrier storage layer and the second sub-carrier storage layer. A part of the second sub-drift region is located within the gap.

[0012] In a feasible embodiment, the semiconductor device further includes a gate dielectric layer located under the gate region. The part of the second sub-drift region located within the gap is in contact with the gate dielectric layer.

[0013] In a feasible embodiment, along the first direction, the first sub-carrier storage layer and the second sub-carrier storage layer are connected. The second sub-drift region is located under the first sub-carrier storage layer and the second sub-carrier storage layer.

[0014] The connected first sub-carrier storage layer and second sub-carrier storage layer can not only maintain the function of the carrier storage layer, but also reduce the process difficulty, thereby reducing the production cost and improving the product yield.

[0015] In a feasible embodiment, the semiconductor device further includes a gate dielectric layer located under the gate region. Parts of the first sub-carrier storage layer and the second sub-carrier storage layer both extend towards the gate region and are in contact with the gate dielectric layer.

[0016] When the semiconductor device operates in the breakdown voltage withstand state, the PN junction formed by the second sub-drift region and the first sub-drift region is in the reverse bias state, which will bear part of the electric field, make the electric field distribution more uniform, and can reduce the electric field at the gate dielectric layer, which is beneficial to improving the breakdown voltage of the semiconductor device, and improving the expected lifetime and reliability of the semiconductor device.

[0017] In a feasible embodiment, the first emitter region includes a first sub-emitter region and a second sub-emitter region with different doping types. The first sub-emitter region and the second sub-emitter region are arranged along the first direction, and compared with the second sub-emitter region, the first sub-emitter region is far from the gate region. The second emitter region includes a third sub-emitter region and a fourth sub-emitter region with different doping types. The third sub-emitter region and the fourth sub-emitter region are arranged along the first direction, and compared with the third sub-emitter region, the fourth sub-emitter region is far from the gate region.

[0018] In a feasible embodiment, it further includes: a first well region located between the first emitter region and the first sub-carrier storage layer; a second well region located between the second emitter region and the second sub-carrier storage layer; parts of the first well region and parts of the second well region both extend towards the gate region and contact the gate dielectric layer.

[0019] When the semiconductor device of the present invention operates in the conducting state, the voltage of the gate region is greater than the threshold voltage, the emitter region is at a low potential, and the collector region is at a high potential. Under the action of the voltage of the gate region, an electron inversion layer is formed on the surfaces of the first well region and the second well region. The second sub-emitter region and the third sub-emitter region are respectively connected to the carrier storage layer through the electron inversion layers on the surfaces of the first well region and the second well region. The P-type collector region, the N-type buffer layer, the N-type first sub-drift region, the P-type second sub-drift region, and the N-type carrier storage layer form a PNPN thyristor, and this PNPN thyristor gradually turns on as the collector current increases. If this PNPN thyristor is fully turned on, there are a large number of free carriers in the first sub-drift region and the second sub-drift region, while the PN junction formed by the well region and the carrier storage layer is still in the reverse bias state.

[0020] If the semiconductor device is turned off, that is, switched from the conducting state to the breakdown voltage withstand state, the voltage in the gate region changes from being greater than the threshold voltage to being less than or equal to 0V. The channel of the semiconductor device is gradually turned off, and the depletion region of the semiconductor device gradually expands. The depletion region formed by the PN junction of the first well region / second well region and the carrier storage layer gradually expands towards the second sub-drift region. Since the thickness of the carrier storage layer is relatively narrow, the voltage that the PN junction can withstand is small. When the electric field expands to the second sub-drift region, the P-type doped second sub-drift region makes this region unable to withstand high voltage. Therefore, holes in the second sub-drift region can be extracted at a lower voltage, accelerating the hole extraction during turn-off, improving the turn-off speed, thereby reducing the turn-off loss of the semiconductor device and enhancing the reliability of the semiconductor device.

[0021] In a feasible embodiment, it further includes: a first metal layer located on the side of the collector region away from the drift region; a second metal layer located on the side of the drift region away from the collector region and in ohmic contact with the emitter region; the gate region further includes a second dielectric layer located between the second metal layer and the gate region conductor.

[0022] On the other hand, a method for manufacturing a semiconductor device is provided, including: sequentially forming a stacked collector region, a first sub-drift region, and a second sub-drift region, where the doping types of the first sub-drift region and the second sub-drift region are different; performing ion implantation on the surface of the second sub-drift region away from the collector region to form an emitter region; forming a gate region on the side of the second sub-drift region away from the collector region; the projection of the gate region on a first reference plane does not overlap with the projection of the drift region on the first reference plane, and the first reference plane is parallel to the thickness direction of the second sub-drift region.

[0023] It can be understood that for the method for manufacturing a semiconductor device provided in the above embodiments of the present disclosure, the beneficial effects that can be achieved can refer to the beneficial effects of the semiconductor device in the above text, which will not be elaborated here. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for some embodiments of the present disclosure will be briefly introduced below.

[0025] Figure 1 It is a structural diagram of an electronic device provided according to some embodiments; Figure 2 It is a structural diagram of a chip provided according to some embodiments; Figure 3 It is a structural diagram of a semiconductor device provided according to some embodiments; Figure 4 It is a structural diagram of another semiconductor device provided according to some embodiments; Figure 5 Structural diagram of another semiconductor device provided according to some embodiments; Figure 6 Flowchart of a method for manufacturing a semiconductor device provided according to some embodiments; Figure 7 Flowchart of another method for manufacturing a semiconductor device provided according to some embodiments; Figures 8 to 15 For Figure 7 Semiconductor structural diagrams corresponding to the respective steps in the manufacturing method. Specific embodiments

[0026] Next, in conjunction with the accompanying drawings, the technical solutions in some embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0027] In the description of the present disclosure, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation of the present disclosure.

[0028] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted as an open, inclusive meaning, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any suitable manner.

[0029] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0030] In describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other. Another example is that in describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0031] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0032] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0033] The use of "configured to" herein means open and inclusive language, which does not exclude a device configured to perform additional tasks or steps.

[0034] As used herein, "about", "substantially", or "approximately" includes the stated value and the average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

[0035] In the context of the present disclosure, the meanings of "on", "above", and "over" should be interpreted in the broadest manner such that "on" not only means "directly on something", but also includes "on something" with intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also includes "above" or "over" something without intermediate features or layers therebetween (i.e., directly on something).

[0036] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0037] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself can be patterned. The materials added on the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, silicon carbide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0038] Figure 1 FIG. is a structural diagram of an electronic device provided according to some embodiments. As Figure 1 shown, embodiments of the present disclosure provide an electronic device 1000. The electronic device 1000 can be a product or component with a power conversion function such as a power conversion system of an electric vehicle, a charging device of a mobile phone, a power adapter device of a laptop computer, etc. The electronic device 1000 can also be different types of user devices or terminal devices such as a laptop computer, a tablet computer, a mobile phone, a wearable device, and an in-vehicle device, or can be a power amplification device applied to the above-mentioned electronic devices. It should be understood that the electronic device 1000 can also be a device or component with a signal receiving / transmitting function in devices such as an amplifier, a modulator, a base station, a radar, etc. The embodiments of the present application do not impose special restrictions on the specific form of the above-mentioned electronic device 1000.

[0039] Hereinafter, taking the electronic device 1000 as an electronic device with a power conversion function as an example, some embodiments of the present disclosure will be schematically described. However, the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical concept is applied.

[0040] In Figure 1 , the electronic device 1000 includes, for example, a chip 1001 and a circuit board 1002. The chip 1001 is coupled to the circuit board 1002, and the circuit board 1002 is configured to supply power to the chip 1001 and transmit signals. Exemplarily, referring to Figure 2 , Figure 2A structural diagram of a chip provided according to some embodiments. The chip 1001 includes a semiconductor device 100 and a package substrate 200, and the semiconductor device 100 is coupled to the package substrate 200.

[0041] Figure 3 A structural diagram of a semiconductor device provided according to some embodiments. The semiconductor device 100 can be a semiconductor device such as silicon, silicon carbide, or gallium nitride. The semiconductor device 100 includes a collector region 101, a drift region 103, an emitter region 107, and a gate region 302. Exemplarily, the drift region 103 is located on one side of the collector region 101, the emitter region 107 is located on the side of the drift region 103 away from the collector region 101, the gate region 302 is located on the side of the drift region 103 away from the collector region 101, and the projection of the emitter region 107 on the first reference plane overlaps with the projection of the drift region 103 on the first reference plane, and the projection of the gate region 302 on the first reference plane does not overlap with the projection of the drift region 103 on the first reference plane. Wherein, the first reference plane is parallel to the thickness direction z of the drift region 103. Exemplarily, the doping type of the collector region 101 is P-type, and the doping type of the drift region 103 is N-type.

[0042] In some feasible embodiments, the emitter region 107 includes a first sub-emitter region 107a and a second sub-emitter region 107b with different doping types. The first sub-emitter region 107a and the second sub-emitter region 107b are arranged along the first direction x, and compared with the second sub-emitter region 107b, the first sub-emitter region 107a is farther from the gate region 302. Exemplarily, the doping type of the first sub-emitter region 107a is P-type, the doping type of the second sub-emitter region 107b is N-type, and the doping concentration of the second sub-emitter region 107b is greater than the doping concentration of the well region 106.

[0043] In some feasible embodiments, the semiconductor device 100 further includes a well region 106, a first metal layer 301, a gate dielectric layer 303, an isolation dielectric layer 304, and a second metal layer 305.

[0044] The first metal layer 301 is located on the side of the collector region 101 away from the drift region 103. The gate dielectric layer 303 is located on the side of the gate region 302 close to the collector region 101. The second metal layer 305 is located on the side of the drift region 103 away from the collector region 101, and the second metal layer 305 forms an ohmic contact with the emitter region 107. The isolation dielectric layer 304 is located between the gate region 302 and the second metal layer 305, and a part of the second metal layer 305 extends towards the gate dielectric layer 303 and contacts the gate dielectric layer 303.

[0045] Exemplarily, the material of the gate dielectric layer 303 and / or the isolation dielectric layer 304 includes any one or a combination of several of silicon oxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), and silicon nitride (Si3N4). Among them, the material included in the gate dielectric layer 303 may be the same as or different from that of the isolation dielectric layer 304. If the material of the gate dielectric layer 303 is the same as that of the isolation dielectric layer 304, the gate dielectric layer 303 and the isolation dielectric layer 304 can be regarded as a whole, not including, for example, Figure 3 the dividing line shown in

[0046] The well region 106 is located between the drift region 103 and the emitter region 107. A part of the well region 106 extends towards the gate region 302 and contacts the gate dielectric layer 303. Exemplarily, the doping type of the well region 106 is P-type, and the doping concentration of the well region 106 is less than the doping concentration of the first sub-emitter region 107a.

[0047] Figure 4 It is a structural diagram of another semiconductor device provided according to some embodiments. The semiconductor device 100 includes a collector region 101, a buffer layer 102, a drift region 103, a carrier storage layer 105, a well region 106, an emitter region, a gate region 302, and a gate dielectric layer 303.

[0048] The buffer layer 102 is located on one side of the collector region 101. The drift region 103 is located on the side of the buffer layer 102 away from the collector region 101. The drift region 103 includes a first sub-drift region 103a and a second sub-drift region 103b. The first sub-drift region 103a is located on the side of the buffer layer 102 away from the collector region 101, and the second sub-drift region 103b is located on the side of the first sub-drift region 103a away from the collector region 101. The doping types of the first sub-drift region 103a and the second sub-drift region 103b are different. Exemplarily, the doping type of the first sub-drift region 103a is N-type, and the doping type of the second sub-drift region 103b is P-type.

[0049] The emitter region is located on the side of the drift region 103 away from the collector region 101. The gate region 302 is located on the side of the drift region 103 away from the collector region 101, and the projection of the emitter region on the first reference plane overlaps with the projection of the drift region 103 on the first reference plane, while the projection of the gate region 302 on the first reference plane does not overlap with the projection of the drift region 103 on the first reference plane. Among them, the first reference plane is parallel to the thickness direction z of the drift region 103.

[0050] The emitter region includes a first emitter region 107 and a second emitter region 108, and the first emitter region 107 and the second emitter region 108 are respectively located on both sides of the gate region 302. The first emitter region 107 includes a first sub-emitter region 107a and a second sub-emitter region 107b with different doping types. The first sub-emitter region 107a and the second sub-emitter region 107b are arranged along the first direction x, and they are in contact with each other. The first direction x is the arrangement direction of the first emitter region 107 and the second emitter region 108. Compared with the second sub-emitter region 107b, the first sub-emitter region 107a is farther from the gate region 302. Exemplarily, the doping type of the first sub-emitter region 107a is P-type, and the doping type of the second sub-emitter region 107b is N-type. The second emitter region 108 includes a third sub-emitter region 108a and a fourth sub-emitter region 108b with different doping types. The third sub-emitter region 108a and the fourth sub-emitter region 108b are arranged along the first direction x, and they are in contact with each other. Compared with the third sub-emitter region 108a, the fourth sub-emitter region 108b is farther from the gate region 302. Exemplarily, the doping type of the third sub-emitter region 108a is N-type, and the doping type of the fourth sub-emitter region 108b is P-type. The doping concentration of the first sub-emitter region 107a is the same as that of the fourth sub-emitter region 108b, and the doping concentration of the second sub-emitter region 107b is the same as that of the third sub-emitter region 108a.

[0051] The carrier storage layer 105 includes a first sub-carrier storage layer 105a and a second sub-carrier storage layer 105b. The first sub-carrier storage layer 105a is located between the first emitter region 107 and the second sub-drift region 103b, and the second sub-carrier storage layer 105b is located between the second emitter region 108 and the second sub-drift region 103b. Parts of the first sub-carrier storage layer 105a and the second sub-carrier storage layer 105b both extend towards the gate region 302 and are in contact with the gate dielectric layer 303. Among them, the gate dielectric layer 303 is located on the side of the gate region 302 close to the collector region 101. The doping concentration of the first sub-carrier storage layer 105a is the same as that of the second sub-carrier storage layer 105b, and the doping concentration of the first sub-carrier storage layer 105a is less than that of the second sub-emitter region 107b.

[0052] When the semiconductor device 100 is in the on state, the voltage of the gate region 302 is greater than the threshold voltage, the channel in the gate region is turned on, the second metal layer 305, that is, the first emitter region 107 and the second emitter region 108 are grounded, and the voltage received by the first metal layer 301, that is, the collector region 101, is greater than 0V. When the holes injected from the collector region 101 diffuse in the drift region 103, they are partially blocked by the carrier storage layer 105, forming local hole accumulation, significantly increasing the carrier concentration in the drift region 103, thereby reducing the on-resistance of the semiconductor device 100.

[0053] In some possible embodiments, such as Figure 4 shown, there is a gap between the first sub-carrier storage layer 105a and the second sub-carrier storage layer 105b, and the portion of the second sub-drift region 103b located within this gap is in contact with the gate dielectric layer 303.

[0054] The well region 106 includes a first well region 106a and a second well region 106b. The first well region 106a is located between the first emitter region 107 and the first sub-carrier storage layer 105a, and the second well region 106b is located between the first emitter region 107 and the second sub-carrier storage layer 105b. Portions of both the first well region 106a and the second well region 106b extend towards the gate region 302 and are in contact with the gate dielectric layer 303. The doping concentration of the first well region 106a is the same as that of the second well region 106b. The doping concentration of the first well region 106a is greater than the doping concentration of the second sub-drift region 103b, and the doping concentration of the first well region 106a is less than the doping concentration of the first sub-emitter region 107a.

[0055] When the semiconductor device 100 operates in the breakdown voltage withstand state, the voltage of the gate region 302 is less than or equal to 0V, the gate channel is closed, the second metal layer 305, i.e., the first emitter region 107 and the second emitter region 108, is grounded, and the voltage of the first metal layer 301, i.e., the collector region 101, is greater than 0V. At this time, the PN junction formed by the carrier storage layer 105 and the well region 106 is in the reverse bias state, and the PN junction formed by the second sub-drift region 103b and the first sub-drift region 103a is in the reverse bias state. Both bear the electric field simultaneously, making the electric field distribution more uniform, and can reduce the electric field at the gate dielectric layer 303, which is beneficial to increasing the breakdown voltage of the semiconductor device 100, and improving the expected life and reliability of the semiconductor device 100. In addition, the improvement of the electric field distribution can make the temperature distribution more uniform, avoid overheating on the surface of the semiconductor device 100, and further enhance the expected life and reliability of the semiconductor device 100.

[0056] When the semiconductor device 100 operates in the forward conduction state, the voltage of the gate region 302 is greater than the threshold voltage, the second metal layer 305, i.e., the emitter region, is grounded, and the voltage of the first metal layer 301, i.e., the collector region 101, is greater than 0V. Under the action of the voltage in the gate region 302, an electron inversion layer is formed on the surface of the well region 106, and the second sub-emitter region 107b and the third sub-emitter region 108a are connected to the carrier storage layer 105 through the electron inversion layer on the surface of the well region 106. The P-type collector region 101, the N-type buffer layer 102, the N-type first sub-drift region 103a, the P-type second sub-drift region 103b, and the N-type carrier storage layer 105 form a PNPN thyristor, and this PNPN thyristor gradually turns on as the current in the collector region 101 increases. If, after this PNPN thyristor is fully turned on, there are a large number of free carriers in the first sub-drift region 103a and the second sub-drift region 103b, the PN junction formed by the well region 106 and the carrier storage layer 105 is in the reverse bias state.

[0057] When the semiconductor device 100 is turned off, the voltage of the gate region 302 changes from being greater than the threshold voltage to being less than or equal to 0V, the voltage of the second metal layer 305, i.e., the emitter region, is 0V, and the voltage of the first metal layer 301, i.e., the collector region 101, is greater than or equal to 0V. After the semiconductor device 100 switches from the conduction state to the off state, the channel gradually turns off, and the depletion region of the semiconductor device 100 gradually expands. The depletion region formed by the PN junction of the well region 106 and the carrier storage layer 105 gradually expands towards the second sub-drift region 103b. The existence of the second sub-drift region 103b makes the electric field here very small, and holes in the second sub-drift region 103b can be extracted at a lower voltage, accelerating the hole extraction during turn-off, improving the turn-off speed, thereby reducing the turn-off loss of the semiconductor device 100 and enhancing the reliability of the semiconductor device 100.

[0058] During the process of the semiconductor device 100 switching from the conduction state to the off state, a large number of holes stored in the first sub-drift region 103a are discharged through the collector region 101, and the buffer layer 102 can serve as a fast extraction channel for carriers, accelerating the hole discharge rate, significantly reducing the duration of the tail current, thereby shortening the turn-off time and reducing the turn-off loss.

[0059] In some feasible embodiments, the semiconductor device 100 further includes a first metal layer 301, an isolation dielectric layer 304, and a second metal layer 305. The first metal layer 301 is located on the side of the collector region 101 away from the buffer layer 102. The second metal layer 305 is located on the side of the drift region 103 away from the collector region 101 and forms an ohmic contact with the first emitter region 107 and the second emitter region 108. The isolation dielectric layer 304 is located on the side of the gate region 302 away from the collector region 101, and a part of the isolation dielectric layer 304 extends towards the gate dielectric layer 303 and contacts the gate dielectric layer 303.

[0060] Figure 5 The structural diagram of another semiconductor device provided according to some embodiments. In Figure 5 the semiconductor device 100 shown, the first sub-carrier storage layer 105a and the second sub-carrier storage layer 105b are connected, and the second sub-drift region 103b is located below the first sub-carrier storage layer 105a and the second sub-carrier storage layer 105b. Exemplarily, the first sub-carrier storage layer 105a and the second sub-carrier storage layer 105b can be regarded as a whole. Figure 5 The remaining structure of the semiconductor device 100 shown is basically the same as that of the semiconductor device 100 shown in Figure 4 and will not be described in detail herein.

[0061] If the JFET (Junction Field-Effect Transistor) of the semiconductor device 100 is narrow, that is, the distance between the first well region 106a and the second well region 106b is small, to make Figure 4 the gap between the first sub-carrier storage layer 105a and the second sub-carrier storage layer 105b of the semiconductor device 100 in will cause a significant reduction in the yield of the semiconductor device 100. If the yield is to be improved, the process complexity and production cost will be significantly increased. Therefore, in Figure 5 the embodiment shown, the connected first sub-carrier storage layer 105a and second sub-carrier storage layer 105b are formed, which can not only maintain the function of the carrier storage layer 105, but also reduce the process complexity, thereby reducing the production cost and improving the product yield.

[0062] Figure 6 The flowchart of a preparation method of a semiconductor device provided according to some embodiments. The preparation method of the semiconductor device 100 includes step S10 to step S30.

[0063] In step S10, the collector region 101, the first sub-drift region 103a, and the second sub-drift region 103b are sequentially formed in a stacked manner. The doping types of the first sub-drift region 103a and the second sub-drift region 103b are different, and the semiconductor structure shown in Figure 8 is obtained. Exemplarily, the doping type of the collector region 101 is P-type, the doping type of the first sub-drift region 103a is N-type, and the doping type of the second sub-drift region 103b is P-type.

[0064] In step S20, ion implantation is performed on the surface of the second sub-drift region 103b away from the collector region 101 to form an emitter region, and the semiconductor structure shown in Figure 9 is obtained.

[0065] The projection of the emitter region on the first reference plane overlaps with the projection of the second sub-drift region 103b on the first reference plane, and the first reference plane is parallel to the thickness direction z of the second sub-drift region 103b. The emitter region includes a first emitter region 107 and a second emitter region 108. The first emitter region 107 includes a first sub-emitter region 107a and a second sub-emitter region 107b with different doping types, and the second emitter region 108 includes a third sub-emitter region 108a and a fourth sub-emitter region 108b with different doping types. The first sub-emitter region 107a, the second sub-emitter region 107b, the third sub-emitter region 108a, and the fourth sub-emitter region 108b are arranged along the first direction x. Exemplarily, the doping types of the first sub-emitter region 107a and the fourth sub-emitter region 108b are P-type, and the doping types of the second sub-emitter region 107b and the third sub-emitter region 108a are N-type.

[0066] In step S30, a gate region 302 is formed on the side of the second sub-drift region 103b away from the collector region 101, obtaining a semiconductor structure as Figure 13 shown.

[0067] The projection of the gate region 302 on the first reference plane does not overlap with the projection of the second sub-drift region 103b on the first reference plane, and the first reference plane is parallel to the thickness direction z of the second sub-drift region 103b.

[0068] Figure 7 FIG. is a flowchart of another manufacturing method of a semiconductor device according to some embodiments. Figures 8 to 15 is Figure 7 the semiconductor structure diagrams corresponding to the respective steps in the manufacturing method.

[0069] The manufacturing method of the semiconductor device 100 includes step S11, step S21, steps S31 - S34, and steps S41 - S43.

[0070] In step S11, a collector region 101, a buffer layer 102, a first sub-drift region 103a, and a second sub-drift region 103b are sequentially formed on one side of the substrate 306, obtaining a semiconductor structure as Figure 8 shown. In some feasible embodiments, the collector region 101, the buffer layer 102, the first sub-drift region 103a, and the second sub-drift region 103b can be sequentially formed on one side of the substrate 306 by epitaxial growth. Exemplarily, the substrate 306 is an N-type substrate, the doping type of the collector region 101 is P-type, the doping type of the buffer layer 102 is N-type, the doping type of the first sub-drift region 103a is N-type, and the doping type of 104 is P-type.

[0071] The doping concentration of the substrate 306 is, for example, greater than the doping concentration of the buffer layer 102, and the doping concentration of the collector region 101 is, for example, greater than the doping concentration of the second sub-drift region 103b.

[0072] In step S21, ion implantation is performed on the surface of the second sub-drift region 103b away from the collector region 101 to form a carrier storage layer 105, a well region 106, and an emitter region. The emitter region includes a first emitter region 107 and a second emitter region 108, obtaining a semiconductor structure as shown in Figure 9 the figure. And high-temperature annealing is used to activate the implanted impurity ions.

[0073] Exemplarily, a hard mask layer is formed on the side of the second sub-drift region 103b away from the collector region 101, and the hard mask layer is patterned. Ion implantation is performed on the surface of the second sub-drift region 103b away from the collector region 101 by using an ion implantation process to form a carrier storage layer 105 with an N-type doping type, a well region 106 with a P-type doping type, and an emitter region. The emitter region includes a first emitter region 107 and a second emitter region 108. The first emitter region 107 includes a first sub-emitter region 107a with a P-type doping type and a second sub-emitter region 107b with an N-type doping type. The second emitter region 108 includes a third sub-emitter region 108a with an N-type doping type and a fourth sub-emitter region 108b with a P-type doping type.

[0074] Among them, the carrier storage layer 105 includes a first sub-carrier storage layer 105a and a second sub-carrier storage layer 105b. The first sub-carrier storage layer 105a is located between the first emitter region 107 and the second sub-drift region 103b, and the second sub-carrier storage layer 105b is located between the second emitter region 108 and the second sub-drift region 103b. Parts of the first sub-carrier storage layer 105a and the second sub-carrier storage layer 105b both extend in the direction close to the second sub-drift region 103b away from the collector region 101. When forming the carrier storage layer 105, there is a certain interval between the first sub-carrier storage layer 105a and the second sub-carrier storage layer 105b in the first direction x.

[0075] The well region 106 includes a first well region 106a and a second well region 106b. The first well region 106a is located between the first emitter region 107 and the first sub-carrier storage layer 105a, and the second well region 106b is located between the first emitter region 107 and the second sub-carrier storage layer 105b. Parts of the first well region 106a and the second well region 106b both extend in the direction close to the second sub-drift region 103b away from the collector region 101.

[0076] In some feasible embodiments, step S21 can be replaced by step S22.

[0077] In step S22, ion implantation is performed on the surface of the second sub-drift region 103b away from the collector region 101 to form a carrier storage layer 105, a well region 106, and an emitter region. The emitter region includes a first emitter region 107 and a second emitter region 108, obtaining a semiconductor structure as shown inFigure 9 The semiconductor structure shown.

[0078] Exemplarily, a hard mask layer is formed on the side of the second sub-drift region 103b away from the collector region 101, the hard mask layer is patterned, and ion implantation is performed on the surface of the second sub-drift region 103b away from the collector region 101 by an ion implantation process to form a carrier storage layer 105 with an N-type doping type, a well region 106 with a P-type doping type, and an emitter region. The emitter region includes a first emitter region 107 and a second emitter region 108. The first emitter region 107 includes a first sub-emitter region 107a with a P-type doping type and a second sub-emitter region 107b with an N-type doping type. The second emitter region 108 includes a third sub-emitter region 108a with an N-type doping type and a fourth sub-emitter region 108b with a P-type doping type.

[0079] Among them, the carrier storage layer 105 includes a first sub-carrier storage layer 105a and a second sub-carrier storage layer 105b. The first sub-carrier storage layer 105a is located between the first emitter region 107 and the second sub-drift region 103b. The second sub-carrier storage layer 105b is located between the second emitter region 108 and the second sub-drift region 103b. Parts of the first sub-carrier storage layer 105a and the second sub-carrier storage layer 105b both extend in the direction close to the side of the second sub-drift region 103b away from the collector region 101. When forming the carrier storage layer 105, the first sub-carrier storage layer 105a and the second sub-carrier storage layer 105b are connected in the first direction x, that is, the first sub-carrier storage layer 105a and the second sub-carrier storage layer 105b can be regarded as a whole. The structure of the carrier storage layer 105 is as Figure 5 shown.

[0080] The well region 106 includes a first well region 106a and a second well region 106b. The first well region 106a is located between the first emitter region 107 and the first sub-carrier storage layer 105a. The second well region 106b is located between the first emitter region 107 and the second sub-carrier storage layer 105b. Parts of the first well region 106a and the second well region 106b both extend in the direction close to the side of the second sub-drift region 103b away from the collector region 101.

[0081] In step S31, an initial gate dielectric layer 303a and a gate region conductor layer 302a are sequentially formed on the side of the second sub-drift region 103b away from the collector region 101 to obtain a semiconductor structure as Figure 10 shown.

[0082] In step S32, the gate region conductor layer 302a is etched to form a gate region 302 to obtain a semiconductor structure as Figure 11 shown. Exemplarily, in step S32, over-etching is performed until the initial gate dielectric layer 303a.

[0083] In step S33, an initial isolation dielectric layer 304a is formed on a side of the second sub-drift region 103b away from the collector region 101. The initial isolation dielectric layer 304a covers at least a surface of the gate region 302 away from the collector region 101, obtaining a semiconductor structure as shown in Figure 12 . Exemplarily, the initial isolation dielectric layer 304a is formed by a CVD (Chemical Vapor Deposition) process.

[0084] In step S34, the initial isolation dielectric layer 304a and the initial gate dielectric layer 303a are etched to form a gate dielectric layer 303 and an isolation dielectric layer 304. At least a surface of a part of the first emitter region 107 away from the collector region 101 and a surface of a part of the second emitter region 108 away from the collector region 101 are exposed to form a source contact region, and at least a surface of a part of the gate region 302 away from the collector region 101 is exposed to form a gate region contact region (not shown in the figure), obtaining a semiconductor structure as shown in Figure 13 . Exemplarily, selective dry etching is used to form the source contact region and the gate region contact region. In some feasible embodiments, the source contact region and the gate region contact region may be contact holes penetrating the initial gate dielectric layer 303a and the initial isolation dielectric layer 304a.

[0085] In step S41, a second metal layer 305 is formed on a side of the second sub-drift region 103b away from the collector region 101, obtaining a semiconductor structure as shown in Figure 14 . The second metal layer 305 covers at least a surface of the isolation dielectric layer 304 away from the collector region 101. Exemplarily, processes such as sputtering are used to fill the source contact region and the gate region contact region, and cover the surface of the isolation dielectric layer 304 away from the collector region 101 to form the second metal layer 305.

[0086] In step S42, the substrate 306 is thinned until the collector region 101 is exposed, obtaining a semiconductor structure as shown in Figure 15 . Exemplarily, a back thinning process is used to remove the substrate 306 until a surface of the collector region 101 away from the buffer layer 102 is exposed. In some feasible embodiments, the collector region 101 may also be over-etched.

[0087] In step S43, a first metal layer 301 is formed on a side of the collector region 101 away from the buffer layer 102, obtaining the semiconductor device 100 as shown in Figure 4 . Exemplarily, the first metal layer 301 is formed by sputtering on a side of the collector region 101 away from the drift region 103.

[0088] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims described above.

Claims

1. A semiconductor device, characterized in that, Comprising: Collector region; Drift region, disposed above the collector region; Emitter region, disposed on a side of the drift region away from the collector region; Gate region, disposed on a side of the drift region away from the collector region; a projection of the gate region on a first reference plane does not overlap with a projection of the drift region on the first reference plane, and the first reference plane is parallel to a thickness direction of the drift region; The drift region includes a first sub-drift region and a second sub-drift region which are stacked, the second sub-drift region is located on a side of the first sub-drift region away from the collector region, and doping types of the first sub-drift region and the second sub-drift region are different.

2. The semiconductor device according to claim 1, wherein Further comprising: Carrier storage layer, the carrier storage layer is located between the second sub-drift region and the emitter region, and doping types of the carrier storage layer and the second sub-drift region are different.

3. The semiconductor device according to claim 2, wherein The emitter region includes a first emitter region and a second emitter region respectively located on two sides of the gate region, and an arrangement direction of the first emitter region and the second emitter region is a first direction; The carrier storage layer includes: First sub-carrier storage layer, located between the first emitter region and the second sub-drift region; Second sub-carrier storage layer, located between the second emitter region and the second sub-drift region.

4. The semiconductor device according to claim 3, wherein, Along the first direction, there is a gap between the first sub-carrier storage layer and the second sub-carrier storage layer; A part of the second sub-drift region is located within the gap.

5. The semiconductor device according to claim 4, wherein The semiconductor device further includes a gate dielectric layer located below the gate region; The part of the second sub-drift region located within the gap is in contact with the gate dielectric layer.

6. The semiconductor device according to claim 3, characterized in that, Along the first direction, the first sub-carrier storage layer and the second sub-carrier storage layer are connected; The second sub-drift region is located below the first sub-carrier storage layer and the second sub-carrier storage layer.

7. The semiconductor device according to any one of claims 3 to 6, characterized in that, The semiconductor device further includes a gate dielectric layer located below the gate region; Parts of the first sub-carrier storage layer and the second sub-carrier storage layer both extend towards the gate region and are in contact with the gate dielectric layer.

8. The semiconductor device according to claim 3, wherein The first emitter region includes a first sub-emitter region and a second sub-emitter region with different doping types, the first sub-emitter region and the second sub-emitter region are arranged along the first direction, and compared with the second sub-emitter region, the first sub-emitter region is away from the gate region; The second emitter region includes a third sub-emitter region and a fourth sub-emitter region with different doping types, the third sub-emitter region and the fourth sub-emitter region are arranged along the first direction, and compared with the third sub-emitter region, the fourth sub-emitter region is away from the gate region.

9. The semiconductor device according to claim 7, wherein, Further comprising: First well region, the first well region is located between the first emitter region and the first sub-carrier storage layer; Second well region, the second well region is located between the second emitter region and the second sub-carrier storage layer; Parts of the first well region and the second well region both extend towards the gate region and are in contact with the gate dielectric layer.

10. The semiconductor device according to any one of claims 1-6, characterized in that, Further comprising: First metal layer, located on a side of the collector region away from the drift region; A second metal layer, located on a side of the drift region away from the collector region and in ohmic contact with the emitter region; An isolation dielectric layer, which is located between the second metal layer and the conductor in the gate region.

11. A method for manufacturing a semiconductor device, characterized in that, Comprising: A collector region, a first sub-drift region, and a second sub-drift region are sequentially formed and stacked, and the doping types of the first sub-drift region and the second sub-drift region are different; Ion implantation is performed on a surface of the second sub-drift region away from the collector region to form an emitter region; A gate region is formed on a side of the second sub-drift region away from the collector region; A projection of the gate region on a first reference plane does not overlap with a projection of the drift region on the first reference plane, and the first reference plane is parallel to a thickness direction of the second sub-drift region.

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