A high-reliability planar gate silicon carbide VDMOS and its preparation method

Abstract

The present invention provides a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof. The method comprises: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; performing epitaxial growth on the side of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, and ion implanting to form a P-type first region, a P-type second region, a P-type well region, a gate protection region, a protrusion, and an N-type source region; reforming the barrier layer, etching to obtain a first P-type source region, a second P-type source region, and a groove, and depositing to form a Schottky metal layer, a first protrusion, a second protrusion, a gate metal layer, and an insulating dielectric layer; and depositing metal to form a source metal layer to improve the reliability of the device drain when it withstands voltage.

Description

Technical Field

[0001] The invention relates to a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally have the characteristics of low gate charge and high switching speed compared to silicon VDMOS devices. However, due to the characteristics of silicon carbide materials, there are two problems. First, the quality of its insulating dielectric silicon dioxide is relatively low, which affects the gate reliability of the device. Second, its gate reliability can only be guaranteed when the insulating dielectric is thicker, but the gate control capability is reduced. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, so as to improve the reliability of the device drain when it withstands voltage.

[0004] In a first aspect, the present invention provides a method for preparing a high-reliability planar gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; and epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type first region;

[0007] Step 3: remove the barrier layer in step 2, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type second region;

[0008] Step 4: remove the barrier layer of step 3, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type well region, a gate protection region, and a raised portion respectively;

[0009] Step 5: remove the barrier layer of step 4, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form an N-type source region;

[0010] Step 6: removing the barrier layer of step 5, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the P-type first region and the drift layer to obtain a first P-type source region, a second P-type source region and a groove, and depositing a Schottky metal layer;

[0011] Step 7: removing the barrier layer of step 6, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a first insulating layer;

[0012] Step 8, removing the barrier layer of step 7, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a first protrusion and a second protrusion;

[0013] Step 9: removing the barrier layer of step 8, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing a second insulating layer;

[0014] Step 10: removing the barrier layer of step 9, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a gate metal layer;

[0015] Step 11: removing the barrier layer of step 10, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing a third insulating layer, wherein the insulating dielectric layer includes a first insulating layer, a second insulating layer, and a third insulating layer;

[0016] Step 12: remove the barrier layer of step 11, deposit metal, and form a source metal layer.

[0017] In a second aspect, the present invention provides a high-reliability planar gate silicon carbide VDMOS, which is prepared by the method for preparing a high-reliability planar gate silicon carbide VDMOS according to the first aspect.

[0018] The advantages of the present invention are:

[0019] First, the present invention constructs a structure in which the second P-type source region wraps the P-type well region, and the P-type well region wraps the N-type source region. When the drain is subjected to a large voltage, the electric field strength near the gate and source of the device can be gradually reduced, thereby improving the reliability of the device.

[0020] Second, the present invention constructs a first protrusion and a second protrusion, which are equal in width to the P-type well region between the N-type source region and the protrusion below, thereby achieving good gate control capability. A thick insulating dielectric is provided below the gate metal layer, thereby improving device gate reliability. A P-type gate protection region is provided below the gate metal layer, which has the same doping concentration and thickness as the P-type well region, thereby improving device gate reliability when the device drain is subjected to a large voltage.

[0021] 3. An insulating dielectric is covered on top of the device's gate metal layer, and a source metal layer is covered on top of the insulating dielectric, which can improve the device's ability to withstand external impacts.

[0022] Fourth, an alternating structure of the first P-type source region, the Schottky metal layer, and the second P-type source region is constructed in the body diode area of ​​the device. The Schottky diode and the parasitic pn junction diode jointly freewheel, and the freewheeling capability and conduction loss of the body diode are reduced. The depth of the device's Schottky diode must be greater than the thickness of the first P-type source region. This is to increase the contact surface of the Schottky diode, improve the freewheeling capability of the Schottky diode, and improve the low conduction loss of the body diode while ensuring the device's voltage resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Figure 1 This is a schematic diagram of a high-reliability planar gate silicon carbide VDMOS according to the present invention.

[0025] Figure 2 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 1 .

[0026] Figure 3 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 2 .

[0027] Figure 4 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 3 .

[0028] Figure 5 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 4 .

[0029] Figure 6 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 5 .

[0030] Figure 7 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 6 .

[0031] Figure 8 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 7 .

[0032] Figure 9 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 8 .

[0033] Figure 10 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 9 .

[0034] Figure 11 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 10 .

[0035] Figure 12 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 10 one.

[0036] Figure 13 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 10 two.

[0037] Figure 14 This is a cross-sectional view of the process of a high-reliability planar gate silicon carbide VDMOS of the present invention. Figure 10 three. DETAILED DESCRIPTION

[0038] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0040] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0041] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0042] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] like Figures 1 to 14 As shown, the embodiment of the present application provides a method for preparing a high-reliability planar gate silicon carbide VDMOS, comprising the following steps:

[0044] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9; epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0045] Step 2: forming a barrier layer 100 on the drift layer 2, etching the barrier layer 100 to form a through hole, and implanting ions to form a P-type first region 200;

[0046] Step 3: removing the barrier layer 100 in step 2, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form the P-type second region 300;

[0047] Step 4: removing the barrier layer 100 in step 3, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form a P-type well region 51, a gate protection region 211, and a protrusion 21;

[0048] Step 5: removing the barrier layer 100 in step 4, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form an N-type source region 511;

[0049] Step 6: remove the barrier layer 100 of step 5, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, and etch the P-type first region 200 and the drift layer 2 to obtain the first P-type source region 3, the second P-type source region 5 and the groove 22, and deposit to form a Schottky metal layer 4;

[0050] Step 7: removing the barrier layer 100 in step 6, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and depositing to form a first insulating layer 62;

[0051] Step 8: remove the barrier layer 100 in step 7, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, deposit metal to form the first protrusion 71 and the second protrusion 72;

[0052] Step 9: removing the barrier layer 100 in step 8, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and depositing a second insulating layer 63;

[0053] Step 10: removing the barrier layer 100 of step 9, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and depositing metal to form a gate metal layer 7;

[0054] Step 11: remove the barrier layer 100 in step 10, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, and deposit a third insulating layer 64. The insulating dielectric layer 6 includes a first insulating layer 62, a second insulating layer 63, and a third insulating layer 64.

[0055] Step 12: remove the barrier layer 100 of step 11, and deposit metal to form a source metal layer 8.

[0056] In this embodiment, preferably, a first protrusion 71 and a second protrusion 72 are provided at the lower portion of the gate metal layer 7; the first protrusion 71 and the second protrusion 72 are located directly above the P-type well region 51 between the protrusion 21 and the N-type source region 511, and the width of the first protrusion 71 is equal to the width of the second protrusion 72, and the width of the first protrusion 71 is equal to the distance between the protrusion 21 and the N-type source region 511.

[0057] In this embodiment, preferably, the doping concentration of the first P-type source region 3 is greater than the doping concentration of the drift layer 2; the doping concentration of the second P-type source region 5 is greater than the doping concentration of the P-type well region 51; and the doping concentration of the first P-type source region 3 is equal to the doping concentration of the second P-type source region 5.

[0058] In this embodiment, preferably, the doping concentration of the P-type well region 51 is lower than the doping concentration of the N-type source region 511 .

[0059] In this embodiment, preferably, the thickness of the gate protection region 211 is equal to the thickness of the P-type well region 51 .

[0060] like Figure 1 As shown, the planar gate silicon carbide VDMOS obtained by the above manufacturing method includes:

[0061] Silicon carbide substrate 1;

[0062] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a protrusion 21 and a groove 22 are provided on the drift layer 2; a gate protection area 211 is provided on the protrusion 21;

[0063] a first P-type source region 3 , wherein the lower side of the first P-type source region 3 is connected to the upper side of the drift layer 2 ;

[0064] a Schottky metal layer 4 , wherein a lower portion of the Schottky metal layer 4 is disposed in the groove 22 , and an inner side surface of the first P-type source region 3 is connected to an outer side surface of the Schottky metal layer 4 ;

[0065] a second P-type source region 5, wherein the lower side of the second P-type source region 5 is connected to the upper side of the drift layer 2, the outer side of the second P-type source region 5 is connected to the inner side of the Schottky metal layer 4, a P-type well region 51 is provided on the second P-type source region 5, an N-type source region 511 is provided on the P-type well region 51, and the inner side of the second P-type source region 5 and the inner side of the P-type well region 51 are both connected to the outer side of the protrusion 21;

[0066] an insulating dielectric layer 6, wherein the lower side of the insulating dielectric layer 6 is respectively connected to the upper side of the N-type source region 511, the upper side of the P-type well region 51, the upper side of the protrusion 21, and the upper side of the gate protection region 211; and a hollow groove 61 is provided in the insulating dielectric layer 6;

[0067] a gate metal layer 7, the gate metal layer 7 being disposed in the hollow groove 61;

[0068] a source metal layer 8 , wherein the source metal layer 8 is respectively connected to the first P-type source region 3 , the Schottky metal layer 4 , the second P-type source region 5 , the P-type well region 51 , and the N-type source region 511 ;

[0069] and a drain metal layer 9 , wherein the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1 .

[0070] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 6-10e16cm -3 , the doping concentration of the P-type well region 51 is 1-5e15cm -3The doping concentration of the first P-type source region 3 and the second P-type source region 5 is 1-5e19cm -3 The material of the insulating dielectric layer 6 can be silicon dioxide, and the doping concentration of the N-type source region 511 is 2-8e18cm -3 The doping concentration of the N-type silicon carbide substrate 1 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 9, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the first P-type source region 3 is to reduce the contact resistance between the first P-type source region 3 and the source metal layer 8, thereby reducing the conduction loss of the parasitic pn junction diode of the device; the doping concentration of the second P-type source region 5 is to reduce the diffusion speed of the space charge region when diffusing to the gate and source of the device when the drain voltage is high; the doping concentration of the P-type well region 51 is to reduce the gate-controlled charge of the device gate, thereby increasing the switching speed of the device, and forming a buffer zone between the second P-type source region 5 and the N-type source region 511, thereby reducing the electric field strength near the N-type source region 511 and improving the reliability of the device near the N-type source region 511;

[0071] The thickness of the N-type silicon carbide substrate 1 of the device is 1μm, and the thickness of the N-type drift layer 2 is 50-100μm, which is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device. The thickness of the insulating medium under the first protrusion 71 and the second protrusion 72 is 50nm, which is to ensure the gate control capability of the device. The thickness of the insulating medium under the gate metal layer 7 is 200nm, which is to ensure the reliability of the middle area of ​​the device gate, while reducing the gate-drain capacitance of the device and improving the switching speed of the device; the width of the insulating medium on the left and right sides of the gate metal layer 7 is 500nm, which is to achieve isolation from the source metal layer 8, and its width does not affect the device characteristics. The maximum thickness of the first P-type source region 3 and the second P-type source region 5 is 600nm, the thickness of the N-type source region 511 is 150nm, and the P-type well region 5 is 100nm. 1 has a maximum thickness of 300nm, and the thickness of the Schottky metal layer 4 is 800nm. This is to improve the Schottky metal contact surface, improve the freewheeling capability of the Schottky diode, and reduce the freewheeling loss of the body diode. The width of the first protrusion 71 and the second protrusion 72 are both 500nm, and the thickness is both 250nm. The width of the gate metal layer 7 is 3μm, and the thickness of the middle of the gate metal layer 7 is 100nm. The maximum thickness of the source metal layer 8 is 600nm. The width of the Schottky metal layer 4 and the first P-type source region 3 are both 500nm. The width of the N-type source region 511 is 500nm. The width of the P-type well region inside the N-type source region 511 is 500nm. The width of the P-type gate protection region 211 is 1μm. This is to ensure the conductive channel of the device while protecting the gate metal layer 7 of the device.

[0072] The present invention constructs a structure in which the second P-type source region 5 encloses the P-type well region 51, and the P-type well region 51 encloses the N-type source region 511. When the drain is subjected to a large voltage, the electric field strength near the gate and source of the device can be gradually reduced, thereby improving the reliability of the device.

[0073] The present invention constructs a first protrusion 71 and a second protrusion 72, which are equal in width to the P-type well region 51 between the N-type source region 511 below and the protrusion 21, which can achieve good gate control capability. A thick insulating dielectric is provided below the gate metal layer 7 to improve the device gate reliability. Correspondingly, a P-type gate protection region 211 with the same doping concentration and thickness as the P-type well region 51 is provided below it, which can improve the device gate reliability when the device drain is subjected to a large voltage.

[0074] The top of the gate metal layer 7 of the device is covered with an insulating dielectric, and the top of the insulating dielectric is covered with a source metal layer 8, which can improve the ability of the top of the device to withstand external impact;

[0075] In the body diode area of ​​the device, an interlaced structure of the first P-type source region 3, the Schottky metal layer 4, and the second P-type source region 5 is constructed. The Schottky diode and the parasitic pn junction diode jointly freewheel, and the freewheeling capability and conduction loss of the body diode are reduced. The depth of the Schottky diode of the device is greater than the thickness of the first P-type source region 3. This is to increase the contact surface of the Schottky diode, improve the freewheeling capability of the Schottky diode, and improve the low conduction loss of the body diode while ensuring the voltage resistance of the device.

[0076] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a high-reliability planar gate silicon carbide VDMOS, characterized by: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type first region; Step 3: Ion implantation to form a P-type second region; Step 4: ion implantation to form a P-type well region, a gate protection region, and a raised portion; Step 5: Ion implantation to form an N-type source region; Step 6: Etching the P-type first region and the drift layer to obtain a first P-type source region, a second P-type source region, and a groove between the first P-type source region and the second P-type source region; depositing a Schottky metal layer in the groove; the second P-type source region wraps the P-type well region, and the P-type well region wraps the N-type source region; Step 7: depositing to form a first insulating layer; Step 8: depositing metal to form a first protrusion and a second protrusion; Step 9: depositing a second insulating layer; Step 10: depositing metal to form a gate metal layer; Step 11: depositing a third insulating layer, wherein the insulating dielectric layer includes a first insulating layer, a second insulating layer and a third insulating layer; Step 12: removing the barrier layer of step 11 and depositing metal to form a source metal layer; Before ion implantation in steps 3-5, before etching the P-type first region and the drift layer in step 6, and before deposition in steps 7-11, it is necessary to remove the barrier layer from the previous step, re-form the barrier layer, and etch the barrier layer to form a through hole; A first protrusion and a second protrusion are provided at the lower portion of the gate metal layer; the first protrusion and the second protrusion are located directly above the P-type well region between the protrusion and the N-type source region, the width of the first protrusion is equal to the width of the second protrusion, and the width of the first protrusion is equal to the distance between the protrusion and the N-type source region.

2. The method for preparing a high-reliability planar gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the first P-type source region is greater than the doping concentration of the drift layer; the doping concentration of the second P-type source region is greater than the doping concentration of the P-type well region; and the doping concentration of the first P-type source region is equal to the doping concentration of the second P-type source region.

3. The method for preparing a high-reliability planar gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the P-type well region is lower than the doping concentration of the N-type source region.

4. The method for preparing a high-reliability planar gate silicon carbide VDMOS according to claim 1, wherein: The thickness of the gate protection region is equal to the thickness of the P-type well region.

5. A high-reliability planar gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 4.

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