Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors, and the method comprises the steps: providing a substrate, carrying out the doping of the substrate, forming a channel doped region, forming a gate structure on the channel doped region, and forming an offset side wall surrounding the gate structure, and removing the substrate which is not covered by the gate structure and the offset side wall in the channel doping region and the substrate which is located at the bottom of the offset side wall, and forming a semiconductor layer in the region where the substrate is removed, so that the semiconductor layer is not doped or the doping concentration of the semiconductor layer is smaller than that of the channel doping region, and therefore, the semiconductor layer is not doped or the doping concentration of the semiconductor layer is smaller than that of the channel doping region. The gate-induced drain leakage current of a semiconductor device such as an MOS transistor can be reduced, and the reliability of the semiconductor device such as the MOS transistor can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As the size of Metal Oxide Semiconductor (MOS) transistors becomes smaller and smaller, the thickness of their gate oxide layers becomes thinner and thinner, resulting in an increasing Gate-induced Drain Leakage (GIDL) caused by the band-to-band tunneling of electrons in the substrate in the region near the interface of the gate-drain overlap region between the valence band and the conduction band, and leading to poorer reliability. Summary of the Invention

[0003] The present invention discloses a semiconductor device and a manufacturing method thereof to solve the problem of poor reliability of semiconductor devices caused by relatively large gate-induced drain leakage current.

[0004] In a first aspect, the present invention discloses a manufacturing method of a semiconductor device, including: providing a substrate; doping the substrate to form a channel doping region, and forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping region; removing the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall, and the substrate at the bottom of the offset sidewall; forming a semiconductor layer in the region where the substrate is removed, the material of the semiconductor layer being the same as that of the substrate, and the semiconductor layer being undoped or having a doping concentration lower than that of the channel doping region.

[0005] In some embodiments of the present invention, the substrate includes a first region, a second region, and a shallow trench isolation structure located between the first region and the second region. The first region is at least used to form PMOS transistors, and the second region is at least used to form NMOS transistors. Doping the substrate to form a channel doping region, and forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping region includes: doping the substrates of the first region and the second region in sequence to form a channel doping region; synchronously forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping regions of the first region and the second region; Removing the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate located at the bottom of the offset sidewall includes: synchronously removing the substrate in the channel doping regions of the first region and the second region that is not covered by the gate structure and the offset sidewall and the substrate located at the bottom of the offset sidewall; Forming a semiconductor layer in the region where the substrate is removed includes: synchronously forming a semiconductor layer in the regions where the substrate is removed in the first region and the second region, and the semiconductor layer is undoped.

[0006] In some embodiments of the present invention, removing the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate located at the bottom of the offset sidewall includes: removing a part of the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall; removing the remaining substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate located at the bottom of the offset sidewall.

[0007] In some embodiments of the present invention, removing a part of the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall includes: anisotropically etching the part of the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall; removing the remaining substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate located at the bottom of the offset sidewall includes: isotropically etching the remaining substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate located at the bottom of the offset sidewall.

[0008] In some embodiments of the present invention, the thickness of the part of the substrate is greater than or equal to the difference between the thickness of the channel doping region and the thickness of the offset sidewall; the thickness of the remaining substrate is equal to the thickness of the offset sidewall.

[0009] In some embodiments of the present invention, the doping of the substrate to form the channel doping region includes: forming a mask layer on the substrate that exposes the entire active region; using the mask layer as a mask to dope the active region of the substrate to form the channel doping region; the channel doping region includes a first channel doping region and a second channel doping region, the first channel doping region and the second channel doping region are a bilayer structure, the doping concentration of the first channel doping region is greater than that of the second channel doping region, and the doping ions of the first channel doping region include fluoride ions.

[0010] In some embodiments of the present invention, it further includes: doping the semiconductor layers on both sides of the gate structure to form lightly doped drain regions, pocket doping regions, source regions, and drain regions.

[0011] In some embodiments of the present invention, the upper surface of the semiconductor layer is flush with the upper surface of the substrate; the thickness of the semiconductor layer is greater than or equal to the thickness of the channel doping region.

[0012] In some embodiments of the present invention, the semiconductor layer includes a single crystal silicon layer.

[0013] In a second aspect, the present invention discloses a semiconductor device, which is fabricated by using the fabrication method of the semiconductor device described in any one of the above.

[0014] The present invention discloses a semiconductor device and its manufacturing method, which provides a substrate, dopes the substrate to form a channel doping region, forms a gate structure and an offset sidewall surrounding the gate structure on the channel doping region, removes the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate at the bottom of the offset sidewall, and forms a semiconductor layer in the region where the substrate is removed. The material of the semiconductor layer is the same as that of the substrate. Because the semiconductor layer is undoped or the doping concentration of the semiconductor layer is less than that of the channel doping region, the doping concentration of the substrate in the region where the semiconductor layer is located, that is, the region near the interface of the gate-drain overlap region, can be reduced. Furthermore, the impurity state energy level of the electrons in the substrate in this region between the valence band and the conduction band can be reduced, and further the occurrence probability of band-to-band tunneling can be reduced. Furthermore, the gate-induced drain leakage current of a semiconductor device such as a MOS transistor can be reduced, and the reliability of a semiconductor device such as a MOS transistor can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the following will describe the drawings required to be used in the embodiments of the present invention or the background art.

[0016] Figure 1 It is a flowchart of a manufacturing method of a semiconductor device disclosed in an embodiment of the present invention.

[0017] Figures 2 to 9 Schematic cross-sectional structures of a semiconductor device in various manufacturing steps disclosed in an embodiment of the present invention.

[0018] Figures 10 to 17 Schematic cross-sectional structures of another semiconductor device in various manufacturing steps disclosed in an embodiment of the present invention. Detailed implementation manners

[0019] Next, the technical solutions in the embodiments of the present invention will be described with reference to the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0020] As described in the background art, the gate-induced drain leakage current of current MOS transistors is relatively large, resulting in poor reliability of the MOS transistors. Among them, the gate-induced drain leakage current is caused by the band-to-band tunneling of electrons in the substrate near the interface of the gate-drain overlap region between the valence band and the conduction band.

[0021] The inventors have found through research that in the manufacturing process of conventional MOS transistors, channel doping ions are usually implanted into the entire active region of the MOS transistor to form a channel doping region. However, this will increase the impurity state energy levels in the bandgap between the valence band and the conduction band of electrons in the substrate near the interface of the gate-drain overlap region, thereby increasing the probability of band-to-band tunneling, and further resulting in a relatively large gate-induced drain leakage current of the MOS transistor, leading to poor reliability of the MOS transistor.

[0022] Based on this, the present invention discloses a manufacturing solution for a semiconductor device such as a MOS transistor. By removing the substrate that is not covered by the gate structure and the offset sidewall and the substrate at the bottom of the offset sidewall in the channel doping region, and forming an undoped or lightly doped semiconductor layer in the region where the substrate is removed, the doping concentration of the substrate in the region where the semiconductor layer is located, that is, near the interface of the gate-drain overlap region, is reduced, so as to reduce the impurity state energy levels of electrons in the substrate in this region between the valence band and the conduction band, reduce the probability of band-to-band tunneling, reduce the gate-induced drain leakage current, and improve the reliability of the semiconductor device.

[0023] As an optional implementation of the disclosed content of the present invention, an embodiment of the present invention discloses a manufacturing method for a semiconductor device, such as Figure 1 shown, the manufacturing method includes: S101: Provide a substrate.

[0024] In the embodiments of the present invention, the semiconductor device includes NMOS transistors and / or PMOS transistors, etc. In some embodiments of the present invention, taking the semiconductor device including NMOS transistors or PMOS transistors as an example for illustration, such asFigure 2 As shown, first, a substrate 10 is provided. The substrate 10 has a plurality of shallow trench isolation structures 101 arranged at intervals. Among them, the material of the substrate 10 can be any material suitable for forming semiconductor devices, such as silicon carbide, gallium nitride, aluminum nitride, indium nitride, indium phosphide, gallium arsenide, silicon germanium, sapphire or silicon wafer, etc.; the shallow trench isolation structure 101 is a shallow trench structure filled with insulating materials such as silicon oxide.

[0025] Of course, the present invention is not limited to this. In some other embodiments, the substrate 10 may not have the shallow trench isolation structure 101. It should be noted that if the semiconductor device includes a plurality of transistors, the substrate 10 requires the shallow trench isolation structure 101 to achieve isolation between transistors. However, if the semiconductor device includes only one transistor, the substrate 10 may not have the shallow trench isolation structure 101.

[0026] S102: Dope the substrate to form a channel doping region, and form a gate structure and an offset sidewall surrounding the gate structure on the channel doping region.

[0027] In some embodiments of the present invention, as Figure 3 shown, first, a mask layer 100 exposing the entire active region is formed on the substrate 10 by using a photomask with a preset pattern. The mask layer 100 includes a photoresist layer. Then, using the mask layer 100 as a mask, the substrate 10 of the entire active region is sequentially subjected to well doping and channel doping to form a well region 102 and a channel doping region 103 as Figure 4 shown. Among them, well doping and channel doping can share one photomask or mask. Then, a gate structure layer is formed on the substrate 10, and the gate structure layer is anisotropically etched to form a gate structure 20 as Figure 5 shown. The gate structure 20 may include a gate dielectric layer 201, a gate layer 202, a covering layer 203, etc. Then, an offset sidewall layer is formed on the substrate 10, and the offset sidewall layer is anisotropically etched to form an offset sidewall 30 as Figure 6 shown.

[0028] Of course, the present invention is not limited to this. In some other embodiments, the substrate 10 of the entire active region may not be doped to form the channel doping region 103. That is to say, as long as the offset sidewall 30 covers the channel doping region 103, the subsequent steps of the embodiments of the present invention can be used to fabricate the semiconductor device.

[0029] Among them, the material of the gate dielectric layer 201 can be one or several of silicon oxide, silicon oxynitride, hafnium oxide, hafnium oxynitride, zirconium oxide, zirconium oxynitride, zirconium oxynitridosilicate, hafnium silicate, hafnium oxynitridosilicate, lanthanum oxyhafnium nitride or hafnium aluminum oxide, etc.; the material of the gate layer 202 can be polysilicon, etc.; the material of the capping layer 203 can be silicon oxynitride or silicon carbide, etc.; the offset sidewall 30 can be a stacked structure composed of silicon oxide and silicon nitride.

[0030] S103: Remove the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall, and the substrate located at the bottom of the offset sidewall.

[0031] In some embodiments of the present invention, such as Figure 7 shown, first remove the partial substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30, and then, as Figure 8 shown, remove the remaining substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30, and the substrate 10 located at the bottom of the offset sidewall 30.

[0032] On this basis, in some embodiments of the present invention, the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 can be anisotropically etched first to remove the partial substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30, and then the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 and the substrate 10 located at the bottom of the offset sidewall 30 are isotropically etched to remove the remaining substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 and the substrate 10 located at the bottom of the offset sidewall 30.

[0033] Of course, the present invention is not limited thereto. In other embodiments, the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 and the substrate 10 located at the bottom of the offset sidewall 30 can be isotropically etched first, and then the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 can be anisotropically etched. Other methods can also be used to remove the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 and the substrate 10 located at the bottom of the offset sidewall 30, which will not be elaborated here.

[0034] It should be noted that, as Figure 8As shown, after removing the substrate 10 within the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30, and the substrate 10 located at the bottom of the offset sidewall 30, a groove 104 is formed on the substrate 10. Moreover, the inner sidewall of the groove 104 is flush with the outer sidewall of the gate structure 20, so as to minimize the doping concentration in the region near the interface of the gate-drain overlap region on the basis of ensuring the performance of the semiconductor device. Among them, the region of the substrate within the channel doping region that is not covered by the gate structure and the offset sidewall and the region of the substrate located at the bottom of the offset sidewall include the region near the interface of the gate-drain overlap region.

[0035] In some embodiments of the present invention, as Figure 7 shown, the thickness D1 of the removed part of the substrate 10 is equal to the difference between the thickness D of the channel doping region 103 and the thickness D2 of the offset sidewall 30. As Figure 7 and Figure 8 shown, the thickness of the remaining substrate 10 after removal is equal to the thickness D2 of the offset sidewall 30. At this time, the depth of the groove 104 is equal to the thickness D of the channel doping region 103.

[0036] Of course, the present invention is not limited thereto. In some other embodiments, the thickness D1 of the removed part of the substrate 10 may also be greater than the difference between the thickness D of the channel doping region 103 and the thickness D2 of the offset sidewall 30, and the depth of the groove 104 may also be greater than the thickness D of the channel doping region 103.

[0037] S104: Form a semiconductor layer in the region where the substrate is removed. The material of the semiconductor layer is the same as that of the substrate. The semiconductor layer is undoped or the doping concentration of the semiconductor layer is less than the doping concentration of the channel doping region.

[0038] In some embodiments of the present invention, as Figure 9 shown, a semiconductor layer 40 is formed in the region where the substrate 10 is removed, that is, the semiconductor layer 40 is formed in the groove 104. For example, a selective epitaxial growth process can be used to epitaxially grow the semiconductor layer 40 in the region where the substrate 10 is removed, that is, in the groove 104.

[0039] Among them, the material of the semiconductor layer 40 is the same as that of the substrate 10. For example, the materials of both the semiconductor layer 40 and the substrate 10 are silicon or silicon germanium, etc. In some embodiments of the present invention, the substrate 10 is a silicon substrate and the semiconductor layer 40 is a single-crystalline silicon layer. Since NMOS transistors etc. need to apply tensile stress rather than compressive stress in the channel, making the material of the semiconductor layer 40 the same as that of the substrate 10 can avoid the semiconductor layer 40 applying compressive stress to the channel and affecting the performance of NMOS transistors etc.

[0040] Moreover, the semiconductor layer 40 is undoped or the doping concentration of the semiconductor layer 40 is less than that of the channel doping region 103. For example, in the case where the semiconductor device includes only PMOS transistors, the doping concentration of the semiconductor layer 40 may be less than that of the channel doping region 103. However, in the case where the semiconductor device includes NMOS transistors or includes both NMOS transistors and PMOS transistors, the semiconductor layer 40 needs to be an undoped semiconductor layer to prevent the semiconductor layer 40 from applying stress to the channel doping region 103 and affecting the performance of the NMOS transistors.

[0041] Based on this, the doping concentration of the substrate 10 in the region near the interface of the gate-drain overlap region where the semiconductor layer 40 is located can be reduced, thereby reducing the impurity state energy level of the electrons in the valence band and conduction band of the substrate 10 in this region, further reducing the occurrence probability of band-to-band tunneling, and further reducing the gate-induced drain leakage current of semiconductor devices such as MOS transistors, improving the reliability of semiconductor devices such as MOS transistors.

[0042] In some embodiments of the present invention, the upper surface of the semiconductor layer 40 is flush with the upper surface of the substrate 10, and the thickness of the semiconductor layer 40 is equal to the thickness of the channel doping region 103. For example, in the case where the depth of the groove 104 is equal to the thickness of the channel doping region 103, the formed semiconductor layer 40 has a thickness equal to that of the channel doping region 103. Of course, the present invention is not limited thereto. In some other embodiments, the thickness of the semiconductor layer 40 may also be greater than the thickness of the channel doping region 103. For example, in the case where the depth of the groove 104 is greater than the thickness of the channel doping region 103, the formed semiconductor layer 40 has a thickness greater than that of the channel doping region 103.

[0043] In some other embodiments of the present invention, taking the semiconductor device including both NMOS transistors and PMOS transistors as an example for illustration, as Figure 10 shown, first, a substrate 10 is provided, which includes a first region A1, a second region A2, and a shallow trench isolation structure 101 located between the first region A1 and the second region A2. Among them, the first region A1 is at least used to form PMOS transistors, and the second region A2 is at least used to form NMOS transistors.

[0044] Then, as Figure 11 shown, a mask layer 100 exposing the entire active region of the first region A1 is formed on the substrate 10 using a photomask with a preset pattern, and with the mask layer 100 as a mask, well doping and channel doping are sequentially performed on the entire active region of the first region A1 to form a well region 102 and a channel doping region 103 of the first region A1. Then, as Figure 12As shown, a mask layer 100 that exposes the entire active region of the second region A2 is formed on the substrate 10 using a photomask with the preset pattern. Using the mask layer 100 as a mask, well doping and channel doping are sequentially performed on the entire active region of the second region A2 to form a well region 102 and a channel doping region 103 in the second region A2. Among them, the first region A1 and the second region A2 can share one photomask, without increasing the number of photomasks.

[0045] Then, a gate structure layer is synchronously formed on the substrates 10 of the first region A1 and the second region A2, and anisotropic etching is performed on the gate structure layer to synchronously form the gate structures 20 of the first region A1 and the gate structures 20 of the second region A2 as shown in Figure 13 Then, an offset spacer layer is synchronously formed on the substrates 10 of the first region A1 and the second region A2, and anisotropic etching is performed on the offset spacer layer to synchronously form the offset spacers 30 of the first region A1 and the offset spacers 30 of the second region A2 as shown in Figure 14 Then, as shown in

[0046] Then, as shown in Figure 15 anisotropic etching is performed on the substrate 10 in the channel doping regions 103 of the first region A1 and the second region A2 that is not covered by the gate structures 20 and the offset spacers 30 to synchronously remove a part of the substrate 10 in the channel doping regions 103 of the first region A1 and the second region A2 that is not covered by the gate structures 20 and the offset spacers 30. Then, as shown in Figure 16 isotropic etching is performed on the substrate 10 in the channel doping regions 103 of the first region A1 and the second region A2 that is not covered by the gate structures 20 and the offset spacers 30 and the substrate 10 at the bottom of the offset spacers 30 to synchronously remove the remaining substrate 10 in the channel doping regions 103 of the first region A1 and the second region A2 that is not covered by the gate structures 20 and the offset spacers 30 and the substrate 10 at the bottom of the offset spacers 30.

[0047] Then, as shown in Figure 17 a semiconductor layer 40 is synchronously formed in the first region A1 and the second region A2 by removing the substrate 10. The material of the semiconductor layer 40 is the same as that of the substrate 10. For example, the materials of the semiconductor layer 40 and the substrate 10 are both silicon or silicon germanium, etc. Moreover, the semiconductor layer 40 is undoped to prevent the semiconductor layer 40 from applying stress to the channel doping region 103 and affecting the performance of the NMOS transistor.

[0048] Because the material of the semiconductor layer 40 is the same as that of the substrate 10 and the semiconductor layer 40 is undoped, the steps of epitaxial growth can be synchronously performed on the first region A1 and the second region A2, which can not only simplify the process steps and reduce the manufacturing cost, but also will not apply stress to the channel doping region 103 and affect the performance of the NMOS transistor.

[0049] It should be noted that when performing well doping on the first region A1, i.e., the PMOS transistor, the doping ions can be phosphorus ions. When performing channel doping on the first region A1, i.e., the PMOS transistor, first, fluorine ions are implanted at a certain depth from the surface of the substrate 10 to form a first channel doping region. The function of implanting fluorine ions is to inhibit the diffusion of channel doping ions, which is beneficial to forming an inverted well; then, phosphorus ions with a higher concentration are implanted into the substrate 10 to form a second channel doping region, and the implantation depth is the same as that of the fluorine ions, so that the first channel doping region and the second channel doping region form a double-layer structure, and the adjustment of the threshold voltage of the NMOS transistor is determined by the doping of this part of phosphorus ions. Among them, the doping concentration of the first channel doping region is greater than that of the second channel doping region; then, phosphorus ions with a lower concentration are implanted into the substrate 10, and the implantation depth is between the surface of the substrate 10 and above the doping region of the phosphorus ions with a higher concentration, so as to reduce the doping concentration of the surface of the channel, i.e., the surface of the substrate 10, improve the carrier mobility, and improve the performance of the semiconductor device.

[0050] When performing well doping on the second region A2, i.e., the NMOS transistor, the doping ions can be boron ions. When performing channel doping on the second region A2, i.e., the NMOS transistor, first, fluorine ions are implanted at a certain depth from the surface of the substrate 10 to form a first channel doping region. The function of implanting fluorine ions is to inhibit the diffusion of channel doping ions, which is beneficial to forming an inverted well; then, boron ions with a higher concentration are implanted into the substrate 10 to form a second channel doping region, and the implantation depth is the same as that of the fluorine ions, so that the first channel doping region and the second channel doping region form a double-layer structure, and the adjustment of the threshold voltage of the NMOS transistor is determined by the doping of this part of boron ions. Among them, the doping concentration of the first channel doping region is greater than that of the second channel doping region; then, boron ions with a lower concentration are implanted into the substrate 10, and the implantation depth is between the surface of the substrate 10 and above the doping region of the boron ions with a higher concentration, so as to reduce the doping concentration of the surface of the channel, i.e., the surface of the substrate 10, improve the carrier mobility, and improve the performance of the semiconductor device.

[0051] It should also be noted that in some embodiments of the present invention, the gate structure formed on the channel doping region is the gate structure. However, the present invention is not limited thereto. In some other embodiments, the gate structure formed on the channel doping region may also be a dummy gate structure. Based on this, after forming the semiconductor layer, it further includes doping the semiconductor layers on both sides of the dummy gate structure to form a lightly doped drain (LDD) and a pocket implantation (PKT) doping region, depositing a main sidewall film and anisotropically etching the main sidewall film to form a main sidewall structure, using a wet etching process to remove the covering layer, doping the source and drain regions of the semiconductor layers on both sides of the dummy gate structure to form a source region and a drain region, replacing the dummy gate layer with a metal gate layer, and forming source and drain electrodes, etc.

[0052] As another optional implementation of the disclosed content of the present invention, embodiments of the present invention also disclose a semiconductor device, which is fabricated by using the fabrication method disclosed in any of the above embodiments. The semiconductor device includes, but is not limited to, NMOS transistors and / or PMOS transistors.

[0053] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0054] The above embodiments only represent several implementation manners of this specification, and the description thereof is relatively specific and detailed. However, it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several modifications and improvements can still be made, and these all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a substrate; Doping the substrate to form a channel doping region, and forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping region; Removing the substrate within the channel doping region that is not covered by the gate structure and the offset sidewall, and the substrate located at the bottom of the offset sidewall; Forming a semiconductor layer in the region where the substrate is removed, the material of the semiconductor layer being the same as that of the substrate, and the semiconductor layer being undoped or having a doping concentration lower than that of the channel doping region.

2. The manufacturing method of the semiconductor device according to claim 1, wherein, The substrate includes a first region, a second region, and a shallow trench isolation structure located between the first region and the second region. The first region is at least used to form a PMOS transistor, and the second region is at least used to form an NMOS transistor; The doping the substrate to form a channel doping region, and forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping region includes: successively doping the substrates of the first region and the second region to form a channel doping region; synchronously forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping regions of the first region and the second region; The removing the substrate within the channel doping region that is not covered by the gate structure and the offset sidewall, and the substrate located at the bottom of the offset sidewall includes: synchronously removing the substrate within the channel doping regions of the first region and the second region that is not covered by the gate structure and the offset sidewall, and the substrate located at the bottom of the offset sidewall; The forming a semiconductor layer in the region where the substrate is removed includes: synchronously forming a semiconductor layer in the regions where the substrates are removed in the first region and the second region, and the semiconductor layer is undoped.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein The removing the substrate within the channel doping region that is not covered by the gate structure and the offset sidewall, and the substrate located at the bottom of the offset sidewall includes: Removing a partial substrate within the channel doping region that is not covered by the gate structure and the offset sidewall; Removing the remaining substrate within the channel doping region that is not covered by the gate structure and the offset sidewall, and the substrate located at the bottom of the offset sidewall.

4. The method for manufacturing a semiconductor device according to claim 3, wherein The removing a partial substrate within the channel doping region that is not covered by the gate structure and the offset sidewall includes: anisotropically etching the partial substrate within the channel doping region that is not covered by the gate structure and the offset sidewall; The removing the remaining substrate within the channel doping region that is not covered by the gate structure and the offset sidewall, and the substrate located at the bottom of the offset sidewall includes: isotropically etching the remaining substrate within the channel doping region that is not covered by the gate structure and the offset sidewall, and the substrate located at the bottom of the offset sidewall.

5. The manufacturing method of the semiconductor device according to claim 3, characterized in that, The thickness of the partial substrate is greater than or equal to the difference between the thickness of the channel doping region and the thickness of the offset sidewall; the thickness of the remaining substrate is equal to the thickness of the offset sidewall.

6. The manufacturing method of the semiconductor device according to claim 1, wherein The doping the substrate to form a channel doping region includes: Forming a mask layer on the substrate that exposes the entire active region; Using the mask layer as a mask, doping the substrate of the active region to form a channel doping region; The channel doping region includes a first channel doping region and a second channel doping region. The first channel doping region and the second channel doping region are of a double-layer structure. The doping concentration of the first channel doping region is greater than that of the second channel doping region. The doping ions of the first channel doping region include fluoride ions.

7. The manufacturing method of the semiconductor device according to claim 1, wherein It further includes: Doping the semiconductor layers on both sides of the gate structure to form lightly doped drain regions, pocket doping regions, source regions, and drain regions.

8. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The upper surface of the semiconductor layer is flush with the upper surface of the substrate; the thickness of the semiconductor layer is greater than or equal to the thickness of the channel doping region.

9. The method for manufacturing a semiconductor device according to claim 1, wherein, The semiconductor layer includes a single crystal silicon layer.

10. A semiconductor device, characterized in that, The semiconductor device is fabricated by using the manufacturing method of the semiconductor device according to any one of claims 1 to 9.

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