Semiconductor device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, and can greatly improve the line width effect of a first conductive layer and a second conductive layer, thereby reducing the switching delay of the semiconductor device. The semiconductor device may include a substrate, a gate, and an active region. The grid electrode and the substrate are stacked in the first direction, and the active region is located in a first substrate region of the substrate. The semiconductor device may also include a first conductive layer and / or a second conductive layer. The first conductive layer and the gate are stacked in the first direction, and the size of a partial region of the first conductive layer in the second direction is larger than that of the gate in the second direction. The second conductive layer and the active region are stacked in the first direction, and the distance between the first surface of the second conductive layer and the first surface of the active region in the first direction is larger than the distance between the first surface of the substrate and the first surface of the active region in the first direction. The first direction is perpendicular to the second direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a method for manufacturing the same, a chip, and an electronic device. Background Art

[0002] With the rapid development of semiconductor technology, chips including semiconductor devices have been widely used in electronic devices such as mobile phones. Semiconductor devices such as transistors may include a substrate, an active region, a gate, a gate sidewall, a first conductive layer, and a second conductive layer. Among them, the substrate, the gate, and the first conductive layer may be stacked, the substrate, the active region, and the second conductive layer may be stacked, and the gate sidewall may surround the gate. Both the first conductive layer and the second conductive layer may be formed of silicides such as cobalt silicide and nickel silicide.

[0003] In related technologies, the first conductive layer is usually formed by consuming the silicon material of the gate, and the second conductive layer is usually formed by consuming the silicon material of the active region. Therefore, the first conductive layer is flush with the gate sidewall, and the second conductive layer is flush with the substrate. It can be seen that the first conductive layer and the second conductive layer in related technologies are prone to clustering and disconnection. In addition, since the active region may have N-type or P-type doping, it is easy to cause an obvious line width effect in the first conductive layer and the second conductive layer (that is, the resistance of the first conductive layer and the second conductive layer increases as the line width or the contact area decreases), thereby resulting in a large switching delay of the semiconductor device.

[0004] Therefore, there is an urgent need for a technical solution that can reduce the switching delay of semiconductor devices. Summary of the Invention

[0005] The present application provides a semiconductor device, a method for manufacturing the same, a chip, and an electronic device, which can greatly improve the line width effect of the first conductive layer and the second conductive layer, and thereby reduce the switching delay of the semiconductor device.

[0006] In a first aspect, the present application provides a semiconductor device, which may include a substrate, a gate, and an active region. Among them, the gate and the substrate may be stacked along a first direction. It can be seen that the first direction is the stacking direction of the gate and the substrate. The active region may be located in a first substrate region of the substrate. The first substrate region may be used to indicate the substrate region around the projection region of the gate on the substrate.

[0007] The semiconductor device provided by the present application may further include a first conductive layer and / or a second conductive layer.

[0008] Optionally, the first conductive layer and the gate may be stacked in a first direction, and the size of a partial region of the first conductive layer (i.e., not all regions, namely the second partial region hereinafter) in a second direction may be greater than the size of the gate in the second direction. Herein, the second direction may be perpendicular to the first direction. Define the size in the first direction as the thickness, and the size in the second direction as the width. Then, the width of a partial region of the first conductive layer may be greater than the width of the gate.

[0009] The second conductive layer may be stacked with the active region in the first direction. The distance between the first surface of the second conductive layer and the first surface of the active region in the first direction is greater than the distance between the first surface of the substrate and the first surface of the active region in the first direction. Herein, the first surface of the second conductive layer may be used to indicate the surface of the second conductive layer away from the substrate. The first surface of the active region may be used to indicate the surface of the active region away from the substrate. The first surface of the substrate may be used to indicate the surface of the substrate close to the gate.

[0010] It can be understood that the distance between the first surface of the second conductive layer and the first surface of the active region in the first direction is the thickness of the second conductive layer. That is to say, the thickness of the second conductive layer may be greater than the distance between the first surface of the substrate and the first surface of the active region in the first direction. Further, it can be understood that a partial region of the second conductive layer is located inside the substrate, and a partial region is located on the first surface of the substrate.

[0011] Since the width of a partial region of the first conductive layer in this application is greater than the width of the gate, and the thickness of the second conductive layer is greater than the distance between the first surface of the substrate and the first surface of the active region in the first direction, the relatively wide first conductive layer and / or the relatively thick second conductive layer in this application are not prone to clustering and wire breakage. Therefore, the line width effect of the first conductive layer and / or the second conductive layer can be greatly improved, and further the switching delay of the semiconductor device can be reduced to ensure the reliability of the semiconductor device.

[0012] In a possible implementation manner, the first surface of the gate may be used to indicate the surface of the gate close to the first conductive layer. The second surface of the gate may be used to indicate the surface of the gate close to the substrate. The projection of the second surface of the gate on the substrate may be located inside the projection of the first surface of the gate on the substrate. That is to say, the width of the first surface of the gate may be greater than the width of the second surface of the gate. It can also be understood that the cross-section of the gate in the first direction may be trapezoidal. It can be imagined that the width of the first surface of the gate being greater than the width of the second surface of the gate can further reduce the possibility of clustering and wire breakage of the first conductive layer, thereby further improving the line width effect of the first conductive layer.

[0013] In another possible implementation manner, the semiconductor device provided in this application may further include a gate sidewall. The gate sidewall may surround the gate.

[0014] Exemplarily, the gate sidewall may include a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer stacked along a second direction. It is conceivable that the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are all disposed around the gate and stacked.

[0015] Furthermore, the first conductive layer may include a first partial region and a second partial region stacked along a first direction.

[0016] Wherein, the first partial region may be surrounded by the gate sidewall. Since the first partial region is stacked with the gate, that is to say, the sum of the thickness of the first partial region and the thickness of the gate may be the height of the gate sidewall. In other words, the surface of the first partial region away from the gate may be flush with the gate sidewall.

[0017] In the related art, the first conductive layer is flush with the gate sidewall, while in the present application, the width of the second partial region may be greater than the width of the gate and the second partial region may cover the gate sidewall and the first partial region. By comparison, it can be found that the first conductive layer in the present application is wider and thicker, which can further reduce the possibility of the first conductive layer having clusters and broken lines, thereby further improving the line width effect of the first conductive layer.

[0018] Exemplarily, the first conductive layer and / or the second conductive layer adopt metal silicides, etc. The metal silicides may be cobalt silicide and nickel silicide, etc. Among them, cobalt silicide may include Co2Si, CoSi, or CoSi2, etc. Nickel silicide may include Ni2Si, NiSi, or NiSi2, etc. Of course, the first conductive layer and / or the second conductive layer may also adopt other conductive materials, which are not limited in the present application.

[0019] In a possible implementation manner, the semiconductor device provided by the present application may further include a gate oxide layer. The gate oxide layer may be stacked between the substrate and the gate along a first direction. That is to say, the substrate, the gate oxide layer, the gate, and the first conductive layer may be stacked along a first direction.

[0020] In a possible implementation manner, the semiconductor device provided by the present application may further include an oxide layer. The oxide layer is located in the second substrate region of the substrate. The second substrate region may be used to indicate the substrate region other than the first substrate region and the projection region of the gate on the substrate.

[0021] Of course, in addition to the substrate, the active region, the gate oxide layer, the gate, the conductive layer (including the first conductive layer and / or the second conductive layer), and the gate sidewall, etc., the semiconductor device provided by the present application may further include other parts, which are not limited in the present application.

[0022] In a second aspect, the present application provides a method for manufacturing a semiconductor device, which may include: forming a gate and an active region on a substrate along a first direction. Forming a first conductive layer on the gate and / or forming a second conductive layer on the active region.

[0023] Optionally, the active region may be located in a first substrate region of the substrate. The first substrate region may be used to indicate the substrate region around the projected region of the gate on the substrate.

[0024] The size of a partial region of the first conductive layer (i.e., not all regions, namely the second partial region) in a second direction may be greater than the size of the gate in the second direction. Wherein, the second direction may be perpendicular to the first direction. Defining the size in the first direction as the thickness and the size in the second direction as the width. Then, the width of the partial region of the first conductive layer may be greater than the width of the gate.

[0025] The second conductive layer may be stacked with the active region along the first direction. The distance between the first surface of the second conductive layer and the first surface of the active region in the first direction is greater than the distance between the first surface of the substrate and the first surface of the active region in the first direction. Wherein, the first surface of the second conductive layer may be used to indicate the surface of the second conductive layer away from the substrate. The first surface of the active region may be used to indicate the surface of the active region away from the substrate. The first surface of the substrate may be used to indicate the surface of the substrate close to the gate.

[0026] It can be understood that the distance between the first surface of the second conductive layer and the first surface of the active region in the first direction is the thickness of the second conductive layer. That is to say, the thickness of the second conductive layer may be greater than the distance between the first surface of the substrate and the first surface of the active region in the first direction. Further, it can be understood that a partial region of the second conductive layer is located inside the substrate and a partial region is located on the first surface of the substrate.

[0027] Since the manufacturing method provided by the related art usually forms the first conductive layer by consuming the silicon material of the gate and forms the second conductive layer by consuming the silicon material of the active region. As a result, the first conductive layer is flush with the sidewall of the gate and the second conductive layer is flush with the substrate. In the semiconductor device manufactured by the manufacturing method provided by the present application, the width of a partial region of the first conductive layer is greater than the width of the gate, and the thickness of the second conductive layer is greater than the distance between the first surface of the substrate and the first surface of the active region in the first direction. That is to say, in the semiconductor device manufactured by the manufacturing method provided by the present application, the first conductive layer is wider and the second conductive layer is thicker. The wider first conductive layer or the thicker second conductive layer are not prone to clusters and wire breaks, thereby greatly improving the linewidth effect of the first conductive layer and / or the second conductive layer, and further reducing the switching delay of the semiconductor device to ensure the reliability of the semiconductor device.

[0028] In a possible implementation, forming a first conductive layer on the gate and / or a second conductive layer on the active region may include: forming a first sacrificial layer on a first surface of the gate and / or forming a second sacrificial layer on a first surface of the active region. A metal layer is formed on the first sacrificial layer and / or the second sacrificial layer. Laser anneal (LSA) or rapid thermal process (RTP) or other methods may be used to anneal the metal layer to form a third conductive layer and / or a fourth conductive layer. The metal layer is removed, and LSA or RTP or other methods may be used to anneal the third conductive layer and / or the fourth conductive layer to form the first conductive layer and / or the second conductive layer. Herein, the first surface of the gate may be used to indicate the surface of the gate away from the substrate.

[0029] Optionally, the substrate may be made of single crystal silicon or the like. The gate may be made of polysilicon (poly) or the like. The active region is formed by ion implantation of doped ions, and the active region may be doped single crystal silicon or the like.

[0030] The first sacrificial layer and the second sacrificial layer may be made of silicon materials such as amorphous silicon, single crystal silicon or polysilicon. It can be seen that in this application, by consuming the first sacrificial layer and / or the second sacrificial layer, the first conductive layer and / or the second conductive layer are formed by forming the third conductive layer and / or the fourth conductive layer.

[0031] Exemplarily, the first conductive layer, the second conductive layer, the third conductive layer or the fourth conductive layer may all be metal silicides. The metal silicides may be cobalt silicide and nickel silicide or the like. Among them, cobalt silicide may include Co2Si, CoSi or CoSi2 or the like. Nickel silicide may include Ni2Si, NiSi or NiSi2 or the like.

[0032] It can be conceived that the third conductive layer and / or the fourth conductive layer formed by annealing the metal layer may be high-resistance metal silicides such as Co2Si in the C49 phase. The first conductive layer and / or the second conductive layer formed by annealing the third conductive layer and / or the fourth conductive layer may be low-resistance metal silicides such as CoSi2 in the C54 phase.

[0033] The related art mainly forms the first conductive layer by consuming the gate and forms the second conductive layer by consuming the active region. Compared with the related art, the present application can greatly reduce the consumption of the gate and / or the active region during the annealing process. At the same time, since the present application mainly consumes the first sacrificial layer, the influence of the doping of the gate on the resistance value of the semiconductor device is avoided. That is to say, the present application can reduce the resistance value of the semiconductor device, and can reduce the possibility of clusters and disconnections in the first conductive layer and the second conductive layer, that is, the defects of the first conductive layer and the second conductive layer, so as to greatly improve the line width effect of the first conductive layer and / or the second conductive layer, and further reduce the switching delay of the semiconductor device to ensure the reliability of the semiconductor device.

[0034] In another possible implementation, forming the first conductive layer on the gate and / or forming the second conductive layer on the active region may include: forming a metal layer on the first surface of the gate and / or the first surface of the active region. The metal layer can be annealed by means such as LSA or RTP to form the third conductive layer and / or the fourth conductive layer, and the metal layer is removed. A first sacrificial layer is formed on the third conductive layer and / or a second sacrificial layer is formed on the fourth conductive layer. The first sacrificial layer and / or the second sacrificial layer can be annealed by means such as LSA or RTP to form the first conductive layer and / or the second conductive layer. The first sacrificial layer and / or the second sacrificial layer are removed. Wherein, the first surface of the gate can be used to indicate the surface of the gate away from the substrate.

[0035] Optionally, the substrate can be made of silicon materials such as single crystal silicon. The gate can be made of silicon materials such as polysilicon (poly). The active region is formed by ion implantation of doped ions, and the active region can be single crystal silicon with doping. The first sacrificial layer and the second sacrificial layer can be made of silicon materials such as amorphous silicon, single crystal silicon or polysilicon.

[0036] It can be conceived that the third conductive layer and / or the fourth conductive layer formed by annealing the metal layer can be high-resistance metal silicides such as Co2Si in the C49 phase. The first conductive layer and / or the second conductive layer formed by annealing the first sacrificial layer and / or the second sacrificial layer can be low-resistance metal silicides such as CoSi2 in the C54 phase.

[0037] It can be seen that in this application, the metal layer is annealed to form the third conductive layer and / or the fourth conductive layer. Since the metal layer is on the first surface of the gate and / or the first surface of the active region, this application consumes a part of the region of the gate and / or a part of the region of the active region. However, in the process of forming the first conductive layer and / or the second conductive layer in this application, the first sacrificial layer and / or the second sacrificial layer are consumed. Compared with the related art, in the annealing process of this application, the consumption of the gate and / or the active region can be reduced to a certain extent. At the same time, since the process of forming the first conductive layer in this application also consumes the first sacrificial layer, the influence of the doping of the gate on the resistance value of the semiconductor device can be avoided to a certain extent. That is to say, this application can reduce the resistance value of the semiconductor device, and can reduce the possibility of clusters and disconnections in the first conductive layer and the second conductive layer, that is, the defects of the first conductive layer and the second conductive layer, thereby greatly improving the line width effect of the first conductive layer and / or the second conductive layer, and further reducing the switching delay of the semiconductor device to ensure the reliability of the semiconductor device.

[0038] Exemplarily, the manufacturing method provided in this application may further include: depositing a dielectric material on the gate and the active region. Etching the dielectric material to form a gate sidewall.

[0039] Optionally, the gate sidewall may include a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer stacked along the second direction. It can be imagined that the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are all stacked around the gate.

[0040] Furthermore, the first conductive layer may include a first partial region and a second partial region stacked along the first direction.

[0041] Among them, the first partial region can be surrounded by the gate sidewall. Since the first partial region is stacked with the gate, that is to say, the sum of the thickness of the first partial region and the thickness of the gate can be the height of the gate sidewall. In other words, the surface of the first partial region away from the gate can be flush with the gate sidewall.

[0042] In the related art, the first conductive layer is flush with the gate sidewall, while in this application, the width of the second partial region can be greater than the width of the gate and the second partial region can cover the gate sidewall and the first partial region. By comparison, it can be found that the first conductive layer in this application is wider and thicker, which can further reduce the possibility of clusters and disconnections in the first conductive layer, thereby further improving the line width effect of the first conductive layer.

[0043] In a possible implementation, forming a gate and an active region on a substrate along a first direction may include: forming an active region in a first substrate region along the first direction by means of ion implantation or the like. A gate is formed on a substrate region surrounded by the active region (which may be called a third substrate region, that is, the projection region of the gate on the substrate).

[0044] The projection of the second surface of the gate on the substrate may be located inside the projection of the first surface of the gate on the substrate. Among them, the first surface of the gate may be used to indicate the surface of the gate close to the first conductive layer. The second surface of the gate may be used to indicate the surface of the gate close to the substrate.

[0045] That is to say, the width of the second surface of the gate may be greater than the width of the first surface of the gate. It can also be understood that the cross-section of the gate in the first direction may be trapezoidal. It can be imagined that the width of the second surface of the gate being greater than the width of the first surface of the gate can further reduce the possibility of clustering and wire breakage of the first conductive layer, thereby further improving the line width effect of the first conductive layer and the second conductive layer.

[0046] In another possible implementation, the manufacturing method provided by the present application may further include: forming a gate oxide layer on the third substrate region. It can be imagined that the gate oxide layer may be stacked between the substrate and the gate.

[0047] In yet another possible implementation, the manufacturing method provided by the present application may further include: forming an oxide layer in a second substrate region. Among them, the second substrate region may be used to indicate the substrate region other than the first substrate region and the third substrate region.

[0048] In a third aspect, the present application provides a chip, which may include a passive device and the semiconductor device provided by the first aspect and its possible implementations. The passive device may be electrically connected to the semiconductor device.

[0049] In a fourth aspect, the present application provides an electronic device, which may include a circuit board and the chip provided by the first aspect and its possible implementations. The chip may be disposed on the circuit board.

[0050] Optionally, the electronic device may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc. The embodiments of the present application do not limit the form of the electronic device.

[0051] Schematically, the above-mentioned consumer electronics products can be mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (such as smart watches, smart bands, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can be smart door locks, TVs, smart speakers, refrigerators, floor-sweeping robots, etc. In-vehicle electronics products can be in-vehicle navigators, in-vehicle displays, etc. Financial terminal products can be automated teller machines (ATMs), electronic devices for self-service business handling, etc. Communication electronics products can be communication devices such as servers, memories, radars, base stations, etc.

[0052] It should be understood that the technical solutions of the second to fourth aspects of this application are consistent with those of the first aspect of this application, and the beneficial effects obtained by each aspect and the corresponding feasible implementation manners are similar, so they will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0054] Figure 1 It is a schematic structural diagram of an electronic device in an embodiment of this application;

[0055] Figure 2 It is a schematic structural diagram of a semiconductor device in an embodiment of this application;

[0056] Figure 3 It is a partial structural diagram of a semiconductor device in an embodiment of this application;

[0057] Figure 4 It is a schematic flow chart of a preparation process in an embodiment of this application;

[0058] Figure 5 It is a schematic structural diagram of a semiconductor device in an embodiment of this application;

[0059] Figure 6 It is another schematic structural diagram of a semiconductor device in an embodiment of this application;

[0060] Figure 7 A schematic flowchart for forming a first conductive layer and a second conductive layer in an embodiment of the present application;

[0061] Figure 8 A schematic structural diagram of a semiconductor device in an embodiment of the present application;

[0062] Figure 9 Another schematic structural diagram of a semiconductor device in an embodiment of the present application;

[0063] Figure 10 Another schematic structural diagram of a semiconductor device in an embodiment of the present application;

[0064] Figure 11 Another schematic flowchart for forming a first conductive layer and a second conductive layer in an embodiment of the present application;

[0065] Figure 12 A schematic structural diagram of a semiconductor device in an embodiment of the present application;

[0066] Figure 13 Another schematic structural diagram of a semiconductor device in an embodiment of the present application;

[0067] Figure 14 Another schematic structural diagram of a semiconductor device in an embodiment of the present application. Detailed implementation manners

[0068] The technical solutions in the present application will be described below with reference to the accompanying drawings.

[0069] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings in the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present application belong to the scope of protection of the present application.

[0070] The terms "first", "second", etc. in the description, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and should not be construed as indicating or implying relative importance, nor as indicating or implying order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0071] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the relationship between associated objects and indicates that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously. Here, A and B can be singular or plural. The character " / " generally indicates an "or" relationship between the associated objects before and after. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0072] An embodiment of this application provides an electronic device, which can be any electronic product equipped with a storage chip. The electronic device can be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc. The embodiment of this application does not limit the form of the electronic device.

[0073] Illustratively, the above-mentioned consumer electronic products can be mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (such as smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products can be smart door locks, TVs, smart speakers, refrigerators, floor-sweeping robots, etc. Vehicle-mounted electronic products can be vehicle-mounted navigators, vehicle-mounted displays, etc. Financial terminal products can be automated teller machines (ATMs), electronic devices for self-service business handling, etc. Communication electronic products can be communication devices such as servers, memories, radars, base stations, etc.

[0074] According to actual requirements, other devices electrically connected to the storage device, such as printed circuit boards (PCBs; also known as printed wiring boards) and input / output devices, can also be provided in the above-mentioned electronic device. This application does not limit this.

[0075] Illustratively, taking the above-mentioned electronic device as a mobile phone as an example. Refer to Figure 1As shown in the figure, the mobile phone 1000 may include a bus 101, a system on chip (SoC) 110 connected to the bus 101, a second RAM 120, a communication chip 130, and a power management chip 140.

[0076] Among them, the SoC 110 can be used to process data, such as processing data of application programs, processing image data, and caching temporary data. The SoC 110 may include an application processor (AP) 111 for processing application programs, a graphics processing unit (GPU) 112 for processing image data, and a first RAM (random access memory) 113 for caching high-speed data. The AP 111, GPU 112, and first RAM 113 can be integrated in one die or can be separately provided in multiple dies. The first RAM 113 can be a dynamic random access memory (DRAM). The second RAM 120 can be a dynamic random access memory (DRAM). The power management chip 140 can be used to supply power to other chips.

[0077] The above-mentioned first RAM 110 and second RAM 120 can adopt the chips provided by the embodiments of the present application. The chips provided by the embodiments of the present application can be arranged on a circuit board.

[0078] Furthermore, the chip can include passive devices and semiconductor devices. The passive devices can be electrically connected to the semiconductor devices. The passive devices can be devices such as capacitors and inductors.

[0079] Next, the semiconductor devices provided by the embodiments of the present application will be introduced.

[0080] As Figure 2 shown. The semiconductor device 10 can be a transistor, etc., and can include a substrate 1, a gate 2, and an active region. Among them, the active region can include an active region 31 and an active region 32. Among them, the active region 31 can be used as the source electrode of the semiconductor device 10, and the active region 32 can be used as the drain electrode of the semiconductor device 10.

[0081] Optionally, the gate 2 and the substrate 1 can be along a first direction (i.e., Figure 2Stacked in the Y direction). It can be seen that the first direction is the stacking direction of the gate 2 and the substrate 1. The active regions 31 and 32 can be located in the first substrate region of the substrate 1. The first substrate region can be used to indicate the substrate region around the projection region of the gate 2 on the substrate 1.

[0082] The semiconductor device 10 provided by the embodiment of the present application may further include a first conductive layer 41 and / or a second conductive layer 42. The embodiment of the present application will be described by taking the semiconductor device 10 further including a first conductive layer 41 and a second conductive layer 42 as an example.

[0083] Optionally, the first conductive layer 41 and the gate 2 can be stacked in the first direction, and a partial region of the first conductive layer 41 (that is, not all regions, namely the second partial region 412 hereinafter) in the second direction (i.e., Figure 2 the X direction in) can have a size greater than the size of the gate in the second direction. Wherein, the X direction can be perpendicular to the Y direction. The size in the Y direction is defined as the thickness, and the size in the X direction is defined as the width. Then, the width of the second partial region 412 of the first conductive layer 41 can be greater than the width of the gate 2.

[0084] The second conductive layer 42 can be stacked with the active regions (i.e., the active regions 31 and 32) in the Y direction. The distance between the first surface of the second conductive layer 42 and the first surface of the active region in the Y direction is greater than the distance between the first surface of the substrate 1 and the first surface of the active region in the Y direction. Wherein, the first surface of the second conductive layer 42 can be used to indicate the surface of the second conductive layer 42 away from the substrate 1 (i.e., Figure 2 the upper surface of the second conductive layer 42 in). The first surface of the active region can be used to indicate the surface of the active region away from the substrate 1 (i.e., Figure 2 the upper surface of the active region in). The first surface of the substrate 1 can be used to indicate the surface of the substrate 1 close to the gate 3 (i.e., Figure 2 the upper surface of the substrate 1 in).

[0085] It can be understood that in Figure 2 , the distance between the upper surface of the second conductive layer 42 and the upper surface of the active region in the Y direction is the thickness of the second conductive layer 42. That is to say, the thickness of the second conductive layer 42 can be greater than the distance between the upper surface of the substrate 1 and the upper surface of the active region in the Y direction. Further, it can be understood that a partial region of the second conductive layer 42 can be located inside the substrate 1, and a partial region is located on the upper surface of the substrate 1.

[0086] In the semiconductor device 10 provided by the embodiment of the present application, a partial region of the first conductive layer 41 (i.e., Figure 2In the second part region 412), the width is greater than the width of the gate. In the semiconductor device 10 provided by the embodiment of the present application, the thickness of the second conductive layer 42 is greater than the distance in the Y direction between the upper surface of the substrate 1 and the upper surface of the active region. In the embodiment of the present application, the relatively wide first conductive layer 41 and the relatively thick second conductive layer 42 are not prone to cluster and wire breakage, so that the line width effect of the first conductive layer 41 and the second conductive layer 42 can be greatly improved, thereby reducing the switching delay of the semiconductor device 10 and ensuring the reliability of the semiconductor device 10.

[0087] In some embodiments, the first surface of the gate 2 can be used to indicate the surface of the gate 2 close to the first conductive layer 41 (i.e., Figure 2 the upper surface of the gate 2 in ). The second surface of the gate 2 can be used to indicate the surface of the gate 2 close to the substrate 1 (i.e., Figure 2 the lower surface of the gate 2 in ). The projection of the lower surface of the gate 2 on the substrate 1 can be located inside the projection of the upper surface of the gate 2 on the substrate 1. That is to say, the width of the upper surface of the gate 2 can be greater than the width of the lower surface of the gate 2, as Figure 3 shown.

[0088] It can also be understood that the cross-section of the gate 2 in the Y direction can be trapezoidal, referring to Figure 3 . It can be imagined that the width of the upper surface of the gate 2 being greater than the width of the lower surface of the gate 2 can further reduce the possibility of the first conductive layer 41 appearing in clusters and wire breakage, thereby further improving the line width effect of the first conductive layer 41.

[0089] In other embodiments, the semiconductor device 10 provided by the embodiment of the present application may further include a gate sidewall. The gate sidewall can be disposed around the gate 2.

[0090] Exemplarily, as Figure 2 shown, the gate sidewall may include a first dielectric layer 71, a second dielectric layer 72, a third dielectric layer 73, and a fourth dielectric layer 74 stacked in the X direction. It can be imagined that the first dielectric layer 71, the second dielectric layer 72, the third dielectric layer 73, and the fourth dielectric layer 74 are all disposed around the gate 2 and stacked.

[0091] Optionally, the first dielectric layer 71, the second dielectric layer 72, the third dielectric layer 73, and the fourth dielectric layer 74 can be made of silicon nitride, etc., which is not limited in the embodiment of the present application.

[0092] It can be understood that during the formation of the gate sidewall, the third dielectric layer 73 and the fourth dielectric layer 74 will also be stacked on the upper surface of the substrate 1, as Figure 2 shown.

[0093] Further, referring to Figure 2, the first conductive layer 41 may include a first partial region 411 and a second partial region 412 stacked along the Y direction.

[0094] Among them, the first partial region 411 may be surrounded by the gate sidewall. Since the first partial region 411 is stacked with the gate 2, that is to say, the sum of the thickness of the first partial region 411 and the thickness of the gate 2 may be the height of the gate sidewall. In other words, the surface of the first partial region 411 away from the gate 2 (i.e., Figure 2 the upper surface of the gate 2 in the middle) may be flush with the gate sidewall.

[0095] In the related art, the first conductive layer 41 is flush with the gate sidewall, while in the embodiment of the present application, the width of the second partial region 412 may be greater than the width of the gate 2 and the second partial region 412 may cover the gate sidewall and the first partial region 411. By comparison, it can be found that the first conductive layer 41 in the embodiment of the present application is wider and thicker, which can further reduce the possibility of the first conductive layer 41 appearing clusters and broken wires, thereby further improving the line width effect of the first conductive layer 41.

[0096] Exemplarily, the first conductive layer 41 may adopt metal silicide, etc. Similarly, the second conductive layer 42 may also adopt metal silicide, etc. The metal silicide may be cobalt silicide and nickel silicide, etc. Among them, cobalt silicide may include Co2Si, CoSi or CoSi2, etc. Nickel silicide may include Ni2Si, NiSi or NiSi2, etc. Of course, the first conductive layer 41 and the second conductive layer 42 may also adopt other conductive materials, which are not limited in the embodiment of the present application.

[0097] Exemplarily, the substrate 1 may adopt single crystal silicon, etc. The gate 2 may adopt polysilicon (poly), etc. The active regions 31 and 32 are formed by ion implantation doping ions, and the active regions 31 and 32 may be doped single crystal silicon, etc.

[0098] In a possible implementation manner, the semiconductor device 10 provided in the embodiment of the present application may further include a gate oxide layer 5, as Figure 2 shown. The gate oxide layer 5 may be stacked between the substrate 1 and the gate 2 along the Y direction. That is to say, the substrate 1, the gate oxide layer 5, the gate 2 and the first conductive layer 41 may be stacked along the Y direction.

[0099] In another possible implementation manner, the semiconductor device 10 provided in the embodiment of the present application may further include an oxide layer 6. The oxide layer 6 may be located in the second substrate region of the substrate 1. The second substrate region may be used to indicate the substrate region other than the first substrate region and the projection region of the gate 2 on the substrate 1 (i.e., the substrate region surrounded by the active region).

[0100] Of course, in addition to the substrate 1, the active region, the gate oxide layer 5, the gate 2, the conductive layers (including the first conductive layer 41 and the second conductive layer 42), and the gate sidewall, etc., the semiconductor device 10 provided by the embodiments of the present application may further include other parts, which are not limited in the embodiments of the present application.

[0101] The present application also provides a method for manufacturing a semiconductor device 10, and the manufacturing process 200 is as Figure 4 shown. The manufacturing process 200 can be implemented through the following steps:

[0102] Step S201: Form an active region and an oxide layer 6 on the substrate 1 by means of ion implantation or the like, as Figure 5 shown. Among them, the active region includes an active region 31 and an active region 32.

[0103] Step S202: Form a gate oxide layer 5, a gate 2, and a gate sidewall on the substrate 1, as Figure 6 shown. Among them, the gate sidewall may include a first dielectric layer 71, a second dielectric layer 72, a third dielectric layer 73, and a fourth dielectric layer 74 stacked in the X direction. The first dielectric layer 71, the second dielectric layer 72, the third dielectric layer 73, and the fourth dielectric layer 74 are all stacked around the gate 2. It can be imagined that the third dielectric layer 73 and the fourth dielectric layer 74 can also be stacked on the substrate, referring to Figure 6 . Among them, the active region 31 and the active region 32 may be located in the substrate region (i.e., the first substrate region) around the projection area of the gate 2 on the substrate 1.

[0104] Optionally, the first surface of the gate 2 can be used to indicate the surface of the gate 2 close to the first conductive layer 41 (i.e., the upper surface of the gate 2). The second surface of the gate 2 can be used to indicate the surface of the gate 2 close to the substrate 1 (i.e., the lower surface of the gate 2). The projection of the lower surface of the gate 2 on the substrate 1 may be located inside the projection of the upper surface of the gate 2 on the substrate 1. That is to say, the width of the upper surface of the gate 2 may be greater than the width of the lower surface of the gate 2, and reference can be made to Figure 3 . It can also be understood that the cross-section of the gate 2 in the Y direction may be trapezoidal. It can be imagined that the width of the upper surface of the gate 2 being greater than the width of the lower surface of the gate can further reduce the possibility of the first conductive layer 41 appearing in clusters and disconnection, thereby further improving the line width effect of the first conductive layer 41.

[0105] Exemplarily, a dielectric material is deposited on the gate 2 and the active region. The dielectric material is etched to form the gate sidewall. The detailed process of forming the gate sidewall in the embodiments of the present application will not be specifically introduced herein.

[0106] Step S203: Form a first conductive layer 41 on the gate 2, and form a second conductive layer 42 on the active region 31 and the active region 32, asFigure 2 as shown

[0107] Referring to Figure 2 , the first conductive layer 41 may include a first partial region 411 and a second partial region 412. Among them, the first partial region 411 may be surrounded by the gate sidewall. The size of the second partial region 411 in the X direction may be greater than the size of the gate in the X direction. Define the size in the Y direction as the thickness and the size in the X direction as the width. Then, the width of the second partial region 412 may be greater than the width of the gate 2.

[0108] It can be conceived that since the first partial region 411 is stacked with the gate 2, that is to say, the sum of the thickness of the first partial region 411 and the thickness of the gate 2 may be the height of the gate sidewall. In other words, the surface of the first partial region 411 away from the gate 2 (i.e., the upper surface of the gate 2) may be flush with the gate sidewall.

[0109] The second conductive layer 42 may be stacked with the active regions (i.e., the active region 31 and the active region 32) in the Y direction. The distance between the first surface of the second conductive layer 42 and the first surface of the active region in the Y direction is greater than the distance between the first surface of the substrate 1 and the first surface of the active region in the Y direction. Among them, the first surface of the second conductive layer 42 may be used to indicate the surface of the second conductive layer 42 away from the substrate 1 (i.e., the upper surface of the second conductive layer 42). The first surface of the active region may be used to indicate the surface of the active region away from the substrate 1 (i.e., the upper surface of the active region). The first surface of the substrate 1 may be used to indicate the surface of the substrate 1 close to the gate 3 (i.e., the upper surface of the substrate 1).

[0110] It can be understood that in Figure 2 , the distance between the upper surface of the second conductive layer 42 and the upper surface of the active region in the Y direction is the thickness of the second conductive layer 42. That is to say, the thickness of the second conductive layer 42 may be greater than the distance between the upper surface of the substrate 1 and the upper surface of the active region in the Y direction. Further, it can be understood that part of the second conductive layer 42 may be located inside the substrate 1 and part of it may be located on the upper surface of the substrate 1.

[0111] Since the preparation methods provided by the related technologies usually form the first conductive layer by consuming the silicon material of the gate and form the second conductive layer by consuming the silicon material of the active region, the first conductive layer is flush with the sidewall of the gate, and the second conductive layer is flush with the substrate. In the semiconductor device 10 prepared by the preparation method provided by the embodiment of the present application, the width of a partial region of the first conductive layer 41 is greater than the width of the gate 2, and the thickness of the second conductive layer 42 is greater than the distance between the upper surface of the substrate 1 and the upper surface of the active region in the Y direction. That is to say, in the semiconductor device 10 prepared by the preparation method provided by the embodiment of the present application, the first conductive layer 41 is wider and the second conductive layer 42 is thicker. The wider first conductive layer 41 or the thicker second conductive layer 42 is not prone to clusters and wire breaks, thereby greatly improving the line width effect of the first conductive layer 41 and the second conductive layer 42, further reducing the switching delay of the semiconductor device 10, and ensuring the reliability of the semiconductor device 10.

[0112] In some embodiments, as Figure 7 shown, the above step S203 can be specifically implemented through the following steps:

[0113] Step S203a1: Form a first sacrificial layer 8 on the gate 2 and form a second sacrificial layer 9 on the active region, as Figure 8 shown.

[0114] Step S203a2: Form a metal layer 10 on the first sacrificial layer 8 and the second sacrificial layer 9, as Figure 9 shown.

[0115] Step S203a3: Anneal the metal layer 10 to form a third conductive layer 11 and a fourth conductive layer 12, as Figure 10 shown.

[0116] Exemplarily, the metal layer 10 can be annealed by means of laser annealing (LSA) or rapid thermal process (RTP). Of course, other methods can also be used to anneal the metal layer 10, which is not limited in the embodiment of the present application.

[0117] Step S203a4: Remove the metal layer 10 and anneal the third conductive layer 11 and the fourth conductive layer 12 to form the first conductive layer 41 and the second conductive layer 42, as Figure 2 shown.

[0118] Similarly, the third conductive layer 11 and the fourth conductive layer 12 can be annealed by means of LSA or RTP. Of course, other methods can also be used to anneal the third conductive layer 11 and the fourth conductive layer 12, which is not limited in the embodiment of the present application.

[0119] Optionally, the first conductive layer 41, the second conductive layer 42, the third conductive layer 11, or the fourth conductive layer 12 can all be metal silicides. The metal silicides can be cobalt silicide, nickel silicide, etc. Among them, cobalt silicide can include Co2Si, CoSi, or CoSi2, etc. Nickel silicide can include Ni2Si, NiSi, or NiSi2, etc.

[0120] It is conceivable that the third conductive layer 11 and the fourth conductive layer 12 formed by annealing the metal layer 10 can be high-resistance metal silicides such as Co2Si in the C49 phase. The first conductive layer 41 and the second conductive layer 42 formed by annealing the third conductive layer 11 and the fourth conductive layer 12 can be low-resistance metal silicides such as CoSi2 in the C54 phase.

[0121] Optionally, the substrate 1 can be made of silicon materials such as single-crystalline silicon. The gate 2 can be made of silicon materials such as polysilicon (poly). The active region is formed by ion implantation doping ions, and the active region can be doped single-crystalline silicon.

[0122] It can be understood that the first sacrificial layer and the second sacrificial layer 9 can both be made of silicon materials such as amorphous silicon, single-crystalline silicon, or polysilicon. It can be seen that in the embodiment of the present application, by consuming the polysilicon of the first sacrificial layer 8 and the polysilicon of the second sacrificial layer 9, the first conductive layer 41 and the second conductive layer 42 are formed by forming the third conductive layer 11 and the fourth conductive layer 12.

[0123] The related technology mainly forms the first conductive layer by consuming the gate and forms the second conductive layer by consuming the active region. Compared with the related technology, the embodiment of the present application can greatly reduce the consumption of the gate 2 and the active region during the annealing process. At the same time, since the embodiment of the present application mainly consumes the first sacrificial layer 8, the influence of the doping of the gate 2 on the resistance value of the semiconductor device 10 is avoided. That is to say, the embodiment of the present application can reduce the resistance value of the semiconductor device 10, and can reduce the possibility of clustering and disconnection of the first conductive layer 41 and the second conductive layer 42, that is, the defects of the first conductive layer 41 and the second conductive layer 42, thereby greatly improving the line width effect of the first conductive layer 41 and the second conductive layer 42, and further reducing the switching delay of the semiconductor device 10 to ensure the reliability of the semiconductor device 10.

[0124] In some other embodiments, as Figure 11 shown, the above step S203 can specifically be implemented through the following steps:

[0125] Step S203b1: Form a metal layer 10 on the gate 2 and the source region, as Figure 12 shown.

[0126] Step S203b2: Anneal the metal layer 10 to form a third conductive layer 11 and a fourth conductive layer 12, and remove the metal layer 10, as Figure 13 shown.

[0127] The metal layer 10 can be annealed by means such as LSA or RTP. Of course, other methods can also be used to anneal the metal layer 10, which is not limited in the embodiments of the present application.

[0128] Step S203b3: Form a sacrificial layer 13 on the third conductive layer 11 and the fourth conductive layer 12, as Figure 14 shown.

[0129] Step S203b4: Anneal the sacrificial layer 13 to form a first conductive layer 41 and a second conductive layer 42, and remove the sacrificial layer 13, as Figure 2 shown.

[0130] Similarly, the sacrificial layer 13 can be annealed by means such as LSA or RTP. Of course, other methods can also be used to anneal the sacrificial layer 13, which is not limited in the embodiments of the present application.

[0131] Optionally, the substrate 1 and the sacrificial layer 13 can be made of single crystal silicon, etc. The gate 2 can be made of polysilicon (poly), etc. The active region is formed by ion implantation of doped ions, and the active region can be doped single crystal silicon, etc. The first sacrificial layer and the second sacrificial layer 9 can both be made of silicon materials such as amorphous silicon, single crystal silicon or polysilicon.

[0132] It can be conceived that the third conductive layer 11 and the fourth conductive layer 12 formed by annealing the metal layer 10 can be high-resistance metal silicides such as Co2Si in the C49 phase. The first conductive layer 41 and the second conductive layer 42 formed by annealing the sacrificial layer 13 can be low-resistance metal silicides such as CoSi2 in the C54 phase.

[0133] It can be seen that in the embodiment of the present application, the third conductive layer 11 and the fourth conductive layer 12 can be formed by annealing the metal layer 10. Since the metal layer 10 is on the gate 2 and the active region, only part of the region of the gate 2 and part of the region of the active region are consumed in the embodiment of the present application. However, the sacrificial layer 13 is consumed in the process of forming the first conductive layer 41 and the second conductive layer 42 in the embodiment of the present application. Compared with the related art, the consumption of the gate 2 and the active region can be reduced to a certain extent during the annealing process in the embodiment of the present application. At the same time, since the sacrificial layer 13 is also consumed in the process of forming the first conductive layer 41 in the embodiment of the present application, the influence of the doping of the gate 2 on the resistance value of the semiconductor device 10 can be avoided to a certain extent. That is to say, the embodiment of the present application can reduce the resistance value of the semiconductor device 10, and can reduce the possibility of clustering and disconnection of the first conductive layer 41 and the second conductive layer 42, that is, the defects of the first conductive layer 41 and the second conductive layer 42, so as to greatly improve the line width effect of the first conductive layer 41 and the second conductive layer 42, and further reduce the switching delay of the semiconductor device 10 to ensure the reliability of the semiconductor device 10.

[0134] Only two possible implementation processes of the embodiment of the present application are provided above. The semiconductor device 10 provided by the embodiment of the present application can also be manufactured by other manufacturing processes, which are not limited in the embodiment of the present application. At the same time, the above order of steps will not play any limiting role in the manufacturing process. That is to say, the embodiment of the present application does not limit the order of each step in the manufacturing process, as long as the manufacturing of the semiconductor device 10 can be completed.

[0135] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, It includes a substrate, a gate, and an active region; wherein, the gate and the substrate are stacked in a first direction, and the active region is located in a first substrate region of the substrate, and the first substrate region is used to indicate the substrate region around the projection region of the gate on the substrate; The semiconductor device further includes a first conductive layer and / or a second conductive layer; The first conductive layer and the gate are stacked in the first direction, and a dimension of a partial region of the first conductive layer in a second direction is greater than a dimension of the gate in the second direction; wherein, the second direction is perpendicular to the first direction; The second conductive layer and the active region are stacked in the first direction, and a distance between a first surface of the second conductive layer and a first surface of the active region in the first direction is greater than a distance between a first surface of the substrate and the first surface of the active region in the first direction; wherein, the first surface of the second conductive layer is used to indicate the surface of the second conductive layer away from the substrate, the first surface of the active region is used to indicate the surface of the active region away from the substrate, and the first surface of the substrate is used to indicate the surface of the substrate close to the gate.

2. The semiconductor device according to claim 1, wherein A projection of a second surface of the gate on the substrate is located inside a projection of a first surface of the gate on the substrate; wherein, the first surface of the gate is used to indicate the surface of the gate close to the first conductive layer, and the second surface of the gate is used to indicate the surface of the gate close to the substrate.

3. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device further includes a gate sidewall that surrounds the gate.

4. The semiconductor device according to claim 3, characterized in that, The first conductive layer includes a first partial region and a second partial region that are stacked in the first direction; The first partial region is surrounded by the gate sidewall, and the second partial region covers the gate sidewall and the first partial region.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The first conductive layer and / or the second conductive layer is made of metal silicide.

6. A method for manufacturing a semiconductor device, characterized in that, It includes: Forming a gate and an active region on a substrate in a first direction; wherein, the active region is located in a first substrate region of the substrate, and the first substrate region is used to indicate the substrate region around the projection region of the gate on the substrate; Forming a first conductive layer on the gate, and / or, forming a second conductive layer on the active region; wherein, a dimension of a partial region of the first conductive layer in a second direction is greater than a dimension of the gate in the second direction, and the second direction is perpendicular to the first direction; a distance between a first surface of the second conductive layer and a first surface of the active region in the first direction is greater than a distance between a first surface of the substrate and the first surface of the active region in the first direction; the first surface of the second conductive layer is used to indicate the surface of the second conductive layer away from the substrate, the first surface of the active region is used to indicate the surface of the active region away from the substrate, and the first surface of the substrate is used to indicate the surface of the substrate close to the gate.

7. The preparation method according to claim 6, characterized in that, The forming the first conductive layer on the gate, and / or, forming the second conductive layer on the active region includes: Form a first sacrificial layer on a first surface of the gate, and / or form a second sacrificial layer on a first surface of the active region; wherein, the first surface of the gate is used to indicate the surface of the gate away from the substrate. Form a metal layer on the first sacrificial layer and / or the second sacrificial layer. Anneal the metal layer to form a third conductive layer and / or a fourth conductive layer. Remove the metal layer, and anneal the third conductive layer and / or the fourth conductive layer to form the first conductive layer and / or the second conductive layer.

8. The preparation method according to claim 6, characterized in that, Forming the first conductive layer on the gate and / or the second conductive layer on the active region includes: Form a metal layer on the first surface of the gate and / or the first surface of the active region; wherein, the first surface of the gate is used to indicate the surface of the gate away from the substrate. Anneal the metal layer to form a third conductive layer and / or a fourth conductive layer, and remove the metal layer. Form a first sacrificial layer on the third conductive layer and / or a second sacrificial layer on the fourth conductive layer. Anneal the first sacrificial layer and / or the second sacrificial layer to form the first conductive layer and / or the second conductive layer. Remove the first sacrificial layer and / or the second sacrificial layer.

9. The preparation method according to any one of claims 6 to 8, characterized in that, The manufacturing method further includes: Deposit a dielectric material on the gate and the active region. Etch the dielectric material to form a gate sidewall.

10. The preparation method according to claim 9, characterized in that, The first conductive layer includes a first partial region and a second partial region stacked along the first direction. The first partial region is surrounded by the gate sidewall, and the second partial region covers the gate sidewall and the first partial region.

11. The preparation method according to any one of claims 6 to 10, characterized in that, A projection of a second surface of the gate on the substrate is located inside a projection of the first surface of the gate on the substrate; wherein, the first surface of the gate is used to indicate the surface of the gate close to the first conductive layer, and the second surface of the gate is used to indicate the surface of the gate close to the substrate.

12. A chip, characterized in that, Comprising a passive device and a semiconductor device according to any one of claims 1 to 5; the passive device is electrically connected to the semiconductor device.

13. An electronic device, characterized in that, Comprising a circuit board and a chip according to claim 12; the chip is disposed on the circuit board.

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