Groove type silicon carbide MOSFET, module and electronic equipment
By setting the shielded gate and longitudinal ohmic contact in the trench type silicon carbide MOSFET and setting the P+ contact area on the bottom and side walls of the gate trench, the problems of excessive gate oxygen electric field and high switching losses in the prior art are solved, and a smaller device size and higher current density are achieved.
Patent Information
- Application Number
- CN202510415297.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2025-06-27
AI Technical Summary
The existing silicon carbide trench technology faces the problem of excessive gate oxygen electric field and difficulty in obtaining high reliability gate oxygen. At the same time, when power switches are used at high frequencies, the proportion of switching losses to total losses has increased significantly.
By providing a shield gate in the gate trench of the trench type silicon carbide MOSFET and introducing longitudinal ohmic contacts into the source trench, the source contact size is reduced, and a P+ contact region is provided at the bottom and side walls of the gate trench to protect the gate oxygen.
It realizes reducing drain-source capacitance, reducing device size, increasing current density, reducing on-resistance, and reducing switching losses.
Smart Images
Figure CN120224743A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of power semiconductor devices, and particularly to a trench-type silicon carbide MOSFET, a module, and an electronic device. Background Art
[0002] The wide bandgap semiconductor material silicon carbide has advantages such as a high critical breakdown electric field, a high thermal conductivity, and a high electron saturation velocity, which enables the efficiency and power density of power electronic systems to move towards higher levels. According to the chip gate structure, silicon carbide MOSFETs can be divided into planar gate and trench gate structures. With the development of electronic devices towards miniaturization and light weight, designing a high-performance trench-type silicon carbide MOSFET is an inevitable path for the development of silicon carbide devices.
[0003] Currently, the development of silicon carbide trench technology faces problems such as an excessively high gate oxide electric field at the bottom of the trench in the blocking state and difficulty in obtaining a highly reliable gate oxide. Moreover, silicon carbide MOSFET devices are usually used as power switches at high frequencies, and the main losses include switching losses and conduction losses. As the switching frequency increases, the proportion of switching losses in the total losses increases significantly. Summary of the Invention
[0004] The technical problem to be solved by the present disclosure is to overcome the above-mentioned defects in the prior art and provide a trench-type silicon carbide MOSFET, a module, and an electronic device.
[0005] The present disclosure solves the above technical problem through the following technical solutions:
[0006] The present disclosure provides a trench-type silicon carbide MOSFET, which includes: a metallized drain (1), an N-type silicon carbide substrate (2), an N-type silicon carbide epitaxial layer (3), a silicon dioxide interlayer dielectric (10), and a metallized source (12) from bottom to top;
[0007] The metallized source (12) is respectively connected to the top of the N-type silicon carbide epitaxial layer (3) and the top of the silicon dioxide interlayer dielectric (10);
[0008] The N-type silicon carbide epitaxial layer (3) includes gate trenches;
[0009] The gate trenches are located in the middle of the top of the N-type silicon carbide epitaxial layer (3) and are formed by etching. A gate (7) and a shielding gate (8) are vertically arranged in the gate trenches. The gate (7) is located above the shielding gate (8). The gate (7) and the shielding gate (8) are surrounded and separated by the silicon dioxide interlayer dielectric (10), and the top of the shielding gate (8) is connected to the source potential.
[0010] Optionally, the N-type silicon carbide epitaxial layer (3) further includes: a P-type body region (4), a source trench P+ contact region (5-1), a gate trench sidewall P+ contact region (5-2), a gate trench bottom P+ contact region (5-3), an N+ source region (6), and an N-type carrier layer (9);
[0011] The N+ source region (6) is located at the top of the N-type silicon carbide epitaxial layer (3) and is distributed on the left and right sides of the gate trench;
[0012] The P-type body region (4) is located below the N+ source region (6) and is distributed on the left and right sides of the source trench. A source trench (11) is provided between the N+ source region (6) and the P-type body region (4);
[0013] The source trench P+ contact region (5-1) is located within the P-type body region (4) and is periodically provided below the metallized source (12);
[0014] The gate trench bottom P+ contact region (5-3) is provided at the bottom of the gate trench, the gate trench sidewall P+ contact region (5-2) is provided on the left sidewall of the gate trench, and the N-type carrier layer (9) is provided on the right sidewall of the gate trench.
[0015] Optionally, the shield gate is a multi-level stepped polysilicon. The number of polysilicon layers is at least three and is vertically arranged, and the doping types of adjacent two polysilicon layers are opposite. The polysilicon at the top layer close to the gate side is connected to the source potential.
[0016] Optionally, the shield gate includes three layers of doped polysilicon stacked in a direction perpendicular to the bottom of the gate trench;
[0017] The polysilicon at the top layer is heavily doped N-type polysilicon with a doping concentration of 1E20 cm -3 to achieve effective ohmic contact with the source electrode;
[0018] The polysilicon at the middle layer is P-type polysilicon, and the polysilicon at the bottom layer is N-type polysilicon. The doping concentrations of each layer of polysilicon gradually decrease from top to bottom, and the doping concentration of the polysilicon at the bottom layer is the lowest.
[0019] Optionally, the gate trench sidewall P+ contact region (5-2) is periodically connected to the P-type body region (4), and adjacent two gate trench sidewall P+ contact regions (5-2) are separated by the N-type carrier layer (9).
[0020] Optionally, the trench-type silicon carbide MOSFET further includes: a source trench (11);
[0021] The source trench P+ contact region (5-1) is periodically disposed below the source trench (11), and the source trench P+ contact region (5-1) is connected to the metallized source (12) through the source trench (11).
[0022] Optionally, the etching depths of two adjacent source trenches (11) are different, and each source trench (11) forms a contact with the corresponding source trench P+ contact region (5-1) or Schottky metal (13).
[0023] Optionally, the source trench P+ contact regions (5-1) below each source trench (11) are arranged at intervals along the length direction of the source trench (11) to form an ohmic contact with the corresponding source trench (11).
[0024] The present disclosure also provides a module, which includes the foregoing trench-type silicon carbide MOSFET.
[0025] The present disclosure also provides an electronic device, which includes the foregoing module.
[0026] On the basis of conforming to the common knowledge in the art, the above preferred conditions can be combined arbitrarily to obtain various preferred examples of the present disclosure.
[0027] The positive and progressive effects of the present disclosure are as follows: By providing a shielding gate in the gate trench, it is possible to reduce both the drain-source capacitance Cgd and the drain-source capacitance Cds on the basis of reducing the drain-source capacitance Cgd, avoiding an increase in the drain-source capacitance Cds. The shielding gate with a multi-stage stepped sandwich NPN structure has a better effect; by introducing a source trench, changing the lateral ohmic contact to a vertical contact, reducing the source contact size, introducing the surface P+ contact region to the bottom of the P-type body region, short-circuiting the ohmic contacts between the source and the N+ source region and the P-type body region simultaneously, achieving a smaller N+ source region width, thereby reducing the size of the entire cell region, reducing the device size, and increasing the current density of the device; at the same time, a gate trench bottom P+ contact region and a gate trench sidewall P+ contact region are respectively provided at the bottom and sidewalls of the gate trench, that is, the P+ region protects the gate oxide to achieve the protection of the gate trench, and N-type carrier layers are injected between two P+ contact regions and on the right side of the gate trench, reducing the channel resistance and increasing the current density. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 It is a structural diagram of a trench-type silicon carbide MOSFET provided in Embodiment 1 of the present disclosure;
[0029] Figure 2 It is a structural diagram of a specific embodiment without an integrated Schottky diode of a trench-type silicon carbide MOSFET provided in Embodiment 1 of the present disclosure;
[0030] Figure 3 Structural diagram of the source contact region of a specific embodiment of a trench-type silicon carbide MOSFET provided in Embodiment 1 of the present disclosure;
[0031] Figure 4 Component of the drain-source capacitance Cds2 of a specific embodiment of a trench-type silicon carbide MOSFET provided in Embodiment 1 of the present disclosure;
[0032] Figure 5 Equivalent circuit for calculating the drain-source capacitance Cds2 of a specific embodiment of a trench-type silicon carbide MOSFET provided in Embodiment 1 of the present disclosure;
[0033] Figure 6 Structural diagram of the left sidewall P+ region of a specific embodiment of a trench-type silicon carbide MOSFET provided in Embodiment 1 of the present disclosure. Specific embodiment
[0034] The present disclosure will be further described below by way of examples, but the present disclosure is not limited to the scope of the described examples.
[0035] In the embodiments of the present disclosure, prefix words such as "first" and "second" are only used to distinguish different described objects, and have no limiting effect on the position, order, priority, quantity, content, etc. of the described objects. The use of ordinal numbers and other prefix words for distinguishing described objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. The description of the described objects refers to the description in the claims or the context of the embodiments, and no redundant limitation should be formed due to the use of such prefix words. In addition, in the description of this embodiment, unless otherwise specified, the meaning of "a plurality" is two or more.
[0036] Embodiment 1
[0037] Figure 1 Structural diagram of a trench-type silicon carbide MOSFET provided in Embodiment 1 of the present disclosure. The trench-type silicon carbide MOSFET includes: a metallized drain (1), an N-type silicon carbide substrate (2), an N-type silicon carbide epitaxial layer (3), a silicon dioxide interlayer dielectric (10), and a metallized source (12) from bottom to top.
[0038] The metallized source (12) is respectively connected to the top of the N-type silicon carbide epitaxial layer (3) and the top of the silicon dioxide interlayer dielectric (10).
[0039] The N-type silicon carbide epitaxial layer (3) includes gate trenches.
[0040] The gate trench is located at the top middle of the N-type silicon carbide epitaxial layer (3) and is formed by etching. A gate (7) and a shielding gate (8) are vertically arranged in the gate trench. The gate (7) is located above the shielding gate (8). The gate (7) and the shielding gate (8) are surrounded and separated by a silicon dioxide interlayer dielectric (10). The top of the shielding gate (8) is connected to the source potential.
[0041] Among them, the shielding gate (8) may include a top-layer shielding gate (8-1), a middle-layer shielding gate (8-2), and a bottom-layer shielding gate (8-3) arranged in a stepped manner.
[0042] By etching a source trench in the middle between the vertically arranged N+ source region and the P-type body region, the lateral ohmic contact can be changed to a vertical contact, reducing the source contact size. The surface P+ contact region is introduced to the bottom of the P-type body region, and the ohmic contacts of the source with the N+ source region and the P-type body region are short-circuited simultaneously. The initial structure of the P+ contact region on the surface is as Figure 1 shown, and a smaller N+ source region width can be achieved, thereby reducing the size of the entire cell region and increasing the current density of the device.
[0043] In this embodiment, a trench-type shielding gate silicon carbide MOSFET device structure without an integrated Schottky diode can be realized, as Figure 2 shown. A trench-type shielding gate silicon carbide MOSFET device structure with an integrated Schottky diode can also be realized. To integrate the Schottky diode, source trenches with different depths can be etched and arranged at intervals, as Figure 3 shown. A source trench P+ contact region is provided under the source trench with a shallower etching depth, and there is no P+ implantation under the source trench with a deeper etching depth. Titanium metal Ti is deposited in the source trench and directly contacts the N-type epitaxial layer to form a Schottky contact. Integrating a Schottky diode in the source trench can reduce the reverse recovery loss.
[0044] In particular, by introducing a shielding gate between the gate and the drain, the gate-drain Cgd capacitance of the overlapping part of the gate electrode and the source electrode is significantly reduced. Since the shielding gate is connected to the source electrode, the gate-source capacitance Cgs has an additional capacitance part Cgs2 of the overlapping polysilicon of the gate and the source. The bottom of the source polysilicon overlaps with the drain, increasing the drain-source capacitance Cds2. To reduce the introduced drain-source capacitance Cds2, a shielding gate is arranged in the source trench, including at least three doped layers stacked in a direction perpendicular to the bottom of the trench, and their depths are kept consistent, all being 1 / 3 of the total depth of the source polysilicon. The top layer is a heavily doped N-type polysilicon, and the doping concentration range is about 1E20 cm -3 or so, and the doping concentration range can be set according to actual needs to achieve an effective ohmic contact of the source electrode.
[0045] The doping types of adjacent two layers are opposite. In the case where the number of doped layers is three, the middle layer is P-type polysilicon, and the bottom layer is set as N-type polysilicon. The PN junction capacitances of two adjacent layers are connected in series with the introduced drain-source capacitance Cds2 to achieve the reduction of Cds2. The components of the drain-source capacitance Cds2 are as Figure 4 and Figure 5 shown. The doping concentration of each layer of polysilicon gradually decreases from top to bottom, and the doping concentration of the bottom N-type polysilicon is the lowest. Similarly, the width of the three-layer doped layer gradually decreases from top to bottom, reducing the overlapping area between PN junctions to achieve the reduction of the PN junction capacitance and further reducing the magnitude of the drain-source capacitance Cds2.
[0046] A gate oxide protection structure can also be set at the bottom of the trench to improve the electronic performance of the device. The gate oxide protection structure at the bottom of the trench can adopt a direct shielding type, and high-concentration P+ is injected at the bottom and sidewalls of the gate trench to protect the trench. As Figure 6 shown, the P+ on the sidewall of the gate trench is periodically injected, and N-type carrier layers are injected between two P+ contact regions and on the right side of the gate trench, reducing the channel resistance and increasing the current density.
[0047] In this embodiment, through the structure of the trench-type silicon carbide MOSFET, it is finally possible to achieve, on the basis of a high breakdown voltage, the reduction of the device cell size and on-resistance, the reduction of the gate-drain capacitance while improving the problem of the increase in the drain-source capacitance. At the same time, a Schottky diode is integrated in the source trench, reducing the switching loss and achieving higher performance.
[0048] In this embodiment, by setting a shielding gate in the gate trench, it is possible to reduce both the drain-source capacitance Cgd and the drain-source capacitance Cds on the basis of reducing the drain-source capacitance Cds, avoiding the increase in the drain-source capacitance Cds. The shielding gate with a multi-stage stepped sandwich NPN structure has a better effect. By introducing the source trench, the lateral ohmic contact is changed to a vertical contact, reducing the source contact size, introducing the surface P+ contact region to the bottom of the P-type body region, and shorting the ohmic contacts of the source with the N+ source region and the P-type body region simultaneously, achieving a smaller N+ source region width, thereby reducing the size of the entire cell region, reducing the device size, and increasing the current density of the device. At the same time, a P+ contact region at the bottom of the gate trench and a P+ contact region on the sidewall of the gate trench are respectively set at the bottom and sidewalls of the gate trench, that is, the P+ region protects the gate oxide to achieve the protection of the gate trench, and N-type carrier layers are injected between two P+ contact regions and on the right side of the gate trench, reducing the channel resistance and increasing the current density.
[0049] In one embodiment, as Figure 2As shown, the N-type silicon carbide epitaxial layer (3) further includes: a P-type body region (4), a source trench P+ contact region (5-1), a gate trench sidewall P+ contact region (5-2), a gate trench bottom P+ contact region (5-3), an N+ source region (6), and an N-type carrier layer (9).
[0050] The N+ source region (6) is located at the top of the N-type silicon carbide epitaxial layer (3) and is distributed on the left and right sides of the gate trench.
[0051] The P-type body region (4) is located below the N+ source region (6) and is distributed on the left and right sides of the source trench. A source trench (11) is provided in the middle of the N+ source region (6) and the P-type body region (4).
[0052] The source trench P+ contact region (5-1) is located in the P-type body region (4) and is periodically provided below the metallized source (12).
[0053] The gate trench bottom P+ contact region (5-3) is provided at the bottom of the gate trench, the gate trench sidewall P+ contact region (5-2) is provided on the left sidewall of the gate trench, and the N-type carrier layer (9) is provided on the right sidewall of the gate trench.
[0054] Among them, by etching a source trench in the middle of the vertically arranged N+ source region and the P-type body region, changing the lateral ohmic contact to a vertical contact, reducing the source contact size, introducing the surface P+ contact region to the bottom of the P-type body region, short-circuiting the ohmic contacts of the source with the N+ source region and the P-type body region at the same time, the initial structure of the P+ contact region located on the surface is as Figure 1 shown, a smaller N+ source region width can be achieved, thereby reducing the size of the entire cell region and increasing the current density of the device.
[0055] In one embodiment, as Figure 1 、 Figure 2 、 Figure 3 and Figure 6 shown, the shield gate is a multi-stage stepped polysilicon, the number of polysilicon layers is vertically arranged at least three layers, and the doping types of adjacent two layers of polysilicon are opposite. The polysilicon on the top layer close to the gate side is connected to the source potential.
[0056] Among them, the shield gate provided in the source trench includes at least three doped layers stacked in a direction perpendicular to the bottom of the trench, and their depths are kept consistent, all being 1 / 3 of the total source polysilicon depth.
[0057] The top layer (8-1) can be set as heavily doped N-type polysilicon from top to bottom in sequence, and the doping concentration range can be about 1E20 cm -3 or the doping concentration range can be set according to actual needs to achieve effective ohmic contact of the source electrode.
[0058] The doping types of adjacent two layers are opposite. When the number of doping layers is three, the middle layer (8-2) is made of P-type polysilicon, and the bottom layer (8-3) is set as N-type polysilicon. The doping concentration of each polysilicon layer gradually decreases from top to bottom, and the doping concentration of the bottom N-type polysilicon is the lowest. The widths of the three doping layers also gradually decrease from top to bottom, reducing the overlapping area of the PN junction capacitance and further reducing the drain-source capacitance.
[0059] Refer to Figure 4 and Figure 5 , the polysilicon source is set, introducing gate-source capacitance Cgs2 and drain-source capacitance Cds2. Among them, Cds2 includes the capacitance Cp1 formed by the N-type polysilicon 8-1 at the top of the polysilicon shielding gate and the P+ contact region (5-2) of the gate trench sidewall on the left side of the trench, plus the capacitance Cp2 formed by the P+ contact region (5-2) of the gate trench sidewall and the N-type epitaxial layer, the capacitance Cp3 formed by the N-type polysilicon (8-3) at the bottom of the polysilicon shielding gate and the P+ contact region (5-3) at the bottom of the gate trench, plus the capacitance Cp4 formed by the P+ contact region (5-3) at the bottom of the gate trench and the N-type silicon carbide epitaxial layer (3), plus the series-connected Cj1 and Cj2 formed by the PN junction capacitances between adjacent two.
[0060] The PN junction capacitances between adjacent two are connected in series with the introduced drain-source capacitance Cds2 to reduce Cds2. The components of the drain-source capacitance Cds2 are as Figure 4 and Figure 5 shown. The doping concentration of each polysilicon layer gradually decreases from top to bottom, and the doping concentration of the bottom N-type polysilicon is the lowest. Similarly, the widths of the three doping layers gradually decrease from top to bottom, reducing the overlapping area between the PN junctions and reducing the PN junction capacitance, further reducing the magnitude of the drain-source capacitance Cds2.
[0061] More specifically, the P+ contact region (5-2) of the gate trench sidewall at the top of the N-type silicon carbide epitaxial layer (3) is set to be periodically connected to the P-type body region (4), and an N-type carrier layer (9) is arranged between two adjacent P+ contact regions (5-2) of the gate trench sidewall, increasing the current density and reducing the on-resistance while making the P+ contact region (5-2) of the gate trench sidewall connected to the source potential.
[0062] Refer to Figure 3, by etching the source trench (11) between the vertically arranged N+ source region (6) and the P-type body region (4), the lateral ohmic contact is changed to a vertical contact, reducing the source contact size. The P+ region on the surface is introduced to the bottom of the P-type body region (4), shorting the ohmic contacts of the source with the N+ source region (6) and the P-type body region (4) simultaneously. The etching depths of adjacent source trenches (11) are different. A source trench P+ contact region (5-1) is provided under the source trench (11) with a shallower etching depth, and there is no P+ implantation under the source trench (11) with a deeper etching depth. Titanium metal Ti (13) is deposited in the trench, directly contacting the N-type silicon carbide epitaxial layer (3) to form a Schottky contact. A Schottky diode is integrated in the source trench (11), and at the same time, the ohmic contact between the N+ source region (6) and the source trench P+ contact region (5-1) is also achieved.
[0063] In one embodiment, the shield gate includes three-layer doped polysilicon stacked in a direction perpendicular to the bottom of the gate trench.
[0064] The top polysilicon is heavily doped N-type polysilicon with a doping concentration of 1E20 cm -3 , to achieve an effective ohmic contact of the source electrode.
[0065] The middle polysilicon is P-type polysilicon, and the bottom polysilicon is N-type polysilicon, and the doping concentrations of each layer of polysilicon gradually decrease from top to bottom, with the lowest doping concentration of the bottom polysilicon.
[0066] In one embodiment, as Figure 1 、 Figure 2 and Figure 6 shown, the gate trench sidewall P+ contact region (5-2) is periodically connected to the P-type body region (4), and adjacent two gate trench sidewall P+ contact regions (5-2) are separated by an N-type carrier layer (9).
[0067] In one embodiment, as Figure 2 shown, the trench-type silicon carbide MOSFET further includes: a source trench (11).
[0068] The source trench P+ contact region (5-1) is periodically arranged under the source trench (11), and the source trench P+ contact region (5-1) is connected to the metallized source (12) through the source trench (11).
[0069] In one embodiment, as Figure 3 shown, the etching depths of adjacent two source trenches (11) are different, and each source trench (11) forms a contact with the corresponding source trench P+ contact region (5-1) or the Schottky metal (13).
[0070] Among them, the Schottky metal (13) can use metal titanium.
[0071] In one embodiment, as Figure 6 shown, the source trench P+ contact regions (5-1) below each source trench (11) are arranged at intervals along the length direction of the source trench (11) and form ohmic contacts with the corresponding source trenches (11).
[0072] Embodiment 2
[0073] This embodiment provides a module, and the module includes the trench-type silicon carbide MOSFET in Embodiment 1.
[0074] In this embodiment, by arranging a shielding gate in the gate trench, it is possible to simultaneously reduce the drain-source capacitance Cds while reducing the drain-gate capacitance Cgd, avoiding an increase in the drain-source capacitance Cds. A multi-stage stepped sandwich NPN structure for the shielding gate has a better effect; by introducing source trenches, changing the lateral ohmic contact to a vertical contact, reducing the source contact size, introducing the surface P+ contact region to the bottom of the P-type body region, shorting the ohmic contacts of the source with the N+ source region and the P-type body region simultaneously, achieving a smaller N+ source region width, thereby reducing the size of the entire cell region, reducing the device size, and increasing the current density of the device; at the same time, a P+ contact region at the bottom of the gate trench and a P+ contact region on the sidewall of the gate trench are respectively arranged at the bottom and sidewalls of the gate trench, that is, the P+ region protects the gate oxide to achieve the protection of the gate trench, and N-type carrier layers are injected between every two P+ contact regions and on the right side of the gate trench, reducing the channel resistance and increasing the current density.
[0075] Embodiment 3
[0076] This embodiment provides an electronic device, and the electronic device includes the module in Embodiment 2.
[0077] In this embodiment, by arranging a shielding gate in the gate trench, it is possible to simultaneously reduce the drain-source capacitance Cds while reducing the drain-gate capacitance Cgd, avoiding an increase in the drain-source capacitance Cds. A multi-stage stepped sandwich NPN structure for the shielding gate has a better effect; by introducing source trenches, changing the lateral ohmic contact to a vertical contact, reducing the source contact size, introducing the surface P+ contact region to the bottom of the P-type body region, shorting the ohmic contacts of the source with the N+ source region and the P-type body region simultaneously, achieving a smaller N+ source region width, thereby reducing the size of the entire cell region, reducing the device size, and increasing the current density of the device; at the same time, a P+ contact region at the bottom of the gate trench and a P+ contact region on the sidewall of the gate trench are respectively arranged at the bottom and sidewalls of the gate trench, that is, the P+ region protects the gate oxide to achieve the protection of the gate trench, and N-type carrier layers are injected between every two P+ contact regions and on the right side of the gate trench, reducing the channel resistance and increasing the current density.
[0078] Although the specific embodiments of the present disclosure have been described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Without departing from the principles and essence of the present disclosure, those skilled in the art can make various changes or modifications to these embodiments, but these changes and modifications all fall within the protection scope of the present disclosure.
Claims
1. A trench silicon carbide MOSFET, characterized in that: The trench silicon carbide MOSFET comprises: from bottom to top, a metallized drain (1), an N-type silicon carbide substrate (2), an N-type silicon carbide epitaxial layer (3), a silicon dioxide interlayer dielectric (10), and a metallized source (12); The metallized source (12) is respectively connected to the top of the N-type silicon carbide epitaxial layer (3) and the top of the silicon dioxide interlayer dielectric (10); The N-type silicon carbide epitaxial layer (3) comprises a gate trench; The gate trench is located in the middle of the top of the N-type silicon carbide epitaxial layer (3) and is formed by etching. A gate (7) and a shielding gate (8) are vertically arranged in the gate trench. The gate (7) is located above the shielding gate (8). The gate (7) and the shielding gate (8) are surrounded and separated by the silicon dioxide interlayer dielectric (10). The top of the shielding gate (8) is connected to a source potential.
2. The trench silicon carbide MOSFET according to claim 1, characterized in that: The N-type silicon carbide epitaxial layer (3) further comprises: a P-type body region (4), a source trench P+ contact region (5-1), a gate trench sidewall P+ contact region (5-2), a gate trench bottom P+ contact region (5-3), an N+ source region (6) and an N-type carrier layer (9); The N+ source region (6) is located on the top of the N-type silicon carbide epitaxial layer (3) and is distributed on the left and right sides of the gate trench; The P-type body region (4) is located below the N+ source region (6) and is distributed on the left and right sides of the source trench. A source trench (11) is provided between the N+ source region (6) and the P-type body region (4); The source trench P+ contact region (5-1) is located in the P-type body region (4) and is periodically arranged below the metallized source (12); The bottom of the gate trench is provided with the gate trench bottom P+ contact area (5-3), the left side wall of the gate trench is provided with the gate trench side wall P+ contact area (5-2), and the right side wall of the gate trench is provided with the N-type carrier layer (9).
3. The trench silicon carbide MOSFET according to claim 1, characterized in that: The shielding gate is multi-step polysilicon, the number of layers of the polysilicon is at least three layers vertically arranged, and the doping types of two adjacent layers of polysilicon are opposite. The top layer of the multi-step polysilicon close to the gate side is connected to the source potential.
4. The trench silicon carbide MOSFET according to claim 3, characterized in that: The shielding gate includes three layers of doped polysilicon stacked in a direction perpendicular to the bottom of the gate trench; The top layer of polysilicon is heavily doped N-type polysilicon with a doping concentration of 1E20cm -3 , to achieve effective ohmic contact with the source electrode; The polysilicon in the middle layer is P-type polysilicon, the polysilicon in the bottom layer is N-type polysilicon, and the doping concentration of each layer of polysilicon decreases gradually from top to bottom, and the doping concentration of the polysilicon in the bottom layer is the lowest.
5. The trench silicon carbide MOSFET according to claim 2, characterized in that: The gate trench sidewall P+ contact region (5-2) is periodically connected to the P-type body region (4), and two adjacent gate trench sidewall P+ contact regions (5-2) are separated by the N-type carrier layer (9).
6. The trench silicon carbide MOSFET according to claim 2, characterized in that: The trench-type silicon carbide MOSFET further comprises: a source trench (11); The source trench P+ contact region (5-1) is periodically arranged below the source trench (11), and the source trench P+ contact region (5-1) is connected to the metallized source (12) through the source trench (11).
7. The trench silicon carbide MOSFET according to claim 6, characterized in that: The etching depths of two adjacent source trenches (11) are different, and each source trench (11) forms contact with the corresponding source trench P+ contact area (5-1) or Schottky metal (13).
8. The trench silicon carbide MOSFET according to claim 6, characterized in that: The source trench P+ contact regions (5-1) below each source trench (11) are arranged to be spaced apart along the length direction of the source trench (11) to form ohmic contact with the corresponding source trench (11).
9. A module, characterized in that: The module includes the trench silicon carbide MOSFET according to any one of claims 1 to 8.
10. An electronic device, characterized in that: The electronic device comprises the module according to claim 9.