Thin film transistor, array substrate and display device

Abstract

The embodiment of the invention provides a thin film transistor, an array substrate and a display device, relates to the technical field of display, and aims to solve the problem that a display picture of the display device flickers. The thin film transistor includes a control electrode, an active layer, a first conductive pattern, and a second electrode. Wherein the control electrode, the active layer and the first conductive pattern are sequentially arranged on the substrate in a stacked mode, in the direction perpendicular to the substrate, the part, right opposite to the active layer, of the first conductive pattern is a first electrode of the thin film transistor, and in the first direction, the active layer exceeds the first electrode. The second electrode and the first electrode are oppositely arranged in the second direction, the part, located between the first electrode and the second electrode, in the active layer is a channel of the thin film transistor, and the orthographic projection of the channel on the substrate is located within the orthographic projection of the control electrode on the substrate. Wherein the first direction and the second direction are parallel to the substrate, and the first direction and the second direction intersect.

Description

[0001] This application is a divisional application. The original application was filed on September 8, 2021, with the application number 202111050808.7. The entire content of the original application is incorporated herein by reference. Technical Field

[0002] The present invention relates to the field of display technologies, and particularly to a thin film transistor, an array substrate, and a display device. Background Art

[0003] Liquid Crystal Displays (LCDs) have been widely popularized and gradually become mainstream products due to their small size, low power consumption, no radiation, and high display resolution.

[0004] In current liquid crystal display devices, there is a phenomenon of display screen flickering. Especially in liquid crystal display devices with a low refresh rate, the phenomenon of display screen flickering is particularly obvious, affecting the display effect of the liquid crystal display device. Summary of the Invention

[0005] Embodiments of the present invention provide a thin film transistor, an array substrate, and a display device to improve the problem of display screen flickering of the display device.

[0006] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0007] In a first aspect, a thin film transistor is provided, including a control electrode, an active layer, a first conductive pattern, and a second electrode. The control electrode, the active layer, and the first conductive pattern are sequentially stacked on a substrate. In a direction perpendicular to the substrate, the part of the first conductive pattern facing the active layer is the first electrode of the thin film transistor. In a first direction, the active layer extends beyond the first electrode. The second electrode and the first electrode are disposed opposite to each other in a second direction. The part of the active layer located between the first electrode and the second electrode is the channel of the thin film transistor. The orthographic projection of the channel on the substrate is located within the orthographic projection of the control electrode on the substrate. The first direction and the second direction are parallel to the substrate, and the first direction and the second direction intersect.

[0008] In some embodiments, the first conductive pattern is a long strip extending in the second direction, and the first electrode is located at one end of the first conductive pattern in the second direction.

[0009] In some embodiments, the active layer includes a first extending portion located on at least one side of the first electrode in the first direction, and the width of the first extending portion is greater than or equal to 2.5 μm.

[0010] In some embodiments, in the second direction, the control electrode extends beyond the channel.

[0011] In some embodiments, the control electrode includes a second overhang portion located on at least one side of the channel along the second direction, and the width of the second overhang portion is greater than or equal to 2.5 μm.

[0012] In some embodiments, the control electrode includes a first edge, and the active layer includes a second edge. The first edge and the second edge are located on the same side of the channel along the second direction, and the first edge is located on the side closer to the channel than the second edge.

[0013] In some embodiments, in the first direction, the active layer extends beyond the second electrode.

[0014] In a second aspect, an array substrate is provided, including a substrate and thin film transistors disposed on the substrate. The thin film transistors are the thin film transistors provided in any of the above embodiments.

[0015] In some embodiments, the array substrate further includes a pixel electrode disposed on the substrate, and the pixel electrode is coupled to the first electrode of the thin film transistor.

[0016] In some embodiments, the array substrate further includes a second conductive pattern disposed on the substrate. The second conductive pattern is located on the side of the first conductive pattern away from the second electrode along the second direction. The second conductive pattern and the first conductive pattern are coupled and form an integral pattern, and the second conductive pattern is coupled to the pixel electrode. The second conductive pattern protrudes from the first conductive pattern in the first direction, and the distance between the control electrode and the second conductive pattern in the second direction is greater than or equal to 3 μm.

[0017] In some embodiments, the array substrate further includes a data line. The data line and the first conductive pattern are disposed on the same layer. In the direction perpendicular to the substrate, the portion of the data line opposite to the active layer is the second electrode of the thin film transistor.

[0018] In some embodiments, in the thin film transistor, in the first direction, the active layer extends beyond the second electrode. The array substrate further includes a data line. The data line is located on the side of the second electrode away from the first electrode, the data line is coupled to the second electrode, and the data line and the second electrode form an integral pattern.

[0019] In a third aspect, a display device is provided, including the array substrate provided in any of the above embodiments.

[0020] In some embodiments, the refresh rate of the display device is less than or equal to 40 Hz.

[0021] In the thin-film transistor provided by the embodiment of the present disclosure, the portion of the first conductive pattern facing the active layer is the first pole of the thin-film transistor. Moreover, in the first direction, the active layer extends beyond the first pole, that is, the size of the end portion of the first conductive pattern close to the active layer in the first direction is smaller than the size of the end portion of the active layer close to the first conductive pattern in the first direction. In this way, the size of the end portion of the first conductive pattern close to the active layer in the first direction can be smaller. On the premise that the size of the control pole extending beyond the channel in the first direction and / or the second direction is certain, in the direction perpendicular to the substrate, the area of the first conductive pattern facing the control pole can be smaller, so that the capacitance of the capacitor formed by the first conductive pattern and the control pole can be smaller, and the problem of display screen flicker of the display panel can be improved.

[0022] It can be understood that the array substrate described in the second aspect and the display device described in the third aspect include the above-mentioned thin-film transistor. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the thin-film transistor in the above text, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 A top view of a display device provided by some embodiments of the present disclosure;

[0025] Figure 2 For Figure 1 the cross-sectional view of the display device in

[0026] Figure 3 For Figure 1 the cross-sectional view of the display device in

[0027] Figure 4 A top view of an array substrate provided by some embodiments of the present disclosure;

[0028] Figure 5A A top view of a thin-film transistor provided by some embodiments of the present disclosure;

[0029] Figure 5B For Figure 5A the cross-sectional view of the thin-film transistor in

[0030] Figure 6 A microscopic morphology diagram of an array substrate provided by some embodiments of the present disclosure;

[0031] Figure 7 It is a top view of a thin film transistor in the related art;

[0032] Figure 8 It is a top view of a thin film transistor provided by some embodiments of the present disclosure;

[0033] Figure 9 It is a top view of a thin film transistor provided by some embodiments of the present disclosure;

[0034] Figure 10 It is a top view of a thin film transistor provided by some embodiments of the present disclosure;

[0035] Figure 11 It is a top view of another thin film transistor provided by some embodiments of the present disclosure;

[0036] Figure 12A It is a microscopic morphology diagram of an array substrate provided by some embodiments of the present disclosure;

[0037] Figure 12B It is a partial enlarged view of an array substrate provided by some embodiments of the present disclosure;

[0038] Figure 13 It is for Figure 12B a cross-sectional view of the array substrate in [reference] along the section line CC';

[0039] Figure 14 It is a top view of an array substrate provided by some embodiments of the present disclosure;

[0040] Figure 15 It is a top view of an array substrate provided by some embodiments of the present disclosure;

[0041] Figure 16 It is a top view of another array substrate provided by some embodiments of the present disclosure;

[0042] Figure 17 It is a schematic diagram of the verification result of the process stability of the thin film transistor characteristics provided by some embodiments of the present disclosure;

[0043] Figure 18 and Figures 19A - 19D It is a schematic diagram of the LPDT test result of the display device provided by some embodiments of the present disclosure. Detailed implementation manners

[0044] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0045] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms such as the third-person singular form "comprises" and the present participle form "comprising" are interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily directed to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0048] In describing some embodiments, the terms "coupled" and "connected" and their derivatives may be used. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other. As another example, in describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0049] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0050] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0051] "Plurality" means at least two.

[0052] The use of "suitable for" or "configured to" herein means open and inclusive language, which does not exclude devices suitable for or configured to perform additional tasks or steps.

[0053] In addition, the use of "based on" means open and inclusive, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0054] As used herein, "about", "approximate", or "substantially" includes the stated value and the average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by one of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0055] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0056] Some embodiments of the present disclosure provide a display device. The display device is a product with an image display function. For example, the display device may be any one of a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a portable video camera, a viewfinder, a navigator, a vehicle, a large-area wall, a household appliance, an information query device (such as a business query device in departments such as e-government, banks, hospitals, and power), and a monitor.

[0057] The display device may be a display panel, or the display device may also be a product including a display panel and a driving circuit, wherein the driving circuit is coupled to the display panel and is configured to drive the display panel to display an image.

[0058] In some embodiments, the display panel may be an OLED (Organic Light Emitting Diode) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro-LED (including: miniLED or microLED, LED is a light emitting diode) display panel, etc.

[0059] In other embodiments, the display panel may be a liquid crystal display panel. Exemplarily, the liquid crystal display panel may be an ADS (Advanced-Super Dimensional Switching) type liquid crystal display panel or an IPS (In Plane Switch) type liquid crystal display panel. Since the liquid crystal molecules only modulate light and do not emit light by themselves, in some possible implementation manners, in order to implement the image display function of the display device including the liquid crystal display panel, the display device may further include a backlight module. Exemplarily, the backlight module is disposed on the back of the liquid crystal display panel (i.e., the side facing away from the display surface), and the backlight module is configured to provide backlight to the liquid crystal display panel. The embodiments of the present disclosure do not limit the type of the backlight module. Exemplarily, the backlight module may be a side-entry type backlight module or a direct-lit type backlight module.

[0060] Figure 1 The structure of the display panel is shown. Refer to Figure 1, the display panel 1 has a plurality of sub-pixel regions P. Specifically, the plurality of sub-pixel regions P may include sub-pixel regions of different colors, and the light-emitting colors of the sub-pixel regions of different colors are different. Exemplarily, the plurality of sub-pixel regions P include sub-pixel regions of the three primary colors, such as a red sub-pixel region, a green sub-pixel region, and a blue sub-pixel region. By controlling the light-emitting brightness of the plurality of sub-pixel regions P with different light-emitting colors, the display panel 1 can be controlled to display a picture with a specific color, so as to realize the image display function of the display panel 1.

[0061] See Figure 2 , Figure 2 is Figure 1 a cross-sectional view of the display panel in along the section line AA’, showing the structure of a sub-pixel region of the display panel. In some embodiments, the display panel 1 is any one of an OLED display panel, a QLED display panel, and a micro-LED display panel. At this time, the display panel 1 includes an array substrate 10, and may further include at least one (for example, one; or, a plurality of) light-emitting devices 20. One light-emitting device 20 may be provided in one sub-pixel region (for example, each sub-pixel region). The light-emitting device 20 may include a first electrode 21, a second electrode 22, and a light-emitting functional layer 23 located between the first electrode 21 and the second electrode 22. At least one light-emitting device 20 may be disposed on the array substrate 10 and coupled to the array substrate 10. For example, the first electrode 21 of the light-emitting device 20 may be coupled to the array substrate 10. The array substrate 10 may be configured to deliver an electrical signal to at least one light-emitting device 20 to drive at least one light-emitting device 20 to emit light, thereby realizing the image display function of the display panel 1.

[0062] See Figure 3 , Figure 3 is Figure 1 a cross-sectional view of the display panel in along the section line AA’, showing the structure of a sub-pixel region of the display panel. In some embodiments, the display panel 1 is a liquid crystal display panel. At this time, the display panel 1 includes an array substrate 10, and may further include a counter substrate 30 and a liquid crystal layer 40 encapsulated between the array substrate 10 and the counter substrate 30. An electric field may be formed in the liquid crystal layer 40 through the array substrate 10, or through the array substrate 10 and the counter substrate 30. In response to this electric field, the liquid crystal molecules 40’ in the liquid crystal layer 40 may rotate, so that the transmittance of the light passing through the liquid crystal layer 40 is different, thereby the light-emitting brightness of each sub-pixel region of the display panel 1 can be controlled, and further the image display function of the display panel 1 can be realized.

[0063] Some embodiments of the present disclosure further provide an array substrate, which can be used in the display panel provided in any of the above embodiments.

[0064] See Figure 4, the array substrate 10 includes a substrate S (which can also be referred to as a substrate substrate). Exemplarily, the substrate S is a rigid substrate, such as a glass substrate or a PMMA (Polymethyl methacrylate) substrate. Also exemplarily, the substrate S is a flexible substrate, such as a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylenenaphthalate two formic acid glycol ester) substrate, a PI (Polyimide) substrate, or an ultra-thin glass, etc.

[0065] The array substrate 10 may further include a plurality of switching units SW disposed on the substrate S. In the array substrate 10, one switching unit SW may be disposed in one sub-pixel region P, and the respective switching units SW may be arranged in an array. The switching unit SW may be configured to control the emission brightness of the sub-pixel region P. Specifically, one switching unit SW (e.g., each switching unit SW) includes at least one thin-film transistor 100, that is, it can also be said that the array substrate 10 includes at least one (e.g., one; or, multiple) thin-film transistor 100, and at least one thin-film transistor 100 is disposed on the substrate S. By the on and off of at least one thin-film transistor 100, the switching unit SW can control the emission brightness of the sub-pixel region P, thereby realizing the image display function of the display panel.

[0066] In some embodiments, the array substrate 10 is an array substrate in any one of an OLED display panel, a QLED display panel, and a micro-LED display panel. At this time, one switching unit SW (e.g., each switching unit SW) in the array substrate 10 may include a plurality of thin-film transistors 100. In one switching unit SW, the respective thin-film transistors 100 may be coupled to each other to form a pixel driving circuit. In the display panel, the pixel driving circuit may be coupled to the light-emitting device, configured to drive the light-emitting device to emit light and control the emission brightness of the light-emitting device, and further control the light output brightness of the sub-pixel region to realize the image display function of the display panel.

[0067] In some other embodiments, the array substrate 10 is an array substrate in a liquid crystal display panel. At this time, in the array substrate 10, one switching unit SW (e.g., each switching unit SW) may include one thin-film transistor 100. At this time, in the array substrate 10, the respective thin-film transistors 100 may be arranged in an array.

[0068] Furthermore, the array substrate 10 may further include a pixel electrode 200 and a common electrode 300. The specific structures of the pixel electrode 200 and the common electrode 300 will be described below. One pixel electrode 200 and one common electrode 300 may be provided in one sub-pixel region P (for example, each sub-pixel P). Among them, the common electrode 300 is insulated from the pixel electrode 200. The common electrodes 300 in multiple sub-pixel regions P may be coupled to each other and configured to apply a common voltage Vcom. The pixel electrode 200 may be coupled to the switching unit SW. Specifically, the pixel electrode 200 may be coupled to the thin-film transistor 100 in the switching unit SW. The pixel electrode 200 may be configured to write an electrical signal, and this electrical signal may be an electrical signal related to the data signal Vdata. In one sub-pixel region P (for example, each sub-pixel region P), in response to the data signal Vdata and the common voltage Vcom, the pixel electrode 200 and the common electrode 300 may form an electric field in the liquid crystal layer located in this sub-pixel region P, thereby adjusting the light-emitting brightness of this sub-pixel region P in the liquid crystal display panel to achieve the image display function of the liquid crystal display panel. In some other possible implementation manners, the pixel electrode 200 is disposed in the array substrate 10, and the common electrode 300 may be disposed on the counter substrate of the liquid crystal display panel. That is to say, in the liquid crystal display panel, the array substrate 10 includes the pixel electrode 200, and the counter substrate may include the common electrode 300.

[0069] On this basis, the array substrate 10 may further include a data line DL and a gate line GL. The data line DL and the gate line GL may be coupled to at least one (for example, one; or multiple) thin-film transistor 100 in the switching unit SW and configured to write an electrical signal to the thin-film transistor 100.

[0070] In some embodiments of the present disclosure, a thin-film transistor is further provided, and this thin-film transistor may be used in the array substrate provided in any of the above embodiments.

[0071] Figure 5A It is a structural diagram of the thin-film transistor in some embodiments of the present disclosure. Figure 5B is Figure 5A a cross-sectional view of the thin-film transistor along the BB' section line in. Refer to Figure 5A and Figure 5B The thin-film transistor 100 includes a control electrode 110, an active layer 120, and a first conductive pattern 130.

[0072] Among them, the control electrode 110, the active layer 120, and the first conductive pattern 130 are sequentially stacked on the substrate S. That is, in the direction perpendicular to the substrate S (for example, parallel to the z-axis direction), the control electrode 110, the active layer 120, and the first conductive pattern 130 can be sequentially stacked. Exemplarily, the control electrode 110, the active layer 120, and the first conductive pattern 130 are sequentially arranged on the substrate S along the positive z-axis direction. As Figure 5B shown, the control electrode 110 is arranged on the substrate S, the active layer 120 is arranged on the side of the control electrode 110 away from the substrate S, and the first conductive pattern 130 is arranged on the side of the active layer 120 away from the substrate S. Another example is that the control electrode 110, the active layer 120, and the first conductive pattern 130 are sequentially arranged on the substrate S along the negative z-axis direction. That is, the first conductive pattern 130 is arranged on the substrate S, the active layer 120 is arranged on the side of the first conductive pattern 130 away from the substrate S, and the control electrode 110 is arranged on the side of the active layer 120 away from the substrate S.

[0073] It should be noted that the substrate S can be configured to carry the thin film transistor 100, and the thin film transistor in the embodiments of the present disclosure does not include the substrate S. The type and material of the substrate S can refer to the above description and will not be elaborated here. In some embodiments, the substrate S can be the substrate of an array substrate including the thin film transistor 100.

[0074] The material of the control electrode 110 can be a conductive material. Exemplarily, the material of the control electrode 110 is a metal or an alloy. The material of the first conductive pattern 130 can be a conductive material. Exemplarily, the material of the first conductive pattern 130 can be a metal or an alloy. The material of the active layer 120 can be a semiconductor material. Exemplarily, the material of the active layer 120 is, for example, amorphous silicon, IGZO (Indium Gallium Zinc Oxide).

[0075] The thin film transistor 100 may further include a gate insulating layer GI. The gate insulating layer GI is arranged between the control electrode 110 and the active layer 120. Exemplarily, in the direction perpendicular to the substrate S, the gate insulating layer GI can be arranged between the control electrode 110 and the active layer 120. Since the gate insulating layer GI is arranged between the control electrode 110 and the active layer 120, the control electrode 110 and the active layer 120 can be insulated from each other. The material of the gate insulating layer GI can be an insulating material, such as silicon nitride.

[0076] Continue to refer to Figure 5A, in a direction perpendicular to the substrate S, the portion of the first conductive pattern 130 that is directly opposite to the active layer 120 is the first electrode 131 of the thin film transistor 100. Based on this, it can also be said that in a direction perpendicular to the substrate S, all of the first electrode 131 is directly opposite to the active layer 120. At this time, the orthographic projection of the first electrode 131 on the substrate S may be located within the orthographic projection of the active layer 120 on the substrate S.

[0077] The thin film transistor 100 further includes a second electrode 140. In a direction perpendicular to the substrate S, all of the second electrode 140 is directly opposite to the active layer 120. At this time, the orthographic projection of the second electrode 140 on the substrate S may be located within the orthographic projection of the active layer 120 on the substrate S. The second electrode 140 and the first electrode 131 are disposed opposite to each other along a second direction. Wherein, the second direction is parallel to the substrate S, that is, the second direction is parallel to the extension direction of the substrate S. For example, the second direction is parallel to the y-axis direction. Exemplarily, in the thin film transistor 100, the first electrode 131 is a source electrode, and the second electrode 140 is a drain electrode. Another example is that in the thin film transistor 100, the first electrode 131 is a drain electrode, and the second electrode 140 is a source electrode.

[0078] In the thin film transistor 100, the portion of the active layer 120 located between the first electrode 131 and the second electrode 140 is the channel 121 of the thin film transistor 100. And, the orthographic projection of the channel 121 on the substrate S is located within the orthographic projection of the control electrode 110 on the substrate S. Specifically, the orthographic projection of the channel 121 on the substrate S being located within the orthographic projection of the control electrode 110 on the substrate S may include the following three cases:

[0079] First, all of the contour 121s of the orthographic projection of the channel 121 on the substrate S coincides with the contour 110s of the orthographic projection of the control electrode 110 on the substrate S. At this time, it can also be said that in the first direction, the control electrode 110 is flush with the channel 121; and, in the second direction, the control electrode 110 is flush with the channel 121. Wherein, the first direction is parallel to the substrate S, that is, the first direction is parallel to the extension direction of the substrate S, and, the first direction and the second direction intersect. For example, the first direction is parallel to the x-axis direction, the second direction is parallel to the y-axis direction, and at this time, the first direction is perpendicular to the second direction.

[0080] Second, a part of the contour 121s of the orthographic projection of the channel 121 on the substrate S may coincide with the contour 110s of the orthographic projection of the control electrode 110 on the substrate S. In addition, the remaining part of the contour 121s of the orthographic projection of the channel 121 on the substrate S does not coincide with the contour 110s of the orthographic projection of the control electrode 110 on the substrate S and is located inside the contour 110s. At this time, in the first direction or the second direction, the control electrode 110 extends beyond the channel 121. It should be noted that in this article, the expression "in a certain direction, A extends beyond B" means that a part of A is provided on at least one side of B along this direction. For example, a part of A is provided on one side of B along this direction; or, for another example, parts of A are provided on both sides of B along this direction.

[0081] Third, the entire contour 121s of the orthographic projection of the channel 121 on the substrate S is located inside the contour 110s of the orthographic projection of the control electrode 110 on the substrate S. At this time, it can also be said that in the first direction and the second direction, the control electrode 110 extends beyond the channel 121.

[0082] Since the orthographic projection of the channel 121 on the substrate S is located within the orthographic projection of the control electrode 110 on the substrate S, the control electrode 110 can cover the channel 121. In this way, in response to the voltage on the control electrode 110, the thin-film transistor 100 can be turned on and off.

[0083] Furthermore, in the first direction, the active layer 120 extends beyond the first electrode 131. Referring to the above description, in the first direction, the active layer 120 extending beyond the first electrode 131 means that a part of the active layer 120 is provided on at least one side (e.g., one side; or, for another example, both sides) of the first electrode 131 along the first direction, that is, along the first direction, the size of the active layer 120 is larger than the size of the first electrode 131. Also, since the entire first electrode 131 faces the active layer 120 in the direction perpendicular to the substrate S, in the thin-film transistor 100, the positional relationship between the first electrode 131 and the active layer 120 includes the following two cases:

[0084] First, all of the first electrode 131 is directly opposite the active layer 120 in a direction perpendicular to the substrate S, and a part of the active layer 120 is provided on one side of the first electrode 131 along the first direction, and there is no active layer 120 on the other side. Exemplarily, the first direction is parallel to the x-axis direction. A part of the active layer 120 is provided on the side of the first electrode 131 along the positive x-axis direction, and there is no active layer 120 on the side along the negative x-axis direction. At this time, on the positive x-axis direction, the edge of the active layer 120 may protrude beyond the edge of the first electrode 131; and on the negative x-axis direction, the edge of the first electrode 131 is flush with the edge of the active layer 120. Another example is that the first direction is parallel to the x-axis direction. A part of the active layer 120 is provided on the side of the first electrode 131 along the negative x-axis direction, and there is no active layer 120 on the side along the positive x-axis direction. At this time, on the negative x-axis direction, the edge of the active layer 120 protrudes beyond the edge of the first electrode 131; and on the positive x-axis direction, the edge of the first electrode 131 is flush with the edge of the active layer 120.

[0085] Second, all of the first electrode 131 is directly opposite the active layer 120 in a direction perpendicular to the substrate S, and a part of the active layer 120 is provided on both sides of the first electrode 131 along the first direction. Exemplarily, the first direction is parallel to the x-axis direction. A part of the active layer 120 is provided on the side of the first electrode 131 along the positive x-axis direction, and a part of the active layer 120 is also provided on the side along the negative x-axis direction. At this time, on the positive x-axis direction, the edge of the active layer 120 may protrude beyond the edge of the first electrode 131; and on the negative x-axis direction, the edge of the active layer 120 may also protrude beyond the edge of the first electrode 131.

[0086] Based on the structure of the thin-film transistor 100 described above, in some embodiments, in an array substrate including the thin-film transistor 100, the first electrode 131 may be coupled to a pixel electrode (or a light-emitting device), that is, the first conductive pattern 130 may be coupled to the pixel electrode (or the light-emitting device). The second electrode 140 may be coupled to a data line. The control electrode 110 may be coupled to a gate line. In this way, in response to an electrical signal written by the gate line to the control electrode 110, the thin-film transistor 100 may be turned on and off. When the thin-film transistor 100 is in an on state, the electrical signal (such as a data signal or an electrical signal related to the data signal) on the data line may be written to the pixel electrode through the thin-film transistor 100, thereby driving the sub-pixel region to emit light.

[0087] During the manufacturing process of the thin film transistor 100, limited by the size and process precision of the thin film transistor 100, the difference between the dimension h1 in the first direction of the end portion 120a of the active layer 120 corresponding to the first pole 131 of the thin film transistor (i.e., the end portion of the active layer 120 close to the first conductive pattern 130 in the second direction) and the dimension h2 in the first direction of the end portion 130a of the first conductive pattern 130 corresponding to the first pole 131 of the thin film transistor (i.e., the end portion of the first conductive pattern 130 close to the active layer 120 in the second direction) can be set to be greater than a certain value. In this way, within the process error range, it can be ensured that the first pole 131 of the thin film transistor 100 has a certain dimension in the first direction, and this dimension can be equal to the dimension h1 in the first direction of the end portion 120a of the active layer 120 or the dimension h2 in the first direction of the end portion 130a of the first conductive pattern 130. In this way, both the channel 121 of the thin film transistor 100 has an effective width w, and the dimension of the end portion 120a of the active layer 120 or the end portion 130a of the first conductive pattern 130 in the first direction can be fully utilized, which can improve the space utilization rate and make the size of the thin film transistor 100 smaller. Refer to Figure 7, in the related art, in order to make the difference between the dimension h1' of the end 120a' of the active layer 120' in the first direction and the dimension h2' of the end 130a' of the first conductive pattern 130' in the first direction greater than a certain value, the dimension h2' of the end 130a' of the first conductive pattern 130' in the first direction is set to be greater than the dimension h1' of the end 120a' of the active layer 120' in the first direction. On this basis, in order to ensure the normal operation of the control electrode 110' and the channel 121', the control electrode 110' can extend beyond the channel 121' in the first direction and / or the second direction. In this way, in the direction perpendicular to the substrate S, there is a mutually facing part between the control electrode 110' and the first conductive pattern 130' (for example, the end 130a' of the first conductive pattern 130'), so that a capacitor Cgs can be formed between the control electrode 110' and the first conductive pattern 130'. In a display panel, the first conductive pattern 130' of the thin-film transistor can be coupled to a pixel electrode (or a light-emitting device). Therefore, the capacitor Cgs will affect the voltage magnitude on the pixel electrode (or the light-emitting device), thereby affecting the light-emitting brightness of the sub-pixel region. For example, the capacitor Cgs can store charges, so that an electrical signal can be written to the pixel electrode, which may cause a phenomenon of flicker in the display screen of the display panel. Moreover, the larger the capacitance of the capacitor Cgs, the greater the coupling voltage of the control electrode 110' to the voltage Vcom on the common electrode, resulting in poor stability of Vcom, which can further exacerbate the problem of flicker in the display screen of the display panel. In addition, the increase in the capacitance of the capacitor Cgs will cause a load in the plane of the display panel, which has an adverse impact on the power consumption and charging process of the display panel. Further, when the refresh rate of the display device is low, the display period of each frame of the screen is long, so that the charge and discharge time of the capacitor Cgs is long. Therefore, the above-mentioned phenomenon of flicker in the display screen is particularly obvious in a display device with a low refresh rate (i.e., low frequency).

[0088] Continue to refer to Figure 5A, compared with the thin-film transistor in the related art, in the thin-film transistor provided in the embodiments of the present disclosure, in order to achieve that the difference between the dimension h1 of the end portion 120a of the active layer 120 in the first direction and the dimension h2 of the end portion 130a of the first conductive pattern 130 in the first direction is greater than a certain value, the dimension h2 of the end portion 130a of the first conductive pattern 130 in the first direction is set to be smaller than the dimension h1 of the end portion 120a of the active layer 120 in the first direction, that is, in the first direction, the active layer 120 extends beyond the first electrode 131. In this way, the dimension h2 of the end portion 130a of the first conductive pattern 130 in the first direction can be smaller. Compared with the thin-film transistor in the related art, on the premise that the dimension by which the control electrode 110 extends beyond the channel 121 in the first direction and / or the second direction is a certain value, in the direction perpendicular to the substrate S, the area of the first conductive pattern 130 facing the control electrode 110 can be smaller, so that the capacitance of the capacitor Cgs formed by the first conductive pattern 130 and the control electrode 110 can be smaller. In this way, both the effective width w of the channel 121 of the thin-film transistor 100 is ensured, and the problem of the display screen of the display panel flickering as described above can be improved.

[0089] In some embodiments, the first conductive pattern 130 is a long strip extending in the second direction, and the first electrode 131 is located at one end of the first conductive pattern 130 in the second direction. Exemplarily, the first electrode 131 is located at one end of the first conductive pattern 130 in the second direction close to the active layer 120. For example, the end portion 130a of the first conductive pattern 130 close to the active layer 120 can be the first electrode 131.

[0090] In some possible implementation manners, the first conductive pattern 130 can be of equal width in the first direction, and the width of the first conductive pattern 130 in the first direction is the dimension h2 of the end portion 130a of the first conductive pattern 130 in the first direction. Compared with the portion of the first conductive pattern 130 other than the end portion 130a having a larger dimension in the first direction, since the first conductive pattern 130 is a long strip of equal width in the first direction, therefore, the capacitance of the capacitor Cgs formed by the first conductive pattern 130 and the control electrode 110 can be further reduced, and the pattern shape of the first conductive pattern 130 is simple and easy to control in the process, which can improve the yield of the product.

[0091] In some other possible implementation manners, refer to Figure 6, the first conductive pattern 130 has unequal widths in the first direction. Exemplarily, along the second direction, the closer to the channel, the smaller the size of the first conductive pattern 130 in the first direction. In this way, the size of one end of the first conductive pattern 130 away from the channel (i.e., in the negative y-axis direction) along the second direction is larger in the first direction, making its electrical connection stability with other structures (such as the second conductive pattern described below) better. And, the size of one end of the first conductive pattern 130 close to the channel (i.e., in the positive y-axis direction) along the second direction is smaller. In this way, the capacitance of the capacitor Cgs formed by the first conductive pattern 130 and the control electrode 110 can be smaller.

[0092] As described above, in the first direction, the active layer 120 extends beyond the first electrode 131, that is, a part of the active layer 120 is provided on at least one side (for example, one side; or, both sides) of the first electrode 131 along the first direction. Specifically, refer to Figure 8 , in some embodiments, the active layer 120 may include a first extending portion 122. The first extending portion 122 is located on at least one side (for example, one side; or, both sides) of the first electrode 131 along the first direction. It can also be said that the first extending portion 122 is provided on at least one side (for example, one side; or, both sides) of the first electrode 131 along the first direction. Exemplarily, the first extending portion 122 is located on one side of the first electrode 131 along the first direction, such as one side along the positive x-axis direction, or one side along the negative x-axis direction. Another example is that the first extending portion 122 is located on both sides of the first electrode 131 along the first direction. At this time, the first extending portion 122 may include a first extending sub-portion 122a and a second extending sub-portion 122b, and the first extending sub-portion 122a and the second extending sub-portion 122b are respectively located on both sides of the first electrode 131 along the first direction.

[0093] Further, the width h3 of the first extending portion 122 is greater than or equal to 2.5 μm. Exemplarily, the width h3 of the first extending portion 122 is 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm, 3.0 μm, 3.1 μm, 3.2 μm, 3.3 μm, 3.4 μm, 3.5 μm, 3.6 μm, 3.7 μm, 3.8 μm, 3.9 μm, 4.0 μm. Herein, the width h3 of the first extending portion 122 may be the dimension of the first extending portion 122 in the first direction. Exemplarily, the first extending portion 122 includes a first extending sub-portion 122a and a second extending sub-portion 122b. At this time, the width h3 of the first extending portion 122 may be the sum of the width h31 of the first extending sub-portion 122a and the width h32 of the second extending sub-portion 122b. Among them, the width h31 of the first extending sub-portion 122a may be the dimension of the first extending sub-portion 122a in the first direction, and the width h32 of the second extending sub-portion 122b may be the dimension of the second extending sub-portion 122b in the first direction. Referring to the above description, since the width h3 of the first extending portion 122 is greater than or equal to 2.5 μm, therefore, within the process error range, all of the end portion 130a of the first conductive pattern 130 can be directly opposite to the active layer 120 in the direction perpendicular to the substrate S to form the first pole 131, so that the channel 121 of the thin film transistor 100 has an effective width w, and the width w may be equal to the dimension h2 of the end portion 130a of the first conductive pattern 130 in the first direction.

[0094] See Figure 9 , as described above, in order to ensure the normal operation of the control electrode 110 and the channel 121, the control electrode 110 may extend beyond the channel 121 in the first direction and / or the second direction. Specifically, in some embodiments, in the second direction, the control electrode 110 extends beyond the channel 121. That is, a part of the control electrode 110 is disposed on at least one side (for example, one side; or both sides) of the channel 121 along the second direction.

[0095] In some possible implementation manners, the control electrode 110 includes a second extending portion 111. The second extending portion 111 is located on at least one side (for example, one side; or both sides) of the channel 121 along the second direction. It can also be said that the second extending portion 111 is disposed on at least one side (for example, one side; or both sides) of the channel 121 along the second direction. Exemplarily, the second extending portion 111 is located on one side of the channel 121 along the second direction, such as on one side in the positive y-axis direction, or on one side in the negative y-axis direction. Another example is that the second extending portion 111 is located on both sides of the channel 121 along the second direction. At this time, the second extending portion 111 may include a third extending sub-portion 111a and a fourth extending sub-portion 111b, and the third extending sub-portion 111a and the fourth extending sub-portion 111b are respectively located on both sides of the channel 121 along the second direction.

[0096] Further, the width d1 of the second extending portion 111 is greater than or equal to 2.5 μm. Exemplarily, the width d1 of the second extending portion 111 is 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm, 3.0 μm, 3.1 μm, 3.2 μm, 3.3 μm, 3.4 μm, 3.5 μm, 3.6 μm, 3.7 μm, 3.8 μm, 3.9 μm, 4.0 μm. Wherein, the width d1 of the second extending portion 111 may be the dimension of the second extending portion 111 in the second direction. Exemplarily, the second extending portion 111 includes a third extending sub-portion 111a and a fourth extending sub-portion 111b. At this time, the width d1 of the second extending portion 111 may be the sum of the width d11 of the third extending sub-portion 111a and the width d12 of the fourth extending sub-portion 111b. Wherein, the width d11 of the third extending sub-portion 111a may be the dimension of the third extending sub-portion 111a in the second direction, and the width d12 of the fourth extending sub-portion 111b may be the dimension of the fourth extending sub-portion 111b in the second direction. Referring to the above description, since the width d1 of the second extending portion 111 is greater than or equal to 2.5 μm, within the process error range, the entire channel 121 can be directly opposite to the control electrode 110 in the direction perpendicular to the substrate S, so that the channel 121 of the thin film transistor 100 has an effective length l, thereby enabling the control electrode 110 and the channel 121 to operate normally.

[0097] See Figure 10 , in some embodiments, the control electrode 110 includes a first edge 112, and the active layer 120 includes a second edge 123. The first edge 112 and the second edge 123 are located on the same side of the channel 121 along the second direction. For example, the first edge 112 and the second edge 123 are located on the side of the channel 121 along the negative y-axis direction. And, the first edge 112 is located on the side closer to the channel 121 than the second edge 123. In this way, the dimension by which the control electrode 110 extends beyond the channel 121 in the second direction can be smaller. For example, the width d11 of the third extending sub-portion 111a can be smaller. When the dimension of the control electrode 110 in the first direction is fixed, since the dimension by which the control electrode 110 extends beyond the channel 121 in the second direction is smaller, the area of the portion of the control electrode 110 extending beyond the channel 121 in the second direction can be smaller. Thus, the overlapping area of the control electrode 110 and the first conductive pattern 130 in the direction perpendicular to the substrate S can be reduced, the capacitance of the capacitor Cgs formed by the control electrode 110 and the first conductive pattern 130 can be reduced, and further the problem of display screen flicker of the display panel can be improved.

[0098] See Figure 11, in some embodiments, in the first direction, the active layer 120 extends beyond the second electrode 140. That is, a part of the active layer 120 is disposed on at least one side (e.g., one side; or, both sides) of the second electrode 140 along the first direction. Similar to the case where the active layer 120 extends beyond the first electrode in the first direction, when the active layer 120 extends beyond the second electrode 140 in the first direction, the capacitance of the capacitor Cgd formed by the control electrode 110 and the second electrode 140 can be relatively small, which can further improve the problem of display screen flicker of the display panel and improve the display stability of the display panel.

[0099] In addition, similarly, in some embodiments, the control electrode 110 includes a third edge 113, the active layer 120 includes a fourth edge 124, the third edge 113 and the fourth edge 124 are located on the same side of the channel 121 along the second direction. For example, the third edge 113 and the fourth edge 124 are located on one side of the channel 121 along the positive y-axis direction. Moreover, the third edge 113 is located on the side closer to the channel 121 than the fourth edge 124. In this way, the size by which the control electrode 110 extends beyond the channel 121 in the second direction can be relatively small. For example, the width d12 of the fourth extending sub-part 111b can be relatively small. When the size of the control electrode 110 in the first direction is fixed, since the size by which the control electrode 110 extends beyond the channel 121 in the second direction is relatively small, the area of the part of the control electrode 110 that extends beyond the channel 121 in the second direction can be relatively small. For example, the area of the fourth extending sub-part 111b can be relatively small, so that the facing area of the control electrode 110 and the second electrode 140 in the direction perpendicular to the substrate S can be further reduced, the capacitance of the capacitor Cgd formed by the control electrode 110 and the second electrode 140 can be reduced, and further, the problem of display screen flicker of the display panel can be improved.

[0100] As described above, the array substrate in some embodiments of the present disclosure further includes a pixel electrode. In addition, the array substrate may further include a common electrode. Specifically, refer to Figure 12A , Figure 12B and Figure 13 , where Figure 12A is the microscopic morphology diagram of the array substrate in some embodiments of the present disclosure, showing the structures of multiple thin film transistors located in multiple sub-pixel regions. Figure 12B is the partial enlarged view of the array substrate in some embodiments of the present disclosure, showing the structure of one sub-pixel region; Figure 13 is Figure 12BA cross-sectional view of the array substrate along the CC' profile line. In some embodiments, the array substrate 10 includes pixel electrodes 200 and a common electrode 300. The materials of the pixel electrodes 200 and the common electrode 300 can be transparent conductive materials, such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide). The materials of the pixel electrodes 200 and the common electrode 300 can be the same or different. The pixel electrodes 200 can be located on the side of the common electrode 300 away from the substrate S. As described above, the pixel electrodes 200 and the common electrode 300 are insulated from each other. To achieve this, the array substrate may further include a first passivation layer 700. The material of the first passivation layer 700 can be an insulating material, such as silicon nitride. The first passivation layer 700 can be disposed between the pixel electrodes 200 and the common electrode 300. Exemplarily, in the direction perpendicular to the substrate S, the first passivation layer 700 can be disposed between the common electrode 300 and the pixel electrodes 200. In addition, in the second direction, the first passivation layer 700 can be disposed between the pixel electrodes 200 and the common electrode 300.

[0101] As described above, the pixel electrodes 200 can be coupled to the first pole 131 of the thin film transistor 100. Thus, when the thin film transistor 100 is in the on state, an electrical signal can be written into the pixel electrodes 200 through the thin film transistor 100. In some possible implementation manners, the array substrate 10 further includes a second conductive pattern 400. The second conductive pattern 400 can be disposed on the substrate S. The second conductive pattern 400 is located on the side of the first conductive pattern 130 away from the second pole 140 along the second direction. That is, the second conductive pattern 400, the first conductive pattern 130, and the second pole 140 are sequentially disposed along the second direction.

[0102] The second conductive pattern 400 and the first conductive pattern 130 are coupled and form an integral pattern. It should be noted that in this article, A and B forming an integral pattern may mean that A and B are in the same pattern layer, and the outer contour of the pattern formed by A and B is closed.

[0103] In addition, the second conductive pattern 400 is also coupled to the pixel electrodes 200. Thus, through the second conductive pattern 400, the pixel electrodes 200 can be coupled to the first conductive pattern 130, so that the pixel electrodes 200 are coupled to the first pole 131 of the thin film transistor 100.

[0104] Exemplarily, the array substrate 10 may further include a second passivation layer 900. The second passivation layer 900 may be disposed between the common electrode 300 and the second conductive pattern 400, so that the common electrode 300 and the second conductive pattern 400 can be insulated from each other. The material of the second passivation layer 900 may be an insulating material, such as silicon nitride. The array substrate 10 may further include a planarization layer 800. The planarization layer 800 may be disposed on the side of the common electrode 300 close to the substrate S, so that the common electrode 300 can be relatively flat. The material of the planarization layer 800 is, for example, resin.

[0105] Further, vias 500 may be formed on the first passivation layer 700 and the second passivation layer 900. Through the vias 500, the pixel electrode 200 can be in contact with the second conductive pattern 400, thereby realizing the coupling of the pixel electrode 200 and the second conductive pattern 400. In addition, vias 600 may be formed on the common electrode 300 and the planarization layer 800, and the sidewalls of the vias 600 may be covered by the first passivation layer 700, so that the common electrode 300 and the pixel electrode 200 can be insulated from each other.

[0106] In some embodiments, the second conductive pattern 400 may protrude from the first conductive pattern 130 in a first direction. In this way, the area of the second conductive pattern 400 can be larger, and the electrical connection stability between the pixel electrode 200 and the second conductive pattern 400 can be improved. Refer to Figure 14 , Figure 14 which shows the positional relationship between the second conductive pattern and the thin film transistor. Since the second conductive pattern 400 protrudes from the first conductive pattern 130 in the first direction and the size of the second conductive pattern 400 in the first direction is larger, a lateral capacitor C1 may be formed between the second conductive pattern 400 and the control electrode 110. Similar to the capacitor formed by the control electrode 110 and the first conductive pattern 130, the lateral capacitor C1 may also cause problems such as flickering of the display screen of the display panel.

[0107] In order to reduce the capacitance of the lateral capacitor C1, in some embodiments, in the array substrate 10, the distance k between the control electrode 110 and the second conductive pattern 400 in a second direction is greater than or equal to 3 μm, for example, 3.0 μm, 3.1 μm, 3.2 μm, 3.3 μm, 3.4 μm, 3.5 μm, 3.6 μm, 3.7 μm, 3.8 μm, 3.9 μm, 4.0 μm, 4.1 μm, 4.2 μm, 4.3 μm, 4.4 μm, 4.5 μm, 4.6 μm, 4.7 μm, 4.8 μm, 4.9 μm, 5.0 μm, 5.1 μm, 5.2 μm, 5.3 μm, 5.4 μm, 5.5 μm. In this way, the distance k between the control electrode 110 and the second conductive pattern 400 in the second direction is larger, and the capacitance of the lateral capacitor C1 can be reduced.

[0108] Based on the above, referring to Figure 16 , in some embodiments, the active layer 120 may be a long strip with a uniform width in the first direction. Its dimension h1 in the first direction may be 7.3 μm. Moreover, the width h31 of the first extended sub - part and the width h32 of the second extended sub - part in the active layer 120 may be 1.9 μm. The width m11 of the part where the control electrode 110 extends beyond the active layer 120 in the positive x - axis direction may be 3 μm, and the width m12 of the part where the control electrode 110 extends beyond the active layer 120 in the negative x - axis direction may also be 3 μm. That is, the width of the part where the control electrode 110 extends beyond the active layer 120 in the first direction is 6 μm. And, the width d11 of the third extended sub - part in the control electrode 110 may be 2 μm. The dimension h2 of the first conductive pattern 130 in the first direction may be 3.5 μm. The distance k between the second conductive pattern 400 and the control electrode 110 in the second direction may be 5.5 μm. The distance m3 between the second conductive pattern 400 and the gate line GL in the first direction may be 3.5 μm. The distance m4 between the second conductive pattern 400 and the control electrode G in the adjacent sub - pixel region in the first direction may be 4.43 micrometers. The length l of the channel may be 5 μm. The dimension of the data line DL in the second direction may be 3.5 μm or 3.75 μm.

[0109] At this time, Figure 17 shows the verification result of the characteristic process stability of the thin - film transistor with the above dimensions. It can be seen that when there are process errors, the active layer can be offset by 1.0 μm or 2 μm in the first direction, and the control electrode can be offset by 1.5 μm in the second direction. At this time, the characteristics of the thin - film transistor can still remain relatively stable. Moreover, compared with the thin - film transistors in the related art, the value of the Ion (current in the on - state) normalization result of the thin - film transistor provided by the embodiments of the present disclosure is larger. It can be seen that the thin - film transistor provided by the embodiments of the present disclosure is easier to charge, that is, through this thin - film transistor, it is easier to write an electrical signal on the pixel electrode, which is beneficial to improving the display quality of the display device.

[0110] In addition, referring to Figure 18 , Figures 19A - 19D, when the display device includes a thin-film transistor and an array substrate with the above structure, it is based on the LPDT (Low Power Display Technology) test standard proposed by Intel Corporation (a test standard to ensure the screen display image quality at low power consumption). Among them, this test standard requires the display device to display specific pictures, such as L128 (a picture with a gray level of 128), the desktop image of Win10, the home page image of the Intel official website, G186H / V (Gary186H / V, a picture with a gray level of 186), GM193H / V, GM1dot1 / 1dot2_193, etc., and tests the picture flicker degree of the display device when displaying the above pictures. It is required that when the display device displays L128, the desktop image of Win10, and the home page image of the Intel official website, the test result is less than -55dB; when the display device displays the G186H / V, GM193H / V, and GM1dot1 / 1dot2_193 pictures, the test result is less than -30dB. The test results of the display device are as Figure 18 and Figures 19A - 19D shown. Among them, Max represents the maximum value of the picture flicker degree (Flicker) in a group of tests, and Avg. represents the average value of the picture flicker degree in a group of tests. It can be seen that in the 4 tests, the picture flicker of the display device at a low refresh rate (20Hz) after setting the symmetric Gamma (gamma) has reached the LPDT standard.

[0111] Continue to refer to Figure 12B , as described above, the array substrate 10 may further include a data line DL. The data line DL is coupled to the second pole 140 of the thin-film transistor and is configured to write an electrical signal (such as a data signal or an electrical signal related to the data signal) to the second pole 140.

[0112] In some possible implementation manners, as Figure 12B and Figure 5A shown, the thin-film transistor in the array substrate 10 is the Figure 5A thin-film transistor shown. At this time, in the array substrate, the data line DL and the first conductive pattern 130 are provided on the same layer. And, in the direction perpendicular to the substrate S, the part of the data line DL opposite to the active layer 120 is the second pole 140 of the thin-film transistor. Since the part of the data line DL opposite to the active layer 120 is the second pole 140 of the thin-film transistor, therefore, in the first direction, the active layer 120 can be flush with the second pole 140. Exemplarily, the first direction is parallel to the x-axis direction. In the positive x-axis direction, the active layer 120 is flush with the second pole 140, and, in the negative x-axis direction, the active layer 120 is flush with the second pole 140.

[0113] In some other possible implementation manners, refer to Figure 15and Figure 11 , wherein Figure 15 is a partial enlarged view of a part of the array substrate including a thin film transistor and a data line. The thin film transistor in the array substrate is the Figure 11 thin film transistor shown. In the thin film transistor 100, in the second direction, the active layer 120 extends beyond the second electrode 140. The data line DL is located on a side of the second electrode 140 away from the first electrode 131. As described above, the first electrode 131 and the second electrode 140 are oppositely arranged in the second direction. Therefore, the first electrode 131, the second electrode 140, and the data line DL can be arranged in sequence in the second direction. Further, the data line DL is coupled to the second electrode 140, and the data line DL and the second electrode 140 can form an integral pattern, so that the manufacturing process of the thin film transistor is relatively simple.

[0114] In some embodiments, the refresh rate of the display device including the thin film transistor provided in any of the above embodiments is less than or equal to 40 Hz. Exemplarily, the refresh rate of the display device is 24 Hz or 20 Hz. The refresh rate of the display device refers to the frequency at which the display screen of the display device switches (updates). For example, when the refresh rate of the display device is 40 Hz, the display screen switches 40 times in one second. As described above, the phenomenon of display screen flicker is particularly obvious in display devices with a low refresh rate (i.e., low frequency). Therefore, the thin film transistor provided in any of the above embodiments is applied to a display device with a low refresh rate, which can improve the problem of display screen flicker of the display device.

[0115] Some embodiments of the present disclosure also provide a method for manufacturing a thin film transistor, the method including the following steps:

[0116] Fabricate a control electrode, an active layer, and a first conductive pattern on a substrate. Wherein, the control electrode, the active layer, and the first conductive pattern are sequentially stacked on the substrate. In a direction perpendicular to the substrate, the portion of the first conductive pattern opposite to the active layer is the first electrode of the thin film transistor. In the first direction, the active layer extends beyond the first electrode.

[0117] Fabricate a second electrode on the substrate. The second electrode and the first electrode are oppositely arranged in the second direction. The portion of the active layer between the first electrode and the second electrode is the channel of the thin film transistor. The orthographic projection of the channel on the substrate is located within the orthographic projection of the control electrode on the substrate. The first direction and the second direction are parallel to the substrate, and the first direction intersects with the second direction.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A thin film transistor, characterized in that, Comprising: A gate electrode, an active layer, and a first conductive pattern, which are sequentially stacked on a substrate. In a direction perpendicular to the substrate, a portion of the first conductive pattern opposite to the active layer is the first electrode of the thin film transistor. In a first direction, the size of the active layer is larger than the size of the first electrode. A second electrode, the second electrode and the first electrode are oppositely arranged in a second direction. A portion of the active layer located between the first electrode and the second electrode is the channel of the thin film transistor. A projection of the channel on the substrate is located within a projection of the gate electrode on the substrate. Wherein, the first direction and the second direction are parallel to the substrate, and the first direction intersects with the second direction. The gate electrode includes a first edge, the active layer includes a second edge, the first edge and the second edge are located on the same side of the channel along the second direction, and the first edge is located on a side of the second edge closer to the channel.

2. The thin film transistor according to claim 1, wherein The first conductive pattern is a long strip extending in the second direction, and the first electrode is located at one end of the first conductive pattern in the second direction.

3. The thin film transistor according to claim 1, wherein The active layer includes a first overhang portion, the first overhang portion is located on at least one side of the first electrode along the first direction, and a width of the first overhang portion is greater than or equal to 2.5 μm.

4. The thin film transistor according to claim 1, wherein In the second direction, the gate electrode extends beyond the channel.

5. The thin film transistor according to claim 4, wherein The gate electrode includes a second overhang portion, the second overhang portion is located on at least one side of the channel along the second direction, and a width of the second overhang portion is greater than or equal to 2.5 μm.

6. The thin film transistor according to claim 1, wherein The active layer includes a third edge, the second electrode includes a fourth edge, the third edge and the fourth edge are located on the same side of the channel along the second direction, and the third edge overlaps with the fourth edge or the third edge is closer to the channel.

7. The thin film transistor according to claim 1, wherein In the first direction, the active layer extends beyond the second electrode.

8. An array substrate, characterized in that, Comprising: A substrate; The thin film transistor according to any one of claims 1 to 7, disposed on the substrate; A pixel electrode, disposed on the substrate, and the pixel electrode is coupled to the first electrode of the thin film transistor.

9. The array substrate according to claim 8, wherein Further comprising: A second conductive pattern, disposed on the substrate, the second conductive pattern is located on a side of the first conductive pattern away from the second electrode along the second direction, the second conductive pattern and the first conductive pattern are coupled and form an integral pattern, and the second conductive pattern is coupled to the pixel electrode; The second conductive pattern protrudes from the first conductive pattern in the first direction, and a distance between the gate electrode and the second conductive pattern in the second direction is greater than or equal to 3 μm.

10. The array substrate according to claim 8, wherein Further comprising: A data line, the data line and the first conductive pattern are arranged in the same layer. In a direction perpendicular to the substrate, a portion of the data line facing the active layer is the second pole of the thin film transistor.

11. The array substrate according to claim 8, wherein In the thin film transistor, in the second direction, the active layer extends beyond the second pole; The array substrate further includes a data line, the data line is located on a side of the second pole away from the first pole, the data line is coupled to the second pole, and the data line and the second pole form an integral pattern.

12. A display device, characterized in that, Including the array substrate according to any one of claims 8 to 11.

13. The display device according to claim 12, wherein The refresh rate of the display device is less than or equal to 40 Hz.

Images