Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the semiconductor device. A semiconductor device has: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type different from the first conductivity type in the first semiconductor layer; a third semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the second semiconductor layer; a fourth semiconductor layer of the first conductivity type on the third semiconductor layer; a fifth semiconductor layer of the first conductivity type on the fourth semiconductor layer and having a higher impurity concentration than the fourth semiconductor layer; a sixth semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the third semiconductor layer; and a seventh semiconductor layer of the second conductivity type having the same impurity concentration distribution in the depth direction as the third semiconductor layer.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-217922, filed on December 25, 2023, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and particularly to a semiconductor device including a diode and a method of manufacturing such a semiconductor device. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-183039

[0006] Patent Document 1 describes a technique for reducing the number of manufacturing processes by simultaneously forming the cathode of a Zener diode and the source and drain regions of a transistor. Summary of the Invention

[0007] When a transistor having a low impurity concentration region (such as a lightly doped drain (LDD) region) and a diode (such as a Zener diode) are formed simultaneously, there arises a problem that the operating resistance of the diode increases.

[0008] Other problems and novel features will become apparent from the description of this specification and the drawings.

[0009] According to an embodiment, there is provided a semiconductor device having: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type, provided in the first semiconductor layer, the second conductivity type being different from the first conductivity type; a third semiconductor layer, provided in the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer; a fourth semiconductor layer of the first conductivity type, provided on the third semiconductor layer; a fifth semiconductor layer of the first conductivity type, provided on the fourth semiconductor layer, and having an impurity concentration higher than that of the fourth semiconductor layer; a sixth semiconductor layer of the second conductivity type, provided in the second semiconductor layer, and having an impurity concentration higher than that of the third semiconductor layer; and a seventh semiconductor layer of the second conductivity type, having an impurity concentration distribution in the depth direction the same as that of the third semiconductor layer, and having an upper surface in contact with the sixth semiconductor layer.

[0010] According to an embodiment, a method of manufacturing a semiconductor device is provided, including: forming a second semiconductor layer of a second conductivity type in a first semiconductor layer of a first conductivity type, the second conductivity type being different from the first conductivity type; forming a third semiconductor layer of the second conductivity type in the second semiconductor layer, the third semiconductor layer having a higher impurity concentration than the second semiconductor layer; forming a fourth semiconductor layer of the first conductivity type on the third semiconductor layer; forming a fifth semiconductor layer of the first conductivity type on the fourth semiconductor layer, the fifth semiconductor layer having a higher impurity concentration than the fourth semiconductor layer; and forming a sixth semiconductor layer of the second conductivity type in the second semiconductor layer, the sixth semiconductor layer having a higher impurity concentration than the third semiconductor layer, wherein, in the step of forming the third semiconductor layer, a seventh semiconductor layer of the second conductivity type is formed simultaneously with the third semiconductor layer, the seventh semiconductor layer having an upper surface in contact with the sixth semiconductor layer and having a higher impurity concentration than the second semiconductor layer.

[0011] According to an embodiment, a semiconductor device capable of suppressing an increase in the operating resistance of a diode including a semiconductor layer having a low impurity concentration can be provided, and a method of manufacturing such a semiconductor device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic cross-sectional view of a semiconductor device according to a first comparative example.

[0013] Figure 2 is a schematic cross-sectional view of a semiconductor device according to a second comparative example.

[0014] Figure 3 is a graph showing the impurity concentration distributions in the semiconductor devices according to the first comparative example and the second comparative example.

[0015] Figure 4 is a schematic cross-sectional view of a semiconductor device according to a first embodiment.

[0016] Figure 5 is a graph showing the electrical characteristics of the semiconductor device according to the first embodiment.

[0017] Figure 6 is a graph showing the impurity concentration distribution in the semiconductor device according to the first embodiment.

[0018] Figure 7 is a graph showing the change in the electrical characteristics of the semiconductor device according to the first embodiment. DETAILED DESCRIPTION

[0019] For clarity, the following description and the accompanying drawings have been appropriately abbreviated and simplified. In each of the drawings, the same elements are denoted by the same reference symbols, and redundant descriptions are appropriately omitted.

[0020] [Consideration Leading to the Embodiment]

[0021] Figure 1 is a schematic cross-sectional view of a semiconductor device 1 according to a first comparative example. The left figure is a schematic cross-sectional view of a region (also referred to as a diode region) where a Zener diode is formed, and the right figure is a schematic cross-sectional view of a region (also referred to as a transistor region) where an N-channel transistor is formed. Figure 1 The downward direction in is also referred to as the depth direction. The semiconductor device 1 can be a smart power device (IPD), in which a power transistor region and an element region including a diode region and a transistor region are mounted on a single semiconductor chip.

[0022] The semiconductor device 1 includes a semiconductor substrate 11, an epitaxial layer 12, a high-voltage (HV) p-well 13-1, an HV p-well 13-2, a p-well 14-1, a p-well 14-2, a Zener diode (ZD) anode layer 15-1, an n-type semiconductor layer 16-1, an n-type semiconductor layer 16-2, an n+-type semiconductor layer 17-1, an n+-type semiconductor layer 17-2, a p+-type semiconductor layer 18-1, a p+-type semiconductor layer 18-2, an insulating film 19, a gate electrode 20, and a spacer 21.

[0023] For example, the semiconductor substrate 11 is an n-type semiconductor substrate. For example, the epitaxial layer 12 is an epitaxial film formed on the semiconductor substrate 11 by an epitaxial growth method. The semiconductor substrate 11 is connected to a substrate terminal (Sub). The semiconductor substrate 11 and the epitaxial layer 12 correspond to the first semiconductor layer.

[0024] Referring to the left figure, a p-type HV p-well 13-1 is formed in the epitaxial layer 12. A p-type p-well 14-1 is formed in the HV p-well 13-1. The impurity concentration of the p-well 14-1 is higher than that of the HV p-well 13-1. The HV p-well 13-1 and the p-well 14-1 are formed by ion implantation using, for example, a patterned resist as a mask. The HV p-well 13-1 and the p-well 14-1 correspond to the second semiconductor layer.

[0025] A ZD anode layer 15-1 (third semiconductor layer) having a p-type impurity (e.g., boron) is formed in the p-well 14-1. The impurity concentration of the ZD anode layer 15-1 is higher than that of the p-well 14-1. The ZD anode layer 15-1 has an upper surface in contact with the lower surface of the n-type semiconductor layer 16-1. The ZD anode layer 15-1 forms the anode of the Zener diode. The ZD anode layer 15-1 is formed by ion implantation using, for example, a patterned resist as a mask.

[0026] An n-type semiconductor layer 16-1 (fourth semiconductor layer) having an n-type impurity (such as phosphorus) is formed in the ZD anode layer 15-1. The lower surface of the n-type semiconductor layer 16-1 is in contact with the ZD anode layer 15-1 and the p-well 14-1. The n-type semiconductor layer 16-1 is formed by ion implantation using, for example, a patterned resist as a mask.

[0027] An n+-type semiconductor layer 17-1 (fifth semiconductor layer) having an n+-type impurity (such as arsenic, phosphorus) is formed on the n-type semiconductor layer 16-1. The impurity concentration of the n+-type semiconductor layer 17-1 is higher than that of the n-type semiconductor layer 16-1. The n-type semiconductor layer 16-1 and the n+-type semiconductor layer 17-1 form the cathode of the Zener diode. The n+-type semiconductor layer 17-1 is connected to the cathode terminal (C). The n+-type semiconductor layer 17-1 is formed by ion implantation using, for example, a resist as a mask.

[0028] Additionally, a p+-type semiconductor layer 18-1 (sixth semiconductor layer) is formed in the p-well 14-1. The impurity concentration of the p+-type semiconductor layer 18-1 is higher than that of the ZD anode layer 15-1. The p+-type semiconductor layer 18-1 is connected to the anode terminal (A). The p+-type semiconductor layer 18-1 is formed by ion implantation using, for example, a resist as a mask.

[0029] An insulating film 19 is formed on the semiconductor substrate 11. The insulating film 19 insulates the n+-type semiconductor layer 17-1 from the p+-type semiconductor layer 18-1. The insulating film 19 can be formed by, for example, a local oxidation of silicon (LOCOS) method or a trench method.

[0030] Referring to the figure on the right, an HV p-well 13-2 is formed on the epitaxial layer 12, and a p-well 14-2 (well region) is formed on the HV p-well 13-2. The HV p-well 13-2 in the transistor region and the HV p-well 13-1 in the diode region are formed simultaneously and have the same impurity concentration distribution. The p-well 14-2 in the transistor region and the p-well 14-1 in the diode region are formed simultaneously and have the same impurity concentration distribution. The HV p-well 13-2 is formed by ion implantation using, for example, a resist as a mask. The p-well 14-2 is formed by ion implantation using, for example, a resist as a mask.

[0031] Two n-type semiconductor layers 16-2 (LDD regions) are formed in the p-well 14-2, and an n+-type semiconductor layer 17-2 is formed on each of the n-type semiconductor layers 16-2. The n-type semiconductor layer 16-1 in the diode region and the n-type semiconductor layer 16-2 in the transistor region are formed simultaneously and have the same impurity concentration distribution with each other. The n+-type semiconductor layer 17-1 in the diode region and the n+-type semiconductor layer 17-2 in the transistor region are formed simultaneously and have the same impurity concentration distribution with each other. One of the two n+-type semiconductor layers 17-2 is connected to the source terminal (S), and the other of the two n+-type semiconductor layers 17-2 is connected to the drain terminal (D). The n+-type semiconductor layer 16-2 is formed by ion implantation using, for example, the gate electrode 20 as a mask. The n+-type semiconductor layer 17-2 is formed by ion implantation using, for example, the gate electrode 20 and the spacer 21 as masks.

[0032] The gate electrode 20 is located between the two n+-type semiconductor layers 17-2 and is formed on the p-well 14-2. The gate electrode 20 is formed by etching polysilicon using, for example, a resist as a mask. The spacer 21 is formed on each side of the gate electrode 20. The spacer 21 is formed by, for example, anisotropic etching of a deposited oxide film or the like.

[0033] A p+-type semiconductor layer 18-2 is formed in the p-well 14-2. The insulating film 19 insulates the n+-type semiconductor layer 17-2 from the p+-type semiconductor layer 18-2. The p+-type semiconductor layer 18-1 and the p+-type semiconductor layer 18-2 are formed simultaneously and have the same impurity concentration distribution with each other. The p+-type semiconductor layer 18-2 is connected to the back gate terminal (C). The p+-type semiconductor layer 18-2 is formed by ion implantation using, for example, a resist as a mask.

[0034] The source and drain layers including the LDD and the cathode of the Zener diode can be manufactured simultaneously, and thus, the semiconductor device 1 according to the first comparative example can reduce the number of processes required for manufacturing.

[0035] Figure 2 is a schematic cross-sectional view of the diode region of the semiconductor device 1a according to the second comparative example. Note that the transistor region is omitted from the figure. Figure 2 The semiconductor device 1a of Figure 1 differs from the semiconductor device in that it does not include the n-type semiconductor layer 16-1 (LDD).

[0036] Next, a first problem of the semiconductor device 1 according to the first comparative example will be described. The semiconductor device 1 includes an n-type semiconductor layer 16-1 having a low impurity concentration, and thus there is a problem that the operating resistance Ron of the Zener diode becomes higher than that of the second comparative example.

[0037] Next, a second problem of the semiconductor device 1 according to the first comparative example will be described. Figure 3 The upper diagram in... shows a graph of the impurity concentration distribution along the Figure 2 B-B' cross section of... The horizontal axis represents the depth from the surface (the surface on which the Zener diode is formed). The curve C11 represents the carrier concentration distribution, and the curve C12 represents the concentration distribution of the p-type impurities immediately after being implanted into the ZD anode layer 15-1. The dashed line D1 represents the depth position of the center of the depletion layer. The concentration distribution of the p-type impurities forming the ZD anode layer 15-1 is set to have a peak at a predetermined depth position. The peak position corresponds to the depth (also referred to as the range) at which ions enter from the surface of the semiconductor device 1a. At the peak position where the impurity concentration distribution reaches the maximum, point defects are formed due to ion implantation. The cross marks indicate the depth positions where the point defects are formed.

[0038] Figure 3 The lower diagram in... shows a graph of the carrier concentration distribution along the Figure 1 A-A' cross section of... The curve C21 represents the carrier concentration, and the curve C22 represents the concentration distribution of the p-type impurities implanted into the ZD anode layer 15-1. The dashed line D2 represents the depth position of the center of the depletion layer. The presence of the n-type semiconductor layer 16-1 (LDD) shifts the depletion layer to a deeper position, as indicated by the right arrow. Therefore, point defects are formed in the depletion layer due to ion implantation. Thus, there is a problem with the semiconductor device 1 according to the first comparative example that the point defects cause an increase in the leakage current of the Zener diode.

[0039] [First Embodiment]

[0040] Figure 4 is a schematic cross-sectional view of a semiconductor device 10 according to the first embodiment. Figure 3 The semiconductor device 10 of... is different from the Figure 1 semiconductor device in that it further includes a p-type semiconductor layer 15-2 (seventh semiconductor layer) in the diode region. The p-type semiconductor layer 15-2 is formed simultaneously with the ZD anode layer 15-1 and has the same impurity concentration distribution as the ZD anode layer 15-1. The p-type semiconductor layer 15-2 is formed in the p-well 14-1. The p-type semiconductor layer 15-2 has an upper surface that contacts the lower surface of the p+-type semiconductor layer 18-1. The p-type semiconductor layer 15-2 is formed by ion implantation using, for example, a resist as a mask.

[0041] A p-type semiconductor layer 15-2 having a high impurity concentration is formed on the path of the current after breakdown of the Zener diode, and thus, the first embodiment can reduce the operating resistance of the Zener diode.

[0042] In addition, HV p-wells 13-1 and 13-2 are replaced by a common HV p-well 13, and p-wells 14-1 and 14-2 are replaced by a common p-well 14. For example, the HV p-well 13 and the p-well 14 can be arranged across the entire lower layer of the semiconductor chip.

[0043] In addition, the ion implantation range of the p-type impurity when forming the ZD anode layer 15-1 and the p-type semiconductor layer 15-2 is set at a position deeper or shallower than the depletion layer formed between the anode and the cathode of the Zener diode. Note that the anode of the Zener diode is formed by the ZD anode layer 15-1, and the cathode of the Zener diode is formed by the n-type semiconductor layer 16-1 and the n+-type semiconductor layer 17-1. The point defects formed when forming the ZD anode layer 15-1 are located at a position deeper or shallower than the depletion layer, and thus, the first embodiment can reduce the leakage current of the Zener diode.

[0044] Figure 5 is a graph showing the electrical characteristics of the Zener diode according to the first embodiment. The horizontal axis represents the Zener voltage Vz [a.u.], and the vertical axis represents the Zener current Iz [a.u.]. The two-point dotted line represents the electrical characteristics of the Zener diode according to the first embodiment, and the solid line represents the electrical characteristics of the Zener diode according to the second comparative example. It is found that the first embodiment can reduce the operating resistance of the Zener diode according to the second comparative example by about 24%.

[0045] Refer to Figure 6 , curve C31 represents the carrier concentration distribution along the Figure 4 C-C' cross-section. The double-headed arrow represents the range of the depletion layer in the pn junction.

[0046] Curve C32 represents the impurity concentration distribution when the acceleration voltage of the ions is 70 keV. Curve C33 represents the impurity concentration distribution when the acceleration voltage of the ions is 150 keV. Curve C34 represents the impurity concentration distribution when the acceleration voltage of the ions is 180 keV. When the acceleration voltage of the ions is 70 keV, the point defects formed due to ion implantation are located in the depletion layer, resulting in an increase in leakage current. Setting the acceleration voltage of the ions to 150 keV allows point defects to be formed at a position deeper than the depletion layer, and thus the increase in leakage current can be suppressed. In addition, setting the acceleration voltage of the ions to 180 keV allows point defects to be formed at an even deeper position, as shown by the right arrow. Note that the increase in leakage current can be suppressed by setting the acceleration voltage to an even smaller value and setting the ion implantation range at a position shallower than the depletion layer.

[0047] Figure 7 The upper figure therein is a graph showing the change in the electrical characteristics of a Zener diode when the acceleration voltage of ions is 70 keV, and Figure 7 the lower figure therein is a graph showing the change in the electrical characteristics of a Zener diode when the acceleration voltage of ions is 150 keV. The vertical axis of the graph represents the current value Ik [a.u.], and the horizontal axis represents the voltage value Vk [a.u.]. By setting the acceleration voltage of ions to 150 keV, the change in electrical characteristics can be suppressed and the yield can be improved.

[0048] The first embodiment can reduce the operating resistance of the diode. In addition, the first embodiment can reduce the leakage current flowing in the diode.

[0049] Previously, the invention proposed by the present inventors has been described in detail based on embodiments. However, there is no doubt that the present invention is not limited to the above embodiments, and can be changed in various ways without departing from the gist of the present invention.

[0050] For example, the IGBT according to the above embodiment may have a configuration in which the conductivity type (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer, etc. is inverted. For example, one of the n-type conductivity type and the p-type conductivity type may be the first conductivity type, and the other conductivity type may be the second conductivity type. In this case, the first conductivity type may be p-type and the second conductivity type may be n-type, or conversely, the first conductivity type may be n-type and the second conductivity type may be p-type.

Claims

1. A semiconductor device, comprising: a first semiconductor layer of a first conductivity type; A second semiconductor layer of a second conductivity type is disposed in the first semiconductor layer, the second conductivity type being different from the first conductivity type; a third semiconductor layer disposed in the second semiconductor layer and having a higher impurity concentration than the second semiconductor layer; The fourth semiconductor layer of the first conductivity type is disposed on the third semiconductor layer; The fifth semiconductor layer of the first conductivity type is disposed on the fourth semiconductor layer and has a higher impurity concentration than the fourth semiconductor layer; The sixth semiconductor layer of the second conductivity type is provided in the second semiconductor layer and has a higher impurity concentration than the third semiconductor layer; as well as The second conductivity type seventh semiconductor layer has the same impurity concentration distribution as the third semiconductor layer in the depth direction and has an upper surface in contact with the sixth semiconductor layer.

2. The semiconductor device according to claim 1, wherein a depletion layer is formed between one of an anode and a cathode formed by the third semiconductor layer and the other of the anode and the cathode formed by the fourth semiconductor layer and the fifth semiconductor layer, and Point defects formed when ions of the second conductivity type impurity are implanted into the third semiconductor layer are located at a position deeper or shallower than the depletion layer.

3. The semiconductor device according to claim 2 further includes a transistor, which is arranged in the second semiconductor layer, and has a lightly doped drain (LDD) region of the first conductivity type, and the LDD region has the same impurity concentration distribution as the fourth semiconductor layer in the depth direction.

4. The semiconductor device according to claim 3, The third semiconductor layer forms an anode of a Zener diode, and the fifth semiconductor layer and the sixth semiconductor layer form a cathode of the Zener diode.

5. The semiconductor device according to claim 4, The semiconductor device is an intelligent power device (IPD), wherein the Zener diode and the transistor are mounted on a single semiconductor chip.

6. A method for manufacturing a semiconductor device, comprising: forming a second semiconductor layer of a second conductivity type in the first semiconductor layer of the first conductivity type, the second conductivity type being different from the first conductivity type; forming a third semiconductor layer of the second conductivity type in the second semiconductor layer, the third semiconductor layer having a higher impurity concentration than the second semiconductor layer; forming a fourth semiconductor layer of the first conductivity type on the third semiconductor layer; forming a fifth semiconductor layer of the first conductivity type on the fourth semiconductor layer, the fifth semiconductor layer having a higher impurity concentration than the fourth semiconductor layer; as well as forming a sixth semiconductor layer of the second conductivity type in the second semiconductor layer, the sixth semiconductor layer having a higher impurity concentration than the third semiconductor layer, In the step of forming the third semiconductor layer, the seventh semiconductor layer of the second conductivity type is formed simultaneously with the third semiconductor layer, the seventh semiconductor layer has an upper surface in contact with the sixth semiconductor layer, and has a higher impurity concentration than the second semiconductor layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein a depletion layer is formed between one of an anode and a cathode formed by the third semiconductor layer and the other of the anode and the cathode formed by the fourth semiconductor layer and the fifth semiconductor layer, and The range of ions of the second conductivity type impurity implanted in the step of forming the third semiconductor layer is set at a position deeper or shallower than the depletion layer.

8. The method for manufacturing a semiconductor device according to claim 7, in, In the step of forming the fourth semiconductor layer, a lightly doped drain (LDD) region of the first conductivity type is formed in the second semiconductor layer simultaneously with the formation of the fourth semiconductor layer.

9. The method for manufacturing a semiconductor device according to claim 8, The third semiconductor layer forms an anode of a Zener diode, and the third semiconductor layer and the fifth semiconductor layer form a cathode of the Zener diode.

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