Transverse PIN photoelectric detector and manufacturing method thereof

Abstract

The invention relates to the technical field of photoelectric detectors, in particular to a transverse PIN photoelectric detector and a manufacturing method thereof. The invention provides a manufacturing method of a transverse PIN photoelectric detector, and the method comprises the following steps: providing a detector substrate which comprises a SiN layer, a SiO2 layer and a Si layer which are stacked; etching the Si layer to form a plurality of parallel and spaced strip-shaped structures; the strip-shaped structure is thermally oxidized to form an oxidation shell with the top surface, the side surface and the end surface fully surrounding the strip-shaped structure; removing a part of oxide shell on the top surface of the strip-shaped structure to form an opening; etching the Si layer in the strip-shaped structure from the opening until the remaining part, far away from the opening, of the Si layer is used as a PIN seed layer; forming a basic nucleating layer on the lateral surface of the PIN seed layer; sequentially forming a P-type doping layer, an intrinsic layer and an N-type doping layer on the lateral surface of the basic nucleating layer; and removing the top layer of the oxide shell to form a detector electrode partially covering the P-type doping layer and partially covering the N-type doping layer.

Description

Technical Field

[0001] This application relates to the technical field of photodetectors, and specifically relates to a lateral PIN photodetector and a manufacturing method thereof. Background Art

[0002] PIN photodetectors have advantages such as high response speed, high sensitivity, and low noise, and thus have a wide range of applications in multiple fields. The following are its main application fields: optical fiber communication, automated production detection, material analysis, medical imaging, etc. Compared with other types of photodetectors, PIN photodetectors have significant advantages in terms of response speed, quantum efficiency, noise level, linearity, operating voltage, etc. The structure of traditional PIN photodetectors is relatively simple, consisting of a three-layer structure of P-type, I-type, and N-type semiconductors stacked longitudinally. The preparation process is relatively mature, easy for large-scale production, and has a low cost. It is important to develop new PIN photodetectors to meet the requirements of different application scenarios. For example, nanostructures, micro-nano processing technologies, etc. are used to optimize the structure of PIN photodetectors, such as preparing nanostructures such as nanowires, quantum wells, superlattices, etc., to increase the light absorption efficiency and carrier collection efficiency, and further improve the performance of the detector; or integrating PIN photodetectors with signal processing circuits, amplifiers, etc. to achieve the integration of photodetection and signal processing, improve the integration and reliability of the system, and reduce costs and power consumption. It can also be integrated with other optoelectronic devices such as lasers and optical waveguides to construct optoelectronic integrated chips for fields such as optical communication and optical sensing. Traditional PIN photodetectors have a vertical stacked structure, which will increase the overall structure height when integrated with other devices, and it is difficult to meet the usage requirements for some scenarios with thickness limitations. Therefore, a solution is needed to solve the problem that the PIN photodetector affects the overall height of the integrated device and limits the application scenarios. Summary of the Invention

[0003] In view of this, the present invention provides a lateral PIN photodetector and a manufacturing method thereof to solve the problem that the PIN photodetector affects the overall height of the integrated device and limits the application scenarios.

[0004] In the first aspect of the present application, the present application provides a method for manufacturing a lateral PIN photodetector, including the following steps: providing a detector substrate, the detector substrate including a stacked SiN layer, a SiO2 layer, and a Si layer; etching the Si layer to form a plurality of parallel and spaced bar structures; thermally oxidizing the bar structures to form an oxide shell that completely surrounds the bar structures on the top surface, side surfaces, and end surfaces; removing a part of the oxide shell on the top surface of the bar structures to form an opening; etching the Si layer in the bar structures from the opening until a part of the Si layer that is far away from the opening remains, as the PIN seed layer; forming a base nucleation layer on the lateral surface of the PIN seed layer; sequentially forming a P-type doped layer, an intrinsic layer, and an N-type doped layer on the lateral surface of the base nucleation layer; removing the top layer of the oxide shell to form a detector electrode that partially covers the P-type doped layer and partially covers the N-type doped layer.

[0005] Through the method for manufacturing a lateral PIN photodetector provided by the present application, a lateral oxide shell is formed by using the laterally formed bar structures. Then, a part of the bar structures in the oxide shell is removed to provide a laterally deposited seed layer. Thus, the P-I-N layers are laterally stacked. After that, the corresponding metal electrode is formed by removing the oxide shell as the detector electrode, which can be used to connect an external circuit, thereby forming a lateral PIN detector. When external light irradiates the PIN detector, the energy of the photons is absorbed by the semiconductor material, enabling the electrons in the valence band to obtain sufficient energy to transition to the conduction band, thereby generating holes in the valence band and electrons in the conduction band, that is, generating photo-generated carriers; the separated carriers form a photocurrent in the external circuit, thereby converting the optical signal into an electrical signal and outputting it. The detection function is realized by monitoring the magnitude of the conversion of light into an electrical signal. Such a PIN photodetector, due to the lateral arrangement of the P-I-N layers and its low overall thickness, will not significantly increase the device height when integrated with other devices. Especially when there is a recessed space in the device height direction, it can be arranged in the corresponding recessed space, and it will not increase the overall device height even more. This enables the integrated overall device to be applied to some scenarios with thickness limitations, avoiding affecting the overall device height and broadening the application scenarios of the PIN photodetector.

[0006] Optionally, in some embodiments, the {111} crystal plane of the PIN seed layer serves as the nucleation surface of the base nucleation layer.

[0007] Optionally, in some embodiments, in the step of etching the Si layer to form a plurality of parallel and spaced bar structures, the number of formed bar structures is greater than or equal to 3.

[0008] Optionally, in some embodiments, the size of the bar structure is 1400 nm × 200 nm × 110 nm; the shell thickness of the oxide shell is 50 nm.

[0009] Optionally, in some embodiments, the length dimension of the PIN seed layer is 200 nm ± 20 nm; the length dimension of the P-type doped layer is 300 nm ± 30 nm; the length dimension of the intrinsic layer is 300 nm ± 30 nm; the length dimension of the N-type doped layer is 300 nm ± 30 nm; the thickness of the SiN layer is 200 nm; the thickness of the SiO2 layer is 187 nm; the thickness of the Si layer is 110 nm ± 10 nm; in the step of forming the opening, the length dimension of the opening is 200 nm, and the width dimension is 200 nm; the distance from the edge of the opening facing the nearest end of the strip structure to the end face of this end is 100 nm.

[0010] Optionally, in some embodiments, the following steps are further included: forming a VCSEL substrate, the VCSEL substrate includes a P-side electrode on the top layer, and the P-side electrode is a ring-shaped metal layer; a detector substrate is formed within the space surrounded by the ring-shaped metal layer.

[0011] The lateral PIN photodetector manufactured by the manufacturing method of the lateral PIN photodetector provided in this application can apply a voltage / current to the VCSEL to make it emit light, irradiate the lateral PIN photodetector at the light outlet, use an external current source meter, and make point contact with the metal electrode of the lateral PIN photodetector. By the magnitude of the current of the current source meter, it can be known whether the PIN structure is working properly or has been damaged. By integrating the PIN detection at the light outlet of the VCSEL, in addition to realizing the conventional photoelectric detection function, a re-inspection function is built for later detection at the same time, and the problem points can be quickly checked when abnormalities occur.

[0012] Optionally, in some embodiments, the steps of forming the VCSEL substrate include: providing a substrate, and sequentially forming an N-type grating mirror layer, a quantum well layer, a P-type grating mirror layer, and a cover layer on the substrate; etching the quantum well layer, the P-type grating mirror layer, and the cover layer so that the diameters of the quantum well layer, the P-type grating mirror layer, and the cover layer are smaller than those of the N-type grating mirror layer and the substrate, forming a mesa structure; forming a first SiN protection layer to cover the side and top surfaces of the mesa structure, and the top surface of the N-type grating mirror layer; forming an oxidation confinement layer between the P-type grating mirror layer and the quantum well layer through a wet oxidation confinement process; removing the first SiN protection layer, and forming a second SiN protection layer, which covers the side and top surfaces of the mesa structure, and the top surface of the N-type grating mirror layer; etching the second SiN protection layer to form an annular opening to expose a part of the cover layer; forming a P-side metal layer, which is an annular structure, at least fills the annular opening and contacts the exposed cover layer, and covers a part of the second SiN protection layer; forming a lateral PIN photodetector on the second SiN protection layer within the annular surrounding space of the P-side metal layer; after forming the lateral PIN photodetector, forming an N-side metal layer on the side of the substrate facing away from the P-side metal layer, and then thinning the P-side metal layer to form a P-side electrode, and thinning the N-side metal layer to form an N-side electrode.

[0013] Optionally, in some embodiments, in the step of providing the detector substrate, the SiN layer of the detector substrate is the part of the second SiN protection layer of the VCSEL located in the space surrounded by the annular metal layer; the SiO2 layer and the Si layer are sequentially formed on the SiN layer.

[0014] In the second aspect of the present application, the present application provides a lateral PIN photodetector, which is manufactured by the manufacturing method of the lateral PIN photodetector provided in the first aspect of the present application, and includes: a P-type doped layer, an intrinsic layer, and an N-type doped layer arranged horizontally; detector electrodes located at one end in the length direction of the P-type doped layer and one end in the length direction of the N-type doped layer, and the detector electrodes partially cover the upper surface of the P-type doped layer and partially cover the upper surface of the N-type doped layer.

[0015] For the lateral PIN photodetector provided by the present application, since the P-I-N layers are arranged horizontally and the overall thickness is low, when integrated with other devices, it will not greatly increase the device height. Especially when there is a recessed space in the device height direction, it can be arranged in the corresponding recessed space, and will not increase the overall device height, enabling the integrated overall device to be applied to some scenarios with thickness limitations, avoiding affecting the overall device height, and broadening the application scenarios of the PIN photodetector.

[0016] Optionally, in some embodiments, the lateral PIN photodetector provided in the present application further includes a VCSEL laser substrate, including: a substrate, and an N-type grating mirror layer, a quantum well layer, a P-type grating mirror layer, and a cover layer stacked on the substrate; wherein, the diameters of the quantum well layer, the P-type grating mirror layer, and the cover layer are smaller than those of the N-type grating mirror layer and the substrate, forming a mesa structure; an oxidation confinement layer disposed between the P-type grating mirror layer and the quantum well layer; a SiN protection layer covering the side and top of the mesa structure, and the top of the N-type grating mirror layer; the SiN protection layer is provided with an annular opening to expose a part of the cover layer; a P-side electrode, the P-side electrode being an annular structure, at least filling the annular opening and contacting the exposed cover layer, and covering a part of the SiN protection layer; an N-side electrode covering the surface of the substrate on the side opposite to the P-side electrode.

[0017] The lateral PIN photodetector provided in the present application is integrated with a VCSEL. A voltage / current can be applied to the VCSEL to make it emit light, irradiating the lateral PIN photodetector at the light outlet. By using an external current source meter and making point contact with the metal electrodes of the lateral PIN photodetector, it can be known whether the PIN structure is working properly or has been damaged according to the magnitude of the current through the current source meter. By integrating the PIN detection at the light outlet of the VCSEL, in addition to realizing the conventional photoelectric detection function, a re-inspection function is built for later detection at the same time, and the problem points can be quickly checked when abnormalities occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0019] Figure 1 It is a top view schematic diagram of the lateral PIN photodetector according to an embodiment of the present application;

[0020] Figure 2 It is a side view schematic diagram of the lateral PIN photodetector according to another embodiment of the present application;

[0021] Figure 3 For Figure 2 the top view schematic diagram of the lateral PIN photodetector;

[0022] Figure 4 It is a schematic diagram of the detector substrate in the manufacturing method of the lateral PIN photodetector according to an embodiment of the present application;

[0023] Figure 5In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, it is a schematic diagram of forming a photoresist layer before etching the detector substrate;

[0024] Figure 6 In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, it is a schematic diagram of etching the Si layer of the detector substrate to form a strip structure;

[0025] Figure 7 In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, it is a schematic diagram of removing the photoresist layer after etching the Si layer of the detector substrate to form a strip structure;

[0026] Figure 8 It is Figure 7 a three-dimensional schematic diagram of one of the strip structures in;

[0027] Figure 9 In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, it is a schematic diagram of the structure after thermally oxidizing the strip structure to form an oxide shell;

[0028] Figure 10 In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, it is a schematic diagram of forming a photoresist layer on the surface of the formed oxide shell;

[0029] Figure 11 In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, it is a schematic diagram of etching a part of the top surface of the oxide shell to form an opening;

[0030] Figure 12 It is Figure 11 a cross-sectional view of the A-A cross-section in;

[0031] Figure 13 In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, it is a schematic diagram of etching and removing a part of the Si layer through the opening;

[0032] Figure 14 In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, it is a schematic diagram of forming the lateral P-I-N layers;

[0033] Figure 15 In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, it is a schematic diagram of self-aligned etching to remove the oxide shell on the top surface of the PIN structure;

[0034] Figure 16 In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, it is a schematic diagram of forming a photoresist layer on the PIN structure;

[0035] Figure 17In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, a schematic diagram of forming a detector metal layer;

[0036] Figure 18 In the manufacturing method of a lateral PIN photodetector according to an embodiment of the present application, a schematic diagram of removing a photoresist layer on the PIN structure and a metal layer on the photoresist layer to form a detector electrode.

[0037] Reference numerals:

[0038] 110 - Substrate; 120 - N-type grating mirror layer; 130 - Quantum well layer; 140 - Oxide confinement layer; 150 - P-type grating mirror layer; 160 - Capping layer; 170 - SiN protective layer; 180 - P-side metal layer; 190 - N-side metal layer; 200 - Lateral PIN photodetector; 201 - SiN layer 201; 202 - SiO2 layer; 203 - Si layer; 204 - Oxide shell; 210 - P-type doped layer; 220 - Intrinsic layer; 230 - N-type doped layer; 240 - Detector electrode; PR - Photoresist layer; m - Metal layer. Detailed implementation manners

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only parts related to the present invention are shown in the drawings, rather than all structures.

[0040] In the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention. Schematic diagrams of various structures according to embodiments of the present invention are shown in the drawings. These figures are not drawn to scale, and for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0041] Embodiment 1

[0042] Reference Figure 1 and Figures 4 to 18, this embodiment provides a manufacturing method for a lateral PIN photodetector, including the following steps:

[0043] Reference Figure 4 , provide a detector substrate, the detector substrate includes a SiN layer 201, a SiO2 layer 202, and a Si layer 203 that are stacked;

[0044] Reference Figures 5 to 7 , etch the Si layer 203 to form a plurality of parallel and spaced bar-shaped structures; specifically, form a photoresist layer PR on the Si layer 203 and pattern the photoresist layer PR ( Figure 5 ), use the photoresist layer PR as a mask to etch the underlying Si layer 203 to form a plurality of bar-shaped structures ( Figure 6 ); then remove the photoresist layer PR ( Figure 7 );

[0045] Reference Figure 9 , thermally oxidize the bar-shaped structures to form an oxide shell 204 that completely surrounds the bar-shaped structures on the top surface, side surfaces, and end surfaces;

[0046] Reference Figures 10 to 12 , remove a part of the oxide shell on the top surface of the bar-shaped structures to form an opening; specifically, form a photoresist layer PR on the top surface of the oxide shell and pattern the photoresist layer PR ( Figure 10 ), use the photoresist layer PR as a mask to etch the exposed oxide shell 204 below it to form an opening ( Figure 11 , Figure 12 ).

[0047] Reference Figure 13 , etch the Si layer in the bar-shaped structures from the opening until a part of the Si layer that is far away from the opening remains as a PIN seed layer;

[0048] Reference Figure 14 , form a base nucleation layer 205 on the lateral surface of the PIN seed layer; sequentially form a P-type doped layer 210, an intrinsic layer 220, and an N-type doped layer 230 on the lateral surface of the base nucleation layer; specifically, in some embodiments, the base nucleation layer 205 is an InAs layer with a length of 20 nm, and the P-I-N structure is a P-type InGaAs doped layer with a length of 300 nm, an intrinsic InGaAs layer with a length of 300 nm, and an N-type InGaAs doped layer with a length of 300 nm respectively;

[0049] Reference Figures 15 - 18 , remove the top layer of the oxide shell 204 to form a detector electrode that partially covers the P-type doped layer and partially covers the N-type doped layer. Specifically, self-align and etch the oxide shell 204, and the etching gas is a mixed gas of C4F8 / He / H2 three gases to remove the top layer of the oxide shell 204 on the PIN structure ( Figure 15); Then, use the photoresist layer PR to partially block the PIN structure ( Figure 16 ), forming a metal layer m covering the remaining PIN structure and the photoresist layer PR, and at least filling the gap between the PIN structure and the remaining oxide shell 204 to form a metal layer on the PIN end face ( Figure 17 ). Then, remove the photoresist layer PR and the metal layer m thereon, and the remaining metal layer m forms the detector electrode 240.

[0050] Through the manufacturing method of the lateral PIN photodetector provided by the present application, a lateral oxide shell is formed by using a laterally formed strip structure, then a part of the strip structure in the oxide shell is removed, a seed layer for lateral deposition is provided, and then the P-I-N layers are formed laterally in a stacked manner. Then, the oxide shell is removed to correspondingly form a metal electrode as the detector electrode, which can be used to connect an external circuit, thereby forming a lateral PIN detector. When external light irradiates the PIN detector, the energy of photons is absorbed by the semiconductor material, enabling electrons in the valence band to obtain sufficient energy to jump to the conduction band, thereby generating holes in the valence band and electrons in the conduction band, that is, generating photo-generated carriers; the separated carriers form a photocurrent in the external circuit, thereby converting the optical signal into an electrical signal and outputting it. The detection function is realized by monitoring the magnitude of the conversion of light into an electrical signal. Such a PIN photodetector, due to the lateral arrangement of the P-I-N layers, has a low overall thickness. When integrated with other devices, it will not greatly increase the device height. Especially when there is a recessed space in the device height direction, it can be arranged in the corresponding recessed space, and it will not increase the overall device height, enabling the integrated overall device to be applied to some scenarios with thickness limitations, avoiding affecting the overall device height, and broadening the application scenarios of the PIN photodetector.

[0051] Optionally, in some embodiments, refer to Figure 13 and Figure 14 , the {111} crystal plane of the PIN seed layer (i.e., the remaining Si layer 203) is used as the nucleation surface of the base nucleation layer.

[0052] Specifically, in some embodiments, in the step of etching the Si layer to form a plurality of parallel and spaced strip structures, the number of formed strip structures is greater than or equal to 3.

[0053] Specifically, in some embodiments, refer to Figure 8 , the size of the strip structure is length A × width B × height C = 1400 nm × 200 nm × 110 nm; refer to Figure 9 , the shell thickness of the oxide shell 204 is 50 nm.

[0054] Specifically, in some embodiments, refer to Figure 13 and Figure 14, the length dimension d of the PIN seed layer (i.e., the remaining Si layer 203) is 200 nm ± 20 nm; the length dimension e1 of the P-type doped layer 210 is 300 nm ± 30 nm; the length dimension e2 of the intrinsic layer 220 is 300 nm ± 30 nm; the length dimension e3 of the N-type doped layer 230 is 300 nm ± 30 nm; the thickness of the SiN layer 201 is 200 nm; the thickness of the SiO2 layer 202 is 187 nm; the thickness of the Si layer 203 is 110 nm ± 10 nm; reference Figure 10 , in the step of forming the opening, the length dimension a of the opening is 200 nm, and the width dimension b is 200 nm; the distance c from the edge of the opening facing the nearest end of the bar-shaped structure to the end face of this end is 100 nm. It should be noted that the thickness of the SiN layer 201 and the thickness of the SiO2 layer 202 form an optical path difference passing through these two layers in the positive direction. When the detector is integrated with the laser, the light passes from directly above or directly below. Without changing the lasing intensity of the laser, this optical path difference needs to satisfy half of the wavelength of the lasing light, that is, the thickness difference between the two layers satisfies half of the wavelength.

[0055] Furthermore, reference Figure 2 、 Figure 3 , in some embodiments, the following steps are further included: forming a VCSEL substrate, the VCSEL substrate includes a P-side metal layer 180 on the top layer, serving as a P-side electrode, and the P-side electrode is a ring-shaped metal layer; the detector substrate is formed within the space surrounded by the ring-shaped metal layer. Thus, a structure as Figure 2 、 Figure 3 is formed.

[0056] The lateral PIN photodetector manufactured by the manufacturing method of the lateral PIN photodetector provided in this application can apply a voltage / current to the VCSEL to make it emit light, irradiating the lateral PIN photodetector at the light outlet. Using an external current source meter, touching the metal electrode of the lateral PIN photodetector, the magnitude of the current through the current source meter can indicate whether the PIN structure is working properly or has been damaged. By integrating the PIN detection at the light outlet of the VCSEL, in addition to realizing the conventional photoelectric detection function, a re-inspection function is also set up for later detection, and the problem points can be quickly checked when abnormalities occur.

[0057] Furthermore, in some embodiments, the step of forming the VCSEL substrate includes:

[0058] Providing a substrate 110, and sequentially forming an N-type grating mirror layer 120, a quantum well layer 130, a P-type grating mirror layer 150, and a capping layer 160 on the substrate 110;

[0059] Etch the quantum well layer 130, the P-type grating mirror layer 150, and the capping layer 160 so that the diameters of the quantum well layer 130, the P-type grating mirror layer 150, and the capping layer 160 are smaller than those of the N-type grating mirror layer 120 and the substrate 110 to form a mesa structure;

[0060] Form a first SiN protective layer (not shown in the figure, refer to the coverage area of 170 in the figure) to cover the side and top surfaces of the mesa structure, and the top surface of the N-type grating mirror layer 120; form an oxidation confinement layer between the P-type grating mirror layer and the quantum well layer through a wet oxidation confinement process; remove the first SiN protective layer to form a second SiN protective layer (also refer to the coverage area of 170 in the figure), and the second SiN protective layer covers the side and top surfaces of the mesa structure, and the top surface of the N-type grating mirror layer 120; etch the second SiN protective layer to form an annular opening to expose a part of the capping layer 160 as the final SiN protective layer 170; form a P-side metal layer 180, and the P-side metal layer 180 is an annular structure that at least fills the annular opening and contacts the exposed capping layer 160, and covers a part of the SiN protective layer 170; the lateral PIN photodetector 200 is formed on the SiN protective layer 170 within the annular surrounding space of the P-side metal layer 180; after forming the lateral PIN photodetector 200, form an N-side metal layer 190 on the side of the substrate 110 opposite to the P-side metal layer 180, and then thin the P-side metal layer 180 to form a P-side electrode, and thin the N-side metal layer 190 to form an N-side electrode.

[0061] Further, in some embodiments, in the step of providing the detector substrate, the SiN layer 201 of the detector substrate is the part of the SiN protective layer 170 of the VCSEL located in the space surrounded by the annular P-side metal layer 180; the SiO2 layer 202 and the Si layer 203 are sequentially formed on the SiN layer 201 / 170.

[0062] Embodiment 2

[0063] This embodiment provides a lateral PIN photodetector, which is manufactured by the manufacturing method of the lateral PIN photodetector provided in the above Embodiment 1, refer to Figure 1 , including: a laterally arranged P-type doped layer 210, an intrinsic layer 220, and an N-type doped layer 230; detector electrodes 240 located at one end in the length direction of the P-type doped layer 210 and one end in the length direction of the N-type doped layer 230, and the detector electrodes 240 partially cover the upper surface of the P-type doped layer 210 and partially cover the upper surface of the N-type doped layer 230.

[0064] The lateral PIN photodetector provided in this embodiment has a low overall thickness due to the lateral arrangement of the P-I-N layers. When integrated with other devices, it will not significantly increase the device height. Especially when there is a recessed space in the device height direction, it can be arranged in the corresponding recessed space, and it will not increase the overall device height either. This enables the integrated overall device to be applied to some scenarios with thickness limitations, avoiding affecting the overall device height and broadening the application scenarios of the PIN photodetector.

[0065] Further, referring to Figure 2 , Figure 3 , in some embodiments, the lateral PIN photodetector provided in this application further includes a VCSEL laser matrix, including: a substrate 110, an N-type grating mirror layer 120, a quantum well layer 130, a P-type grating mirror layer 150, and a cover layer 160 stacked on the substrate 110; wherein, the diameters of the quantum well layer 130, the P-type grating mirror layer 150, and the cover layer 160 are smaller than those of the N-type grating mirror layer 120 and the substrate 110, forming a mesa structure; an oxidation confinement layer 140, arranged between the P-type grating mirror layer 150 and the quantum well layer 130; an SiN protection layer 170, covering the side and top of the mesa structure, and the top of the N-type grating mirror layer 120; the SiN protection layer 170 is provided with an annular opening to expose a part of the cover layer; a P-side electrode, which is an annular structure, at least fills the annular opening and contacts the exposed cover layer, and covers a part of the SiN protection layer 170; an N-side electrode, covering the surface of the substrate on the side opposite to the P-side electrode; the lateral PIN photodetector 200 is arranged on the SiN protection layer 170 in the annular surrounding space of the P-side electrode.

[0066] For the lateral PIN photodetector provided in this application, when the lateral PIN photodetector is integrated with the VCSEL, a voltage / current can be applied to the VCSEL to make it emit light, irradiating the lateral PIN photodetector at the light outlet. By using an external current source meter and making a point contact with the metal electrode of the lateral PIN photodetector, whether the PIN structure is working properly or has been damaged can be known from the magnitude of the current measured by the current source meter. By integrating the PIN detection at the light outlet of the VCSEL, in addition to realizing the conventional photoelectric detection function, a re-inspection function is built for later detection, and the problem points can be quickly checked when abnormalities occur.

[0067] In the description of this specification, the descriptions referring to terms such as "this embodiment", "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of these features. In the description of the present invention, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0068] In the above description, no detailed description is made of the technical details such as the layout and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shapes. In addition, for forming the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0069] The above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the above specific embodiments, and various obvious changes, re-adjustments, combinations with each other, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments only. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the protection scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for manufacturing a lateral PIN photodetector, characterized in that: The following steps are involved: Providing a detector substrate, the detector substrate comprising a stacked SiN layer, a SiO2 layer and a Si layer; Etching the Si layer to form a plurality of parallel and spaced strip structures; Thermally oxidizing the strip structure to form an oxidation shell that completely surrounds the strip structure on the top, side, and end surfaces; Removing a portion of the oxide shell on the top surface of the strip structure to form an opening; Etching the Si layer in the strip structure from the opening until a portion of the Si layer remaining away from the opening serves as a PIN seed layer; forming a basic nucleation layer on a lateral surface of the PIN seed layer; sequentially forming a P-type doping layer, an intrinsic layer and an N-type doping layer on the lateral surface of the basic nucleation layer; The top layer of the oxide shell is removed to form a detector electrode that partially covers the P-type doped layer and partially covers the N-type doped layer.

2. The method for manufacturing a lateral PIN photodetector according to claim 1, characterized in that: The {111} crystal orientation plane of the PIN seed layer serves as the nucleation surface of the basic nucleation layer.

3. The method for manufacturing a lateral PIN photodetector according to claim 1, characterized in that: In the step of etching the Si layer to form a plurality of parallel and spaced strip structures, The number of formed strip structures is greater than or equal to 3.

4. The method for manufacturing a lateral PIN photodetector according to claim 1, characterized in that: The size of the strip structure is 1400nm×200nm×110nm; The shell thickness of the oxide shell is 50 nm.

5. The method for manufacturing a lateral PIN photodetector according to claim 1, characterized in that: The length dimension of the PIN seed layer is 200 nm ± 20 nm; The length dimension of the P-type doped layer is 300nm±30nm; The length dimension of the intrinsic layer is 300nm±30nm The length dimension of the N-type doped layer is 300nm±30nm; The thickness of the SiN layer is 200 nm; The thickness of the SiO2 layer is 187nm; The thickness of the Si layer is 110nm±10nm; In the step of forming an opening, the length dimension of the opening is 200 nm and the width dimension is 200 nm; The distance from the edge of the opening facing the nearest end of the strip structure to the end surface of the end is 100 nm.

6. The method for manufacturing a lateral PIN photodetector according to claim 1, characterized in that: The following steps are also included: Forming a VCSEL substrate, wherein the VCSEL substrate includes a P-surface electrode on the top layer, and the P-surface electrode is an annular metal layer; The detector substrate is formed in the space surrounded by the annular metal layer.

7. The method for manufacturing a lateral PIN photodetector according to claim 6, characterized in that: The step of forming the VCSEL matrix comprises: Providing a substrate, and sequentially forming an N-type grating reflector layer, a quantum well layer, a P-type grating reflector layer and a cap layer on the substrate; etching the quantum well layer, the P-type grating reflector layer and the cap layer so that the diameters of the quantum well layer, the P-type grating reflector layer and the cap layer are smaller than those of the N-type grating reflector layer and the substrate, so as to form a mesa structure; Forming a first SiN protective layer to cover the side and top surface of the mesa structure and the top surface of the N-type grating reflector layer; forming an oxidation confinement layer between the P-type grating reflector layer and the quantum well layer by a wet oxidation confinement process; removing the first SiN protective layer to form a second SiN protective layer, wherein the second SiN protective layer covers the side and top surface of the mesa structure and the top surface of the N-type grating reflector layer; etching the second SiN protective layer to form an annular opening to expose a portion of the cap layer; forming a P-side metal layer, wherein the P-side metal layer is an annular structure, at least filling the annular opening and contacting the exposed cap layer, and covering a portion of the second SiN protective layer; The lateral PIN photodetector is formed on the second SiN protective layer within the annular surrounding space of the P-side metal layer; After forming the lateral PIN photodetector, an N-side metal layer is formed on the side of the substrate facing away from the P-side metal layer, and then the P-side metal layer is thinned to form a P-side electrode, and the N-side metal layer is thinned to form an N-side electrode.

8. The method for manufacturing a lateral PIN photodetector according to claim 7, characterized in that: In the step of providing a detector substrate, the SiN layer of the detector substrate is a portion of the second SiN protective layer of the VCSEL located in the space surrounded by the annular metal layer; The SiO2 layer and the Si layer are sequentially formed on the SiN layer.

9. A lateral PIN photodetector manufactured by the method for manufacturing a lateral PIN photodetector according to any one of claims 1 to 8, characterized in that: include: A P-type doped layer, an intrinsic layer and an N-type doped layer arranged laterally; A detector electrode is located at one end of the P-type doped layer in the length direction and one end of the N-type doped layer in the length direction, and the detector electrode partially covers the upper surface of the P-type doped layer and partially covers the upper surface of the N-type doped layer.

10. The lateral PIN photodetector according to claim 9, characterized in that: Also includes: VCSEL laser substrate, including: A substrate and an N-type grating reflector layer, a quantum well layer, a P-type grating reflector layer and a cap layer stacked on the substrate; wherein the diameters of the quantum well layer, the P-type grating reflector layer and the cap layer are smaller than those of the N-type grating reflector layer and the substrate, forming a mesa structure; An oxidation restriction layer, disposed between the P-type grating reflector layer and the quantum well layer; A SiN protective layer, the SiN protective layer covers the side and top surface of the mesa structure and the top surface of the N-type grating reflector layer; the SiN protective layer is provided with an annular opening exposing a portion of the cover layer; A P-side electrode, the P-side electrode is an annular structure, at least fills the annular opening and contacts the exposed cap layer, and covers a portion of the SiN protective layer; An N-side electrode, covering a surface of the substrate facing away from the P-side electrode; The lateral PIN photodetector is arranged on the SiN protection layer in the annular surrounding space of the P-surface electrode.

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