Display device

Abstract

According to one embodiment, a display device includes: a plurality of first sub-pixels arranged in a display area; a plurality of second sub-pixels arranged in the display region; a first signal line that supplies a video signal to each of the plurality of first sub-pixels; a second signal line that supplies a video signal to each of the plurality of second sub-pixels; a first compensation capacitance unit that is disposed in a peripheral region around the display region and that is connected to the first signal line; a second compensation capacitance unit disposed in the peripheral region and connected to the second signal line; and a meandering connection wiring that connects the first compensation capacitance section and the second compensation capacitance section.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023 - 220902 filed on December 27, 2023, and incorporates by reference all of the descriptions recorded in the Japanese patent application. Technical field

[0003] Embodiments of the present invention relate to a display device. Background art

[0004] In recent years, display devices using organic light - emitting diodes (OLEDs) as display elements have been put into practical use. In such display devices, technologies for further improving display quality are required. Summary of the invention

[0005] Generally, according to an embodiment, a display device includes: a plurality of first sub - pixels arranged in a display area; a plurality of second sub - pixels arranged in the display area; a first signal line that supplies an image signal to each of the plurality of first sub - pixels; a second signal line that supplies an image signal to each of the plurality of second sub - pixels; a first compensation capacitor portion disposed in a peripheral area around the display area and connected to the first signal line; a second compensation capacitor portion disposed in the peripheral area and connected to the second signal line; and a meandering connection wiring that connects the first compensation capacitor portion and the second compensation capacitor portion.

[0006] According to another aspect of the embodiment, a display device includes: a plurality of sub - pixels disposed in a display area; a signal line that supplies an image signal to each of the plurality of sub - pixels; a power supply line that supplies a power supply voltage to each of the plurality of sub - pixels; and a compensation capacitor portion disposed in a peripheral area around the display area and connected to the signal line. Each of the plurality of sub - pixels includes: a pixel circuit connected to the signal line and the power supply line; a lower electrode connected to the pixel circuit; an upper electrode opposed to the lower electrode; and an organic layer located between the lower electrode and the upper electrode and emitting light according to the application of a voltage. Moreover, the compensation capacitor portion includes: a first capacitor electrode formed of the same material as the signal line in the same layer as the signal line and connected to the signal line; and a second capacitor electrode formed of the same material as the power supply line in the same layer as the power supply line and forming a compensation capacitor with the first capacitor electrode.

[0007] According to still another aspect of the embodiment, the display device includes: a plurality of sub-pixels disposed in a display area; signal lines that supply video signals to each of the plurality of sub-pixels; and a compensation capacitor unit disposed in a peripheral area around the display area and connected to the signal lines. Each of the plurality of sub-pixels includes: a pixel circuit having a transistor including a gate electrode and a semiconductor and connected to the signal lines; a lower electrode connected to the pixel circuit; an upper electrode opposed to the lower electrode; and an organic layer located between the lower electrode and the upper electrode and emitting light upon application of a voltage. Further, the compensation capacitor unit includes: a first capacitor electrode formed of the same material as the gate electrode in the same layer as the gate electrode and connected to the signal lines; and a second capacitor electrode formed of the same material as the semiconductor in the same layer as the semiconductor and forming a compensation capacitor with the first capacitor electrode.

[0008] With these configurations, a display device capable of further improving display quality can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. is a diagram showing a structural example of a display device according to an embodiment.

[0010] Figure 2 FIG. is a circuit diagram showing an example of a structure applicable to a pixel circuit included in a sub-pixel.

[0011] Figure 3 FIG. is a schematic plan view showing an example of an arrangement state of three pixel circuits arranged for one pixel.

[0012] Figure 4 FIG. is a schematic plan view showing an example of a layout of display elements of three sub-pixels.

[0013] Figure 5 is along Figure 4 a schematic cross-sectional view of the display device taken along line V-V in

[0014] Figure 6 FIG. is a schematic cross-sectional view showing an example of a layer structure applicable to a circuit layer.

[0015] Figure 7 FIG. is a diagram showing a structural example of a transistor included in a circuit layer.

[0016] Figure 8 FIG. is a diagram showing another structural example of a transistor included in a circuit layer.

[0017] Figure 9 FIG. is a schematic plan view showing a circuit related to a power supply voltage (VDDEL).

[0018] Figure 10 It is a plan view schematically showing the structure of the connection part.

[0019] Figure 11 It is a diagram for explaining the function of the compensation capacitor.

[0020] Figure 12 It is a diagram showing an example of the arrangement state of the compensation capacitor section.

[0021] Figure 13 It is a diagram showing another example of the arrangement state of the compensation capacitor section.

[0022] Figure 14 It is a schematic plan view of a plurality of compensation capacitor sections of the first embodiment.

[0023] Figure 15 It is Figure 14 a schematic plan view of magnifying one of the compensation capacitor sections in

[0024] Figure 16 It is along Figure 15 a schematic cross-sectional view of the compensation capacitor section along line XVI-XVI in

[0025] Figure 17 It is a schematic plan view of a plurality of compensation capacitor sections of the second embodiment.

[0026] Figure 18 It is Figure 17 a schematic plan view of magnifying one of the compensation capacitor sections in

[0027] Figure 19 It is along Figure 18 a schematic cross-sectional view of the compensation capacitor section along line IXX-IXX in

[0028] Figure 20 It is a schematic cross-sectional view of the compensation capacitor section of the third embodiment. Detailed implementation mode

[0029] While referring to the attached Figure 1 several implementation modes will be described.

[0030] The disclosed content is only an example, and for those skilled in the art, appropriate changes that can easily be thought of while maintaining the gist of the invention are of course also included in the scope of the present invention. In addition, for the sake of clarity of the description, there are cases where the width, thickness, shape, etc. of each part are schematically shown in the drawings as compared with the actual state, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each drawing, sometimes the same reference numerals are given to structural elements having the same or similar functions as those of the structural elements described above with respect to the drawings that have appeared, and repeated detailed descriptions are appropriately omitted.

[0031] In addition, in the drawings, for easy understanding as needed, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are depicted. The direction along the X-axis is referred to as the X-direction, the direction along the Y-axis is referred to as the Y-direction, and the direction along the Z-axis is referred to as the Z-direction. The Z-direction is the normal direction of the plane including the X-direction and the Y-direction. In addition, the case of observing various elements parallel to the Z-direction is referred to as a planar view.

[0032] The display device of each embodiment is an organic electroluminescent display device having an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as a television, a personal computer, a vehicle-mounted device, a tablet terminal, a smart phone, a mobile phone terminal, and a wearable terminal.

[0033] Figure 1 It is a diagram showing a structural example of the display device DSP of one embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 can be glass or a flexible resin film.

[0034] In the present embodiment, the shapes of the substrate 10 and the display area DA in a planar view are elliptical. However, the shapes of the substrate 10 and the display area DA in a planar view are not limited to an ellipse, and may be other shapes such as a rectangle, a square, or a perfect circle.

[0035] The display area DA includes a plurality of pixels PX arranged in a matrix in the X-direction and the Y-direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, it is assumed that the pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. However, the pixel PX may also include sub-pixels SP of other colors such as white, together with or instead of one of the sub-pixels SP1, SP2, and SP3.

[0036] The display device DSP further includes a terminal portion T disposed in the peripheral area SA. A flexible circuit board for supplying, for example, a voltage and a signal for driving the display device DSP is connected to the terminal portion T.

[0037] Figure 2 It is a circuit diagram showing an example of the structure of a pixel circuit PC applicable to each of the sub-pixels SP (SP1, SP2, SP3). The pixel circuit PC shown in this figure includes seven transistors TR1 to TR7 and one holding capacitor Cst.

[0038] In the following description, one of the source-drain electrodes of each of the transistors TR1 to TR7 is referred to as the first electrode, and the other is referred to as the second electrode. Similarly, one of the electrodes holding the storage capacitor Cst is referred to as the first electrode, and the other is referred to as the second electrode.

[0039] The first electrode of the transistor TR1 is connected to the node n1. The second electrode of the transistor TR1 is connected to the signal line SL for supplying the video signal Sdata. The video signal Sdata is a signal written to the pixel for displaying an image.

[0040] The transistor TR2 is equivalent to a driving transistor that supplies current to the light-emitting element DE included in the sub-pixel SP. The first electrode of the transistor TR2 is connected to the node n1. The second electrode of the transistor TR2 is connected to the node n2.

[0041] The first electrode of the transistor TR3 is connected to the node n3. The second electrode of the transistor TR3 is connected to the node n2.

[0042] The first electrode of the transistor TR4 is connected to the node n2. The second electrode of the transistor TR4 is connected to the power supply line PL1 for supplying the power supply voltage VDDEL.

[0043] The first electrode of the transistor TR5 is connected to the node n4. The second electrode of the transistor TR5 is connected to the node n1.

[0044] The first electrode of the transistor TR6 is connected to the node n4. The second electrode of the transistor TR6 is connected to the initialization line IL for supplying the initialization voltage Vini.

[0045] The first electrode of the transistor TR7 is connected to the node n2. The second electrode of the transistor TR7 is connected to the power supply line PL2 for supplying the power supply voltage VSH.

[0046] The first electrode of the storage capacitor Cst is connected to the node n3. The second electrode of the storage capacitor Cst is connected to the node n4.

[0047] The gate electrode of the transistor TR1 is connected to the scan line GL1 for supplying the scan signal Sg1. The gate electrode of the transistor TR3 is connected to the scan line GL2 for supplying the scan signal Sg2. The gate electrodes of the transistors TR4, TR5, and TR6 are connected to the scan line GL3 for supplying the scan signal Sg3. The gate electrode of the transistor TR7 is connected to the scan line GL4 for supplying the scan signal Sg4.

[0048] The anode of the display element DE is connected to the node n4. The cathode of the display element DE is connected to the power supply line PL3 that supplies the power supply voltage VSSEL. The above-mentioned power supply voltage VDDEL corresponds to the anode voltage supplied to the display element DE, and the power supply voltage VSSEL corresponds to the cathode voltage supplied to the display element DE.

[0049] In addition, the structure of the pixel circuit PC is not limited to Figure 2 the example shown. For example, the pixel circuit PC may include six or fewer or eight or more transistors. In addition, the pixel circuit PC may include a plurality of holding capacitors Cst.

[0050] Figure 3 is a schematic plan view showing an example of the configuration state of the pixel circuit PC configured for one pixel PX. In Figure 3 the example, the pixel circuits PC (PC1, PC2, PC3) of the sub-pixels SP1, SP2, SP3 are arranged in the X direction.

[0051] The pixel circuits PC1, PC2, PC3 are respectively connected to the display elements DE of the sub-pixels SP1, SP2, SP3 through the contact holes CH1, CH2, CH3 provided in the organic insulating layer 12 described later. In Figure 3 the example, the contact holes CH1, CH2, CH3 are arranged in the X direction.

[0052] Figure 4 is a schematic plan view showing an example of the layout of the display elements DE (DE1, DE2, DE3) of the sub-pixels SP1, SP2, SP3. In Figure 4 the example, the display elements DE1, DE2 are arranged in the X direction with respect to the display element DE3 respectively. Moreover, the display elements DE1, DE2 are arranged in the Y direction.

[0053] When the display elements DE1, DE2, DE3 are in such a layout, columns in which the display elements DE1, DE2 are alternately arranged in the Y direction and columns in which a plurality of display elements DE3 are repeatedly arranged in the Y direction are formed in the display area DA. These columns are alternately arranged in the X direction. In addition, the layout of the display elements DE1, DE2, DE3 is not limited to Figure 4 the example.

[0054] In the display area DA, ribs 5 are arranged. The rib 5 has a pixel opening AP1 that surrounds the display element DE1, a pixel opening AP2 that surrounds the display element DE2, and a pixel opening AP3 that surrounds the display element DE3.

[0055] In Figure 4In the example, pixel aperture AP2 is larger than pixel aperture AP1, and pixel aperture AP3 is larger than pixel aperture AP2. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP3 has the largest aperture ratio, and sub-pixel SP1 has the smallest aperture ratio. However, the relationship of the aperture ratios of sub-pixels SP1, SP2, and SP3 is not limited to this example.

[0056] The display element DE1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that respectively overlap with pixel aperture AP1. The display element DE2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that respectively overlap with pixel aperture AP2. The display element DE3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that respectively overlap with pixel aperture AP3.

[0057] A lattice-shaped partition wall 6 is disposed above the rib 5. The partition wall 6 integrally overlaps with the rib 5 and has the same planar shape as the rib 5. That is, the partition wall 6 has an opening that surrounds the display elements DE1, DE2, and DE3. The partition wall 6 functions as a wiring for supplying a cathode voltage to the upper electrodes UE1, UE2, and UE3. The above contact holes CH1, CH2, and CH3 respectively overlap with the rib 5 and the partition wall 6.

[0058] Figure 5 is a schematic cross-sectional view of the display device DSP along the V-V line in Figure 4 Above the substrate 10, a circuit layer 11 is disposed. The circuit layer 11 includes Figure 2 the pixel circuits PC (PC1, PC2, PC3), signal lines SL, initialization line IL, power supply lines PL1, PL2, PL3, and scan lines GL1, GL2, GL3, GL4, etc. shown in, and various circuits and wirings. The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film that planarizes the unevenness generated by the circuit layer 11.

[0059] The lower electrodes LE1, LE2, and LE3 are disposed above the organic insulating layer 12. The rib 5 is disposed above the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. The lower electrodes LE1, LE2, and LE3 are respectively connected to the pixel circuits PC1, PC2, and PC3 of the circuit layer 11 through the contact holes CH1, CH2, and CH3 provided in the organic insulating layer 12 (refer to Figure 3 and Figure 4 ).

[0060] The partition wall 6 includes a lower portion 61 having conductivity disposed on the rib 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a larger width than the lower portion 61. Accordingly, both end portions of the upper portion 62 protrude compared to the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is referred to as an overhanging shape.

[0061] In Figure 5 the example of, the lower portion 61 includes a bottom layer 63 disposed on the rib 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Further, in Figure 5 the example of, both end portions of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0062] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0063] The display element DE1 includes an overlying layer CP1 disposed on the upper electrode UE1. The display element DE2 includes an overlying layer CP2 disposed on the upper electrode UE2. The display element DE3 includes an overlying layer CP3 disposed on the upper electrode UE3. The overlying layers CP1, CP2, and CP3 each function as an optical adjustment layer that improves the light extraction efficiency of the light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0064] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the overlying layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the overlying layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the overlying layer CP3 is referred to as the stacked film FL3.

[0065] A part of the stacked film FL1 is located above the upper portion 62. This part is separated from the part of the stacked film FL1 located around the partition wall 6 (the part constituting the display element DE1). Similarly, a part of the stacked film FL2 is located above the upper portion 62, and this part is separated from the part of the stacked film FL2 located around the partition wall 6 (the part constituting the display element DE2). Moreover, a part of the stacked film FL3 is located above the upper portion 62, and this part is separated from the part of the stacked film FL3 located around the partition wall 6 (the part constituting the display element DE3).

[0066] The sealing layers SE11, SE12, and SE13 are respectively disposed in the sub-pixels SP1, SP2, and SP3. The sealing layer SE11 continuously covers the upper cover layer CP1 and the partition wall 6 around the sub-pixel SP1. The sealing layer SE12 continuously covers the upper cover layer CP2 and the partition wall 6 around the sub-pixel SP2. The sealing layer SE13 continuously covers the upper cover layer CP3 and the partition wall 6 around the sub-pixel SP3.

[0067] In Figure 5 the example of, the laminated film FL1 and the sealing layer SE11 on the partition wall 6 between the display elements DE1 and DE3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6. In addition, the laminated film FL2 and the sealing layer SE12 on the partition wall 6 between the display elements DE2 and DE3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6.

[0068] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are at least continuously provided in the entire display area DA, and a part thereof also reaches the peripheral area SA.

[0069] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member can be bonded to the resin layer RS2 by an adhesive layer such as OCA (Optical Clear Adhesive), for example.

[0070] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The ribs 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the ribs 5 are formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as an epoxy resin or an acrylic resin, for example.

[0071] The lower electrodes LE1, LE2, and LE3 have a reflective layer formed of, for example, silver, and a pair of conductive oxide layers covering the upper surface and the lower surface of the reflective layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0072] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). In the present embodiment, the lower electrodes LE1, LE2, and LE3 correspond to anodes, and the upper electrodes UE1, UE2, and UE3 correspond to cathodes.

[0073] The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in the Z direction in sequence. However, the organic layers OR1, OR2, and OR3 may also have other structures such as a so-called columnar structure including a plurality of light-emitting layers.

[0074] The upper cover layers CP1, CP2, and CP3 have a stacked structure obtained by overlapping, for example, a plurality of transparent layers. These transparent layers can include a layer formed of an inorganic material and a layer formed of an organic material. In addition, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the refractive indices of the sealing layers SE11, SE12, and SE13. In addition, at least one of the upper cover layers CP1, CP2, and CP3 may be omitted.

[0075] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. As the metal material of the bottom layer 63, for example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used. As the metal material of the shaft layer 64, for example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used. In addition, the shaft layer 64 may also be formed of an insulating material.

[0076] For example, the upper portion 62 of the partition wall 6 has a stacked structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. As the metal material for forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide for forming the upper layer, for example, ITO or IZO can be used. In addition, the upper portion 62 may also have a single-layer structure of a metal material. Moreover, the upper portion 62 may also include a layer formed of an insulating material.

[0077] A cathode voltage is supplied to the partition wall 6. This cathode voltage is supplied to the upper electrodes UE1, UE2, and UE3 that are in contact with the side surfaces of the lower portion 61, respectively. To the lower electrodes LE1, LE2, and LE3, voltages corresponding to the video signal Sdata of the signal line SL are supplied through the pixel circuits PC (PC1, PC2, and PC3) of the sub-pixels SP1, SP2, and SP3, respectively.

[0078] The organic layers OR1, OR2, and OR3 emit light according to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the red wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the blue wavelength region.

[0079] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer into light of colors corresponding to the sub-pixels SP1, SP2, and SP3. Additionally, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layer and generate light of colors corresponding to the sub-pixels SP1, SP2, and SP3.

[0080] Figure 6 It is a schematic cross-sectional view showing an example of the layer structure applicable to the circuit layer 11. In the example of this figure, the circuit layer 11 includes semiconductor layers 31, 32, metal layers 41, 42, 43, 44, inorganic insulating layers 51, 52, 53, 54, 55, and an organic insulating layer 56.

[0081] For example, the semiconductor layer 31 corresponds to the lowermost layer of the circuit layer 11. However, an insulating layer may be disposed below the semiconductor layer 31. The inorganic insulating layer 51 covers the semiconductor layer 31. The metal layer 41 is disposed on the inorganic insulating layer 51. The inorganic insulating layer 52 covers the metal layer 41. The semiconductor layer 32 is disposed on the inorganic insulating layer 52. The inorganic insulating layer 53 covers the semiconductor layer 32. The metal layer 42 is disposed on the inorganic insulating layer 53. The inorganic insulating layer 54 covers the metal layer 42. The metal layer 43 is disposed on the inorganic insulating layer 54. The inorganic insulating layer 55 covers the metal layer 43. The organic insulating layer 56 covers the inorganic insulating layer 55. The metal layer 44 is disposed on the organic insulating layer 56 and is covered by Figure 5 the organic insulating layer 12 shown.

[0082] For example, the semiconductor layer 31 is formed of low-temperature polysilicon formed at a low temperature, and the semiconductor layer 32 is formed of an oxide semiconductor. A single-layer structure of a metal material or a stacked structure using multiple metal materials can be applied to the metal layers 41 to 44. In one example, the metal layers 41 and 42 are formed of a molybdenum-tungsten alloy (MoW), and the metal layers 43 and 44 are formed of a stacked structure (so-called TAT) in which an aluminum layer is sandwiched between a pair of tungsten layers.

[0083] The inorganic insulating layers 51 to 55 are formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. The organic insulating layer 56 is formed of an organic insulating material such as polyimide and is thicker than the inorganic insulating layers 51 to 55.

[0084] Figure 7 and Figure 8 Each of them is a diagram showing a structural example of a transistor (TFT) included in the circuit layer 11 . Figure 7 The transistor TRa shown includes a semiconductor SCa and a gate electrode GEa opposite to the semiconductor SCa. The semiconductor SCa is formed of a semiconductor layer 31. The gate electrode GEa is formed of a metal layer 41.

[0085] on the other hand, Figure 8 The transistor TRb shown includes a semiconductor SCb and gate electrodes GEb1 and GEb2 facing the semiconductor SCb. The semiconductor SCb is formed of a semiconductor layer 32. The gate electrode GEb1 is formed of a metal layer 41. The gate electrode GEb2 is formed of a metal layer 42.

[0086] Can Figure 2 The transistors TR1 to TR7 shown in the figure apply the structure of one of the transistors TRa and TRb. The source-drain electrodes (first electrode and second electrode) of the transistors TR1 to TR7 can be formed by at least one of the metal layers 41 to 44.

[0087] in addition, Figure 2 The signal line SL, initialization line IL, power lines PL1 to PL3, and scan lines GL1 to GL4 shown are formed by any one of the metal layers 41 to 44. In one example, the signal line SL, power line PL1, and initialization line IL are formed by the metal layer 43, the power lines PL2 and PL3 are formed by the metal layer 44, and the scan lines GL1 to GL4 are formed by at least one of the metal layers 41 and 42.

[0088] Figure 9 1 is a schematic plan view showing a circuit related to the power supply voltage VDDEL. Figure 2 As shown in FIG. 1 , the pixel circuit PC of each sub-pixel SP is supplied with a power supply voltage VDDEL via a power supply line PL1 . Figure 9 In the example of FIG. 1 , a plurality of power supply lines PL1 extending in the Y direction are arranged in the display area DA.

[0089] One end of each power line PL1 is connected to the connection part CN1, and the other end is connected to the connection part CN2. The connection parts CN1 and CN2 are both located in the surrounding area SA. Figure 9 In the example, the connection parts CN1 and CN2 have a shape bent along the display area DA.

[0090] The connection portion CN1 is located between the display area DA and the terminal portion T and is connected to the terminal portion T through a pair of wirings L1 and L2. The power supply voltage VDDEL is supplied to each power supply line PL1 via the terminal portion T, the wirings L1 and L2, and the connection portion CN1.

[0091] Figure 10 It is a plan view schematically showing the structure of the connection portion CN2. In this figure, as elements arranged in the display area DA, the pixel circuit PC, the power supply line PL1, and the signal line SL are shown.

[0092] As Figure 1 and Figure 9 shown, the display area DA as a whole is oval. Such a shape is achieved by arranging pixel circuits PC (sub-pixels SP) in a stepped manner at the edge of the display area DA as Figure 10 shown.

[0093] A plurality of pixel circuits PC (sub-pixels SP) supplied with the power supply voltage VDDEL through one power supply line PL1 are arranged in the Y direction. From another perspective, a plurality of pixel circuits PC (sub-pixels SP) supplied with the video signal Sdata through one signal line SL are arranged in the Y direction.

[0094] The connection portion CN2 includes a plurality of compensation capacitor portions 7. In the Figure 10 example, one compensation capacitor portion 7 is provided for each pair of the power supply line PL1 and the signal line SL. However, there may be a signal line SL without a compensation capacitor portion 7.

[0095] The compensation capacitor portion 7 includes at least one capacitor electrode 71 (first capacitor electrode) and at least one capacitor electrode 72 (second capacitor electrode). The capacitor electrode 71 is connected to the signal line SL. The capacitor electrode 72 is connected to the power supply line PL1. The voltage of the signal line SL is applied to the capacitor electrode 71, and the power supply voltage VDDEL of the power supply line PL1 is applied to the capacitor electrode 72.

[0096] The capacitor electrodes 71 and 72 face each other in the Z direction. Thus, a compensation capacitor C that loads the signal line SL is formed between the capacitor electrodes 71 and 72.

[0097] Each capacitor electrode 72 is connected through a connection wiring CL arranged in the peripheral area SA. The connection wiring CL has a meandering shape. That is, the connection wiring CL bends multiple times between adjacent capacitor electrodes 72. From another perspective, the connection wiring CL is a waveform that repeatedly protrudes upward (away from the display area DA) and downward (toward the display area DA) in the figure. The connection wiring CL has a width sufficiently smaller than that of the capacitor electrode 72.

[0098] Figure 11 This is a diagram for explaining the function of the compensation capacitor C. For example, when the display area DA is elliptical as in the present embodiment, the number of sub-pixels SP (pixel circuits PC) connected to each signal line SL may be different.

[0099] Specifically, the more signal lines SL are closer to the center O of the display area DA, the more pixel circuits PC are connected to them. As a result, the loads (capacitances) of the respective signal lines SL are different.

[0100] In Figure 11 The graph in shows an example of the load Cx of the signal line SL located between the center O of the display area DA and the end E in the X direction. In this graph, the horizontal axis is the distance Dx from the center O. The solid line in the graph shows the distribution Q1 of the load Cx without the compensation capacitor section 7. In addition, the dashed line in the graph shows the distribution Q2 of the load Cx when the compensation capacitor section 7 is present.

[0101] Many pixel circuits PC are connected to the signal lines SL near the center O. Therefore, as shown in the distribution Q1, without the compensation capacitor section 7, the load Cx of the signal line SL becomes smaller as it is farther from the center O. Such a difference in the load Cx may cause an undesired brightness distribution in the display area DA. Specifically, the brightness of the sub-pixels SP near the end E with a small load Cx becomes higher.

[0102] The compensation capacitor C of the compensation capacitor section 7 alleviates such a brightness distribution. That is, the closer the signal line SL is to the end E, the larger the compensation capacitor C is provided, thereby reducing the difference in the load Cx of each signal line SL. As a result, the brightness distribution in the display area DA is alleviated. In one example, it is preferable that the load Cx of each signal line SL is the same as shown in the distribution Q2.

[0103] Figure 12 This is a diagram showing an example of the arrangement state of the compensation capacitor section 7. In this diagram, three signal lines SL (SLa, SLb, SLc) are focused on. The signal line SLa is connected to the pixel circuits PC of Na sub-pixels SPa. The signal line SLb is connected to the pixel circuits PC of Nb sub-pixels SPb. The signal line SLc is connected to the pixel circuits PC of Nc sub-pixels SPc.

[0104] In the pixel circuits PC of the respective sub-pixels SPa, the power supply voltage VDDEL is supplied via the power supply line PL1a. In the pixel circuits PC of the respective sub-pixels SPb, the power supply voltage VDDEL is supplied via the power supply line PL1b. In the pixel circuits PC of the respective sub-pixels SPc, the power supply voltage VDDEL is supplied via the power supply line PL1c.

[0105] Compensation capacitor sections 7a, 7b, and 7c are respectively connected to signal lines SLa, SLb, and SLc. Specifically, the signal line SLa is connected to the capacitive electrode 71a of the compensation capacitor section 7a, and the power line PL1a is connected to the capacitive electrode 72a of the compensation capacitor section 7a. The signal line SLb is connected to the capacitive electrode 71b of the compensation capacitor section 7b, and the power line PL1b is connected to the capacitive electrode 72b of the compensation capacitor section 7b. The signal line SLc is connected to the capacitive electrode 71c of the compensation capacitor section 7c, and the power line PL1c is connected to the capacitive electrode 72c of the compensation capacitor section 7c.

[0106] The signal line SLb is located between the signal line SLa and the center O of the display area DA. Therefore, the number Nb of sub-pixels SPb is larger than the number Na of sub-pixels SPa (Nb > Na). In order to mitigate the load difference between the signal lines SLa and SLb caused by such a difference in the number of sub-pixels SPa and SPb, the compensation capacitance Ca of the compensation capacitor section 7a is set larger than the compensation capacitance Cb of the compensation capacitor section 7b (Cb < Ca).

[0107] On the other hand, the signal line SLc is located between the signal line SLa and the end E in the X direction of the display area DA. Therefore, the number Nc of sub-pixels SPc is smaller than the number Na of sub-pixels SPa (Nc < Na). In order to mitigate the load difference between the signal lines SLa and SLc caused by such a difference in the number of sub-pixels SPa and SPc, the compensation capacitance Cc of the compensation capacitor section 7c is set larger than the compensation capacitance Ca of the compensation capacitor section 7a (Ca < Cc).

[0108] Figure 13 It is a diagram showing another example of the arrangement state of the compensation capacitor section 7. Also in the example of this diagram, the signal lines SLa, SLb, and SLc are considered in the same way as in Figure 12 the example.

[0109] In Figure 13 the example, the compensation capacitor section 7a has two capacitive electrodes 71a and two capacitive electrodes 72a respectively opposed to these capacitive electrodes 71a. In addition, the compensation capacitor section 7c has three capacitive electrodes 71c and three capacitive electrodes 72c respectively opposed to these capacitive electrodes 71c. The compensation capacitor section 7b has one capacitive electrode 71b and one capacitive electrode 72b in the same way as in Figure 12 the example.

[0110] In this way, in Figure 13In the example, a plurality of capacitor electrodes 71 are connected to the signal line SL with a small load caused by the pixel circuit PC, and capacitors are formed between each of these capacitor electrodes 71 and the capacitor electrode 72. Thereby, the compensation capacitors Ca, Cb, and Cc of the compensation capacitor portions 7a, 7b, and 7c can be adjusted, and the difference in load of the signal lines SLa, SLb, and SLc can be alleviated.

[0111] For example, the capacitor formed by one capacitor electrode 71a and one capacitor electrode 72a, the capacitor formed by one capacitor electrode 71b and one capacitor electrode 72b, and the capacitor formed by one capacitor electrode 71c and one capacitor electrode 72c are the same. As another example, these capacitors may also be different.

[0112] In addition, the number of capacitor electrodes 71 connected to one signal line SL is not limited to one, two, or three as in the Figure 13 example, and more capacitor electrodes 71 may be connected.

[0113] Next, with reference to Figures 14 to 20 , several specific embodiments applicable to the compensation capacitor portion 7 are shown. These embodiments are not limiting, and various structures can be applied to the compensation capacitor portion 7.

[0114] Figure 14 is a schematic plan view of a plurality of compensation capacitor portions 7 (compensation capacitor portion 7p) of the first embodiment. Figure 15 is a schematic plan view of an enlarged single compensation capacitor portion 7p. Figure 16 is a schematic cross-sectional view of the compensation capacitor portion 7p along the XVI-XVI line in Figure 15 .

[0115] Figure 14 and Figure 15 The elements shown are mainly formed by the metal layers 41 to 44 shown in Figure 6 . Figure 14 and Figure 15 collectively describe the correspondence between the line types and shading of each element and the metal layers 41 to 44.

[0116] As shown in Figure 14 and Figure 15 , the compensation capacitor portion 7p includes a capacitor electrode 71p, a capacitor electrode 72p, and a capacitor electrode 73. The capacitor electrode 71p is formed by the metal layer 43. The capacitor electrode 72p is formed by the metal layer 44. The capacitor electrode 73 is formed by the metal layer 42. In addition, the signal line SL and the power supply line PL1 are formed by the metal layer 43. Thus, in the first embodiment, the capacitor electrode 71p (the first capacitor electrode) is formed of the same material as the signal line SL in the same layer as the signal line SL.

[0117] For example, the capacitive electrode 71p is formed integrally with the signal line SL. The capacitive electrode 72p is connected to the power line PL1 through a contact hole CHa that penetrates the inorganic insulating layer 55 and the organic insulating layer 56. The capacitive electrode 73 is connected to the power line PL1 through a contact hole CHb that penetrates the inorganic insulating layer 54.

[0118] In Figure 14 's example, the capacitive electrode 72p has a size that overlaps with the three capacitive electrodes 71p. As another example, one capacitive electrode 72p can be provided for each capacitive electrode 71p.

[0119] In Figure 14 and Figure 15 's example, a part of the capacitive electrode 73 extends upward in the figure. This part is connected to the relay wiring 74 formed by the metal layer 43 through a contact hole CHc that penetrates the inorganic insulating layer 54.

[0120] Figure 10 The connection wiring CL shown is connected to the relay wiring 74. The connection wiring CL can be formed by, for example, the metal layer 42. In this case, the relay wiring 74 and the connection wiring CL are connected through a contact hole that penetrates the inorganic insulating layer 54. Not limited to this example, the connection wiring CL can also be formed by one of the metal layers 41, 43, and 44.

[0121] In Figure 14 and Figure 15 's example, wirings L11 to L15 formed by the metal layer 41 and wirings L21 and L22 formed by the metal layer 44 are arranged. The wirings L11 to L15, L21, and L22 all extend in the X direction. The wirings L11 to L15, L21, and L22 are insulated from the signal line SL, the power line PL1, and the capacitive electrodes 71p, 72p, and 73 and the relay wiring 74.

[0122] For example, Figure 2 the scan lines GL1 to GL4 shown are one of the wirings L11 to L15. In addition, Figure 2 the power lines PL2 and PL3 shown are one of the wirings L21 and L22. That is, in the first embodiment, the capacitive electrode 72p (the second capacitive electrode) is formed of the same material as the power lines PL2 and PL3 in the same layer as the power lines PL2 and PL3.

[0123] As Figure 16 shown, the organic insulating layer 56 has an opening 56a. As Figure 14 and Figure 15 shown, the opening 56a overlaps with the capacitive electrodes 71p and 72p.

[0124] In a region where such an opening 56a is provided, a capacitive electrode 71p connected to the signal line SL and a capacitive electrode 72p connected to the power line PL1 face each other with a relatively thin inorganic insulating layer 55 therebetween. Thus, a favorable capacitance is formed between the capacitive electrodes 71p and 72p. In addition, a capacitance can also be formed between the capacitive electrodes 71p and 73. These capacitances correspond to Figure 10 the compensation capacitance C shown (as compensation capacitances Ca, Cb, and Cc in Figure 12 and Figure 13 ).

[0125] Figure 17 is a schematic plan view of a plurality of compensation capacitance portions 7 (compensation capacitance portion 7q) of the second embodiment. Figure 18 is a schematic plan view of an enlarged single compensation capacitance portion 7q. Figure 19 is a schematic cross-sectional view of the compensation capacitance portion 7q along the IXX-IXX line in Figure 18 .

[0126] Figure 17 and Figure 18 The elements shown are mainly formed of the semiconductor layer 31 and metal layers 41 to 44 shown in Figure 6 . In Figure 17 and Figure 18 , the line types and shading of each element are described together with the correspondence to the semiconductor layer 31 and metal layers 41 to 44.

[0127] As shown in Figure 17 and Figure 18 , the compensation capacitance portion 7q has a capacitive electrode 71q, a capacitive electrode 72q, and a relay wiring 75. In addition, similar to the compensation capacitance portion 7p of the first embodiment, the compensation capacitance portion 7q has capacitive electrodes 72p and 73 and a relay wiring 74. Further, in the second embodiment, no opening 56a is provided in the organic insulating layer 56.

[0128] The capacitive electrode 71q is formed of the metal layer 41. The capacitive electrode 72q is formed of the semiconductor layer 31. The relay wiring 75 is formed of the metal layer 42. Similar to the first embodiment, the capacitive electrode 73 is formed of the metal layer 42, and the signal line SL, the power line PL1, and the relay wiring 74 are formed of the metal layer 43.

[0129] In this way, the capacitive electrode 71q (first capacitive electrode) in the second embodiment is formed of the same material as these gate electrodes GEa and GEb1 in the same layer as the gate electrode GEa shown in Figure 7 and the gate electrode GEb1 shown in Figure 8 . In addition, the capacitive electrode 72q (second capacitive electrode) is in the same layer as Figure 7It is formed of the same material as the semiconductor SCa in the same layer as the semiconductor SCa shown.

[0130] The relay wiring 75 is connected to the signal line SL through a contact hole CHd that penetrates the inorganic insulating layer 54. The capacitive electrode 71q is connected to the relay wiring 75 through a contact hole CHe that penetrates the inorganic insulating layers 52 and 53. Similar to the first embodiment, the capacitive electrode 72p is connected to the power supply line PL1 through a contact hole CHa that penetrates the inorganic insulating layer 55 and the organic insulating layer 56. In addition, the capacitive electrode 73 is connected to the power supply line PL1 through a contact hole CHb that penetrates the inorganic insulating layer 54. The capacitive electrode 72q is connected to the capacitive electrode 73 through a contact hole CHf that penetrates the inorganic insulating layers 51 to 53.

[0131] As Figure 17 and Figure 18 shown, the capacitive electrodes 71q, 72q, and 73 overlap in a plan view. As Figure 19 shown, the capacitive electrodes 71q and 72q face each other across a relatively thin inorganic insulating layer 51. Thereby, a good capacitance is formed between the capacitive electrode 71q connected to the signal line SL and the capacitive electrode 72q connected to the power supply line PL1. In addition, a capacitance can also be formed between the capacitive electrodes 71q and 73. These capacitances correspond to Figure 10 the compensation capacitance C shown (in Figure 12 and Figure 13 it is the compensation capacitances Ca, Cb, and Cc).

[0132] Figure 20 is a schematic cross-sectional view of the compensation capacitance section 7 (compensation capacitance section 7r) of the third embodiment. The compensation capacitance section 7r has a structure in which the compensation capacitance section 7p of the first embodiment and the compensation capacitance section 7q of the second embodiment are combined.

[0133] Specifically, the compensation capacitance section 7r has a capacitive electrode 71p (first capacitive electrode) connected to the signal line SL, a capacitive electrode 72p (second capacitive electrode) connected to the power supply line PL1, a capacitive electrode 71q (third capacitive electrode) connected to the signal line SL, a capacitive electrode 72q (fourth capacitive electrode) connected to the power supply line PL1, and a capacitive electrode 73. With such a structure, through the compensation capacitance section 7r, a compensation capacitance C having a magnitude obtained by combining the compensation capacitances of the compensation capacitance sections 7p and 7q can be obtained.

[0134] The planar shapes of the capacitive electrodes 71p, 72p, 73, and the opening 56a of the organic insulating layer 56 are the same as those Figure 15 shown. The planar shapes of the capacitive electrodes 71q and 72q are the same as those Figure 18 shown.

[0135] For example, the compensation capacitor C of the compensation capacitor section 7p is larger than the compensation capacitor C of the compensation capacitor section 7q. In such a case, the compensation capacitor section 7p can be applied to the Figure 12 shown compensation capacitor section 7a, the compensation capacitor section 7q can be applied to the compensation capacitor section 7b, and the compensation capacitor section 7r can be applied to the compensation capacitor section 7c.

[0136] According to the present embodiment described above, as described using Figure 11 , by providing the compensation capacitor section 7, it is possible to reduce the difference in the load Cx of each signal line SL and alleviate the undesired luminance distribution in the display area DA.

[0137] In an electronic device equipped with a display device DSP, an antenna for near-field wireless communication (NFC) is sometimes arranged on the back side of the display device DSP. In this case, if the structure is such that both ends of each power supply line PL1 are connected by connection portions CN1 and CN2, the conductor formed by the power supply line PL1 and the connection portions CN1 and CN2 is one of the reasons for reducing the sensitivity of the wireless communication of the above antenna. Figure 9 Specifically, eddy currents are generated in the above conductor due to the magnetic field formed by the above antenna. Through this eddy current, a magnetic field in the direction of eliminating the above magnetic field is formed, and the signal intensity attenuates. Therefore, in the case of performing wireless communication via the display device DSP, the communication sensitivity may be reduced. In particular, when the capacitor electrode 72 of the compensation capacitor section 7 is formed of a metal material with a large width, the connection portion CN2 has a low resistance. As a result, large eddy currents and accompanying strong magnetic fields are generated in the above conductor, and the communication sensitivity is likely to be reduced.

[0138] In contrast, in the present embodiment, each capacitor electrode 72 is connected by a meandering connection wiring CL as

[0139] shown. In this case, compared with the case where the capacitor electrodes 72 are integrally connected to each other and connected by a linear wiring, the connection portion CN2 can be made to have a higher resistance. As a result, the generation of the above eddy currents can be suppressed, and the communication sensitivity of the near-field wireless communication can be improved. Figure 10 Moreover, in the present embodiment, the structure of the compensation capacitor section 7 has been described by taking the display device DSP with an elliptical display area DA as an example. That is, if the display area DA has such a shape, as described using

[0140] , the loads of the respective signal lines SL are not the same, and therefore it is necessary to adjust the load based on the compensation capacitor section 7. Figure 9 As described, the loads of the respective signal lines SL are not the same, and therefore it is necessary to adjust the load based on the compensation capacitor section 7.

[0141] Not only in the case of an oval shape, the loads of the respective signal lines SL may also become uneven in the circular display area DA. Further, for example, when the display area DA is generally rectangular but has a notch for disposing a camera or the like on one side thereof, the loads of the respective signal lines SL may also become uneven. The structure of the compensation capacitor unit 7 disclosed in the present embodiment also exhibits good effects when applied to a display device DSP having a display area DA other than such an oval shape.

[0142] All display devices that those skilled in the art can implement by making appropriate design changes based on the display devices disclosed in the above respective embodiments also fall within the scope of the present invention as long as they include the gist of the present invention.

[0143] In the scope of the idea of the present invention, various modifications can be conceived by those skilled in the art, and these modifications are also interpreted as falling within the scope of the present invention. For example, a solution obtained by appropriately adding, deleting, or changing the design of structural elements with respect to the above-described embodiments by those skilled in the art, or a solution obtained by adding, omitting, or changing conditions of processes also falls within the scope of the present invention as long as it has the gist of the present invention.

[0144] Further, with regard to other effects brought about by the modes described in the above embodiments, effects that are clear from the description of this specification or effects that can be appropriately conceived by those skilled in the art are of course interpreted as being brought about by the present invention.

Claims

1. A display device, characterized in that: have: A plurality of first sub-pixels arranged in a display area; a plurality of second sub-pixels arranged in the display area; a first signal line for supplying an image signal to each of the plurality of first sub-pixels; a second signal line for supplying an image signal to each of the plurality of second sub-pixels; a first compensation capacitor portion, which is disposed in a peripheral area around the display area and connected to the first signal line; a second compensation capacitor portion, which is disposed in the peripheral region and connected to the second signal line; and A meander-shaped connection wiring connects the first compensation capacitor section and the second compensation capacitor section.

2. The display device according to claim 1, characterized in that The first compensation capacitor section and the second compensation capacitor section each include a first capacitor electrode and a second capacitor electrode forming a compensation capacitor between the first capacitor electrode and the second capacitor electrode. The first capacitor electrode of the first compensation capacitor section is connected to the first signal line. The first capacitor electrode of the second compensation capacitor section is connected to the second signal line. The second capacitor electrode of the first compensation capacitor section and the second capacitor electrode of the second compensation capacitor section are connected to the connection wiring.

3. The display device according to claim 2, characterized in that: The number of the plurality of first sub-pixels is different from the number of the plurality of second sub-pixels. The compensation capacitance of the first compensation capacitance unit is different from the compensation capacitance of the second compensation capacitance unit.

4. The display device according to claim 3, characterized in that: The number of the plurality of first sub-pixels is greater than the number of the plurality of second sub-pixels. The compensation capacitance of the first compensation capacitance unit is smaller than the compensation capacitance of the second compensation capacitance unit.

5. The display device according to claim 2, characterized in that: The first capacitor electrode of at least one of the first compensation capacitor section and the second compensation capacitor section is formed of the same material as the first signal line and the second signal line in the same layer as the first signal line and the second signal line.

6. The display device according to claim 5, characterized in that: further comprising a power supply line for supplying a power supply voltage to each of the plurality of first sub-pixels and the plurality of second sub-pixels, Each of the plurality of first sub-pixels and the plurality of second sub-pixels comprises: a pixel circuit connected to the power line; a lower electrode connected to the pixel circuit; an upper electrode opposite to the lower electrode; and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage, The second capacitor electrode of at least one of the first compensation capacitor section and the second compensation capacitor section is formed in the same layer as the power line and is made of the same material as the power line.

7. The display device according to claim 2, characterized in that: The plurality of first sub-pixels and the plurality of second sub-pixels each include: A pixel circuit having a transistor including a gate electrode and a semiconductor; a lower electrode connected to the pixel circuit; an upper electrode opposite to the lower electrode; and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage, The first capacitor electrode of at least one of the first compensation capacitor section and the second compensation capacitor section is formed in the same layer as the gate electrode and is made of the same material as the gate electrode.

8. The display device according to claim 7, characterized in that: The second capacitor electrode of at least one of the first compensation capacitor section and the second compensation capacitor section is formed in the same layer as the semiconductor and made of the same material as the semiconductor.

9. The display device according to any one of claims 1 to 4, characterized in that: The plurality of first sub-pixels and the plurality of second sub-pixels each include: Lower electrode; an upper electrode opposite to the lower electrode; and An organic layer is located between the lower electrode and the upper electrode and emits light according to application of voltage.

10. The display device according to claim 9, characterized in that: further comprising a partition wall surrounding each of the plurality of first sub-pixels and the plurality of second sub-pixels, The partition wall includes a conductive lower portion and an upper portion protruding from a side surface of the lower portion.

11. The display device according to claim 10, characterized in that: The upper electrode contacts a side surface of the lower portion.

12. A display device, characterized in that: have: A plurality of sub-pixels are arranged in a display area; a signal line that supplies an image signal to each of the plurality of sub-pixels; a power supply line that supplies a power supply voltage to each of the plurality of sub-pixels; and a compensation capacitor portion, which is arranged in a peripheral area around the display area and connected to the signal line, Each of the plurality of sub-pixels comprises: A pixel circuit connected to the signal line and the power line; a lower electrode connected to the pixel circuit; an upper electrode opposite to the lower electrode; and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage, The compensation capacitor unit comprises: a first capacitor electrode formed of the same material as the signal line in the same layer as the signal line and connected to the signal line; and The second capacitor electrode is formed in the same layer as the power line and made of the same material as the power line, and forms a compensation capacitor between the second capacitor electrode and the first capacitor electrode.

13. The display device according to claim 12, characterized in that: The compensation capacitor unit further comprises: a third capacitor electrode connected to the signal line; and A fourth capacitor electrode is provided to form a compensation capacitor with the third capacitor electrode.

14. The display device according to claim 13, characterized in that: The pixel circuit includes a transistor including a gate electrode and a semiconductor. The third capacitor electrode is formed in the same layer as the gate electrode and made of the same material as the gate electrode.

15. The display device according to claim 14, characterized in that: The fourth capacitor electrode is formed in the same layer as the semiconductor and made of the same material as the semiconductor.

16. The display device according to claim 13, characterized in that: further comprising a partition wall surrounding each of the plurality of sub-pixels, The partition wall includes a conductive lower portion and an upper portion protruding from a side surface of the lower portion.

17. The display device according to claim 16, characterized in that: The upper electrode contacts a side surface of the lower portion.

18. A display device, characterized in that: have: A plurality of sub-pixels are arranged in a display area; a signal line that supplies an image signal to each of the plurality of sub-pixels; and a compensation capacitor portion, which is arranged in a peripheral area around the display area and connected to the signal line, Each of the plurality of sub-pixels comprises: a pixel circuit including a transistor including a gate electrode and a semiconductor, connected to the signal line; a lower electrode connected to the pixel circuit; an upper electrode opposite to the lower electrode; and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage, The compensation capacitor unit comprises: a first capacitor electrode formed of the same material as the gate electrode in the same layer as the gate electrode and connected to the signal line; and The second capacitor electrode is formed in the same layer as the semiconductor and made of the same material as the semiconductor, and forms a compensation capacitor between the second capacitor electrode and the first capacitor electrode.

19. The display device according to claim 18, characterized in that further comprising a partition wall surrounding each of the plurality of sub-pixels, The partition wall includes a conductive lower portion and an upper portion protruding from a side surface of the lower portion.

20. The display device according to claim 19, characterized in that The upper electrode contacts a side surface of the lower portion.

Images