Gate driver circuit

Abstract

A gate driver circuit includes a pull-up circuit (118), a pull-down circuit (126), a level shifter circuit (116), and a drive strength control circuit (144). The pull-up circuit (118) includes a pull-up output, a first signal input, and a first enable input. The pull-up output is coupled to a gate drive output. The first signal input is coupled to a drive signal input. The pull-down circuit (126) includes a pull-down output, a second signal input, and a second enable input. The pull-down output is coupled to the gate drive output. The second signal input is coupled to the drive signal input. The level shifter circuit (116) includes a shifter output and a drive intensity input. The shifter output is coupled to the first enable input and the second enable input. The drive intensity control circuit (144) includes a drive intensity output coupled to the drive intensity input.

Description

Background Art

[0001] A DC-DC converter is an electronic circuit that converts an input direct current (DC) power supply voltage into one or more DC output voltages that are higher or lower in magnitude than the input DC power supply voltage. A DC-DC converter that generates an output voltage lower than the input voltage is referred to as a buck or step-down converter. A DC-DC converter that generates an output voltage higher than the input voltage is referred to as a boost or step-up converter.

[0002] Some DC-DC converter topologies include switching transistors coupled to an energy storage inductor / transformer at a switching node. By alternately opening and closing the switch according to a switching signal, electrical energy is transferred to the load through the energy storage inductor / transformer. The amount of electrical energy transferred to the load is a function of the on / off duty cycle of the switch and the frequency of the switching signal. DC-DC converters are widely used in power electronic devices, especially battery-powered devices such as portable cellular phones, laptop computers, and other electronic systems where efficient use of power is required.

[0003] To reduce switching losses in power transistors, the switching transistors must turn on and off very quickly. Since the control terminals of the switching transistors can exhibit a significant capacitance, a gate driver circuit can be used to buffer the input signal and drive the control terminals of the switching transistors. The gate driver circuit receives a low-power input signal and buffers the input signal to generate a high-current signal that quickly charges or discharges the input capacitance of the power transistor. Examples of power transistors that can employ a gate driver circuit include insulated gate bipolar transistors and metal oxide semiconductor field effect transistors. Summary of the Invention

[0004] Described herein is a gate driver circuit that uses a single level shifter to control the sink current and source current strengths for a high-side switching transistor. In one example, a gate driver circuit includes a pull-up circuit, a pull-down circuit, a level shifter circuit, and a drive strength control circuit. The pull-up circuit includes a pull-up output, a first signal input, and a first enable input.

[0005] The pull-up output is coupled to a gate drive output. The first signal input is coupled to a drive signal input. The pull-down circuit includes a pull-down output, a second signal input, and a second enable input. The pull-down output is coupled to the gate drive output. The second signal input is coupled to the drive signal input. The level shifter circuit includes a shifter output and a drive strength input. The shifter output is coupled to the first enable input and the second enable input. The drive strength control circuit includes a drive strength output coupled to the drive strength input.

[0006] In another example, a gate driver circuit includes a pull-up circuit, a pull-down circuit, a level shifter circuit, and a drive strength control circuit. The pull-up circuit is configured to provide current to a gate drive output in response to a drive signal at a drive signal input and an enable signal at an enable input. The pull-down circuit is configured to draw current from the gate drive output in response to the drive signal and the enable signal. The level shifter circuit is coupled to the pull-up circuit and the pull-down circuit. The level shifter circuit is configured to generate the enable signal by level shifting a drive strength control signal. The drive strength control circuit is coupled to the level shifter circuit. The drive strength control circuit is configured to set the drive strength control signal to a first state or a second state for an edge of the drive signal.

[0007] In another example, a DC-DC converter circuit includes a high-side transistor, a low-side transistor, a modulation circuit, and a high-side gate driver circuit. The high-side transistor has a control terminal. The low-side transistor is coupled to the high-side transistor. The modulation circuit is coupled to the high-side transistor and the low-side transistor. The modulation circuit is configured to generate a modulation signal. The high-side gate driver circuit is coupled between the high-side transistor and the modulation circuit. The high-side gate driver circuit includes a pull-up circuit, a pull-down circuit, a level shifter circuit, and a drive strength control circuit. The pull-up circuit is configured to provide current to the control terminal in response to the modulation signal and an enable signal. The pull-down circuit is configured to draw current from the control terminal of the high-side transistor in response to the modulation signal and the enable signal. The level shifter circuit is coupled to the pull-up circuit and the pull-down circuit. The level shifter circuit is configured to generate the enable signal by level shifting a drive strength control signal. The drive strength control circuit is coupled to the level shifter circuit. The drive strength control circuit is configured to set the drive strength control signal to a first state or a second state for an edge of the modulation signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. is a schematic hierarchical diagram of an example gate driver circuit having a single level shifter applied in a DC-DC converter.

[0009] Figure 2 FIG. is suitable for use in Figure 1 FIG. is a block diagram of an example drive strength control circuit for a gate driver circuit.

[0010] Figures 3-5 FIG. shows Figure 2 FIG. is a timing diagram showing the operation of the drive strength control circuit.

[0011] Figure 6 FIG. is a block diagram of an example memory module of a DC-DC converter including a gate driver circuit having Figure 1 FIG. DETAILED DESCRIPTION

[0012] Efficiency is an important consideration in DC-DC converters. To improve efficiency, the gate driver provides fast turn-on and turn-off of the power transistors in the DC-DC converter, and the power transistors provide low on-resistance. However, the fast turn-on and turn-off increase ringing, which increases the drain-source voltage (V DS ) across the power transistor. If V DS exceeds the safe operating voltage of the transistor, the power transistor may be damaged. The breakdown voltage of the power transistor may decrease along with a particular on-resistance, which increases the likelihood of transistor damage due to ringing overvoltage.

[0013] When powering a larger load, the ringing and stress on the power transistor increase. To protect the power transistor, the ringing can be controlled by reducing the driver strength when the load increases. In a gate driver that controls the switching of a high-side power transistor, a level shifter converts a logic signal that controls the drive strength (e.g., high or low drive strength) from a low-voltage domain to a high-voltage domain. Some high-side gate driver circuits use two level shifters to provide individual control of the drive strength during the turn-on and turn-off of the high-side power transistor. One level shifter controls the drive strength used to turn on the high-side transistor, and the other level shifter controls the drive strength used to turn off the high-side power transistor. The use of two level shifters increases the circuit area and cost.

[0014] The gate driver circuit described herein uses a single level shifter to individually control the drive strength for turning on and turning off the high-side power transistor. The drive strength control circuit generates an enable signal based on a load-related status signal. The enable signal can enable a higher or lower drive strength only during the turn-on of the high-side power transistor, only during the turn-off of the high-side power transistor, or during both turn-on and turn-off. The turn-on and turn-off drive strengths can be selected by a drive code stored in the gate driver circuit.

[0015] Figure 1 FIG. is a schematic hierarchical diagram of an example gate driver circuit 102 applied to a DC-DC converter 100. For the sake of clarity, has been removed from Figure 1Various components of the DC-DC converter 100 (e.g., the output feedback circuitry) are omitted. More specifically, in the DC-DC converter 100, a high-side transistor 108, a low-side transistor 110, an inductor 112, and an output capacitor 114 are shown. The high-side transistor 108 and the low-side transistor 110 may be n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). The drain of the high-side transistor 108 is coupled to the power voltage terminal. The source of the high-side transistor 108 is coupled to the inductor 112, and the inductor 112 is coupled to the output capacitor 114. The drain of the low-side transistor 110 is coupled to the source of the high-side transistor 108, and the source of the low-side transistor 110 is coupled to the ground terminal. The gate of the high-side transistor 108 is coupled to the gate driver circuit 102. The gate of the low-side transistor 110 is coupled to the gate driver 106. A pulse-width modulation (PWM) logic circuit 104 is coupled to the gate driver circuit 102 and the gate driver 106 to control the switching of the high-side transistor 108 and the low-side transistor 110. The PWM logic circuit 104 receives a PWM signal 150 provided by a pulse-width modulator (not shown) and generates a high-side drive signal (HDRV) and a low-side drive signal (LDRV) based on the PWM signal 150.

[0016] The gate driver circuit 102 is coupled between the PWM logic circuit 104 and the high-side transistor 108. The gate driver circuit 102 includes a level shifter circuit 116, a pull-up circuit 118, a pull-down circuit 126, a pull-up circuit 134, a pull-down circuit 140, and a drive strength control circuit 144. The pull-up circuit 118 and the pull-up circuit 134 pull current to the gate drive terminal 146 and the gate of the high-side transistor 108 to turn on the high-side transistor 108. The pull-down circuit 126 and the pull-down circuit 140 sink current from the gate drive terminal 146 and the gate of the high-side transistor 108 to turn off the high-side transistor 108.

[0017] The pull-up circuit 134 and the pull-down circuit 140 are coupled to the PWM logic circuit 104 via the drive signal input 148 of the gate driver circuit 102. The pull-up circuit 134 includes a transistor 136 and a driver 138. The transistor 136 is a pull-up transistor and includes a first current terminal (e.g., source) coupled to a power supply terminal and a second current terminal (e.g., drain) coupled to the gate drive terminal 146. The control terminal (e.g., gate) of the transistor 136 is coupled to the first output of the driver circuit 138. The pull-down circuit 140 includes a transistor 142 coupled to the driver 138. The transistor 142 is a pull-down transistor and includes a first current terminal (e.g., drain) coupled to the gate drive terminal 146 and a second current terminal (e.g., source) coupled to a ground terminal. The control terminal (e.g., gate) of the transistor 142 is coupled to the second output of the driver 138. The input of the driver 138 is coupled to the drive signal input 148 and the PWM logic circuit 104. The transistor 136 may be a p-channel field effect transistor (PFET), and the transistor 142 may be an n-channel field effect transistor (NFET).

[0018] The pull-up circuit 118 and the pull-down circuit 126 are coupled to the drive signal input 148 via the driver 138. The pull-up circuit 118 includes a transistor 120, a driver 124, and a logic gate 122. The transistor 120 is a pull-up transistor and includes a first current terminal (e.g., source) coupled to a power supply terminal and a second current terminal (e.g., drain) coupled to the gate drive terminal 146. The control terminal (e.g., gate) of the transistor 120 is coupled to the output of the driver 124. The input of the driver 124 is coupled to the output of the logic gate 122. The first input of the logic gate 122 is coupled to the drive signal input 148 via the driver 138. The second input of the logic gate 122 serves as the enable input of the pull-up circuit 118 and is coupled to the output of the level shifter circuit 116. In Figure 1 the example of the pull-up circuit 118 shown, based on the output of the driver 138 and the output of the level shifter circuit 116 being logic low, the logic gate 122 turns on the transistor 120. The output of the level shifter is an enable signal that allows the transistor 120 to drive the high-side transistor 108 when logic low. The transistor 120 may be a PFET.

[0019] The pull-down circuit 126 includes a transistor 128, a driver 132, and a logic gate 130. The transistor 128 is a pull-down transistor and includes a first current terminal (e.g., drain) coupled to a gate drive terminal 146 and a second current terminal (e.g., source) coupled to a ground terminal. A control terminal (e.g., gate) of the transistor 128 is coupled to an output of the driver 132. An input of the driver 132 is coupled to an output of the logic gate 130. A first input of the logic gate 130 is coupled to a drive signal input 148 via a driver 138. A second input of the logic gate 130 serves as an enable input of the pull-down circuit 126 and is coupled to an output of a level shifter circuit 116. In Figure 1 the illustrated example of the pull-down circuit 126, based on the output of the driver 138 being logic high and the output of the level shifter circuit 116 being logic low, the logic gate 130 turns on the transistor 128. The output of the level shifter is an enable signal that allows the transistor 128 to drive the high-side transistor 108 when logic low. The transistor 128 may be an NFET.

[0020] An input of the level shifter circuit 116 is coupled to a drive strength output of a drive strength control circuit 144. The drive strength control circuit 144 generates a drive strength control signal 152. The level shifter circuit 116 shifts the drive strength control signal 152 from the low voltage domain of the drive strength control circuit 144 to the high voltage domain of the pull-up circuit 118 and the pull-down circuit 126. Based on the load powered by the DC-DC converter 100 and the edge control value stored in the gate driver circuit 102, the drive strength control circuit 144 activates the drive strength control signal 152 for each edge (rising edge and falling edge) of the PWM signal 150 to enable or disable the pull-up circuit 118 and the pull-down circuit 126. When the pull-up circuit 118 is enabled, the turn-on drive strength is greater than when the pull-up circuit 118 is disabled. When the pull-down circuit 126 is enabled, the turn-off drive strength is greater than when the pull-down circuit 126 is disabled. The pull-up circuit 118 and the pull-down circuit 126 are both enabled by default to provide fast turn-on and turn-off.

[0021] In one example of the gate driver circuit 102, the drive strength control circuit 144 controls the drive strength as shown in Table 1. In Table 1, "OC" is overcurrent. In other examples, the drive strength control circuit 144 may provide different drive strength controls.

[0022] Table 1

[0023]

[0024] Figure 2FIG. 0 is a block diagram of an example-driven strength control circuit 144. The drive strength control circuit 144 includes a high-on (HON) input, an edge selection (SEL_WEAK_EDGE) input, a low-on (LON) input, a PWM input, an overcurrent (OC_RAW) input, a latch 202, a selector circuit 204, a latch 206, a pulse generation circuit 208, a latch 210, a logic gate 212, and a latch 214. The high-on (HON) signal received at the high-on input indicates whether the gate-to-source voltage of the high-side transistor 108 is sufficient to turn on the high-side transistor 108. The low-on signal received at the low-on input indicates whether the gate-to-source voltage of the low-side transistor 110 is sufficient to turn on the low-side transistor 110. A PWM signal 150 is received at the PWM input. The overcurrent signal (OC_RAW) received at the overcurrent input indicates that the DC-DC converter 100 has a heavy load and that the current flowing to the load exceeds a predetermined threshold. The edge selection input can be a multi-bit edge selection input that receives an edge control value (e.g., a multi-bit edge control value, SEL_WEAK_EDGE), and the edge control value indicates whether a high or low drive strength can be applied to turn on and turn off the high-side transistor 108.

[0025] Latch 202 can be a D-type flip-flop and generates a drive strength control signal 152 that is provided to the level shifter circuit 116. Latch 202 includes a latch output that is coupled to an input of the level shifter circuit 116. The clock input of latch 202 is coupled to the high-on input. The data input of latch 202 is coupled to a logic high voltage source (e.g., a logic high voltage terminal). The reset input of latch 202 is coupled to the selector output of selector circuit 204. For any switching cycle, if the reset input of latch 202 is logic high, the drive strength control signal 152 is set to be high on the rising edge of the high-on signal. This implements a lower drive strength for turning on and off for consecutive cycles until the reset input of latch 202 is set to logic low by the output of selector circuit 204. Selector circuit 204 includes a selection control input (e.g., a multi-bit selection control input) that is coupled to the output of non-volatile memory 216 (or a register coupled to non-volatile memory 216) for receiving an edge control value. Selector circuit 204 routes a signal from one of its data inputs to its output based on the edge control value. The first selector input of selector circuit 204 is coupled to a logic high voltage source. The second selector input of selector circuit 204 is coupled to a logic low voltage source (e.g., a logic low voltage terminal or a ground terminal). The third selector input of selector circuit 204 is coupled to the output of latch 206. The fourth selector input of selector circuit 204 is coupled to the output of latch 210. Some embodiments of selector circuit 204 may include a different number of selector inputs.

[0026] If the edge control value selects the connection of the first data input of the selector circuit 204 to the output of the selector circuit 204, the latch 202 is never reset (until the edge control value changes), and the drive strength control signal 152 disables the pull-up circuit 118 and the pull-down circuit 126 at both edges of the PWM signal 150 to provide a slow turn-on and slow turn-off of the high-side transistor 108.

[0027] If the edge control value selects the connection of the second data input of the selector circuit 204 to the output of the selector circuit 204, the latch 202 is always reset (until the edge control value changes), and the drive strength control signal 152 enables the pull-up circuit 118 and the pull-down circuit 126 at both edges of the PWM signal 150 to provide a fast turn-on and fast turn-off of the high-side transistor 108.

[0028] If the edge control value selects the connection of the third data input of the selector circuit 204 to the output of the selector circuit 204, the selector circuit 204 routes the output of the latch 206 to the reset input of the latch 202. The latch 206 can be a D-type flip-flop and includes a clock input coupled to the PWM input, a data input coupled to the overcurrent input, and a reset input coupled to the output of the pulse generation circuit 208. The pulse input of the pulse generation circuit 208 is coupled to the low turn-on input. The pulse generation circuit 208 provides a pulse (low-to-pulse) at the pulse output in response to the rising edge of the low turn-on signal. If the overcurrent signal is high, the output (SLOW_HS_FALL) of the latch 206 is set at the rising edge of the PWM signal 150 and reset at the rising edge of the low turn-on signal. Based on the output of the latch 206, when an overcurrent is detected, the drive strength control signal 152 enables the pull-up circuit 118 at the rising edge of the low turn-on signal and disables the pull-down circuit 126 at the rising edge of the high turn-on signal to provide a fast turn-on and slow turn-off of the high-side transistor 108. Further refer to Figure 3 Describe the operation of the drive strength control circuit 144 when the selector circuit 204 selects the output of the latch 206.

[0029] If the connection of the fourth data input of the edge control value selector circuit 204 to the output of the selector circuit 204 is selected, the selector circuit 204 routes the output of the latch 210 to the reset input of the latch 202. The latch 210 can be a D-type flip-flop and includes a clock input coupled to the output of the latch 206 and a data input coupled to a logic high voltage source. The reset input of the latch 210 is coupled to the output (gate output) of the logic gate 212. The first input of the logic gate 212 is coupled to the output of the pulse generation circuit 208. The second input of the logic gate 212 is coupled to the output of the latch 214. The latch 214 can be a D-type flip-flop and includes a clock input coupled to a high turn-on input via an inverter and a data input coupled to the output of the latch 206. The output (SLOW_HS_BOTH) of the latch 210 is set at the rising edge of SLOW_HS_FALL (output by the latch 206), indicating that an overcurrent condition exists, and remains set until reset by the output of the latch 214. If SLOW_HS_FALL is high, indicating that an overcurrent condition exists, the output of the latch 214 is set at the falling edge of the high turn-on signal and remains set while the overcurrent condition persists. As long as the output of the latch 214 is high, SLOW_HS_BOTH remains high. When the output of the latch 214 goes low, SLOW_HS_BOTH is reset. Based on the output of the latch 210, while the overcurrent condition exists, the drive strength control signal 152 disables the pull-up circuit 118 and the pull-down circuit 126 at the rising edge of the high turn-on signal for all consecutive cycles, after which the pull-up circuit 118 and the pull-down circuit 126 are enabled at the rising edge of the low turn-on signal. Thus, selecting the fourth data input of the selector circuit 204 provides slow turn-on and slow turn-off of the high-side transistor 108. Further reference Figure 4 Describe the operation of the drive strength control circuit 144 when the selector circuit 204 selects the output of the latch 210.

[0030] Figure 3 A timing diagram showing the operation of the drive strength control circuit 144, where the drive strength only weakens during the turn-off of the high-side transistor 108 during an overcurrent condition. At the rising edge 302 of the PWM signal 150, the overcurrent signal (OC_RAW) is at Figure 3The middle is high, which sets latch 206. OC_HFET output by selector circuit 204 goes high, and latch 202 does not hold reset. Latch 202 holds reset from the previous assertion of OC_HFET, and while high-side transistor 108 is turned on (shown as HDRV going high), drive strength control signal 152 is low to enable pull-up circuit 118. The rising edge 304 of the high turn-on signal (HON) sets latch 202, and while high-side transistor 108 is turned off, drive strength control signal 152 goes high to deactivate pull-down circuit 126. At the rising edge 306 of the low turn-on signal (LON), latch 206 is reset, SLOW_HS_FALL and OC_FET go low, latch 202 is reset, and drive strength control signal 152 goes low to achieve a high drive strength on the next turn-on of high-side transistor 108.

[0031] Figure 4 is a timing diagram showing the operation of drive strength control circuit 144, where drive strength is reduced during the turn-on and turn-off of high-side transistor 108 under an overcurrent condition. At the rising edge 402 of PWM signal 150, the overcurrent signal (OC_RAW) is high in Figure 4 the middle, which sets latch 206. The rising edge of SLOW_HS_FALL output by latch 206 sets latch 210. SLOW_HS_BOTH generated by latch 210 goes high, OC_HFET output by selector circuit 204 goes high, and latch 202 does not hold reset. Latch 202 holds reset from the previous assertion of OC_HFET, and while Figure 4 high-side transistor 108 is turned on (shown as HDRV going high) in the initial PWM cycle of

[0032] SLOW_HS_BOTH and drive strength control signal 152 remain high until the rising edge of the low turn-on signal after the overcurrent signal goes low at the rising edge of PWM signal 150. At the rising edge 406 of drive strength control signal 152, the overcurrent signal is high, so OC_HFET and drive strength control signal 152 remain high to deactivate pull-up circuit 118 and pull-down circuit 126. At the rising edge 407 of drive strength control signal 152, the overcurrent signal is low, and SLOW_HS_FALL remains low. At the falling edge 408 of the high turn-on signal, latch 214 is reset, and at the rising edge 409 of the low turn-on signal, latch 210 is reset. OC_HFET goes low, latch 202 is reset, and drive strength control signal 152 goes low to enable pull-up circuit 118 to achieve a high drive strength on the next turn-on of high-side transistor 108.

[0033] Figure 5 A timing diagram showing the operation of an embodiment of a drive strength control circuit 144 that provides a weak drive strength only during the turn-on of a high-side transistor 108. At the rising edge 502 of the PWM signal 150, the overcurrent signal (OC_RAW) is high in Figure 5 and OC_HFET goes high. After the low-side transistor 110 turns on, as indicated by the rising edge 504 of the low turn-on signal, OC_HFET goes low and the drive strength control signal 152 goes high to disable the pull-up circuit 118 during the next turn-on of the high-side transistor 108. At the rising edge 505 of the PWM signal 150, the overcurrent signal is high and OC_HFET goes high. At the rising edge 507 of the high turn-on signal, the turn-on of the high-side transistor 108 with a reduced gate drive is completed, and the drive strength control signal 152 goes low to effect the turn-off of the high-side transistor 108 with a high drive strength.

[0034] Figure 6 A block diagram of an example memory module 600. The memory module 600 includes a DC-DC converter 602, a memory 604, and a buffer circuit 606. The DC-DC converter 602 receives an input voltage VIN and generates an output voltage VOUT for powering the memory 604 and / or the buffer circuit 606. The buffer circuit 606 may include static or dynamic random access memory. The buffer circuit 606 may buffer signals provided between the memory 604 and a module input / output interface (not shown). The DC-DC converter 602 includes a gate driver circuit 102 to provide a variable drive strength to a high-side switching transistor of the DC-DC converter 602 to reduce ringing while employing a single level shifter to reduce circuit area and cost.

[0035] In this specification, the term "coupled" may cover connections, transmissions, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, if an intermediate component C does not change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C such that device B is controlled by device A via the control signal generated by device A.

[0036] Additionally, in this specification, the recitation of "based on" means "at least partially based on". Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0037] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed by firmware and / or software programming of the device, by construction and / or layout of hardware components, and interconnection of the device, or a combination thereof.

[0038] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to denote an interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components, or their ends.

[0039] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuitry or device. For example, what is described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage sources and / or current sources) may instead include semiconductor elements (e.g., semiconductor die and / or integrated circuit (IC) packages) within only a single physical device, and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, e.g., at the time of and / or after manufacture by an end user and / or a third party.

[0040] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may alternatively be used with little or no change to the remaining circuitry. For example, field effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs - e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion mode devices, drain extended devices, enhancement mode devices, native transistors, or other types of device structure transistors. Additionally, the device may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0041] In the claims, reference may be made to the control input of a transistor and its current terminals. In the context of an FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0042] As used herein, "turning on" an FET means that there is a conductive channel in the FET and a drain current can flow through the FET. As used herein, "turning off" an FET means that there is no conductive channel in the FET and a drain current does not flow through the FET. However, a "turned off" FET may have a current flowing through the body diode of the transistor.

[0043] The circuits described herein may be reconfigured to include additional or different components to provide at least partially similar functionality to that available prior to component replacement. Unless otherwise specified, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide a given amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0044] Although some elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features shown as external to the integrated circuit may be included in the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in a semiconductor substrate / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0045] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this description. In this specification, unless otherwise specified, "about", "approximately", or "substantially" preceding a parameter means within + / - 10% of the stated parameter.

[0046] Modifications may be made to the described examples within the scope of the claims, and other examples are possible.

Claims

1. A gate driver circuit, comprising: A pull-up circuit, comprising: A pull-up output coupled to a gate drive output; A first signal input coupled to a drive signal input; And A first enable input; A pull-down circuit, comprising: A pull-down output coupled to the gate drive output; A second signal input coupled to the drive signal input; And A second enable input; A level shifter circuit, comprising: A shifter output coupled to the first enable input and the second enable input; And A drive strength input; And A drive strength control circuit comprising a drive strength output coupled to the drive strength input.

2. The gate driver circuit according to claim 1, wherein the pull-up circuit comprises: A transistor having a first current terminal, a second current terminal, and a control terminal, wherein: The first current terminal is coupled to a power supply terminal; and The second current terminal is coupled to the gate drive output; And A logic gate having a gate output, a first input, and a second input, wherein: The first input is coupled to the drive signal input; The second input is coupled to the shifter output; and The gate output is coupled to the control terminal.

3. The gate driver circuit according to claim 1, wherein the pull-down circuit comprises: A transistor having a first current terminal, a second current terminal, and a control terminal, wherein: The first current terminal is coupled to the gate drive output; and The second current terminal is coupled to a ground terminal; And A logic gate having a gate output, a first input, and a second input, wherein: The first input is coupled to the drive signal input; The second input is coupled to the shifter output; and The gate output is coupled to the control terminal.

4. The gate driver circuit according to claim 1, wherein: The pull-up circuit is a first pull-up circuit; and The gate driver circuit comprises a second pull-up circuit, the second pull-up circuit comprising: A transistor having a first current terminal, a second current terminal, and a control terminal, wherein: The first current terminal is coupled to a power supply terminal; The second current terminal is coupled to the gate drive output; and The control terminal is coupled to the drive signal input.

5. The gate driver circuit according to claim 1, wherein: The pull-down circuit is a first pull-down circuit; and The gate driver circuit comprises a second pull-down circuit, the second pull-down circuit comprising: A transistor having a first current terminal, a second current terminal, and a control terminal, wherein: The first current terminal is coupled to the gate drive output; The second current terminal is coupled to a ground terminal; and The control terminal is coupled to the drive signal input.

6. The gate driver circuit according to claim 1, wherein the drive strength control circuit comprises: A high-on input; A multi-bit edge selection input; A first latch, comprising: A first latch output coupled to the drive strength output; A first clock input coupled to the high-on input; A first data input coupled to a logic high voltage terminal; And A first reset input; And A selector circuit, comprising: A selector output, which is coupled to the first reset input; A multi-bit selection control input, which is coupled to the multi-bit edge selection input; A first selector input, which is coupled to a logic low voltage terminal; And A second selector input, which is coupled to the logic high voltage terminal.

7. The gate driver circuit according to claim 6, wherein: The selector circuit includes a third selector input; and The drive strength control circuit includes: A pulse width modulation (PWM) input; An overcurrent input; A low turn-on input; A second latch, which includes: A second latch output, which is coupled to the third selector input; A second clock input, which is coupled to the PWM input; A second data input, which is coupled to the overcurrent input; And A second reset input; And A pulse generation circuit, which includes: A pulse input, which is coupled to the low turn-on input; and A pulse output, which is coupled to the second reset input.

8. The gate driver circuit according to claim 7, wherein: The selector circuit includes a fourth selector input; and The drive strength control circuit includes: A third latch, which includes: A third latch output; A third clock input, which is coupled to the high turn-on input; and A third data input, which is coupled to the second latch output; And A fourth latch, which includes: A fourth latch output, which is coupled to the fourth selector input; A fourth clock input, which is coupled to the second latch output; A fourth data input, which is coupled to the logic high voltage terminal; And A fourth reset input, which is coupled to the pulse output and the third latch output.

9. A gate driver circuit, which includes: A pull-up circuit, which is configured to provide current to a gate drive output in response to a drive signal at a drive signal input and an enable signal at an enable input; A pull-down circuit, which is configured to draw current from the gate drive output in response to the drive signal and the enable signal; A level shifter circuit, which is coupled to the pull-up circuit and the pull-down circuit, and the level shifter circuit is configured to generate the enable signal by level shifting a drive strength control signal; And A drive strength control circuit, which is coupled to the level shifter circuit, and the drive strength control circuit is configured to set the drive strength control signal to a first state or a second state for an edge of the drive signal.

10. The gate driver circuit according to claim 9, wherein: The pull-up circuit is a first pull-up circuit; The pull-down circuit is a first pull-down circuit; and The gate driver circuit includes: A second pull-up circuit, which is configured to provide current to the gate drive output in response to the drive signal; And A second pull-down circuit, which is configured to draw current from the gate drive output in response to the drive signal.

11. The gate driver circuit according to claim 9, wherein: The gate driver circuit is configured to provide an edge control value; and The drive strength control circuit is configured to set the drive strength control signal to the first state or the second state based on the edge control value.

12. The gate driver circuit according to claim 11, wherein: The first state deactivates the pull-up circuit and the pull-down circuit; The second state activates the pull-up circuit and the pull-down circuit; and The drive strength control circuit is configured to set the drive strength control signal to the first state during the rising edge of the drive signal and during the falling edge of the drive signal based on the edge control value.

13. The gate driver circuit according to claim 11, wherein: The first state deactivates the pull-up circuit and the pull-down circuit; The second state activates the pull-up circuit and the pull-down circuit; and The drive strength control circuit is configured to set the drive strength control signal to the second state during the rising edge of the drive signal and during the falling edge of the drive signal based on the edge control value.

14. The gate driver circuit according to claim 11, wherein: The first state deactivates the pull-up circuit and the pull-down circuit; The second state activates the pull-up circuit and the pull-down circuit; and The drive strength control circuit is configured to set the drive strength control signal to the second state during the rising edge of the drive signal and to set the drive strength control signal to the first state during the falling edge of the drive signal based on the edge control value.

15. The gate driver circuit according to claim 11, wherein: The first state deactivates the pull-up circuit and the pull-down circuit; The second state activates the pull-up circuit and the pull-down circuit; and The drive strength control circuit is configured to set the drive strength control signal to the first state during the rising edge of the drive signal and to set the drive strength control signal to the second state during the falling edge of the drive signal based on the edge control value.

16. A DC-DC converter circuit, comprising: A high-side transistor having a control terminal; A low-side transistor coupled to the high-side transistor; A modulation circuit coupled to the high-side transistor and the low-side transistor, the modulation circuit being configured to generate a modulation signal; A high-side gate driver circuit coupled between the high-side transistor and the modulation circuit, the high-side gate driver circuit comprising: A pull-up circuit configured to supply current to the control terminal in response to the modulation signal and an enable signal; A pull-down circuit configured to draw current from the control terminal of the high-side transistor in response to the modulation signal and the enable signal; A level shifter circuit coupled to the pull-up circuit and the pull-down circuit, the level shifter circuit being configured to generate the enable signal by level shifting a drive strength control signal; And A drive strength control circuit coupled to the level shifter circuit, the drive strength control circuit being configured to set the drive strength control signal to a first state or a second state for an edge of the modulation signal.

17. The DC-DC converter circuit according to claim 16, wherein: The pull-up circuit is a first pull-up circuit; The pull-down circuit is a first pull-down circuit; and The high-side gate driver circuit includes: A second pull-up circuit configured to supply current to the control terminal of the high-side transistor in response to the modulation signal; And A second pull-down circuit configured to draw current from the control terminal of the high-side transistor in response to the modulation signal.

18. The DC-DC converter circuit according to claim 16, wherein: The high-side gate driver circuit is configured to store an edge control value; and The drive strength control circuit is configured to set the drive strength control signal to the first state or the second state based on the edge control value.

19. The DC-DC converter circuit according to claim 18, wherein: The first state deactivates the pull-up circuit and the pull-down circuit; The second state activates the pull-up circuit and the pull-down circuit; and The drive strength control circuit is configured to set the drive strength control signal to the second state during the rising edge of the modulation signal and to the first state during the falling edge of the modulation signal based on the edge control value.

20. The DC-DC converter circuit according to claim 18, wherein: The first state deactivates the pull-up circuit and the pull-down circuit; The second state activates the pull-up circuit and the pull-down circuit; and The drive strength control circuit is configured to set the drive strength control signal to the first state during the rising edge of the modulation signal and to the second state during the falling edge of the modulation signal based on the edge control value.

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