Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device includes first to third transistors, first to fourth insulating layers, the first transistor including first to third conductive layers, a fifth insulating layer and a first semiconductor layer, the first insulating layer, the third conductive layer and the second insulating layer on the first conductive layer having a first opening, the fifth insulating layer being in contact with a sidewall of the first opening, and the second insulating layer being in contact with a sidewall of the second opening. The first semiconductor layer is in contact with the bottom of the first opening and the side face of the fifth insulating layer, the second conductive layer is located on the first semiconductor layer and is in contact with the first semiconductor layer, and the second (third) transistor comprises second, fourth and fifth (sixth to eighth) conductive layers, a sixth (seventh) insulating layer and a second (third) semiconductor layer. A third (fourth) insulating layer on the second (sixth) conductive layer, a fourth (seventh) conductive layer having a second (third) opening, the second (third) semiconductor layer being in contact with the bottom and sidewall of the second (third) opening, the sixth (seventh) insulating layer being on and in contact with the second (third) semiconductor layer, and the fifth (eighth) conductive layer being on and in contact with the sixth (seventh) insulating layer.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Another aspect of the present invention relates to a storage device and a method for manufacturing the storage device. Another aspect of the present invention relates to a transistor and a method for manufacturing the transistor. Another aspect of the present invention relates to a capacitor and a method for manufacturing the capacitor. Another aspect of the present invention relates to an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As an example of the technical field of one aspect of the present invention, there can be cited a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), an electronic device incorporating them, a driving method thereof, or a manufacturing method thereof.

[0003] In the present specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), and a device including such a circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips having integrated circuits, and electronic components in which chips are housed in packages. In addition, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device, etc. are themselves semiconductor devices and sometimes all include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, for example, large-scale integration (LSI) is used for semiconductor devices. For example, a central processing unit (CPU) and a memory are used for semiconductor devices. The CPU is an aggregate of semiconductor elements including a semiconductor integrated circuit (including at least transistors and a memory) obtained by processing a semiconductor wafer into a chip and having electrodes as connection terminals formed thereon.

[0005] Semiconductor circuits (IC chips) such as a CPU and a memory are mounted on a circuit board such as a printed wiring board and used as one of the components of various electronic devices.

[0006] In addition, a technique of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. This transistor is widely used in electronic devices such as integrated circuits (ICs) and display devices. As a semiconductor thin film that can be applied to a transistor, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0007] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in a non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device that can utilize the low leakage current characteristic of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0008] In recent years, as electronic devices have become smaller and lighter, there has been an increased demand for further high-density integrated circuits. In addition, there is a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a plurality of memory cells are arranged in an overlapping manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of the integrated circuit.

[0009] Furthermore, if vertical transistors are used, integrated circuits can be made more dense. For example, Patent Document 4 discloses a vertical transistor in which the side surfaces of an oxide semiconductor are covered with a gate electrode via a gate insulating layer.

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Publication No. 2013-211537

[0011] [Non-patent document 1] M. Oota, et al., "3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm", IEDM Tech. Dig., 2019, pp. 50-53 Summary of the invention Technical problem to be solved by the invention

[0012] One of the objectives of one embodiment of the present invention is to provide a semiconductor device, a memory device, or a transistor that can achieve miniaturization or high integration. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device, a memory device, or a transistor with high reliability. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device or a memory device with high read accuracy. In addition, one of the objectives of one embodiment of the present invention is to provide a transistor with a large on-state current. In addition, one of the objectives of one embodiment of the present invention is to provide a transistor with good electrical characteristics. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device or a memory device at low cost. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device or a memory device with low power consumption. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device or a memory device with a high operating speed. In addition, one of the objectives of one embodiment of the present invention is to provide a novel semiconductor device, a memory device, or a transistor.

[0013] In addition, one of the objectives of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device, a memory device, or a transistor that can achieve miniaturization or high integration. In addition, one of the objectives of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device, a memory device, or a transistor with high reliability. In addition, one of the objectives of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with high read accuracy. In addition, one of the objectives of one embodiment of the present invention is to provide a method for manufacturing a transistor with a large on-state current. In addition, one of the objectives of one embodiment of the present invention is to provide a method for manufacturing a transistor with good electrical characteristics. In addition, one of the objectives of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with a high yield. In addition, one of the objectives of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with low power consumption. In addition, one of the objectives of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with a high operating speed. In addition, one of the objectives of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device, a memory device, or a transistor.

[0014] Note that the description of these objectives does not preclude the existence of other objectives. One embodiment of the present invention does not need to achieve all of the above objectives. Other objectives than the above can be extracted from the description of the specification, the drawings, and the claims. Means for Solving Technical Problems

[0015] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring. Among them, the source and drain of the first transistor, the second transistor, and the third transistor are disposed at different heights with respect to the substrate surface. The second transistor is disposed on the first transistor in a manner overlapping the first transistor, and the third transistor is disposed on the second transistor in a manner overlapping the second transistor. The gate of the first transistor is electrically connected to the first wiring, one of the source and drain of the first transistor is electrically connected to the gate of the second transistor, and the other of the source and drain of the first transistor is electrically connected to the second wiring. One of the source and drain of the second transistor is electrically connected to one of the source and drain of the third transistor, and the other of the source and drain of the second transistor is electrically connected to the third wiring. The gate of the third transistor is electrically connected to the fourth wiring, and the other of the source and drain of the third transistor is electrically connected to the fifth wiring.

[0016] In the semiconductor device according to one embodiment of the present invention described above, preferably, at least one of the first transistor, the second transistor, and the third transistor contains a metal oxide.

[0017] In the semiconductor device according to one embodiment of the present invention described above, preferably, it further includes a node electrically connecting one of the source and drain of the first transistor to the gate of the second transistor. The first transistor has a function of writing data corresponding to the potential provided by the second wiring into the node when a first potential is provided from the first wiring and has a function of holding the data in the node when a second potential is provided from the first wiring. The second transistor and the third transistor have a function of reading the data held in the node when a third potential is provided to the third wiring, a fourth potential is provided to the fifth wiring, and a fifth potential is provided to the fourth wiring. The first potential is a potential at which the first transistor becomes an on state, the second potential is a potential at which the first transistor becomes an off state, the fourth potential is a potential higher than the third potential, and the fifth potential is a potential at which the third transistor becomes an on state.

[0018] In addition, one aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring. Here, the sources and drains of the first transistor, the second transistor, and the third transistor are provided at different heights with respect to the substrate surface. The second transistor is provided on the first transistor in a manner overlapping the first transistor. The third transistor is provided on the second transistor in a manner overlapping the second transistor. The first transistor is provided such that the gate surrounds the semiconductor layer when viewed from the plane. The second transistor is provided such that the semiconductor layer surrounds the gate when viewed from the plane. The third transistor is provided such that the semiconductor layer surrounds the gate when viewed from the plane. The gate of the first transistor is electrically connected to the first wiring. One of the source and drain of the first transistor is electrically connected to the gate of the second transistor. The other of the source and drain of the first transistor is electrically connected to the second wiring. One of the source and drain of the second transistor is electrically connected to one of the source and drain of the third transistor. The other of the source and drain of the second transistor is electrically connected to the third wiring. The gate of the third transistor is electrically connected to the fourth wiring. The other of the source and drain of the third transistor is electrically connected to the fifth wiring.

[0019] In the semiconductor device according to one aspect of the present invention described above, preferably, the semiconductor layer in at least one of the first transistor, the second transistor, and the third transistor contains a metal oxide.

[0020] In the semiconductor device according to one aspect of the present invention described above, preferably, it further includes a node electrically connecting one of the source and drain of the first transistor and the gate of the second transistor. The first transistor has a function of writing data corresponding to the potential provided by the second wiring into the node when a first potential is provided from the first wiring and has a function of holding the data in the node when a second potential is provided from the first wiring. The second transistor and the third transistor have a function of reading the data held in the node when a third potential is provided to the third wiring, a fourth potential is provided to the fifth wiring, and a fifth potential is provided to the fourth wiring. The first potential is a potential at which the first transistor becomes in an on state. The second potential is a potential at which the first transistor becomes in an off state. The fourth potential is a potential higher than the third potential. The fifth potential is a potential at which the third transistor becomes in an on state.

[0021] In addition, one aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. Among them, the first transistor, the second transistor, and the third transistor are stacked in this order. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fifth insulating layer, and a first semiconductor layer. The first insulating layer, the third conductive layer, and the second insulating layer are sequentially stacked on the first conductive layer. A first opening reaching the first conductive layer is provided in the first insulating layer, the third conductive layer, and the second insulating layer. The fifth insulating layer is provided in a manner of contacting the sidewall of the first opening. The first semiconductor layer is provided in a manner of contacting the top surface of the first conductive layer in the first opening, the side surface of the fifth insulating layer in the first opening, and the top surface of the second insulating layer. The second conductive layer is provided in a manner of contacting the top surface of the first semiconductor layer and having a region overlapping with the first conductive layer. The second transistor includes a second conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth insulating layer, and a second semiconductor layer. The third insulating layer and the fourth conductive layer are sequentially stacked on the second conductive layer. A second opening reaching the second conductive layer is provided in the third insulating layer and the fourth conductive layer. The second semiconductor layer is provided in a manner of contacting the top surface of the second conductive layer in the second opening, the side surface of the third insulating layer in the second opening, the side surface of the fourth conductive layer in the second opening, and the top surface of the fourth conductive layer. The sixth insulating layer is provided in a manner of contacting the top surface of the second semiconductor layer, the side surface of the second semiconductor layer, the top surface of the fourth conductive layer, the side surface of the fourth conductive layer, and the top surface of the third insulating layer. The fifth conductive layer is provided on the sixth insulating layer in a manner of contacting it and filling the second opening. The third transistor includes a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a seventh insulating layer, and a third semiconductor layer. The sixth conductive layer is provided in a manner of contacting the top surface of the fifth conductive layer. The fourth insulating layer and the seventh conductive layer are sequentially stacked on the sixth conductive layer. A third opening reaching the sixth conductive layer is provided in the fourth insulating layer and the seventh conductive layer. The third semiconductor layer is provided in a manner of contacting the top surface of the sixth conductive layer in the third opening, the side surface of the fourth insulating layer in the third opening, the side surface of the seventh conductive layer in the third opening, and the top surface of the seventh conductive layer. The seventh insulating layer is provided in a manner of contacting the top surface of the third semiconductor layer, the side surface of the third semiconductor layer, the top surface of the seventh conductive layer, the side surface of the seventh conductive layer, and the top surface of the fourth insulating layer. The eighth conductive layer is provided on the seventh insulating layer in a manner of contacting it and filling the third opening.

[0022] In the semiconductor device according to one aspect of the present invention described above, preferably, at least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer contains a metal oxide.

[0023] In the semiconductor device according to one embodiment of the present invention described above, preferably, the second conductive layer includes a ninth conductive layer and a tenth conductive layer. The ninth conductive layer is disposed in such a manner as to contact the top surface of the first semiconductor layer and have a region overlapping with the first conductive layer. The tenth conductive layer is disposed in such a manner as to contact the top surface of the ninth conductive layer and have a region overlapping with the first conductive layer. The second semiconductor layer is disposed in such a manner as to contact the top surface of the tenth conductive layer.

[0024] In the semiconductor device according to one embodiment of the present invention described above, preferably, the second conductive layer includes a ninth conductive layer, a tenth conductive layer, and an eleventh conductive layer. The ninth conductive layer is disposed in such a manner as to contact the top surface of the first semiconductor layer and have a region overlapping with the first conductive layer. The tenth conductive layer is disposed in such a manner as to contact the top surface of the ninth conductive layer. The eleventh conductive layer is disposed in such a manner as to contact the top surface of the tenth conductive layer and have a region overlapping with the first conductive layer. The second semiconductor layer is disposed in such a manner as to contact the top surface of the eleventh conductive layer.

[0025] In the semiconductor device according to one embodiment of the present invention described above, preferably, there is a capacitor between the first transistor and the second transistor. The first transistor, the second transistor, the capacitor, and the third transistor are stacked in this order. The capacitor includes a ninth conductive layer, a tenth conductive layer, and an eighth insulating layer. The eighth insulating layer has a region in contact with the side surface of the ninth conductive layer. The tenth conductive layer covers at least a part of the side surface of the ninth conductive layer with the eighth insulating layer interposed therebetween. The ninth conductive layer is disposed in such a manner as to contact the top surface of the fifth conductive layer. The sixth conductive layer is disposed in such a manner as to contact the top surface of the ninth conductive layer.

[0026] In addition, one aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. Among them, the first transistor, the second transistor, and the third transistor are stacked in this order. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fifth insulating layer, and a first semiconductor layer. The first insulating layer, the third conductive layer, and the second insulating layer are sequentially stacked on the first conductive layer. A first opening reaching the first conductive layer is provided in the first insulating layer, the third conductive layer, and the second insulating layer. The fifth insulating layer is provided in a manner of contacting the side wall of the first opening. The first semiconductor layer is provided in a manner of contacting the top surface of the first conductive layer in the first opening, the side surface of the fifth insulating layer in the first opening, and the top surface of the second insulating layer. The second conductive layer is provided in a manner of contacting the top surface of the first semiconductor layer and having an area overlapping with the first conductive layer. The third conductive layer is provided in a manner of surrounding the first semiconductor layer with the fifth insulating layer interposed therebetween when viewed in plan. The second transistor includes a second conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth insulating layer, and a second semiconductor layer. The third insulating layer and the fourth conductive layer are sequentially stacked on the second conductive layer. A second opening reaching the second conductive layer is provided in the third insulating layer and the fourth conductive layer. The second semiconductor layer is provided in a manner of contacting the top surface of the second conductive layer in the second opening, the side surface of the third insulating layer in the second opening, the side surface of the fourth conductive layer in the second opening, and the top surface of the fourth conductive layer, and surrounding the fifth conductive layer with the sixth insulating layer interposed therebetween when viewed in plan. The sixth insulating layer is provided in a manner of contacting the top surface of the second semiconductor layer, the side surface of the second semiconductor layer, the top surface of the fourth conductive layer, the side surface of the fourth conductive layer, and the top surface of the third insulating layer. The fifth conductive layer is provided on the sixth insulating layer in a manner of contacting and filling the second opening. The third transistor includes a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a seventh insulating layer, and a third semiconductor layer. The sixth conductive layer is provided in a manner of contacting the top surface of the fifth conductive layer. The fourth insulating layer and the seventh conductive layer are sequentially stacked on the sixth conductive layer. A third opening reaching the sixth conductive layer is provided in the fourth insulating layer and the seventh conductive layer. The third semiconductor layer is provided in a manner of contacting the top surface of the sixth conductive layer in the third opening, the side surface of the fourth insulating layer in the third opening, the side surface of the seventh conductive layer in the third opening, and the top surface of the seventh conductive layer, and surrounding the eighth conductive layer with the seventh insulating layer interposed therebetween when viewed in plan. The seventh insulating layer is provided in a manner of contacting the top surface of the third semiconductor layer, the side surface of the third semiconductor layer, the top surface of the seventh conductive layer, the side surface of the seventh conductive layer, and the top surface of the fourth insulating layer. The eighth conductive layer is provided on the seventh insulating layer in a manner of contacting and filling the third opening.

[0027] In the semiconductor device according to one aspect of the present invention described above, preferably, at least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer contains a metal oxide.

[0028] In the semiconductor device according to one embodiment of the present invention described above, preferably, the second conductive layer includes a ninth conductive layer and a tenth conductive layer. The ninth conductive layer is disposed in contact with the top surface of the first semiconductor layer and has a region overlapping with the first conductive layer. The tenth conductive layer is disposed in contact with the top surface of the ninth conductive layer and has a region overlapping with the first conductive layer. The second semiconductor layer is disposed in contact with the top surface of the tenth conductive layer.

[0029] In the semiconductor device according to one embodiment of the present invention described above, preferably, the second conductive layer includes a ninth conductive layer, a tenth conductive layer, and an eleventh conductive layer. The ninth conductive layer is disposed in contact with the top surface of the first semiconductor layer and has a region overlapping with the first conductive layer. The tenth conductive layer is disposed in contact with the top surface of the ninth conductive layer. The eleventh conductive layer is disposed in contact with the top surface of the tenth conductive layer and has a region overlapping with the first conductive layer. The second semiconductor layer is disposed in contact with the top surface of the eleventh conductive layer.

[0030] In the semiconductor device according to one embodiment of the present invention described above, preferably, there is a capacitor between the first transistor and the second transistor. The first transistor, the second transistor, the capacitor, and the third transistor are stacked in this order. The capacitor includes a ninth conductive layer, a tenth conductive layer, and an eighth insulating layer. The eighth insulating layer has a region in contact with the side surface of the ninth conductive layer. The tenth conductive layer covers at least a part of the side surface of the ninth conductive layer with the eighth insulating layer interposed therebetween. The ninth conductive layer is disposed in contact with the top surface of the fifth conductive layer. The sixth conductive layer is disposed in contact with the top surface of the ninth conductive layer.

[0031] In addition, one aspect of the present invention is a method of manufacturing a semiconductor device, including the following steps: forming a first conductive layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a second insulating layer on the first insulating layer and the second conductive layer; processing the second conductive layer and the second insulating layer to form a first opening reaching the first conductive layer, and forming a first insulating film that contacts the top surface of the first conductive layer within the first opening, the side surface of the first insulating layer within the first opening, the side surface of the second conductive layer within the first opening, the side surface of the second insulating layer within the first opening, and the top surface of the second insulating layer; processing the first insulating film to expose the top surface of the first conductive layer within the first opening and the top surface of the second insulating layer, and forming a third insulating layer that contacts the side surface of the first insulating layer within the first opening, the side surface of the second conductive layer within the first opening, and the side surface of the second insulating layer within the first opening; forming a first metal oxide film that contacts the top surface of the first conductive layer, the side surface of the third insulating layer, the top surface of the third insulating layer, and the top surface of the second insulating layer; processing the first metal oxide film to form a first semiconductor layer having a region overlapping with the first opening; forming a third conductive layer that contacts the top surface of the first semiconductor layer; forming a fourth insulating layer on the third conductive layer and the second insulating layer; forming a first conductive film on the fourth insulating layer; processing the first conductive film and the fourth insulating layer to form a second opening reaching the third conductive layer; forming a second metal oxide film that contacts the top surface of the third conductive layer within the second opening, the side surface of the fourth insulating layer within the second opening, the side surface of the first conductive film within the second opening, and the top surface of the first conductive film; processing the second metal oxide film to form a second semiconductor layer having a region overlapping with the second opening; processing the first conductive film to form a fourth conductive layer having a region overlapping with the third conductive layer; forming a fifth insulating layer on the second semiconductor layer, the fourth conductive layer, and the fourth insulating layer; forming a second conductive film on the fifth insulating layer; processing the second conductive film to form a fifth conductive layer having a region overlapping with the second semiconductor layer; forming a sixth insulating layer on the fifth conductive layer and the fifth insulating layer; processing the top surface of the sixth insulating layer and the top surface of the fifth conductive layer so that their heights relative to the substrate surface are substantially the same; forming a sixth conductive layer that contacts the top surface of the fifth conductive layer; forming a seventh insulating layer on the fifth conductive layer and the sixth insulating layer; forming a third conductive film on the seventh insulating layer; processing the third conductive film and the seventh insulating layer to form a third opening reaching the sixth conductive layer; forming a third metal oxide film that contacts the top surface of the sixth conductive layer within the third opening, the side surface of the seventh insulating layer within the third opening, the side surface of the third conductive film within the third opening, and the top surface of the third conductive film; processing the third metal oxide film to form a third semiconductor layer having a region overlapping with the third opening; processing the third conductive film to form a seventh conductive layer having a region overlapping with the sixth conductive layer; forming an eighth insulating layer on the third semiconductor layer, the seventh conductive layer, and the seventh insulating layer;Form a fourth conductive film on the eighth insulating layer; process the fourth conductive film to form an eighth conductive layer having a region overlapping with the third semiconductor layer. Advantages of the Invention

[0032] According to one aspect of the present invention, a semiconductor device, a storage device, or a transistor capable of miniaturization or high integration can be provided. In addition, according to one aspect of the present invention, a semiconductor device, a storage device, or a transistor with high reliability can be provided. In addition, according to one aspect of the present invention, a semiconductor device or a storage device with high read accuracy can be provided. In addition, according to one aspect of the present invention, a transistor with a large on-state current can be provided. In addition, according to one aspect of the present invention, a transistor with good electrical characteristics can be provided. In addition, according to one aspect of the present invention, an inexpensive semiconductor device or a storage device can be provided. In addition, according to one aspect of the present invention, a semiconductor device or a storage device with low power consumption can be provided. In addition, according to one aspect of the present invention, a semiconductor device or a storage device with a high operating speed can be provided. In addition, according to one aspect of the present invention, a novel semiconductor device, a storage device, or a transistor can be provided.

[0033] In addition, according to one aspect of the present invention, a method for manufacturing a semiconductor device, a storage device, or a transistor capable of miniaturization or high integration can be provided. In addition, according to one aspect of the present invention, a method for manufacturing a semiconductor device, a storage device, or a transistor with high reliability can be provided. In addition, according to one aspect of the present invention, a method for manufacturing a semiconductor device or a storage device with high read accuracy can be provided. In addition, according to one aspect of the present invention, a method for manufacturing a transistor with a large on-state current can be provided. In addition, according to one aspect of the present invention, a method for manufacturing a transistor with good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a method for manufacturing a semiconductor device or a storage device with a high yield can be provided. In addition, according to one aspect of the present invention, a method for manufacturing a semiconductor device or a storage device with low power consumption can be provided. In addition, according to one aspect of the present invention, a method for manufacturing a semiconductor device or a storage device with a high operating speed can be provided. In addition, according to one aspect of the present invention, a method for manufacturing a novel semiconductor device, a storage device, or a transistor can be provided.

[0034] Note that the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have all of the above effects. Effects other than the above can be extracted from the description in the specification, the drawings, and the claims. Brief Description of the Drawings

[0035] Figure 1A It is a block diagram showing a structural example of a semiconductor device. Figure 1B and Figure 1C It is a circuit diagram showing an example of the structure of a memory cell. Figure 2A and Figure 2B It is a circuit diagram showing an example of the structure of a memory cell. Figure 3A It is a block diagram showing an example of the structure of a semiconductor device. Figure 3B and Figure 3C It is a circuit diagram showing an example of the structure of a memory cell. Figure 4A It is a plan view showing an example of the structure of a semiconductor device. Figure 4B and Figure 4C It is a cross-sectional view showing an example of the structure of a semiconductor device. Figure 5A It is a plan view showing an example of the structure of a semiconductor device. Figure 5B and Figure 5C It is a cross-sectional view showing an example of the structure of a semiconductor device. Fig. 6A and Figure 6B It is a cross-sectional view showing an example of the structure of a transistor. Fig. 7A It is a plan view showing an example of the structure of a semiconductor device. Figure 7B and Figure 7C It is a cross-sectional view showing an example of the structure of a semiconductor device. Fig. 8A It is a plan view showing an example of the structure of a semiconductor device. Figure 8B and Figure 8C It is a cross-sectional view showing an example of the structure of a semiconductor device. Fig. 9A It is a plan view showing an example of the structure of a semiconductor device. Fig. 9B and Fig. 9C It is a cross-sectional view showing an example of the structure of a semiconductor device. Fig. 10A It is a plan view showing an example of the structure of a semiconductor device. Fig. 10B and Fig. 10C It is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.11A It is a plan view showing an example of the structure of a semiconductor device. Fig. 11B and Fig. 11C It is a cross-sectional view showing an example of the structure of a semiconductor device. Fig. 12A It is a plan view showing an example of the structure of a semiconductor device. Fig. 12B and Fig. 12C It is a cross-sectional view showing an example of the structure of a semiconductor device. FIG. 13A to FIG. 13C It is a plan view showing an example of the structure of a semiconductor device. FIG. 14A to FIG. 14C is a plan view showing an example of the structure of a semiconductor device. FIG. 15A to FIG. 15C is a plan view showing an example of the structure of a semiconductor device. Fig.16A and Fig. 16B is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.17A and Fig. 17B is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.18A and Fig.18B is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.19A and Fig.19B is a cross-sectional view showing an example of the structure of a semiconductor device. Fig. 20A and Fig. 20B is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.21A and Fig.21B is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.22A and Fig. 22B is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.23A and Fig. 23B is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.24A and Fig. 24B is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.25A is a block diagram showing an example of the structure of a display device. Fig.25B is a plan view showing an example of the structure of a pixel. Fig.25C is a circuit diagram showing an example of the structure of a pixel. Fig.26A and Fig.26B is a plan view showing an example of the structure of a semiconductor device. Fig. 27 is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.28 is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.29A and Fig.29B is a plan view showing an example of the structure of a semiconductor device. Fig. 30A and Fig. 30B is a plan view showing an example of the structure of a semiconductor device. Fig.31A and Fig.31BIt is a plan view showing an example of the structure of a semiconductor device. Fig.32A and Fig.32B It is a plan view showing an example of the structure of a semiconductor device. Fig.33A and Fig.33B It is a plan view showing an example of the structure of a semiconductor device. Fig.34A It is a plan view showing an example of the manufacturing method of a semiconductor device. Fig.34B and Fig.34C It is a cross-sectional view showing an example of the manufacturing method of a semiconductor device. Fig.35A It is a plan view showing an example of the manufacturing method of a semiconductor device. Fig.35B and Fig.35C It is a cross-sectional view showing an example of the manufacturing method of a semiconductor device. Fig.36A It is a plan view showing an example of the manufacturing method of a semiconductor device. Fig.36B and Fig.36C It is a cross-sectional view showing an example of the manufacturing method of a semiconductor device. Fig.37A It is a plan view showing an example of the manufacturing method of a semiconductor device. Fig.37B and Fig.37C It is a cross-sectional view showing an example of the manufacturing method of a semiconductor device. Fig.38A It is a plan view showing an example of the manufacturing method of a semiconductor device. Fig.38B and Fig.38C It is a cross-sectional view showing an example of the manufacturing method of a semiconductor device. Fig.39A It is a plan view showing an example of the manufacturing method of a semiconductor device. Fig.39B and Fig.39C It is a cross-sectional view showing an example of the manufacturing method of a semiconductor device. Fig.40A It is a plan view showing an example of the manufacturing method of a semiconductor device. Fig.40B and Fig.40C It is a cross-sectional view showing an example of the manufacturing method of a semiconductor device. Fig.41A It is a plan view showing an example of the manufacturing method of a semiconductor device. Fig.41B and Fig.41C It is a cross-sectional view showing an example of the manufacturing method of a semiconductor device. Fig.42A It is a plan view showing an example of the manufacturing method of a semiconductor device. Fig.42B and Fig.42C It is a cross-sectional view showing an example of the manufacturing method of a semiconductor device. Fig.43AIt is a plan view showing an example of a manufacturing method of a semiconductor device. Fig.43B and Fig.43C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Fig.44A It is a plan view showing an example of a manufacturing method of a semiconductor device. Fig.44B and Fig.44C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Fig.45A It is a plan view showing an example of a manufacturing method of a semiconductor device. Fig.45B and Fig.45C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Fig.46A It is a plan view showing an example of a manufacturing method of a semiconductor device. Fig.46B and Fig.46C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Fig.47A It is a plan view showing an example of a manufacturing method of a semiconductor device. Fig.47B and Fig.47C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Fig.48A It is a plan view showing an example of a manufacturing method of a semiconductor device. Fig.48B and Fig.48C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Fig.49A It is a plan view showing an example of a manufacturing method of a semiconductor device. Fig.49B and Fig.49C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Fig.50A It is a plan view showing an example of a manufacturing method of a semiconductor device. Fig.50B and Fig.50C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Fig.51A It is a plan view showing an example of a manufacturing method of a semiconductor device. Fig.51B and Fig.51C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Fig.52A It is a plan view showing an example of a manufacturing method of a semiconductor device. Fig.52B and Fig.52C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Fig.53A It is a plan view showing an example of a manufacturing method of a semiconductor device. Fig.53B and Fig.53C It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device. Fig.54A is a plan view showing an example of a method for manufacturing a semiconductor device. Fig.54B and Fig.54C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Fig.55A is a plan view showing an example of a method for manufacturing a semiconductor device. Fig.55B and Fig.55C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Fig.56 is a perspective view showing an example of the structure of a semiconductor device. Fig.57 is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.58 is a cross-sectional view showing an example of the structure of a semiconductor device. Fig.59A and Fig.59B is a view showing an example of an electronic component. Fig.60A and Fig.60B is a view showing an example of the structure of an electronic device. Figures 60C to 60E is a view showing an example of a mainframe computer. Fig.61 is a view showing an example of a space device. Fig.62 is a view showing an example of a storage system that can be used in a data center. Mode for Carrying Out the Invention

[0036] The embodiments will be described in detail with reference to the accompanying drawings. However, those of ordinary skill in the art can easily understand the fact that the present invention is not limited to the following description and can be transformed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following embodiments.

[0037] Note that in the structure of the invention described below, the same reference numerals are used in common between different drawings to denote the same parts or parts having the same function, and the repeated description thereof is omitted. In addition, the same hatching is sometimes used when indicating parts having the same function, and no particular reference numeral is attached.

[0038] In addition, for ease of understanding, the positions, sizes, ranges, etc. of the respective components shown in the drawings do not necessarily represent their actual positions, sizes, ranges, etc. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings. For example, in an actual manufacturing process, layers or resist masks, etc. may be unintentionally thinned due to processing such as etching, but the illustration may be omitted for ease of understanding.

[0039] In this specification and the like, for convenience, ordinal numbers such as "first" and "second" are used, and such ordinal numbers do not limit the number of components or the order of components (for example, the process order or the stacking order). In addition, the ordinal numbers attached to a component in one part of this specification may be inconsistent with the ordinal numbers attached to the same component in another part of this specification or in the claims.

[0040] A transistor is a type of semiconductor device, and can perform functions such as amplifying current or voltage, and switching operations for controlling conduction or non - conduction. The transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin - film transistors (TFTs: Thin Film Transistors).

[0041] In this specification and the like, a transistor refers to a device having at least three terminals: a gate, a drain, and a source. The transistor has a region (also referred to as a channel - forming region) for forming a channel between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel - forming region. Note that in this specification and the like, the channel - forming region refers to the region through which current mainly flows.

[0042] In addition, in cases where transistors with different polarities are used or the direction of current changes during circuit operation, etc., the functions of the "source" and "drain" may be swapped. Therefore, in this specification and the like, "source" and "drain" can be used interchangeably.

[0043] Note that impurities in a semiconductor refer to elements other than the main components constituting the semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity. When impurities are included, for example, an increase in the defect state density of the semiconductor or a decrease in crystallinity may occur. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, for example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In addition, water sometimes acts as an impurity. Further, for example, the incorporation of impurities sometimes leads to the formation of oxygen vacancies (also denoted as V O ) in the oxide semiconductor.

[0044] Note that in this specification and the like, an oxynitride refers to a material in which the oxygen content is more than the nitrogen content in its composition. A nitride oxide refers to a material in which the nitrogen content is more than the oxygen content in its composition.

[0045] For example, the content of elements such as hydrogen, oxygen, carbon, and nitrogen in a film can be analyzed by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy). When the content ratio of the target element is high (for example, 0.5 atomic% or more or 1 atomic% or more), it is preferable to perform analysis using XPS. On the other hand, when the content ratio of the target element is low (for example, 0.5 atomic% or less or 1 atomic% or less), it is preferable to perform analysis using SIMS. When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analysis techniques.

[0046] In addition, in this specification and the like, depending on the situation, phrases such as "film" and "layer" can be interchanged with each other. For example, "conductive layer" can sometimes be changed to "conductive film", and "conductive film" can sometimes be changed to "conductive layer". Further, for example, "insulating film" can sometimes be changed to "insulating layer", and "insulating layer" can sometimes be changed to "insulating film". Moreover, for example, "semiconductor film" can sometimes be changed to "semiconductor layer", and "semiconductor layer" can sometimes be changed to "semiconductor film".

[0047] In this specification and the like, "parallel" means a state where the angle formed by two straight lines is -10 degrees or more and 10 degrees or less. Therefore, it also includes a state where the angle is -5 degrees or more and 5 degrees or less. "Substantially parallel" means a state where the angle formed by two straight lines is -30 degrees or more and 30 degrees or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80 degrees or more and 100 degrees or less. Therefore, it also includes a state where the angle is 85 degrees or more and 95 degrees or less. "Substantially perpendicular" means a state where the angle formed by two straight lines is 60 degrees or more and 120 degrees or less.

[0048] In this specification and the like, "electrically connected" includes cases where connection is made through "elements having a certain electrical function". Here, there are no particular restrictions on "elements having a certain electrical function" as long as they can transmit and receive electrical signals between the connection objects. For example, "elements having a certain electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, coils, capacitors, and other elements having various functions.

[0049] Furthermore, in this specification and the like, when it is described that "X is connected to Y", it means that the following cases are disclosed in this specification and the like: the case where X is electrically connected to Y; the case where X is functionally connected to Y; and the case where X is directly connected to Y. Therefore, it is not limited to the connection relationships shown in the drawings or the text. For example, other connection relationships are also within the scope described in the drawings or the text. X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, or layers).

[0050] As an example of the case where X and Y are electrically connected, one or more elements capable of electrically connecting X and Y (such as switches, transistors, capacitive elements, inductors, resistive elements, diodes, display devices, light-emitting devices, loads, etc.) can be connected between X and Y. In addition, the switch has a function of controlling on or off. In other words, whether current flows is controlled by making the switch in a conducting state (on state) or a non-conducting state (off state).

[0051] In addition, when both an element and a power supply line (e.g., VDD (high power supply potential), VSS (low power supply potential), GND (ground potential), or a wiring for supplying a desired potential) are disposed between X and Y, it cannot be said that X and Y are electrically connected. In addition, when only a power supply line is disposed between X and Y, there are no other elements between X and Y, and thus it can be said that X and Y are directly connected. Therefore, when only a power supply line is disposed between X and Y, it can also be said that "X and Y are electrically connected". However, when both an element and a power supply line are disposed between X and Y, it can be said that X is electrically connected to the power supply line (through the element) and Y is electrically connected to the power supply line, but it cannot be said that X and Y are electrically connected. In addition, when the gate and source of a transistor are interposed between X and Y, it cannot be said that X and Y are electrically connected. In addition, when the gate and drain of a transistor are interposed between X and Y, it cannot be said that X and Y are electrically connected. That is, with respect to a transistor, when the drain and source of the transistor are interposed between X and Y, it can be said that X and Y are electrically connected. In addition, when a capacitive element is disposed between X and Y, sometimes it can be said that X and Y are electrically connected, and sometimes it cannot be said that X and Y are electrically connected. For example, in the structure of a digital circuit or a logic circuit, when a capacitive element is disposed between X and Y, sometimes it cannot be said that X and Y are electrically connected. On the other hand, for example, in the structure of an analog circuit, when a capacitive element is disposed between X and Y, sometimes it can be said that X and Y are electrically connected.

[0052] As an example of a case where X and Y are functionally connected, for example, one or more circuits capable of functionally connecting X and Y (e.g., logic circuits (e.g., inverters, NAND circuits, and NOR circuits), signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (e.g., (power supply circuits such as boost circuits or buck circuits), level shift circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (e.g., circuits capable of increasing the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, and buffer circuits), signal generation circuits, storage circuits, and control circuits) can be connected between X and Y. Additionally, as an example, even when other circuits are included between X and Y, it can be said that X and Y are functionally connected when the signal output from X is transmitted to Y.

[0053] In addition, for example, it can be expressed as "X, the source of the transistor (sometimes alternatively referred to as one of the first and second terminals) and the drain of the transistor (sometimes alternatively referred to as the other of the first and second terminals) are electrically connected to each other, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence". Or, it can be expressed as "The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence". Or, it can be expressed as "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are arranged to be connected to each other in sequence". By specifying the connection order in the circuit structure using the same expression method as these examples, the source and drain of the transistor can be distinguished and the technical scope can be determined. Note that this expression method is an example and is not limited to the above expression method. Here, X and Y are objects (for example, devices, components, circuits, wirings, electrodes, terminals, conductive films or layers).

[0054] In addition, even when independent components on a circuit diagram are electrically connected to each other, sometimes one component has the functions of multiple components. For example, when a part of the wiring is used as an electrode, one conductive film has the two functions of wiring and electrode. Therefore, the scope of "electrically connected" in this specification also includes the case where one conductive film has the functions of multiple components.

[0055] In this specification and the like, a "resistive element" can be, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification and the like, a "resistive element" includes a wiring having a resistance value, a transistor through which current flows between the source and drain, a diode, or a coil. Therefore, a "resistor" can sometimes be alternatively referred to as a "resistance", a "load", or a "region having a resistance value". In contrast, a "resistance", a "load", or a "region having a resistance value", etc. can sometimes be alternatively referred to as a "resistive element". As the resistance value, for example, it is preferably 1 mΩ or more and 10Ω or less, more preferably 5 mΩ or more and 5Ω or less, and further preferably 10 mΩ or more and 1Ω or less. In addition, for example, it can also be 1Ω or more and 1×10 9 Ω or less.

[0056] In this specification and the like, a "capacitive element" can be, for example, a circuit element having a capacitance value higher than 0 F, a region of a wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, a "capacitive element", a "parasitic capacitance", or a "gate capacitance" can sometimes be interchangeably referred to as a "capacitance". In contrast, a "capacitance" can sometimes be interchangeably referred to as a "capacitive element", a "parasitic capacitance", or a "gate capacitance". In addition, a "capacitance" (including a "capacitance" having three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Thus, the "pair of conductors" of a "capacitance" can be interchangeably referred to as a "pair of electrodes", a "pair of conductive regions", a "pair of regions", or a "pair of terminals". In addition, "one of a pair of terminals" and "the other of a pair of terminals" are sometimes referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. In addition, for example, it can also be 1 pF or more and 10 μF or less.

[0057] In this specification and the like, a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal for controlling the conduction state of the transistor. The two terminals used as the source or the drain are the input / output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type or p-channel type) and the magnitudes of the potentials applied to the three terminals of the transistor, one of the two input / output terminals serves as the source and the other serves as the drain. Therefore, in this specification and the like, the source and the drain can be interchanged with each other. In this specification and the like, when describing the connection relationship of a transistor, the expressions "one of the source and the drain" (a first electrode or a first terminal) and "the other of the source and the drain" (a second electrode or a second terminal) are used. In addition, depending on the structure of the transistor, sometimes in addition to the above three terminals, it also includes a back gate. In this case, in this specification and the like, sometimes one of the gate and the back gate of the transistor is referred to as a first gate, and the other of the gate and the back gate of the transistor is referred to as a second gate. And in the same transistor, sometimes the "gate" and the "back gate" can be interchanged with each other. In addition, when a transistor includes three or more gates, in this specification and the like, sometimes each gate is referred to as a first gate, a second gate, a third gate, and the like.

[0058] For example, in this specification and the like, as an example of a transistor, a multi-gate structure transistor having two or more gates can be adopted. When the multi-gate structure is adopted, since the channel formation regions are connected in series, a structure in which a plurality of transistors are connected in series is formed. Therefore, by adopting the multi-gate structure, the off-state current can be reduced, and the breakdown voltage of the transistor (reliability improvement) can be increased. Alternatively, by using the multi-gate structure, when the transistor operates in the saturation region, even if the voltage between the drain and the source changes, the change in the drain-source current is not very large, so that a voltage-current characteristic with a flat slope angle can be obtained. When using the voltage-current characteristic with a flat slope angle, an ideal current source circuit or an active load with an extremely high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0059] In addition, the case where a circuit diagram shows one circuit element sometimes includes the case where the circuit element has a plurality of circuit elements. For example, the case where a circuit diagram shows one resistor includes the case where two or more resistors are connected in series. For example, the case where a circuit diagram shows one resistor includes the case where two or more resistors are connected in series. In addition, for example, the case where a circuit diagram shows one transistor includes the case where two or more transistors are connected in series and the gates of the respective transistors are electrically connected to each other. Similarly, for example, the case where a circuit diagram shows one switch includes the case where the switch has two or more transistors, the two or more transistors are connected in series or in parallel and the gates of the respective transistors are electrically connected to each other.

[0060] In addition, in this specification and the like, a node can also be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region according to the circuit structure and the device structure, etc. In addition, terminals, wirings, etc. can also be referred to as nodes.

[0061] In addition, in this specification and the like, "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from a reference potential. For example, when the reference potential is the ground potential (grounded potential), "voltage" can also be referred to as "potential". Note that the ground potential does not necessarily mean 0V. In addition, potential is relative, and the potential supplied to the wiring, the potential applied to the circuit, etc., and the potential output from the circuit, etc. also change according to the change of the reference potential.

[0062] In addition, in this specification and the like, "high-level potential" and "low-level potential" do not mean specific potentials. For example, in the case where two wirings are both described as "wiring for supplying a high-level potential", the high-level potentials supplied by the two wirings can also be different from each other. Similarly, in the case where two wirings are both described as "wiring for supplying a low-level potential", the low-level potentials supplied by the two wirings can also be different from each other.

[0063] In addition, "electric current" refers to the phenomenon of charge migration (electric conduction). For example, the description "electric conduction of a positively charged object occurs" can be replaced with the description "electric conduction of a negatively charged object occurs in the opposite direction". Therefore, in this specification and the like, unless otherwise specified, "electric current" refers to the phenomenon of charge migration (electric conduction) during carrier migration. Here, examples of carriers include electrons, holes, anions, cations, complex ions, etc., and carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). In addition, the "direction of electric current" in wirings and the like is the direction of migration of positively charged carriers, and is recorded as a positive electric current amount. In other words, the direction of migration of negatively charged carriers is opposite to the direction of electric current, and is recorded as a negative electric current amount. Therefore, in this specification and the like, in the absence of special instructions, regarding the positive and negative of electric current (or the direction of electric current), the description "electric current flows from component A to component B" can be replaced with the description "electric current flows from component B to component A". In addition, the description "input electric current to component A" can be replaced with the description "output electric current from component A".

[0064] In addition, in this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also referred to as the non-conducting state, cut-off state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and the source gs being lower than the threshold voltage V th (in a p-channel transistor, V gs being higher than V th ).

[0065] Note that in this specification and the like, the top surface shape of a component refers to the contour shape of the component in a plan view. In addition, a plan view refers to the view seen from the normal direction of the surface of the support body (e.g., a substrate) on which the component is formed or the surface on which the component is formed.

[0066] Note that in this specification and the like, a conical shape refers to a shape in which at least a part of the side surface of a component is inclined with respect to the substrate surface or the formed surface. For example, it refers to a region having an angle (also referred to as a cone angle) less than 90 degrees formed between the inclined side surface and the substrate surface or the formed surface. In addition, the side surface, substrate surface, and formed surface of the component do not necessarily have to be completely flat, and may be approximately planar with a small curvature or approximately planar with fine irregularities.

[0067] In this specification and the like, in the case where there is a description "A is in contact with B", at least a part of A is in contact with B. Therefore, for example, it can be equivalently described as A including a region in contact with B.

[0068] In this specification and the like, when there is a description that "A is located on B", at least a part of A is located on B. Therefore, for example, it can be alternatively expressed as A includes a region located on B.

[0069] In this specification and the like, when there is a description that "A covers B", at least a part of A covers B. Therefore, for example, it can be alternatively expressed as A includes a region covering B.

[0070] In this specification and the like, when there is a description that "A overlaps with B", at least a part of A overlaps with B. Therefore, for example, it can be alternatively expressed as A includes a region overlapping with B.

[0071] In addition, in this specification and the like, for convenience, words and phrases such as "above", "below", "left", and "right" indicating the arrangement are used to describe the positional relationship of the components with reference to the accompanying drawings. In addition, the positional relationship of the components is appropriately changed according to the directions describing each component. Therefore, it is not limited to the words and phrases described in the specification, and the words and phrases can be appropriately changed according to the situation.

[0072] In this specification and the like, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, or simply referred to as OS), etc. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can refer to a transistor including a metal oxide or an oxide semiconductor. Note that metal oxides containing nitrogen are sometimes collectively referred to as metal oxides. In addition, metal oxides containing nitrogen can also be referred to as metal oxynitrides.

[0073] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to the accompanying drawings. In this embodiment, as an example of a semiconductor device according to one aspect of the present invention, a storage device will be mainly described.

[0074] One aspect of the present invention relates to a storage device including a storage unit in which storage cells are arranged in a matrix. A first transistor, a second transistor, and a third transistor are provided in the storage cells. In this storage device, the first transistor has a function of writing data to the storage cells. In addition, the second transistor and the third transistor have a function of reading the data held in the storage cells.

[0075] In the storage device according to one embodiment of the present invention, two transistors, i.e., a second transistor and a third transistor connected in series with the second transistor, are used to read the data held in the storage cell. By including the third transistor, the storage device according to one embodiment of the present invention can read the data held in the storage cell more stably than in the case where the transistor is not included. As a result, a storage device with high read accuracy can be realized.

[0076] In addition, in the storage device according to one embodiment of the present invention, the first transistor, the second transistor, and the third transistor are arranged to overlap each other. As a result, the occupied area of the storage cell when viewed from the plane can be reduced. Therefore, the storage cell can be miniaturized and highly integrated, and a storage device that can achieve miniaturization and high definition can be provided.

[0077] In addition, the first transistor, the second transistor, and the third transistor in the storage device according to one embodiment of the present invention have a structure in which the source electrode and the drain electrode are respectively provided at different heights with respect to the substrate surface and are arranged to overlap each other, and the drain current flows in the height direction (vertical direction). Therefore, miniaturization can be achieved compared to a transistor having a structure in which the source electrode and the drain electrode are provided on the same plane. By including transistors having the above structure, the storage device according to one embodiment of the present invention can further achieve miniaturization and high definition of the storage device.

[0078] <Structural Example 1 of Semiconductor Device> Figure 1A FIG. is a block diagram showing a structural example of the semiconductor device 10. The semiconductor device 10 can be a storage device.

[0079] The semiconductor device 10 includes a storage unit 20, a word line drive circuit 11, a bit line drive circuit 13, and a power supply circuit 15. The storage unit 20 includes a plurality of storage cells 21 arranged in a matrix. In addition, the power supply circuit 15 may also be provided outside the semiconductor device 10.

[0080] The word line drive circuit 11 is electrically connected to the storage cell 21 through a wiring 31. The wiring 31 extends, for example, in the row direction of the above matrix. The wiring 31 serves as a word line. Figure 1A In FIG., wirings 31R and 31W are shown as the wiring 31.

[0081] The bit line drive circuit 13 is electrically connected to the storage cell 21 through a wiring 33. The wiring 33 extends, for example, in the column direction of the above matrix. The wiring 33 serves as a bit line. Figure 1A In FIG., wirings 33R and 33W are shown as the wiring 33.

[0082] Figure 1AIn the figure, as shown in the figure, the direction in which the wiring 31 serving as a word line extends is the X direction, and the direction in which the wiring 33 serving as a bit line extends is the Y direction. As described above, the wiring 31 extends in the row direction of the above matrix, and the wiring 33 extends in the column direction of the above matrix. Therefore, the X direction can be the row direction, and the Y direction can be the column direction. The X direction and the Y direction can be directions that cross each other, specifically, directions that are orthogonal to each other. In addition, the direction that crosses both the X direction and the Y direction, specifically, the direction that is orthogonal to both the X direction and the Y direction can be the Z direction. Note that although the directions are also shown as the X direction, the Y direction, and the Z direction in the subsequent drawings, their definitions may be the same or different from Figure 1A the definitions therein. In addition, in Figure 1A the X direction, the Y direction, and the Z direction are shown with arrows, and except in the cases where it is clearly indicated, the positive direction and the negative direction are sometimes not distinguished. The same applies to the following drawings.

[0083] The power supply circuit 15 is electrically connected to the storage unit 21 through the wiring 35. Figure 1A An example is shown in which the wiring 35 extends in the column direction of the above matrix. The wiring 35 serves as a power supply line.

[0084] In Figure 1A the wiring 31, the wiring 33, and the wiring 35 are shown as straight lines, but one straight line is not limited to one wiring, and sometimes multiple wirings are shown as one straight line. The same also applies to showing multiple wirings as one straight line in the following block diagrams, circuit diagrams, etc. In addition, regarding wirings other than the wiring 31, the wiring 33, and the wiring 35, sometimes multiple wirings are also shown as one straight line.

[0085] The word line drive circuit 11 has the function of selecting, by row, the storage unit 21 for writing data. In addition, the word line drive circuit 11 has the function of selecting, by row, the storage unit 21 for reading data (specifically, the storage unit 21 that outputs data to the wiring 33). The word line drive circuit 11 can select the storage unit 21 for writing data or the storage unit 21 for reading data by supplying a signal to the wiring 31. Specifically, the word line drive circuit 11 has the function of selecting the storage unit 21 for writing data by supplying a signal to the wiring 31W. In addition, the word line drive circuit 11 has the function of selecting the storage unit 21 for reading data (specifically, the storage unit 21 that outputs data to the wiring 33R) by supplying a signal to the wiring 31R. Here, the wiring 31W is also referred to as a write word line, and the wiring 31R is also referred to as a read word line. In addition, the signal supplied by the word line drive circuit 11 to the wiring 31W is also denoted as a write signal, and the signal supplied to the wiring 31R is also denoted as a read signal.

[0086] As described above, the word line drive circuit 11 has a function of controlling writing data to the memory cell 21 by supplying a write signal to the wiring 31W. Further, the word line drive circuit 11 has a function of controlling reading data from the memory cell 21 by supplying a read signal to the wiring 31R.

[0087] The bit line drive circuit 13 has a function of writing data to the memory cell 21 selected by the word line drive circuit 11 via the wiring 33. Further, the bit line drive circuit 13 has the following functions: amplifying the data output from the memory cell 21 to the wiring 33 and outputting it to the outside of the semiconductor device 10, for example, thereby reading the data held in the memory cell 21. Also, the bit line drive circuit 13 has a function of precharging the wiring 33 before reading data from the memory cell 21.

[0088] Specifically, the bit line drive circuit 13 has a function of writing data to the memory cell 21 selected by the write signal of the word line drive circuit 11 via the wiring 33W. Further, the bit line drive circuit 13 has the following functions: amplifying the data output from the memory cell 21 to the wiring 33R and outputting it to the outside of the semiconductor device 10, for example, thereby reading the data held in the memory cell 21. Also, the bit line drive circuit 13 has a function of precharging the wiring 33R before reading data from the memory cell 21. Here, the wiring 33W is also referred to as a write bit line, and the wiring 33R is also referred to as a read bit line.

[0089] As described above, the bit line drive circuit 13 has a function of writing data to the memory cell 21 via the wiring 33W. Further, the bit line drive circuit 13 has a function of reading the data via the wiring 33R.

[0090] The power supply circuit 15 has a function of supplying a power supply potential to the wiring 35, specifically, a function of supplying a constant potential to the wiring 35. The power supply circuit 15 has, for example, a function of generating a high potential or a low potential and supplying it to the wiring 35. Further, the power supply circuit 15 may also have a function of supplying a power supply potential to one or both of the word line drive circuit 11 and the bit line drive circuit 13.

[0091] Figure 1B It is a circuit diagram showing a structural example of the memory cell 21 according to one aspect of the present invention. The memory cell 21 having this structure includes a transistor 41 and a transistor 42.

[0092] One of the source and drain of transistor 41 is electrically connected to wiring 33R. The other of the source and drain of transistor 41 is electrically connected to wiring 35. The gate of transistor 41 is electrically connected to one of the source and drain of transistor 42. The other of the source and drain of transistor 42 is electrically connected to wiring 33W. The gate of transistor 42 is electrically connected to wiring 31W. Here, the node where the gate of transistor 41 is electrically connected to one of the source and drain of transistor 42 is denoted as node N.

[0093] Transistor 42 has the function of writing data into storage cell 21. In addition, transistor 41 has the function of reading out the data held in storage cell 21. Note that Figure 1B The illustrated storage cell 21 does not have a capacitor for holding data. In this storage cell 21, data is written into node N. For example, when an OS transistor is used as transistor 42, since the leakage current of the OS transistor is small, data can be held at node N for a longer time compared to the case of using a transistor whose semiconductor layer contains silicon (also referred to as an Si transistor). Thus, a storage cell can be constituted by only two transistors (Tr) without including a capacitor (C), and thereby the manufacturing process of the storage cell can be simplified. In addition, a storage cell having the above structure may also be referred to as a 2Tr0C type storage cell.

[0094] In addition, as a storage cell with a simple structure, a 1Tr1C type storage cell DRAM (Dynamic Random Access Memory) constituted by one transistor and one capacitor is well known. However, due to its structure, the DRAM needs to use the same transistor for writing and reading data, and there is a problem that the data may be lost via the transistor when reading out and holding the data (when the transistor is turned on for data reading) (i.e., so-called destructive readout).

[0095] In contrast, Figure 1B In the illustrated storage cell 21, a transistor (transistor 42) for data writing and a transistor (transistor 41) for data reading are respectively provided. Therefore, when reading out data, it is not necessary to turn on the transistor (transistor 42) for data writing, and thus non-destructive readout can be performed.

[0096] Specifically, by providing different magnitudes of potential to wiring 33R and wiring 35 respectively, a potential difference is generated between the source and drain of transistor 41. At this time, the potential corresponding to the data of write node N is applied to the gate of transistor 41. Thus, whether transistor 41 is in the on state or the off state depends on the magnitude relationship between the threshold voltage of transistor 41 and the data of write node N (that is, the potential applied to the gate of transistor 41). When memory cell 21 is a binary memory cell for storing data with a value of "0" or "1", when transistor 41 is in the on state, a current flows between the source and drain of transistor 41, and this current is output to wiring 33R, and it can be detected that data "1" is written to node N. On the other hand, when transistor 41 is in the off state, no current flows between the source and drain of transistor 41, and the current is not output to wiring 33R, and it can be detected that data "0" is written to node N.

[0097] However, in the case of adopting the above data reading method, when reading data, it is necessary to apply potentials to wiring 33R and wiring 35 respectively. Therefore, every time data is read, the applied potential is applied to node N through parasitic capacitances (such as the capacitance components included in transistor 41). Therefore, there is a problem that the magnitude of the data initially written changes in all memory cells 21 (including memory cells 21 that do not perform data reading) connected to wiring 33R and wiring 35 to which the potential is applied.

[0098] In view of the above problems, as Figure 1C shown, a transistor 43 connected in series with transistor 41 is provided in a memory cell according to an aspect of the present invention. Specifically, one of the source and drain of transistor 41 is electrically connected to one of the source and drain of transistor 43. The other of the source and drain of transistor 43 is electrically connected to wiring 33R. The gate of transistor 43 is electrically connected to wiring 31R. The description of the structure other than the above can refer to Figure 1B the description of memory cell 21 shown.

[0099] In Figure 1C a memory cell 21 according to an aspect of the present invention shown, transistor 42 has a function of writing data. In addition, transistors 41 and 43 have a function of reading the data held in memory cell 21.

[0100] Although some parts are repeated with the content described in memory cell 21 shown in the above Figure 1B shown, the operation method of a memory cell 21 according to an aspect of the present invention shown in Figure 1C shown will be described in detail below.

[0101] The transistor 42 functions as a switch for writing data to the memory cell 21. For example, when the transistor 42 is an n-channel transistor, the transistor 42 can be turned on by setting the potential of the wiring 31W to a high potential (the potential between the source and gate of the transistor 42 is a potential equal to or higher than the threshold voltage), and the transistor 42 can be turned off by setting the potential of the wiring 31W to a low potential (the potential between the source and gate of the transistor 42 is a potential less than the threshold voltage). The transistor 42 has a function of controlling the conduction state and non-conduction state between the wiring 33W and the node N according to the potential of the wiring 31W. By turning on the transistor 42, data is written to the memory cell 21 through the wiring 33W, and by turning off the transistor 42, the written data is retained. Specifically, by turning on the transistor 42, charges corresponding to the data are stored in the node N, and by turning off the transistor 42, the charges in the node N are retained. Note that during the above series of operations (when writing data to the memory cell 21 and when retaining data), it is assumed that a constant potential (GND (ground potential) or a low potential) is always applied to the wiring 35).

[0102] The following description will be given assuming that the transistors 41, 42, and 43 are n-channel transistors. However, even if the magnitude relationship of the potentials is appropriately reversed, etc., the following description can be applied when one, any two, or all of the transistors 41, 42, and 43 are p-channel transistors.

[0103] The transistors 41 and 43 have a function of controlling the reading of the data held in the memory cell 21. The following describes a method of reading the data held in the memory cell 21. In the memory cell 21, binary data representing "0" or "1" is held as the potential of the node N, and "1" is represented by a potential higher than "0".

[0104] When reading the data held in the memory cell 21, first, the wiring 33R is pre-charged to a high potential. Also, similar to the above data writing and data retaining operations, the potential of the wiring 35 is set to a constant potential (GND or a low potential). Furthermore, the potential of the wiring 31R is set to a high potential (that is, the transistor 43 is turned on), and a conduction state is established between the wiring 33R and one of the source and drain of the transistor 41.

[0105] At this time, one of the source and drain of the transistor 41 is in a state where a high potential is applied, and the other of the source and drain is in a state where GND or a low potential is applied. In addition, the gate of the transistor 41 is applied with a potential corresponding to the magnitude of the data held in the memory cell 21 (that is, the data written to the node N). That is, the type of this data determines whether the transistor 41 is turned on or off.

[0106] Here, when the data held in the storage cell 21 is "0", the potential difference between the gate potential and the source potential of the transistor 41 is less than the threshold voltage of the transistor 41. Further, when the data held in the storage cell 21 is "1", the potential difference between the gate potential and the source potential of the transistor 41 is greater than the threshold voltage of the transistor 41. At this time, when the data held in the storage cell 21 is "0", the transistor 41 becomes the off state and the transistor 43 becomes the on state, so that current does not flow from the wiring 33R to the wiring 35. On the other hand, when the data held in the storage cell 21 is "1", both the transistor 43 and the transistor 41 become the on state, and current flows from the wiring 33R to the wiring 35. Therefore, the bit line drive circuit 13 can read the data held in the storage cell 21 from the current flowing through the wiring 33R or the potential of the wiring 33R. Further, regardless of whether the data held in the storage cell 21 is "0" or "1", the potential difference between the gate potential and the source potential of the transistor 41 can be greater than the threshold voltage of the transistor 41. In this case, the bit line drive circuit 13 can read the data held in the storage cell 21, for example, by reading the magnitude of the current flowing through the wiring 33R.

[0107] As described above, in the Figure 1C storage cell 21 shown, when any of data writing, data holding, and data reading is performed, the potential of the wiring 35 is always fixed at a certain magnitude (GND or low potential). Further, at the time of data reading (when a high potential is applied to the wiring 33R), only the transistor 43 included in the storage cell 21 that performs data reading can be made to be in the on state through the wiring 31R. On the other hand, since the transistor 43 in the storage cell 21 that does not perform data reading is in the off state, application of potential from the wiring 33R to the node N can be suppressed, and thus change in the magnitude of the data held in the storage cell 21 can be prevented. Therefore, compared with the Figure 1B storage cell 21 shown, the data held in the Figure 1C storage cell 21 shown in one aspect of the present invention can be read more stably, and thus a storage device with high read accuracy can be realized.

[0108] Figure 2A is Figure 1C a modified example of the storage cell 21 shown, in which the wiring 31R is electrically connected to the other of the source and the drain of the transistor 41, and the wiring 35 is electrically connected to the gate of the transistor 43. Figure 2A The storage cell 21 shown can perform data writing and data holding in the same manner as the Figure 1C storage cell 21 shown. Further, data reading can be performed by using the description regarding the wiring 35 in the Figure 1C storage cell 21 shown for Figure 2A The wiring 31R in the memory cell 21 shown is for Figure 1C the description regarding the wiring 31R in the memory cell 21 shown is used for Figure 2A the wiring 35 in the memory cell 21 shown, and Figure 1A the functions of the power supply circuit 15 and the word line drive circuit 11 in the semiconductor device 10 shown are swapped.

[0109] Figure 1C and Figure 2A The memory cells 21 shown do not include capacitors and are 3Tr0C type memory cells composed of three transistors. Therefore, as an example of the transistors 41, 42, and 43, for example, it is preferable to use OS transistors. In particular, it is particularly preferable to use an OS transistor for the transistor 42, and the magnitude of its off-state current directly affects the data retention time of the memory cell 21. As the metal oxide included in the channel formation region of the OS transistor, for example, indium oxide, gallium oxide, and zinc oxide can be cited.

[0110] The transistors 41 and 43 can also use transistors other than OS transistors. For example, the transistors 41 and 43 can use Si transistors that include silicon in the channel formation region. As the silicon, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon (including low-temperature polycrystalline silicon) can be used. Si transistors have a higher on-state current and a higher field-effect mobility than OS transistors. Therefore, by using Si transistors as the transistors 41 and 43, a memory cell 21 with a fast data readout speed can be realized.

[0111] In addition, the transistors 41 and 43 can use transistors with the same structure, or can use transistors with different structures from each other. For example, the transistors 41 and 43 can both use OS transistors, or the transistor 41 can be a Si transistor and the transistor 43 can be an OS transistor. In addition, the transistor 41 can be an OS transistor and the transistor 43 can be a Si transistor.

[0112] Figure 2B is Figure 1C a modified example of the memory cell 21 shown, which is different from the memory cell 21 shown in that it includes a capacitor 51. Figure 1C the memory cell 21 shown.

[0113] In Figure 2BIn the memory cell 21 shown, one electrode of the capacitor 51 is electrically connected to the other of the source and drain of the transistor 42 and the gate of the transistor 41. The other electrode of the capacitor 51 is electrically connected to the wiring 35. Here, the node where the gate of the transistor 41, the other of the source and drain of the transistor 42, and one electrode of the capacitor 51 are electrically connected is denoted as node N. In Figure 2B the memory cell 21 shown, the structure other than the above can be referred to Figure 1C the description of the memory cell 21 shown.

[0114] Figure 2B The data writing, data holding, and data reading operations of the memory cell 21 shown can all be performed in the same manner as Figure 1C the memory cell 21 shown. Since Figure 2B the memory cell 21 shown includes the capacitor 51, compared with Figure 1C the memory cell 21 shown, the data written to node N can be held more stably. Therefore, compared with Figure 1C the memory cell 21 having a structure that does not include the capacitor 51 shown, long-term data holding can be performed more stably.

[0115] Figure 3A shows a block diagram of a structural example of a semiconductor device 10 different from Figure 1A that shown. Figure 3A The semiconductor device 10 shown is different from Figure 1A the semiconductor device 10 shown in that it does not include the wiring 36.

[0116] The memory cells 21 arranged in the same row are electrically connected to the word line drive circuit 11 through a common wiring 36. The wiring 36 serves as a capacitive line.

[0117] Figure 3A The structure other than the above in the semiconductor device 10 shown can be referred to Figure 1A the description of the semiconductor device 10 shown.

[0118] Figure 3B is a circuit diagram showing a structural example of the memory cell 21 in the semiconductor device 10 shown. The memory cell 21 of this structure includes the capacitor 51 in addition to the above-mentioned wiring 36, and is different from Figure 3A the memory cell 21 shown in this respect. Figure 1B the memory cell 21 shown.

[0119] In Figure 3BIn the memory cell 21 shown, one electrode of the capacitor 51 is electrically connected to the other of the source and drain of the transistor 42 and the gate of the transistor 41. The other electrode of the capacitor 51 is electrically connected to the wiring 36. Here, the node connecting the gate of the transistor 41, the other of the source and drain of the transistor 42, and one electrode of the capacitor 51 is denoted as node N. In Figure 3B the memory cell 21 shown, for the structures other than those described above, reference can be made to the description of the memory cell 21 shown in Figure 1C the memory cell 21 shown.

[0120] Figure 3B The data writing, data holding, and data reading operations of the memory cell 21 shown can all be performed in the same manner as those of the memory cell 21 shown in Figure 1C the memory cell 21 shown. Note that during the above series of operations, like the wiring 35, the wiring 36 is constantly applied with a constant potential, that is, constantly applied with GND (ground potential) or a low potential.

[0121] Figure 3C is Figure 3B a modified example of the memory cell 21 shown, which is different from the memory cell 21 shown in Figure 3B the memory cell 21 shown in that it includes the transistor 44.

[0122] In Figure 3C the memory cell 21 shown, one of the source and drain of the transistor 44 is electrically connected to the wiring 35. The other of the source and drain of the transistor 44 is electrically connected to the other electrode of the capacitor 51. The gate of the transistor 44 is electrically connected to the gate of the transistor 41 and one electrode of the capacitor 51 respectively. Figure 3C For the structures other than those described above in the memory cell 21 shown, reference can be made to the description of the memory cell 21 shown in Figure 3B the memory cell 21 shown.

[0123] Figure 3C The data writing, data holding, and data reading operations of the memory cell 21 shown can all be performed in the same manner as those of the memory cell 21 shown in Figure 3B the memory cell 21 shown. Note that during the above series of operations, like the wiring 35, the wiring 36 is constantly applied with a constant potential, that is, constantly applied with GND (ground potential) or a low potential.

[0124] Figure 2B and Figure 3B the memory cell 21 shown are all 3Tr1C type memory cells composed of three transistors and one capacitor. In addition, Figure 3C the memory cell 21 shown is a 4Tr1C type memory cell composed of four transistors and one capacitor. Each transistor in these memory cells can use an OS transistor or a Si transistor.

[0125] In addition, in Figure 2B , Figure 3B and Figure 3C In the memory cell 21 shown, a memory cell having a structure in which an OS transistor is used as each transistor is also called NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor Random Access Memory).

[0126] As described above, the off-state current of the OS transistor is extremely small. Therefore, when the OS transistor is used as the Figure 1C , Figure 2A , Figure 2B , Figure 3B and Figure 3C When the transistor 42 in the memory cell 21 shown is used, the charge accumulated in the node N can be maintained for a long time. Since the data written to the memory cell 21 can be maintained for a long time, the frequency of the refresh operation (rewriting data to the memory cell 21) can be reduced. Thereby, the power consumption of the semiconductor device 10 can be reduced.

[0127] Figure 4A The plan view which shows the structural example of a part of the semiconductor device 10 of the semiconductor device which shows one mode of this invention. Figure 4A Includes Figure 1C The structural example of the memory cell 21 shown. In Figure 4A , for clarity, some constituent elements such as the insulating layer are omitted. Some constituent elements are also omitted in the plan view shown below. Figure 4B Is Figure 4A The cross-sectional view of the dotted line A1 - A2 shown, Figure 4C Is Figure 4A The cross-sectional view of the dotted line A3 - A4 shown.

[0128] A semiconductor device according to an aspect of the present invention includes an insulating layer 101 on a substrate (not shown) and a memory cell 21 on the insulating layer 101. The memory cell 21 includes a transistor 43, a transistor 41 on the transistor 43, and a transistor 42 on the transistor 41.

[0129] In addition, a semiconductor device according to one embodiment of the present invention includes: an insulating layer 103c_1 on an insulating layer 101; an insulating layer 103c_2 on the insulating layer 103c_1; an insulating layer 107c on a transistor 43, on the insulating layer 103c_1, and on the insulating layer 103c_2; an insulating layer 103c_3 on the insulating layer 107c; a transistor 41 and an insulating layer 103a on the insulating layer 103c_3; an insulating layer 107a on the transistor 41 and on the insulating layer 103a; an insulating layer 131 on the insulating layer 107a; a transistor 42 and an insulating layer 103b on the transistor 41 and on the insulating layer 131; an insulating layer 107b on the transistor 42 and on the insulating layer 103b. Here, the insulating layer 101, the insulating layer 103c_1, the insulating layer 103c_2, the insulating layer 103a, the insulating layer 131, and the insulating layer 103b are used as interlayer insulating layers and are preferably planarized. Note that the insulating layers used as interlayer insulating layers may not be planarized.

[0130] The transistor 43 includes a conductive layer 111c, a conductive layer 111a, a semiconductor layer 113c, an insulating layer 105c, and a conductive layer 115c.

[0131] The conductive layer 111c serves as one of a source electrode and a drain electrode of the transistor 43 and also serves as a wiring 33R. The conductive layer 111a serves as the other of the source electrode and the drain electrode of the transistor 43. The insulating layer 105c serves as a gate insulating layer of the transistor 43. The conductive layer 115c serves as a gate electrode of the transistor 43 and also serves as a wiring 31R. The conductive layer 111c serving as the wiring 33R has a region extending in the Y direction. In addition, the conductive layer 115c serving as the wiring 31R has a region extending in the X direction.

[0132] The conductive layer 111c is provided on the insulating layer 101, the insulating layer 103c_1 is provided on the insulating layer 101 and on the conductive layer 111c, the conductive layer 115c is provided on the insulating layer 103c_1, and the insulating layer 103c_2 is provided on the insulating layer 103c_1 and on the conductive layer 115c. The insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2 have an opening 121c reaching the conductive layer 111c. Figure 4A An example is shown in which the shape of the opening 121c is circular when viewed from the plane. By making the top surface shape of the opening 121c circular, the processing accuracy when forming the opening 121c can be improved, and thus a fine opening 121c can be formed. In addition, the top surface shape of the opening 121c may be, for example, an ellipse, a polygon such as a quadrilateral, or the like.

[0133] The insulating layer 105c serving as the gate insulating layer of the transistor 43 is disposed such that it has a region in the opening 121c that contacts a part of the top surface of the conductive layer 111c, the side surface of the insulating layer 103c_1, the side surface of the conductive layer 115c, and the side surface of the insulating layer 103c_2.

[0134] The semiconductor layer 113c is disposed to cover the opening 121c with the insulating layer 105c interposed therebetween such that it has a region located inside the opening 121c. The upper end portion of the insulating layer 105c has a curved shape. The semiconductor layer 113c has a region that contacts the top surface of the insulating layer 103c_2, a region that contacts the curved portion of the insulating layer 105c, a region that contacts the side surface of the insulating layer 105c, and a region that contacts the top surface of the conductive layer 111c. The semiconductor layer 113c has a shape along the top surface of the insulating layer 103c_2, the curved portion of the insulating layer 105c, the side surface of the insulating layer 105c, and the top surface of the conductive layer 111c. Thus, the semiconductor layer 113c has a concave portion at a position overlapping the opening 121c. The layer 114 is disposed so as to be embedded in the concave portion. The layer 114 fills the concave portion and has a function of flattening its top surface. Note that even with this concave portion, it does not affect the coverage of the upper layer formed later, or in the case where the concave portion itself is not formed, the layer 114 does not need to be provided.

[0135] Note that although Figure 4B and Figure 4C an example in which the semiconductor layer 113c is a single-layer structure is shown, one embodiment of the present invention is not limited thereto. The semiconductor layer 113c may also have a stacked structure of two or more layers.

[0136] The insulating layer 107c is disposed so as to cover the side surface of the side end portion of the semiconductor layer 113c and the top surface of the insulating layer 103c_2. The insulating layer 107c has a function of suppressing impurity diffusion into the transistor 43, for example, a function of suppressing impurity diffusion into the semiconductor layer 113c. The insulating layer 103c_3 is provided on the insulating layer 107c. Preferably, the top surfaces of the semiconductor layer 113c, the insulating layer 107c, and the insulating layer 103c_3 are substantially flush with respect to the substrate surface. Thereby, the formation surface of the upper layer (e.g., the conductive layer 111a) formed later can be made flat, and the coverage of the upper layer can be improved. In addition, when the thickness of the insulating layer 107c is substantially equal to the thickness of the semiconductor layer 113c (i.e., when the height of the top surface of the insulating layer 107c is substantially equal to the height of the top surface of the semiconductor layer 113c), the insulating layer 103c_3 may not be provided.

[0137] The conductive layer 111a, which serves as the other of the source electrode and the drain electrode of the transistor 43, is disposed in contact with the uppermost surface of the semiconductor layer 113c, the top surface of the layer 114, the uppermost surface of the insulating layer 107c, and the top surface of the insulating layer 103c_3. In addition, the conductive layer 111a is disposed in such a manner as to have a region overlapping with the conductive layer 111c, which serves as one of the source electrode and the drain electrode of the transistor 43.

[0138] Preferably, the end portion of the conductive layer 111a substantially coincides with the end portion of the semiconductor layer 113c or is located outside the end portion of the semiconductor layer 113c. Thereby, the contact area between the conductive layer 111a and the semiconductor layer 113c can be increased, so that the contact resistance between the conductive layer 111a and the semiconductor layer 113c can be reduced.

[0139] In the transistor 43, the source electrode, the drain electrode, and the gate electrode are overlapped and disposed in such a manner that their heights relative to the substrate surface are different from each other. In addition, the gate electrode is disposed between the source electrode and the drain electrode. Therefore, in the transistor 43, the channel length direction corresponds to the direction along the side surface of the insulating layer 105c when viewed in cross section, and the drain current flows along this direction.

[0140] When the transistor 43 has the above structure, by adjusting the thickness of the layer (the insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2) located between the source electrode and the drain electrode when viewed in cross section, the channel length of the transistor 43 can be controlled. Therefore, the channel length of the transistor 43 can be made smaller than the limit resolution of the exposure apparatus. In addition, compared with a transistor having a structure in which both the source electrode and the drain electrode are provided on the same plane, the occupied area of the transistor when viewed in plan can be reduced.

[0141] In addition, in the transistor 43, when viewed in plan, the gate electrode (the conductive layer 115c) is disposed so as to surround the opening 121c (the semiconductor layer 113c and the insulating layer 105c). Therefore, the entire region of the semiconductor layer 113c in the opening 121c, which faces the conductive layer 115c with the insulating layer 105c interposed therebetween, can be used as the channel formation region of the transistor 43. At this time, the channel width direction of the transistor 43 is the direction parallel to the XY plane, and the channel width of the transistor 43 corresponds to Figure 4A the perimeter of the opening 121c in

[0142] The transistor 41 includes a conductive layer 111a, a conductive layer 112a, a semiconductor layer 113a, an insulating layer 105a, and a conductive layer 115a.

[0143] The conductive layer 111a serves as one of the source electrode and the drain electrode of the transistor 41. The conductive layer 112a serves as the other of the source electrode and the drain electrode of the transistor 41 and also serves as the wiring 35. The insulating layer 105a serves as the gate insulating layer of the transistor 41. The conductive layer 115a serves as the gate electrode of the transistor 41. The conductive layer 112a serving as the wiring 35 has a region extending in the Y direction.

[0144] In addition, as described above, the conductive layer 111a also serves as the other of the source electrode and the drain electrode of the transistor 43. Therefore, in FIG. 4A to FIG. 4C the semiconductor device shown, the conductive layer 111a has the function of serving as both the other of the source electrode and the drain electrode of the transistor 43 and one of the source electrode and the drain electrode of the transistor 41.

[0145] The conductive layer 111a is provided on the semiconductor layer 113c, on the layer 114, on the insulating layer 107c, and on the insulating layer 103c_3. The insulating layer 103a is provided on the insulating layer 103c_3 and on the conductive layer 111a. The conductive layer 112a is provided on the insulating layer 103a. The conductive layer 111a and the conductive layer 112a have a region overlapping each other with the insulating layer 103a therebetween. The insulating layer 103a and the conductive layer 112a have an opening 121a reaching the conductive layer 111a. Note that although Figure 4A and Figure 4B show an example in which the side end portion of the conductive layer 111a in the X direction is located outside the side end portion of the conductive layer 112a that does not face the opening 121a, that is, the side end portion of the conductive layer 112a that does not face the opening 121a overlaps the conductive layer 111a while the side end portion of the conductive layer 111a does not overlap the conductive layer 112a, one embodiment of the present invention is not limited thereto. For example, the side end portion of the conductive layer 111a may also be located inside the side end portion of the conductive layer 112a that does not face the opening 121a.

[0146] Figure 4A An example in which the shape of the opening 121a is circular when viewed from the plane is shown. By making the top surface shape of the opening 121a circular, the processing accuracy when forming the opening 121a can be improved, and a fine opening 121a can be formed. In addition, the top surface shape of the opening 121a may also be, for example, an ellipse, a polygon such as a quadrilateral.

[0147] The semiconductor layer 113a is disposed to cover the opening 121a in such a manner as to have a region located inside the opening 121a. The semiconductor layer 113a includes a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surface of the conductive layer 112a, a region in contact with the side surface of the insulating layer 103a, and a region in contact with the top surface of the conductive layer 111a. The semiconductor layer 113a has a shape along the top surface of the conductive layer 112a, the side surface of the conductive layer 112a, the side surface of the insulating layer 103a, and the top surface of the conductive layer 111a. Accordingly, the semiconductor layer 113a has a concave portion at a position overlapping with the opening 121a.

[0148] The semiconductor layer 113a preferably covers the side end portion on the opening 121a side of the conductive layer 112a. For example, Figure 4B and Figure 4C illustrates a structure in which the side end portion of the semiconductor layer 113a is located on the conductive layer 112a. The lower end portion of the semiconductor layer 113a can also be said to be in contact with the top surface of the conductive layer 112a. In addition, FIG. 4A to FIG. 4C illustrates an example in which the side end portion of the semiconductor layer 113a is located inside the side end portion of the conductive layer 112a that does not face the opening 121a, that is, the whole of the semiconductor layer 113a overlaps with either the conductive layer 112a or the opening 121a. In addition, FIG. 4A to FIG. 4C illustrates an example in which the side end portion of the semiconductor layer 113a is located inside the side end portion of the conductive layer 111a, that is, the whole of the semiconductor layer 113a overlaps with the conductive layer 111a.

[0149] In this specification, the upper end portion refers to the uppermost part of the side end portion, and the lower end portion refers to the lowermost part of the side end portion. In other words, both the upper end portion and the lower end portion are part of the side end portion.

[0150] Note that although Figure 4B and Figure 4C illustrate that the semiconductor layer 113a has a single-layer structure, one aspect of the present invention is not limited thereto. The semiconductor layer 113a may also have a stacked structure of two or more layers.

[0151] The insulating layer 105a serving as the gate insulating layer of the transistor 41 is disposed to cover the opening 121a in such a manner as to have a region inside the opening 121a. The insulating layer 105a is disposed on the semiconductor layer 113a, on the conductive layer 112a, and on the insulating layer 103a. The insulating layer 105a includes a region in contact with the top surface of the semiconductor layer 113a, a region in contact with the side surface of the semiconductor layer 113a, a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surface of the conductive layer 112a, and a region in contact with the top surface of the insulating layer 103a. The insulating layer 105a has a shape along the top surface of the semiconductor layer 113a, the side surface of the semiconductor layer 113a, the top surface of the conductive layer 112a, the side surface of the conductive layer 112a, and the top surface of the insulating layer 103a. Accordingly, the insulating layer 105a has a concave portion at a position overlapping with the opening 121a.

[0152] The conductive layer 115a serving as the gate electrode of the transistor 41 is disposed on the insulating layer 105a and has a region in contact with the top surface of the insulating layer 105a. The conductive layer 115a has a region overlapping with the semiconductor layer 113a with the insulating layer 105a therebetween. Here, the semiconductor layer 113a may have a structure covering the side surface and the bottom surface of the conductive layer 115a with the insulating layer 105a therebetween inside the opening 121a. For example, inside the opening 121a, the insulating layer 105a includes a region in contact with the side surface of the semiconductor layer 113a, a region in contact with the top surface of the concave portion of the semiconductor layer 113a, a region in contact with the side surface of the conductive layer 115a, and a region in contact with the bottom surface of the conductive layer 115a.

[0153] As described above, Figure 4B and Figure 4C the transistor 41 shown is a transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are disposed inside an opening formed in an interlayer insulating layer. In other words, when viewed from a plane, the semiconductor layer is disposed so as to surround the gate electrode with the gate insulating layer therebetween. Accordingly, the channel length direction of the transistor 41 can be a direction along the side surface of the insulating layer 103a in the opening 121a when viewed in cross section. Therefore, the channel length is not affected by the performance of the exposure apparatus used in manufacturing the transistor 41, and thus the channel length can be made smaller than the limit resolution of the exposure apparatus. Accordingly, the transistor 41 can be miniaturized. In addition, for example, although Figure 4A the example in which the entire opening 121a has a region overlapping with the conductive layer 111a, the semiconductor layer 113a, and the conductive layer 115a is shown, a part of the opening 121a may not overlap with at least one of the conductive layer 111a, the semiconductor layer 113a, and the conductive layer 115a.

[0154] The transistor 41 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 113a. Further, since the bottom surface of the semiconductor layer 113a (the surface on the insulating layer 101 side) is in contact with the source electrode and the drain electrode, it can also be referred to as a TGBC (Top Gate Bottom Contact) type transistor.

[0155] As Figure 4B and Figure 4C shown, a part of the insulating layer 105a is located outside the opening 121a, that is, on the conductive layer 112a and on the insulating layer 103a. At this time, the insulating layer 105a preferably covers the side end portion of the semiconductor layer 113a. Thereby, a short circuit between the conductive layer 115a and the semiconductor layer 113a can be prevented. In addition, the insulating layer 105a preferably covers the side end portion of the conductive layer 112a. Thereby, a short circuit between the conductive layer 115a and the conductive layer 112a can be prevented.

[0156] In addition, as Figure 4B and Figure 4C shown, a part of the conductive layer 115a is located outside the opening 121a, that is, on the conductive layer 112a and on the insulating layer 103a. Note that although Figure 4B and Figure 4C show examples in which the side end portion of the conductive layer 115a is located inside the side end portion of the semiconductor layer 113a, it is not limited thereto. The side end portion of the conductive layer 115a may also be located outside the side end portion of the semiconductor layer 113a.

[0157] The insulating layer 107a is provided in contact with the top surface of the insulating layer 105a and the side surface of the conductive layer 115a. In addition, an insulating layer 131 is provided on the insulating layer 107a. The top surface of the conductive layer 115a, the topmost surface of the insulating layer 107a, and the top surface of the insulating layer 131 are substantially at the same height with respect to the substrate surface.

[0158] The insulating layer 107a has a function of suppressing the diffusion of impurities to the transistor 41. For example, it has a function of suppressing the diffusion of impurities to the semiconductor layer 113a. As described above, the insulating layer 131 serves as an interlayer insulating layer.

[0159] The transistor 42 includes a conductive layer 111b, a conductive layer 112b, a semiconductor layer 113b, an insulating layer 105b, and a conductive layer 115b.

[0160] The conductive layer 111b serves as one of the source electrode and the drain electrode of the transistor 42. The conductive layer 112b serves as the other of the source electrode and the drain electrode of the transistor 42 and also serves as the wiring 33W. The insulating layer 105b serves as the gate insulating layer of the transistor 42. The conductive layer 115b serves as the gate electrode of the transistor 42 and also serves as the wiring 31W. The conductive layer 112b serving as the wiring 33W has a region extending in the Y direction. In addition, the conductive layer 115b serving as the wiring 31W has a region extending in the X direction.

[0161] In addition, as described above, the conductive layer 111b also serves as the other of the source electrode and the drain electrode of the transistor 41. Therefore, in FIG. 4A to FIG. 4C the semiconductor device shown, the conductive layer 111b functions as both the other of the source electrode and the drain electrode of the transistor 41 and one of the source electrode and the drain electrode of the transistor 42.

[0162] The conductive layer 111b is provided on the conductive layer 115a, on the insulating layer 107a, and on the insulating layer 131. The conductive layer 111b includes at least a region in contact with the top surface of the conductive layer 115a. The insulating layer 103b is provided on the insulating layer 131 and on the conductive layer 111b. The conductive layer 112b is provided on the insulating layer 103b. The conductive layer 111b and the conductive layer 112b have a region overlapping each other with the insulating layer 103b therebetween.

[0163] The insulating layer 103b and the conductive layer 112b have an opening 121b reaching the conductive layer 111b. Figure 4A An example is shown in which the shape of the opening 121b is circular when viewed from the plane. In addition, the opening 121b may have the same shape as the shape of the opening 121a.

[0164] The structure of the transistor 42 can adopt the same structure as the structure of the transistor 41 described above. For the description of the structure of the transistor 42, reference can be made to the description of the structure of the transistor 41, and the transistor 41, the insulating layer 103a, the insulating layer 105a, the conductive layer 111a, the conductive layer 112a, the semiconductor layer 113a, and the conductive layer 115a can be appropriately replaced with the transistor 42, the insulating layer 103b, the insulating layer 105b, the conductive layer 111b, the conductive layer 112b, the semiconductor layer 113b, and the conductive layer 115b as needed.

[0165] In this specification and the like, the insulating layers 103a, 103b, 103c_1, 103c_2, 103c_3, etc. are sometimes collectively referred to as the insulating layer 103. Additionally, the insulating layers 105a, 105b, and 105c are sometimes collectively referred to as the insulating layer 105. Further, the insulating layers 107a, 107b, and 107c are sometimes collectively referred to as the insulating layer 107. Moreover, the conductive layers 111a, 111b, and 111c are sometimes collectively referred to as the conductive layer 111. Also, the conductive layers 112a and 112b are sometimes collectively referred to as the conductive layer 112. Additionally, the semiconductor layers 113a, 113b, and 113c are sometimes collectively referred to as the semiconductor layer 113. Moreover, the conductive layers 115a, 115b, and 115c are sometimes collectively referred to as the conductive layer 115. Additionally, the openings 121a, 121b, and 121c are sometimes collectively referred to as the opening 121.

[0166] An insulating layer 107b is provided on the conductive layer 115b and on the insulating layer 105b. The insulating layer 107b can be provided in such a way as to cover the top surface and the side surfaces of the conductive layer 115b. The insulating layer 107b has a function of suppressing the diffusion of impurities into the transistor 42. For example, it has a function of suppressing the diffusion into the semiconductor layer 113b.

[0167] As described above, in a semiconductor device according to one embodiment of the present invention, the transistors 43, 41, and 42 are stacked in this order. Further, in the transistor 43, the source electrode, the drain electrode, and the gate electrode are provided in such a way that they have different heights with respect to the substrate surface and have overlapping regions with each other, and the gate insulating layer and the semiconductor layer are provided in such a way that the channel length direction is formed along the height direction. Additionally, in the transistors 41 and 42, a semiconductor layer, a gate insulating layer, and a gate electrode are provided inside an opening formed in the interlayer insulating layer, one of the source electrode and the drain electrode is provided under the opening, and the other of the source electrode and the drain electrode is provided on the interlayer insulating layer. Thereby, the occupied area of the memory cell 21 when viewed from the plane can be reduced. Therefore, miniaturization and high integration of the memory cell can be achieved. Thus, according to one embodiment of the present invention, a semiconductor device capable of achieving miniaturization and high definition can be provided.

[0168] Here, in Figure 4B and Figure 4C In the cross-sectional views shown, the boundaries of each layer may not be clearly confirmed. For example, the boundaries of two insulating layers in contact with each other may not be clearly confirmed. Additionally, the boundaries of two conductive layers in contact with each other may not be clearly confirmed. Moreover, the boundaries of two semiconductor layers in contact with each other may not be clearly confirmed.

[0169] <Structural Example 2 of Semiconductor Device> FIG. 5A to FIG. 5C shows a structure example of a semiconductor device 10 different from FIG. 4A to FIG. 4C a mode of the present invention shown. Figure 5A is a plan view showing a structure example of a part of the semiconductor device 10. Figure 5B is a cross-sectional view along Figure 5A the dotted line A1 - A2 shown, Figure 5C is a cross-sectional view along Figure 5A the dotted line A3 - A4 shown.

[0170] FIG. 5A to FIG. 5C the semiconductor device 10 shown is different from FIG. 4A to FIG. 4C the semiconductor device 10 shown in terms of the structure of the transistor 43.

[0171] FIG. 5A to FIG. 5C the transistor 43 in the semiconductor device 10 shown includes a conductive layer 111c, a conductive layer 111a, a semiconductor layer 113c, an insulating layer 105c, and a conductive layer 115c.

[0172] The conductive layer 111c serves as one of the source electrode and the drain electrode of the transistor 43 and also serves as the wiring 33R. The conductive layer 111a serves as the other of the source electrode and the drain electrode of the transistor 43. The insulating layer 105c serves as the gate insulating layer of the transistor 43. The conductive layer 115c serves as the gate electrode of the transistor 43 and also serves as the wiring 31R. The conductive layer 111c serving as the wiring 33R has a region extending in the Y direction. In addition, the conductive layer 115c serving as the wiring 31R has a region extending in the X direction.

[0173] The conductive layer 111c is provided on the insulating layer 101, the insulating layer 105c is provided on the insulating layer 101 and on the conductive layer 111c, the conductive layer 115c is provided on the insulating layer 105c, and the insulating layer 103c is provided on the insulating layer 105c and on the conductive layer 115c. As FIG. 5A to FIG. 5C shown, a columnar semiconductor layer 113c is formed on the conductive layer 111c. Note that Figure 5A an example in which the shape of the semiconductor layer 113c is circular when viewed from the plane is shown, but it is not limited thereto. The top surface shape of the semiconductor layer 113c can also be, for example, an ellipse, a polygon such as a quadrilateral.

[0174] The insulating layer 105c serving as the gate insulating layer in the transistor 43 has a region in contact with the side surface of the semiconductor layer 113c, the side surface and the bottom surface of the conductive layer 115c, the top surface and the side surface of the conductive layer 111c, and the side surface of the insulating layer 103c. The semiconductor layer 113c and the conductive layer 115c are opposed to each other with the insulating layer 105c interposed therebetween when viewed from the cross section.

[0175] The conductive layer 115c serving as the gate electrode in the transistor 43 is provided so as to cover the columnar semiconductor layer 113c with the insulating layer 105c interposed therebetween. By adopting this structure, a gate electric field (electric field from the conductive layer 115c) can be applied to the semiconductor layer 113c from various directions within the XY plane.

[0176] The insulating layer 103c is provided so as to have regions in contact with the side surface of the conductive layer 115c, the top surface of the conductive layer 115c, the top surface of the insulating layer 105c, and the side surface of the insulating layer 105c.

[0177] The height of the top surface of the semiconductor layer 113c, the uppermost surface of the insulating layer 105c, and the top surface of the insulating layer 103c with respect to the substrate surface is substantially the same.

[0178] The conductive layer 111a serving as the other of the source electrode and the drain electrode of the transistor 43 is provided in contact with the top surface of the semiconductor layer 113c, the uppermost surface of the insulating layer 105c, and the top surface of the insulating layer 103c. In addition, the conductive layer 111a is provided so as to have a region overlapping with the conductive layer 111c serving as one of the source electrode and the drain electrode of the transistor 43.

[0179] The end portion of the conductive layer 111a preferably coincides with the end portion of the semiconductor layer 113c or is located outside the end portion of the semiconductor layer 113c. Thereby, the contact area between the conductive layer 111a and the semiconductor layer 113c can be increased, so the contact resistance between the conductive layer 111a and the semiconductor layer 113c can be reduced.

[0180] Same as FIG. 4A to FIG. 4C the transistor 43 shown, in FIG. 5A to FIG. 5C the transistor 43 shown, the source electrode, the drain electrode, and the gate electrode are provided with different heights with respect to the substrate surface and overlap each other. In addition, the gate electrode is provided so as to be sandwiched between the source electrode and the drain electrode. Therefore, in the transistor 43, the channel length direction corresponds to the direction along the side surface of the insulating layer 105c when viewed from the cross section, and the drain current flows along this direction.

[0181] When the transistor 43 has the above structure, the channel length of the transistor 43 can be controlled by adjusting the thickness of the semiconductor layer 113c located between the source electrode and the drain electrode when viewed from the cross section. Therefore, the channel length of the transistor 43 can be made smaller than the limit resolution of the exposure apparatus. In addition, compared with a transistor having a structure in which both the source electrode and the drain electrode are provided on the same plane, the occupied area of the transistor when viewed from the plane can be reduced.

[0182] In addition, as described above, in Figures 5A to 5CIn the transistor 43 shown, when viewed in plan, the gate electrode (conductive layer 115c) is disposed so as to surround the semiconductor layer 113c. Accordingly, the entire region of the semiconductor layer 113c that faces the conductive layer 115c with the insulating layer 105c interposed therebetween serves as the channel formation region of the transistor 43. At this time, the channel width direction of the transistor 43 is a direction parallel to the XY plane, and the channel width of the transistor 43 corresponds to Figure 5A the perimeter of the semiconductor layer 113c in

[0183] Figures 4A to 4C The transistor 43 shown has a structure in which the semiconductor layer 113c is disposed so as to cover an opening provided in the insulating layer, while Figures 5A to 5C the transistor 43 shown has a structure in which the semiconductor layer 113c is provided in a columnar shape. Accordingly, it can be said that Figures 5A to 5C the transistor 43 having the structure shown is a FIN type transistor. Thus, the transistor 43 in the semiconductor device 10 according to one embodiment of the present invention can have various structures.

[0184] In Figures 5A to 5C the semiconductor device 10 shown, other than the above differences (structures of the transistors 41 and 42, etc.), reference can be made to the description of the semiconductor device 10 shown in Figures 4A to 4C Shown.

[0185] Figure 6A Is Figure 4C an enlarged view of the transistor 42 and its vicinity shown. Further, Figure 6B shows a cross-sectional view of the transistor shown in Figure 6A truncated along the XY plane so as to include the semiconductor layer 113 and the conductive layer 112. Figure 6A And Figure 6B The structures shown can be used not only for the transistor 42 but also for the transistor 41.

[0186] As Figure 6A shown, the semiconductor layer 113 includes a region 113i and regions 113na and 113nb provided so as to sandwich the region 113i.

[0187] The region 113na is a region of the semiconductor layer 113 that contacts the conductive layer 111. At least a part of the region 113na is used as one of the source region and the drain region of the transistor. The region 113nb is a region of the semiconductor layer 113 that contacts the conductive layer 112. At least a part of the region 113nb is used as the other of the source region and the drain region of the transistor. As Figure 6B shown, the conductive layer 112 contacts the entire outer periphery of the semiconductor layer 113. Accordingly, the other of the source region and the drain region of the transistor can be formed on the entire outer periphery of the portion of the semiconductor layer 113 that is formed in the same layer as the conductive layer 112.

[0188] Region 113i is the region between region 113na and region 113nb of the semiconductor layer 113. At least a part of region 113i is used as the channel formation region of the transistor. That is to say, the channel formation region of the transistor is located in the region between the conductive layer 111 and the conductive layer 112 in the semiconductor layer 113. In addition, the channel formation region of the transistor can also be said to be the region in contact with or near the insulating layer 103 in the semiconductor layer 113.

[0189] The channel length of the transistor is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor is determined according to the thickness of the insulating layer 103 on the conductive layer 111. Figure 6A The channel length L of the transistor is shown by a solid double arrow in the figure. When viewed from the cross section, the channel length L becomes the distance between the end of the region where the semiconductor layer 113 contacts the conductive layer 111 and the end of the region where the semiconductor layer 113 contacts the conductive layer 112. That is to say, the channel length L corresponds to the length of the side on the opening 121 side of the insulating layer 103 when viewed from the cross section.

[0190] In a planar transistor, the channel length is set according to the exposure limit of photolithography, for example, but in the present invention, the channel length is set according to the thickness of the insulating layer 103. Therefore, the channel length of the transistor can be set to be very fine, that is, below the exposure limit of photolithography (for example, 1 nm or more and 60 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 40 nm or less, 1 nm or more and 30 nm or less, 1 nm or more and 20 nm or less, 1 nm or more and 10 nm or less, or 5 nm or more and 10 nm or less). Thereby, the on-state current of the transistor increases, and the frequency characteristics can be improved. Therefore, the read speed and write speed of the memory cell can be increased, so a semiconductor device with a high operating speed can be provided.

[0191] Here, the tolerance of the OS transistor to the short-channel effect is higher than that of the Si transistor, and the content will be described in detail later. In addition, as described above, for example, it is possible to make Figure 6A and Figure 6B The channel length of the transistor with the structure shown is shorter than that of the planar transistor. Thus, when the transistor has, for example, Figure 6A and Figure 6B the structure shown, the semiconductor layer 113 is preferably made of metal oxide. In addition, a material other than metal oxide such as silicon can also be used as the semiconductor layer 113.

[0192] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 121. Therefore, compared with a planar transistor in which the channel formation region, the source region, and the drain region are separately provided in the XY plane, the occupation area of the transistor can be reduced. As a result, the semiconductor device can be highly integrated, and thus the storage capacity per unit area can be increased.

[0193] As Figure 6B shown, the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 are arranged in concentric circles on the XY plane of the channel formation region including the semiconductor layer 113. Therefore, the side surface of the conductive layer 115 provided at the center faces the side surface of the semiconductor layer 113 with the insulating layer 105 therebetween. That is, the entire inner circumference of the semiconductor layer 113 is the channel formation region when viewed from the plane. At this time, for example, the channel width of the transistor is determined according to the outer circumference length of the semiconductor layer 113. That is to say, it can be said that the channel width of the transistor is determined according to the size of the maximum width of the opening 121 (when the opening 121 is circular when viewed from the plane, it refers to the diameter). Figure 6A And Figure 6B The maximum width D of the opening 121 is shown by a double-headed arrow of a dashed-dotted line. Figure 6B The channel width W of the transistor is shown by a double-headed arrow of a dotted line. By increasing the size of the maximum width D of the opening 121, the channel width per unit area is increased, and the on-state current can be increased.

[0194] The maximum width D of the opening 121 is preferably 5 nm or more and 100 nm or less, 10 nm or more and 60 nm or less, 20 nm or more and 50 nm or less, 20 nm or more and 40 nm or less, or 20 nm or more and 30 nm or less, for example. In addition, when the opening 121 is circular when viewed from the plane, the maximum width D of the opening 121 corresponds to the diameter of the opening 121, and the channel width W can be calculated as "D×π".

[0195] In the semiconductor device according to one embodiment of the present invention, the channel length L of the transistor is preferably at least smaller than the channel width W of the transistor. The channel length L of the transistor according to one embodiment of the present invention is 0.1 times or more and 0.99 times or less of the channel width W of the transistor, and preferably 0.5 times or more and 0.8 times or less. By adopting such a structure, a transistor having good electrical characteristics and high reliability can be realized.

[0196] Since the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 are arranged in concentric circles, the distance between the conductive layer 115 and the semiconductor layer 113 is substantially uniform. Therefore, a gate electric field can be applied to the semiconductor layer 113 substantially uniformly.

[0197] The side wall of the opening 121 is preferably perpendicular to the top surface of the conductive layer 111, for example. By adopting such a structure, miniaturization or high integration of the semiconductor device can be achieved. In addition, the side wall of the opening 121 can also be in a tapered shape.

[0198] The components of the transistor included in the memory cell will be described below.

[0199] [Components of the transistor] As the semiconductor layer 113, a single layer or a stack of metal oxides described in [Metal Oxides] to be described later can be used. In addition, as the semiconductor layer 113, a single layer or a stack of materials such as silicon described in [Other Semiconductor Materials] to be described later can be used.

[0200] When a metal oxide is used for the semiconductor layer 113, specifically, a metal oxide having a composition of In:M:Zn = 1:3:2 [atomic ratio] or around it, In:M:Zn = 1:3:4 [atomic ratio] or around it, In:M:Zn = 1:1:0.5 [atomic ratio] or around it, In:M:Zn = 1:1:1 [atomic ratio] or around it, In:M:Zn = 1:1:1.2 [atomic ratio] or around it, In:M:Zn = 1:1:2 [atomic ratio] or around it, or In:M:Zn = 4:2:3 [atomic ratio] or around it can be used. In addition, the composition around it includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M.

[0201] In addition, when depositing the metal oxide by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide, but can also be the atomic ratio of the sputtering target used for the deposition of the metal oxide.

[0202] The composition of the metal oxide for the semiconductor layer 113 can be analyzed, for example, using energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, multiple of the above methods can be combined for analysis. Note that elements with low content rates are sometimes affected by the analysis accuracy, and the actual content rate may differ from the content rate obtained by analysis. For example, when the content rate of element M is low, the content rate of element M obtained by analysis may sometimes be lower than the actual content rate.

[0203] The metal oxide can be appropriately formed using atomic layer deposition (ALD) method.

[0204] Alternatively, the metal oxide can also be formed using a sputtering method or a chemical vapor deposition (CVD) method.

[0205] Note that in the case of forming the metal oxide using a sputtering method, the composition of the formed metal oxide sometimes differs from the composition of the sputtering target. In particular, the zinc content rate in the formed metal oxide sometimes decreases to about 50% of the sputtering target.

[0206] The metal oxide for the semiconductor layer 113 preferably has crystallinity. Examples of oxide semiconductors with crystallinity include CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor), nc-OS (nanocrystalline Oxide Semiconductor), polycrystalline oxide semiconductors, and single crystal oxide semiconductors. CAAC-OS or nc-OS is preferably used for the semiconductor layer 113, and CAAC-OS is particularly preferably used.

[0207] CAAC-OS preferably has a plurality of layered crystal regions and its c-axis is oriented in the normal direction of the formation surface. For example, the semiconductor layer 113 preferably has layered crystals substantially parallel to the sidewalls of the opening 121, particularly layered crystals substantially parallel to the side surfaces of the insulating layer 103. By adopting such a structure, the layered crystals of the semiconductor layer 113 are substantially parallel to the channel length direction of the transistor, so that the on-state current of the transistor can be increased.

[0208] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies, etc.). In particular, by performing heat treatment at a temperature at which the metal oxide is not polycrystallized (e.g., 400 °C or higher and 600 °C or lower) after forming the metal oxide, CAAC-OS can have a denser structure with higher crystallinity. Thus, by further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0209] In addition, distinct grain boundaries are not easily observed in CAAC-OS, so a decrease in electron mobility due to grain boundaries is not likely to occur. Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide having CAAC-OS has heat resistance and high reliability.

[0210] In addition, when a crystalline oxide such as CAAC-OS is used as the semiconductor layer 113, the extraction of oxygen from the semiconductor layer 113 by the source electrode or the drain electrode can be suppressed. Therefore, even when heat treatment is performed, the extraction of oxygen from the semiconductor layer 113 can be suppressed, so the transistor is also stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0211] The crystallinity of the semiconductor layer 113 can be analyzed, for example, by X-ray diffraction (XRD: X-Ray Diffraction), transmission electron microscope (TEM: Transmission Electron Microscope), or electron diffraction (ED: Electron Diffraction). Alternatively, multiple of the above methods can be combined for analysis.

[0212] The thickness of the semiconductor layer 113 is, for example, preferably 1 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, 5 nm or more and 12 nm or less, or 5 nm or more and 10 nm or less.

[0213] Note that in Figure 4B , Figure 4C and Figure 6AThe semiconductor layer 113 is shown as a single layer, but the present invention is not limited thereto. The semiconductor layer 113 may also have a stacked structure of a plurality of oxide layers having different chemical compositions. For example, a structure in which a plurality of the above-mentioned metal oxides are appropriately stacked may also be employed.

[0214] As the insulating layer 105 serving as a gate insulating layer, a single layer or a stack of the insulators described in [Insulator] described later may be used. For example, silicon oxide or silicon oxynitride may be used as the insulating layer 105. Silicon oxide and silicon oxynitride have thermal stability, so they are preferred.

[0215] In addition, as the insulating layer 105, a material having a high relative dielectric constant, a so-called high-k material, described in [Insulator] described later may also be used. For example, hafnium oxide or aluminum oxide may be used.

[0216] The thickness of the insulating layer 105 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and further preferably 0.5 nm or more and 10 nm or less. At least a part of the insulating layer 105 preferably includes a region having the above-mentioned thickness.

[0217] The impurity concentration of water, hydrogen, etc. in the insulating layer 105 is preferably reduced. Thereby, the mixing of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 113 can be suppressed.

[0218] In Figure 4B 、 Figure 4C and Figure 6A the insulating layer 105 is shown as a single layer, but the present invention is not limited thereto. The insulating layer 105 may also have a stacked structure.

[0219] As the conductive layer 115 serving as a gate electrode, a single layer or a stack of the conductors described in [Conductor] described later may be used. For example, a highly conductive material such as tungsten, aluminum, or copper may be used as the conductive layer 115.

[0220] As the conductive layer 115, a conductive material that is not easily oxidized or a conductive material having a function of suppressing the diffusion of oxygen is preferably used. As such a conductive material, a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride, etc.) and a conductive material containing oxygen (for example, ruthenium oxide, etc.) can be cited. Thereby, a decrease in the conductivity of the conductive layer 115 can be suppressed. In addition, as the conductive layer 115, a semiconductor having a high conductivity such as polycrystalline silicon containing an impurity element such as phosphorus or a silicide such as nickel silicide may also be used.

[0221] Note that in Figure 4B 、 Figure 4C and Figure 6AIn this case, the conductive layer 115 is shown as a single layer, but the present invention is not limited thereto. The conductive layer 115 may also have a laminated structure.

[0222] As the conductive layer 111, a single layer or a laminate of the conductors described in [Conductor] to be described later can be used. As the conductive layer 111, a conductive material that is not easily oxidized or a conductive material having a function of suppressing the diffusion of oxygen is preferably used. For example, titanium nitride or tantalum nitride can be used. In addition, for example, a structure in which tantalum nitride is laminated on titanium nitride may also be used. At this time, titanium nitride is in contact with the insulating layer 101, the insulating layer 103c, the insulating layer 131, etc., and tantalum nitride is in contact with the semiconductor layer 113. By adopting such a structure, it is possible to suppress the excessive oxidation of the conductive layer 111 due to the semiconductor layer 113. In addition, when an oxide insulator is used as the insulating layer 101, the insulating layer 103c, the insulating layer 131, etc., it is possible to suppress the excessive oxidation of the conductive layer 111 due to the above-mentioned insulating layer. Alternatively, the conductive layer 111 may, for example, have a structure in which tungsten is laminated on titanium nitride.

[0223] Since the conductive layer 111 has a region in contact with the semiconductor layer 113, a conductive material containing oxygen described in [Conductor] to be described later is preferably used. By using a conductive material containing oxygen as the conductive layer 111, the conductivity can be maintained even if the conductive layer 111 absorbs oxygen. As the conductive layer 111, for example, a single layer or a laminate of indium tin oxide (also referred to as ITO), indium tin oxide added with silicon (also referred to as ITSO), or indium zinc oxide (also referred to as IZO (registered trademark)), etc. can be used.

[0224] In Figure 4B , Figure 4C and Figure 6A a structure in which the top surface of the conductive layer 111 is flat is shown, but the present invention is not limited thereto. For example, a recess overlapping the opening 121 may be formed on the top surface of the conductive layer 111. By forming at least a part of the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 so as to fill the recess, it is possible to easily apply the electric field of the conductive layer 115 to the vicinity of the conductive layer 111 of the semiconductor layer 113.

[0225] As the conductive layer 112, a single layer or a laminate of the conductors described in [Conductor] to be described later can be used. For example, as the conductive layer 112, a highly conductive material such as tungsten, aluminum, or copper can be used.

[0226] Similar to the conductive layer 111 and the conductive layer 115, the conductive layer 112 is also preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen, etc. For example, titanium nitride or tantalum nitride, etc. can be used. By adopting such a structure, it is possible to suppress the excessive oxidation of the conductive layer 112 due to the semiconductor layer 113. In addition, similar to the conductive layer 115, the conductive layer 112 can also use a semiconductor with high conductivity represented by polysilicon containing impurity elements such as phosphorus or a silicide such as nickel silicide.

[0227] For example, it is also possible to have a structure in which tungsten is laminated on titanium nitride. By laminating tungsten on titanium nitride in this way, the conductivity of the conductive layer 112 can be improved.

[0228] When the conductive layer 112 has a stacked structure of a first conductive layer and a second conductive layer, for example, a conductive material with high conductivity can be used to form the first conductive layer and a conductive material containing oxygen can be used to form the second conductive layer. By using a conductive material containing oxygen for the second conductive layer whose area in contact with the insulating layer 105 is larger than that of the first conductive layer, it is possible to suppress the diffusion of oxygen in the insulating layer 105 into the first conductive layer of the conductive layer 112. For example, it is preferable to use tungsten as the first conductive layer of the conductive layer 112 and indium tin oxide doped with silicon as the second conductive layer of the conductive layer 112.

[0229] By the semiconductor layer 113 contacting the conductive layer 111, a metal compound or oxygen vacancies are formed in the semiconductor layer 113, and the region 113na of the semiconductor layer 113 is made to have a low resistance. By making the semiconductor layer 113 in contact with the conductive layer 111 have a low resistance, the contact resistance between the semiconductor layer 113 and the conductive layer 111 can be reduced. Similarly, by the semiconductor layer 113 contacting the conductive layer 112, the region 113nb of the semiconductor layer 113 is made to have a low resistance. Therefore, the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced.

[0230] The relative dielectric constants of the insulating layers 101, 103, and 131 used as interlayer insulating layers are preferably low. By using a material with a low relative dielectric constant as the interlayer insulating layer, the parasitic capacitance generated between the wirings can be reduced. As the insulating layers 101, 103, and 131, a single layer or a stack of insulators containing a material with a low relative dielectric constant as described in [Insulator] to be described later can be used. In particular, silicon oxide and silicon oxynitride have thermal stability, so they are preferred.

[0231] The impurity concentrations of water, hydrogen, etc. in the insulating layers 101, 103, and 131 are preferably reduced. Thereby, it is possible to suppress the mixing of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 113.

[0232] The insulating layer 103 disposed near the channel formation region of the semiconductor layer 113 preferably contains oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). By performing heat treatment on the insulating layer 103 containing excess oxygen, oxygen is supplied from the insulating layer 103 to the channel formation region of the semiconductor layer 113, whereby the oxygen vacancies in the semiconductor layer 113 and the defects in which hydrogen enters the oxygen vacancies (hereinafter, sometimes also referred to as V O H) can be reduced. Thereby, the electrical characteristics of the transistor can be stabilized and the reliability can be improved.

[0233] As the insulating layer 103, an insulator having a function of capturing or fixing hydrogen as described in [Insulator] to be described later can also be used. By adopting such a structure, hydrogen in the semiconductor layer 113 is captured or fixed, whereby the hydrogen concentration in the semiconductor layer 113 can be reduced. As the insulating layer 103, magnesium oxide, aluminum oxide, or the like can be used.

[0234] In Figure 4B 、 Figure 4C and Figure 6A the insulating layer 103 is shown as a single layer, but the present invention is not limited thereto. The insulating layer 103 may also have a stacked structure.

[0235] As the insulating layer 107, an insulator having a hydrogen barrier property as described in [Insulator] to be described later is preferably used. Thereby, diffusion of hydrogen from the outside of the transistor through the insulating layer 105 to the semiconductor layer 113 can be suppressed. Since a silicon nitride film and a silicon oxynitride film have characteristics of rarely releasing impurities (for example, water and hydrogen) and being difficult for oxygen and hydrogen to permeate, they can be suitably used for the insulating layer 107.

[0236] As the insulating layer 107, an insulator having a function of capturing or fixing hydrogen as described in [Insulator] to be described later is preferably used. By adopting such a structure, diffusion of hydrogen from above the insulating layer 107 to the semiconductor layer 113 is suppressed, and hydrogen in the semiconductor layer 113 is captured or fixed, whereby the hydrogen concentration in the semiconductor layer 113 can be reduced. As the insulating layer 107, magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. In addition, for example, as the insulating layer 107, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide can also be used.

[0237] Note that although Figure 4B 、 Figure 4C and Figure 6AThe structure in which an insulating layer 107 is formed on top of the transistor is shown, but it is not limited thereto. For example, an insulating layer 107 or an insulating layer having the same function or material as the insulating layer 107 may also be formed on the side and bottom of the transistor to surround the transistor with this insulating layer. Alternatively, an insulating layer 107 may be formed on the top, side, and bottom surfaces of the transistors 43, 41, and 42 to surround the transistors 43, 41, and 42 with the insulating layer 107. By adopting this structure, entry of impurities (e.g., water, hydrogen, etc.) into the interiors of the transistors 43, 41, and 42 can be suppressed.

[0238] <Example structure 3 of semiconductor device> Figures 7A to 7C The structural example of the semiconductor device 10 showing one aspect of the present invention different from the structure described above is shown. Figure 7A It is a plan view showing a structural example of a part of the semiconductor device 10. Figure 7B It is along Figure 7A The cross-sectional view of the dotted line A1 - A2 shown, Figure 7C It is along Figure 7A The cross-sectional view of the dotted line A3 - A4 shown.

[0239] Figures 7A to 7C The difference between the semiconductor device 10 shown and Figures 4A to 4C the semiconductor device 10 shown is that the conductive layer serving as the other of the source electrode and the drain electrode of the transistor 43 and the conductive layer serving as one of the source electrode and the drain electrode of the transistor 41 are provided independently, and these two conductive layers are connected by a conductive layer serving as a plug.

[0240] In Figures 7A to 7C the transistor 43 included in the semiconductor device 10 shown, the conductive layer 112c serves as the other of the source electrode and the drain electrode. The conductive layer 112c can use the material that can be used for the aforementioned conductive layer 111 or conductive layer 112.

[0241] The conductive layer 112c is provided in such a way as to be in contact with the top surfaces of the semiconductor layer 113c, layer 114, insulating layer 107c, and insulating layer 103c_3 and have a region overlapping with the conductive layer 111c. In addition, an insulating layer 103c_4 is provided on the region of the insulating layer 103c_3 that does not overlap with the conductive layer 112c. The top surfaces of the conductive layer 112c and the insulating layer 103c_4 are substantially at the same height with respect to the substrate.

[0242] An insulating layer 132 is provided on the conductive layer 112c and the insulating layer 103c_4. The insulating layer 132 is provided with an opening in a region overlapping with the conductive layer 112c, and a conductive layer 118 is provided in such a manner as to fill the opening. Preferably, the top surface of the conductive layer 118 and the top surface of the insulating layer 132 are substantially at the same height with respect to the substrate. The top surface of the conductive layer 112c is in contact with the bottom surface of the conductive layer 118. In addition, the top surface of the conductive layer 118 is in contact with the bottom surface of the conductive layer 111a. Both the insulating layer 103c_4 and the insulating layer 132 serve as interlayer insulating layers. The insulating layer 103c_4 and the insulating layer 132 can use the materials that can be used for the aforementioned insulating layer 101, insulating layer 103, and insulating layer 131. In addition, the conductive layer 118 serves as a plug for electrically connecting the conductive layer 112c, which serves as the other of the source electrode and the drain electrode of the transistor 43, and the conductive layer 111a, which serves as one of the source electrode and the drain electrode of the transistor 41. The conductive layer 118 can use, for example, a highly conductive conductive material that can be used for the aforementioned conductive layer 115. In addition, in order to prevent the conductive layer 118 from being oxidized due to oxygen contained in the insulating layer 132 or the like, a conductive material that is not easily oxidized or a conductive material that can suppress oxygen diffusion and can be used for the aforementioned conductive layer 111, conductive layer 112, and conductive layer 115 is provided in contact with the side surface of the insulating layer 132, and a highly conductive conductive material is provided inside the conductive material.

[0243] In Figures 7A to 7C the semiconductor device 10 shown, other than the above differences, reference can be made to Figures 4A to 4C the description of the semiconductor device 10 shown.

[0244] <Structural Example 4 of Semiconductor Device> Figures 8A to 8C A structural example of the semiconductor device 10 showing one mode of the present invention different from the structure described above is shown. Figure 8A It is a plan view showing a structural example of a part of the semiconductor device 10. Figure 8B It is Figure 8A a cross-sectional view along the dotted line A1 - A2 shown, Figure 8C It is Figure 8A a cross-sectional view along the dotted line A3 - A4 shown.

[0245] Figures 8A to 8C The semiconductor device 10 shown Figures 7A to 7C is different from the semiconductor device 10 shown in that the conductive layer (conductive layer 112c), which serves as the other of the source electrode and the drain electrode of the transistor 43, and the conductive layer (conductive layer 111a), which serves as one of the source electrode and the drain electrode of the transistor 41, are directly connected without passing through a plug (that is, the top surface of the conductive layer 112c is in contact with the bottom surface of the conductive layer 111a).

[0246] By having the above structure, compared with Figures 7A to 7C the semiconductor device 10 shown, Figures 8A to 8C the semiconductor device 10 shown can further simplify the manufacturing process.

[0247] In Figures 8A to 8C the semiconductor device 10 shown, except for the above differences, reference can be made to Figures 4A to 4C the description of the semiconductor device 10 shown.

[0248] <Structural Example 5 of Semiconductor Device> Figures 9A to 9C Shows a structural example of the semiconductor device 10 according to an aspect of the present invention, which is different from the previously described structure. Figure 9A It is a plan view showing a structural example of a part of the semiconductor device 10. Figure 9B It is a cross-sectional view showing along Figure 9A the dotted line A1 - A2 shown, Figure 9C It is a cross-sectional view showing along Figure 9A the dotted line A3 - A4 shown.

[0249] Figures 9A to 9C The difference between the semiconductor device 10 shown and Figures 4A to 4C the semiconductor device 10 shown is that it does not include the other of the source electrode and the drain electrode of the transistor 43 and the conductive layer 111a that serves as one of the source electrode and the drain electrode of the transistor 41.

[0250] In Figures 9A to 9C the semiconductor device 10 shown, a part of the top surface of the semiconductor layer 113c in the transistor 43 and the top surface of the layer 114 are in direct contact with the bottom surface (the surface on the transistor 43 side) of the semiconductor layer 113a in the transistor 41.

[0251] By having the above structure, compared with Figures 4A to 4C the semiconductor device 10 shown, Figures 9A to 9C the semiconductor device 10 shown can further simplify the manufacturing process.

[0252] In Figures 9A to 9C the semiconductor device 10 shown, except for the above differences, reference can be made to Figures 4A to 4C the description of the semiconductor device 10 shown.

[0253] <Structural Example 6 of Semiconductor Device> Figures 10A to 10C Shows a structural example of the semiconductor device 10 according to an aspect of the present invention, which is different from the previously described structure. Figure 10A It is a plan view showing a structural example of a part of the semiconductor device 10. Figure 10B It is a cross-sectional view showing along Figure 10AThe cross-sectional view along the dotted line A1-A2 shown in FIG. Figure 10C It is shown along Figure 10A A cross-sectional view along the dashed line A3-A4 is shown.

[0254] Figures 10A to 10C The semiconductor device 10 shown is Figures 9A to 9C The semiconductor device 10 shown is different in that the opening 121 c in the transistor 43 and the opening 121 a in the transistor 41 are not formed separately, but one opening 126 is formed for the transistor 43 and the transistor 41 at one time.

[0255] exist Figures 10A to 10C In the semiconductor device 10 shown, an opening 126 reaching the conductive layer 111c is formed in the insulating layer 103c_1, the conductive layer 115c, the insulating layer 103a, and the conductive layer 112a. The insulating layer 105c is provided so as to contact the side surface of the insulating layer 103c_1, the side surface of the conductive layer 115c, the side surface of the insulating layer 103a, and the side surface of the conductive layer 112a on the side of the opening 126. The semiconductor layer 113a is provided so as to fill at least a part of the opening 126 via the insulating layer 105c. The conductive layer 115a is provided so as to fill the concave portion on the semiconductor layer 113a in the opening 126 via the insulating layer 105a.

[0256] By having the above structure, with Figures 9A to 9C Compared with the semiconductor device 10 shown, Figures 10A to 10C The semiconductor device 10 shown can further simplify the manufacturing process.

[0257] exist Figures 10A to 10C In the semiconductor device 10 shown in FIG. 1 , other than the above differences, reference can be made to Figures 4A to 4C A description of a semiconductor device 10 is shown.

[0258] <Semiconductor Device Structure Example 7> Figures 11A to 11C An example of a structure of a semiconductor device 10 according to one embodiment of the present invention that is different from the structure described above is shown. Figure 11A 1 is a plan view showing a structural example of a part of the semiconductor device 10 . Figure 11B It is shown along Figure 11A The cross-sectional view along the dotted line A1-A2 shown in FIG. Figure 11C It is shown along Figure 11A A cross-sectional view along the dashed line A3-A4 is shown.

[0259] Figures 11A to 11C The semiconductor device 10 shown is Figures 9A to 9CThe semiconductor device 10 shown is different in that the semiconductor layer 113a in the transistor 41 is formed so as to fill the recess in the semiconductor layer 113c in the transistor 43.

[0260] In Figures 11A to 11C the semiconductor device 10 shown, the semiconductor layer 113a in the transistor 41 is provided in Figures 9A to 9C the portion where the layer 114 included in the transistor 43 of the semiconductor device 10 shown is provided.

[0261] By having the above structure, compared with Figures 9A to 9C the semiconductor device 10 shown, Figures 11A to 11C the semiconductor device 10 shown can further simplify the manufacturing process.

[0262] In Figures 11A to 11C the semiconductor device 10 shown, except for the above differences, reference can be made to Figures 4A to 4C the description of the semiconductor device 10 shown.

[0263] <Structural Example 8 of Semiconductor Device> Figures 12A to 12C The structural example of the semiconductor device 10 showing one mode of the present invention different from the previously described structure is shown. Figure 12A It is a plan view showing the structural example of a part of the semiconductor device 10. Figure 12B It is a cross-sectional view showing along Figure 12A the dotted line A1 - A2 shown, Figure 12C It is a cross-sectional view showing along Figure 12A the dotted line A3 - A4 shown.

[0264] Figures 12A to 12C The semiconductor device 10 shown is the same as Figures 10A to 10C the semiconductor device 10 shown in that the opening 126 reaching the conductive layer 111c is provided in the insulating layer 103c_1, the conductive layer 115c, the insulating layer 103a, and the conductive layer 112a. However, it is different from Figures 10A to 10C the semiconductor device 10 shown in that the bottom surface of the conductive layer 115a included in the transistor 41 is located below (on the conductive layer 111c side) the conductive layer 115c included in the transistor 43.

[0265] In Figures 12A to 12CIn the semiconductor device 10 shown, an insulating layer 105c is provided on the side surfaces of the insulating layer 103c_1, the conductive layer 115c, the insulating layer 103a, and the conductive layer 112a on the side of the contact opening 126. A semiconductor layer 113a is provided in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 105c, and the top surface of the conductive layer 111c. An insulating layer 105a is provided to cover the semiconductor layer 113a. Here, a concave portion reflecting the shape of the opening 126 is formed on the semiconductor layer 113a and the insulating layer 105a. A conductive layer 115a is provided to fill the concave portion.

[0266] Figures 12A to 12C In the semiconductor device 10 shown, by having the above structure, a region sandwiched between both the conductive layer 115a and the conductive layer 115c is formed in the semiconductor layer 113a. An electric field from the conductive layer 115a and an electric field from the conductive layer 115c are applied to this region. Therefore, compared with Figures 10A to 10C the semiconductor device 10 shown, Figures 12A to 12C the semiconductor device 10 shown can further improve the carrier controllability in the semiconductor layer 113a.

[0267] In Figures 12A to 12C the semiconductor device 10 shown, for the rest other than the above differences, reference can be made to the description of the semiconductor device 10 shown in Figures 4A to 4C the semiconductor device 10 shown.

[0268] The semiconductor device according to one embodiment of the present invention may also include a memory cell having a capacitor as shown in Figure 2B , Figure 3B and Figure 3C shown. The following shows a structural example of a semiconductor device having a capacitor according to one embodiment of the present invention.

[0269] <Structural Example 9 of Semiconductor Device> Figure 13A , Figure 16A and Figure 16B show a structural example of the semiconductor device 10 according to one embodiment of the present invention. Figure 13A is a plan view showing a structural example of a part of the semiconductor device 10. Figure 16A is a cross-sectional view along the dotted line A1 - A2 shown in Figure 13A , Figure 16B is a cross-sectional view along the dotted line A3 - A4 shown in Figure 13A .

[0270] Figure 13A , Figure 16A and Figure 16B The semiconductor device 10 shown in Figures 4A to 4COn top of the structure of the semiconductor device 10 shown, a capacitor 51 is further included. The capacitor 51 is stacked on the transistor 41, and the transistor 42 is stacked on the capacitor 51.

[0271] The capacitor 51 includes a conductive layer 141, a conductive layer 143, and an insulating layer 135.

[0272] The conductive layer 143 is used as one electrode of the capacitor 51. The conductive layer 141 is used as the other electrode of the capacitor 51 and is used as the wiring 36. The insulating layer 135 is used as the dielectric layer of the capacitor 51. The conductive layer 141 serving as the wiring 36 has a region extending in the X direction.

[0273] The conductive layer 141 has an opening 123, and the insulating layer 135 and the conductive layer 143 are provided inside the opening 123. Specifically, the insulating layer 135 is provided inside the opening 123 so as to cover the side surface of the conductive layer 141, and the conductive layer 143 is provided inside the insulating layer 135. Thus, the conductive layer 141 covers at least a part of the side surface of the conductive layer 143 with the insulating layer 135 in between. The insulating layer 135 has, for example, a region in contact with the side surface of the conductive layer 141 and a region in contact with the side surface of the conductive layer 143 inside the opening 123.

[0274] An insulating layer 133 is provided on the conductive layer 141. The conductive layer 141 and the insulating layer 133 may have the same shape when viewed from the plane and both have the opening 123. For example, after successively depositing a conductive film that becomes the conductive layer 141 and an insulating film that becomes the insulating layer 133, a pattern may be formed using photolithography, and then the above-mentioned insulating film and the above-mentioned conductive film may be processed using etching according to the pattern, thereby forming the insulating layer 133 and the conductive layer 141 having the opening 123.

[0275] Figure 13A An example is shown in which the shape of the opening 123 when viewed from the plane is a quadrilateral. In addition, in Figure 13A , the shape of the opening 123 is a square when viewed from the plane, but the shape of the opening 123 is not limited to this. For example, the shape when viewed from the plane may also be a rectangle, a rhombus, or a parallelogram. In addition, the shape of the opening 123 when viewed from the plane may also be a triangle or a polygon with five or more sides. Furthermore, in Figure 13A the example shown, the top surface shape of the conductive layer 143 is a quadrilateral in the same way as the opening 123, but the conductive layer 143 may also have the same top surface shape as the above-mentioned top surface shape that the opening 123 may have. In addition, the top surface shape of the opening 123 may also be different from the top surface shape of the conductive layer 143.

[0276] An insulating layer 135 is provided on the insulating layer 133. Specifically, the insulating layer 135 is provided in such a manner as to cover the top surface and the side surfaces of the insulating layer 133. An insulating layer 137 is provided on the insulating layer 135.

[0277] An opening 125 is provided in the insulating layer 107a, the insulating layer 131, the insulating layer 135, and the insulating layer 137. The opening 125 is provided in such a manner as to have an overlapping area with the opening 123. A conductive layer 143 is provided inside the opening 125. By providing the conductive layer 143 inside the opening 125 that reaches the conductive layer 115a, for example, the top surface of the conductive layer 115a can be brought into contact with the bottom surface of the conductive layer 143. Thereby, the conductive layer 115a serving as the gate electrode of the transistor 41 can be electrically connected to the conductive layer 143 serving as one electrode of the capacitor 51.

[0278] Here, when the insulating layer 133 is not provided on the conductive layer 141, sometimes a region where the thickness of the insulating layer 135 is thin is formed between the conductive layer 141 and the conductive layer 143 in the process of forming the opening 125. That is to say, sometimes a region where the distance between the conductive layer 141 and the conductive layer 143 is short is formed. At this time, sometimes the conductive layer 141 and the conductive layer 143 are short-circuited, for example. Then, by providing the insulating layer 133 on the conductive layer 141, the formation of a region where the distance between the conductive layer 141 and the conductive layer 143 is short can be suppressed. Thereby, the reliability of the memory cell 21 can be improved, and thus a semiconductor device with high reliability can be provided. In addition, the manufacturing yield of the semiconductor device can be improved, and an inexpensive semiconductor device can be provided. Further, for example, if there is no short circuit between the conductive layer 141 and the conductive layer 143, the insulating layer 133 may not be provided. At this time, the manufacturing process of the semiconductor device can be simplified.

[0279] The height of the top surface of the conductive layer 143 and the top surface of the insulating layer 137 with respect to the substrate surface is substantially the same. A conductive layer 111b serving as one of the source electrode and the drain electrode of the transistor 42 is provided on the conductive layer 143 in such a manner as to have an overlapping area with the conductive layer 143.

[0280] The conductive layer 111b has an area in contact with the conductive layer 143. For example, the bottom surface of the conductive layer 111b has an area in contact with the top surface of the conductive layer 143. Thereby, the conductive layer 111b serving as one of the source electrode and the drain electrode of the transistor 42 can be electrically connected to the conductive layer 143 serving as one electrode of the capacitor 51. In addition, as described above, the conductive layer 143 is electrically connected to the conductive layer 115a serving as the gate electrode of the transistor 41. As described above, the gate electrode of the transistor 41, one of the source electrode and the drain electrode of the transistor 42, and one electrode of the capacitor 51 can be electrically connected.

[0281] The components of the capacitor included in the memory cell will be described below.

[0282] [Constituent elements of the capacitor] As the conductive layers 141 and 143, a single layer or a laminate of the conductors described in the [conductor] to be described later can be used. For example, as the conductive layers 141 and 143, highly conductive materials such as tungsten, aluminum, or copper can be used. By using such a highly conductive material, the conductivity of the conductive layers 141 and 143 can be improved.

[0283] The conductive layers 141 and 143 are preferably a single layer or a laminate of a conductive material that is not easily oxidized or a conductive material having a function of suppressing the diffusion of oxygen. For example, indium tin oxide added with titanium nitride or silicon can also be used. Or, for example, a structure in which titanium nitride is laminated on tungsten can be adopted. Or, for example, a structure in which tungsten is laminated on the first titanium nitride and the second titanium nitride is laminated on the tungsten can be adopted. By adopting such a structure, when an oxide insulator is used as the insulating layer 135, oxidation of the conductive layers 141 and 143 due to the insulating layer 135 can be suppressed. In addition, when an oxide insulator is used as the insulating layer 133, oxidation of the conductive layer 141 due to the insulating layer 133 can be suppressed. In addition, as the conductive layers 141 and 143, a highly conductive semiconductor such as polysilicon containing impurity elements such as phosphorus or a silicide such as nickel silicide can also be used.

[0284] As the insulating layer 135, a material having a high relative dielectric constant described in the [insulator] to be described later, a so-called high-k material, is preferably used. By using a high-k material as the insulating layer 135, the insulating layer 135 can be thickened to an extent that can suppress leakage current and sufficiently ensure the electrostatic capacitance of the capacitor 51.

[0285] The insulating layer 135 is preferably laminated with an insulator made of a high-k material, and a laminated structure of a material having a high relative dielectric constant (high-k) and a material having a dielectric strength greater than that of the high-k material is preferably used. For example, as the insulating layer 135, an insulating film in which zirconia, alumina, and zirconia are laminated in sequence can be used. In addition, for example, an insulating film in which zirconia, alumina, zirconia, and alumina are laminated in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina are laminated in sequence can be used. By laminating an insulator having a relatively large dielectric strength such as alumina, the dielectric strength is improved, and thus electrostatic breakdown of the capacitor 51 can be suppressed.

[0286] As the insulating layer 135, a material that can have ferroelectricity can also be used. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO X(X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material in which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide can be cited. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set. For example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or around it. In addition, as a material that can have ferroelectricity, a material in which element J2 (element J2 here is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide can be cited, etc. In addition, the ratio of the number of zirconium atoms to the number of element J2 atoms can be appropriately set. For example, the ratio of the number of zirconium atoms to the number of element J2 atoms can be set to 1:1 or around it. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), bismuth strontium tantalate (SBT), bismuth ferrite (BFO), or barium titanate and other piezoelectric ceramics having a perovskite structure can also be used.

[0287] In addition, as a material that can have ferroelectricity, metal nitrides containing element M1, element M2, and nitrogen can be cited. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the atomic ratio of element M1 to element M2 can be appropriately set. In addition, metal oxides containing element M1 and nitrogen sometimes have ferroelectricity even if they do not contain element M2. In addition, as a material that can have ferroelectricity, a material in which element M3 is added to the above metal nitride can be cited. In addition, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of element M1 atoms, the number of element M2 atoms, and the number of element M3 atoms can be appropriately set.

[0288] In addition, as a material that can have ferroelectricity, perovskite oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 of κ-type alumina can be cited.

[0289] Note that although metal oxides and metal nitrides are shown in the above description, it is not limited thereto. For example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitroxides obtained by adding oxygen to the above metal nitrides can also be used.

[0290] In addition, as a material that may have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the above materials may be used. Alternatively, the insulating layer 135 may have a laminated structure composed of a plurality of materials selected from the above materials. For example, the crystal structure (characteristics) of the materials exemplified above may change not only according to the deposition conditions but also according to various processes. Therefore, in this specification and the like, a material that exhibits ferroelectricity is not only referred to as a ferroelectric material, but also as a material that may have ferroelectricity or a material that imparts ferroelectricity.

[0291] Metal oxides containing one or both of hafnium and zirconium are preferably used because they can have ferroelectricity even when processed into a thin film of several nm. Here, the thickness of the insulating layer 135 may be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and further preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). For example, the thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, a semiconductor device can be formed by combining the capacitor 51 with a semiconductor element such as a miniaturized transistor. In this specification and the like, a material that may have ferroelectricity formed in a layer is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, in this specification and the like, a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0292] Metal oxides containing one or both of hafnium and zirconium are preferably used because they can have ferroelectricity even when they have a small area. For example, the ferroelectric layer can have ferroelectricity even when the area (occupied area) when viewed from above is 100 μm 2 or less, 10 μm 2 or less, 1 μm 2 or less, or 0.1 μm 2 or less. In addition, sometimes it can have ferroelectricity even when the area is 10000 μm 2 or less, 1000 μm 2 or less. By forming a ferroelectric layer with a small area, the occupied area of the capacitor 51 can be reduced.

[0293] A ferroelectric body is an insulator that polarizes internally under the action of an externally applied electric field and retains the polarization even when the electric field is zero. Therefore, by using a capacitor that uses this material as a dielectric (hereinafter sometimes referred to as a ferroelectric capacitor), a non-volatile memory element can be formed. A non-volatile memory element using a ferroelectric capacitor is sometimes called FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Thus, when a ferroelectric capacitor is used as capacitor 51, the semiconductor device shown in this embodiment can be used as a ferroelectric memory.

[0294] In addition, ferroelectricity is considered to be exhibited due to the displacement of oxygen or nitrogen in the crystal contained in the ferroelectric layer under an external electric field. In addition, it is presumed that the manifestation of ferroelectricity depends on the structure of the crystal contained in the ferroelectric layer. Therefore, in order for the insulating layer 135 to exhibit ferroelectricity, the insulating layer 135 needs to contain a crystal. In particular, the insulating layer 135 preferably has a crystal with an orthorhombic crystal structure, thereby exhibiting ferroelectricity. The crystal structure of the crystal contained in the insulating layer 135 may be any one or more selected from the cubic system, tetragonal system, orthorhombic system, monoclinic system, and hexagonal system. In addition, the insulating layer 135 may have an amorphous structure. In this case, the insulating layer 135 may also have a composite structure of an amorphous structure and a crystal structure.

[0295] The relative dielectric constant of the insulating layer 133 is preferably low. Thereby, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 133, a single layer or a stack of insulators containing a material with a low relative dielectric constant as described in [Insulator] to be described later can be used. In particular, silicon oxide and silicon oxynitride have thermal stability, so they are preferred.

[0296] In Figure 16A and Figure 16B the insulating layer 133 is shown as a single layer, but the present invention is not limited thereto. The insulating layer 133 may also have a stacked structure.

[0297] <Structural Example 10 of Semiconductor Device> Figure 13B , Figure 17A and Figure 17B show a structural example of a semiconductor device 10 according to one aspect of the present invention, which is different from the structure described above. Figure 13B is a plan view showing a structural example of a part of the semiconductor device 10. Figure 17A is Figure 13B a cross-sectional view taken along the dotted line A1 - A2 shown in Figure 17B is Figure 13BA cross-sectional view along the dashed line A3-A4 is shown.

[0298] Figure 13B , Figure 17A and Figure 17B The semiconductor device 10 shown is a combination of Figures 7A to 7C The semiconductor device 10 and Figure 13A , Figure 16A and Figure 16B A semiconductor device 10 is shown.

[0299] Specifically, in Figures 7A to 7C The semiconductor device 10 shown in the figure includes a transistor 43, a transistor 41, and a transistor 42, and a transistor 43 is provided between the transistor 41 and the transistor 42. Figure 13A , Figure 16A and Figure 16B The semiconductor device 10 shown includes a capacitor 51 .

[0300] Regarding other than the above Figure 13B , Figure 17A and Figure 17B The semiconductor device 10 shown in FIG. Figures 7A to 7C The semiconductor device 10 shown in FIG. Figure 13A , Figure 16A and Figure 16B A description of a semiconductor device 10 is shown.

[0301] <Semiconductor Device Structure Example 11> Figure 13C , Figure 18A and Figure 18B An example of a structure of a semiconductor device 10 according to one embodiment of the present invention that is different from the structure described above is shown. Figure 13C 1 is a plan view showing a structural example of a part of the semiconductor device 10 . Figure 18A It is shown along Figure 13C The cross-sectional view along the dotted line A1-A2 shown in FIG. Figure 18B It is shown along Figure 13C A cross-sectional view along the dashed line A3-A4 is shown.

[0302] Figure 13C , Figure 18A and Figure 18B The semiconductor device 10 shown is a combination of Figures 8A to 8C The semiconductor device 10 and Figure 13A , Figure 16A and Figure 16B A semiconductor device 10 is shown.

[0303] Specifically, in Figures 8A to 8COn the structures of the transistor 43, the transistor 41, and the transistor 42 included in the semiconductor device 10 shown, a Figure 13A , Figure 16A and Figure 16B the capacitor 51 included in the semiconductor device 10 shown are provided between the transistor 41 and the transistor 42.

[0304] Regarding those other than the above Figure 13C , Figure 18A and Figure 18B shown in the semiconductor device 10, reference can be made to the description of the semiconductor device 10 shown in Figures 8A to 8C and the description of the semiconductor device 10 shown in Figure 13A , Figure 16A and Figure 16B shown in the semiconductor device 10.

[0305] <Structural Example 12 of Semiconductor Device> Figure 14A , Figure 19A and Figure 19B show a structural example of the semiconductor device 10 according to one aspect of the present invention, which is different from the previously described structure. Figure 14A is a plan view showing a structural example of a part of the semiconductor device 10. Figure 19A is a cross-sectional view showing a cross-section along the Figure 14A indicated dash-dotted line A1 - A2, Figure 19B is a cross-sectional view showing a cross-section along the Figure 14A indicated dash-dotted line A3 - A4.

[0306] Figure 14A , Figure 19A and Figure 19B shown in the semiconductor device 10 combine the semiconductor device 10 shown in Figures 9A to 9C and the semiconductor device 10 shown in Figure 13A , Figure 16A and Figure 16B shown in the semiconductor device 10.

[0307] Specifically, on the structures of the transistor 43, the transistor 41, and the transistor 42 included in the semiconductor device 10 shown in Figures 9A to 9C , a Figure 13A , Figure 16A and Figure 16B the capacitor 51 included in the semiconductor device 10 shown are provided between the transistor 41 and the transistor 42.

[0308] In the semiconductor device 10 shown in Figure 14A , Figure 19A and Figure 19B , for those other than the above points, reference can be made to the description of the semiconductor device 10 shown in Figures 9A to 9C and Figure 13A ,Figure 16A and Figure 16B description of the semiconductor device 10 shown

[0309] <Structural example 13 of semiconductor device> Figure 14B 、 Figure 20A and Figure 20B show a structural example of the semiconductor device 10 according to one aspect of the present invention, which is different from the previously described structure Figure 14B is a plan view showing a structural example of a part of the semiconductor device 10 Figure 20A is a cross-sectional view showing a cross-section along the Figure 14B dotted line A1 - A2 shown Figure 20B is a cross-sectional view showing a cross-section along the Figure 14B dotted line A3 - A4 shown

[0310] Figure 14B 、 Figure 20A and Figure 20B The semiconductor device 10 shown combines the semiconductor device 10 shown Figures 10A to 10C with the semiconductor device 10 shown Figure 13A 、 Figure 16A and Figure 16B shown semiconductor device 10

[0311] Specifically, on the structures of the transistor 43, transistor 41, and transistor 42 included in the semiconductor device 10 shown Figures 10A to 10C a capacitor 51 included in the semiconductor device 10 shown Figure 13A 、 Figure 16A and Figure 16B is provided between the transistor 41 and the transistor 42

[0312] In the semiconductor device 10 shown Figure 14B 、 Figure 20A and Figure 20B for the parts other than the above points, reference can be made to the description of the semiconductor device 10 shown Figures 10A to 10C and the description of the semiconductor device 10 shown Figure 13A 、 Figure 16A and Figure 16B shown

[0313] <Structural example 14 of semiconductor device> Figure 14C 、 Figure 21A and Figure 21B show a structural example of the semiconductor device 10 according to one aspect of the present invention, which is different from the previously described structure Figure 14C is a plan view showing a structural example of a part of the semiconductor device 10 Figure 21A is a cross-sectional view showing a cross-section along the Figure 14C dotted line A1 - A2 shownFigure 21B is a cross-sectional view taken along the Figure 14C dash-dotted line A3 - A4 shown.

[0314] Figure 14C , Figure 21A and Figure 21B the semiconductor device 10 shown combines Figures 11A to 11C the semiconductor device 10 shown and Figure 13A , Figure 16A and Figure 16B the semiconductor device 10 shown.

[0315] Specifically, on the structures of the transistor 43, transistor 41, and transistor 42 included in the Figures 11A to 11C semiconductor device 10 shown, a Figure 13A , Figure 16A and Figure 16B capacitor 51 included in the semiconductor device 10 shown is provided between the transistor 41 and the transistor 42.

[0316] In the Figure 14C , Figure 21A and Figure 21B semiconductor device 10 shown, for points other than the above, reference may be made to the description of the Figures 11A to 11C semiconductor device 10 shown and Figure 13A , Figure 16A and Figure 16B description of the semiconductor device 10 shown.

[0317] <Structural Example 15 of Semiconductor Device> Figure 15A , Figure 22A and Figure 22B show a structural example of the semiconductor device 10 according to one aspect of the present invention, which is different from the structures described above. Figure 15A is a plan view showing a structural example of a part of the semiconductor device 10. Figure 22A is a cross-sectional view taken along the Figure 15A dash-dotted line A1 - A2 shown, Figure 22B is a cross-sectional view taken along the Figure 15A dash-dotted line A3 - A4 shown.

[0318] Figure 15A , Figure 22A and Figure 22B the semiconductor device 10 shown combines Figures 12A to 12C the semiconductor device 10 shown and Figure 13A , Figure 16A and Figure 16B the semiconductor device 10 shown.

[0319] Specifically, in the Figures 12A to 12CAbove the structures of the transistor 43, the transistor 41, and the transistor 42 included in the semiconductor device 10 shown, a Figure 13A , Figure 16A and Figure 16B the capacitor 51 included in the semiconductor device 10 shown are provided between the transistor 41 and the transistor 42.

[0320] In Figure 15A , Figure 22A and Figure 22B shown in the semiconductor device 10, for parts other than the above points, reference can be made to the description of the semiconductor device 10 shown in Figures 12A to 12C and the description of the semiconductor device 10 shown in Figure 13A , Figure 16A and Figure 16B shown.

[0321] <Structural Example 16 of Semiconductor Device> Figure 15B , Figure 23A and Figure 23B show a structural example of the semiconductor device 10 according to one aspect of the present invention, which is different from the previously described structure. Figure 15B is a plan view showing a structural example of a part of the semiconductor device 10. Figure 23A is a cross-sectional view showing the section along the Figure 15B shown dash line A1 - A2, Figure 23B is a cross-sectional view showing the section along the Figure 15B shown dash line A3 - A4.

[0322] Figure 15B , Figure 23A and Figure 23B shown, the semiconductor device 10 includes a transistor 43, a transistor 41, and a transistor 42 (3Tr0C type memory cell structure).

[0323] Figure 15B , Figure 23A and Figure 23BIn the semiconductor device 10 shown, an insulating layer 103c_1, a conductive layer 115c, an insulating layer 103a, a conductive layer 112a, an insulating layer 131, and a conductive layer 141 are sequentially provided on an insulating layer 101 and a conductive layer 111c. An opening 120 reaching the conductive layer 111c is provided in these layers. An insulating layer 105c is provided in contact with the side surfaces of the insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103a on the side of the opening 120. A semiconductor layer 113a is provided in contact with the top surface of the conductive layer 141, the side surfaces of the conductive layer 141 in the opening 120, the side surface of the insulating layer 131, the side surface of the conductive layer 112a, the side surface of the insulating layer 105c, and the top surface of the conductive layer 111c. An insulating layer 105a is provided to cover the semiconductor layer 113a. Here, a concave portion reflecting the shape of the opening 120 is formed on the semiconductor layer 113a and the insulating layer 105a. A conductive layer 115a is provided to fill this concave portion.

[0324] In Figure 15B , Figure 23A and Figure 23B In the semiconductor device 10 shown, the semiconductor layer 113a serves as the semiconductor layer of the transistor 43 and the semiconductor layer of the transistor 41. The insulating layer 105a serves as the gate insulating layer of the transistor 43 and the gate insulating layer of the transistor 41. The conductive layer 115a serves as the gate electrode of the transistor 43 and the gate electrode of the transistor 41. The conductive layer 112a serves as the other of the source electrode and the drain electrode of the transistor 43 and one of the source electrode and the drain electrode of the transistor 41. The conductive layer 141 serves as the other of the source electrode and the drain electrode of the transistor 41.

[0325] Here, in Figure 16A and Figure 16B In the semiconductor device 10 shown, etc., the conductive layer 141 serves as the other electrode of the capacitor 51. However, Figure 15B , Figure 23A and Figure 23B The semiconductor device 10 shown does not include the capacitor 51. In such a memory cell structure without a capacitor, the conductive layer that can be used as the other electrode of the capacitor can be used as a part of the conductive layer of the transistor.

[0326] In addition, in the transistor 43, in addition to the insulating layer 105a, the insulating layer 105c also has the function of a gate insulating layer. In addition, in addition to the conductive layer 115a, the conductive layer 115c also has the function of a gate electrode. That is, the transistor 43 has a structure including two gate electrodes. Therefore, compared with a structure having only one gate electrode, the carrier controllability in the semiconductor layer 113a can be further improved.

[0327] In addition, as described above, since multiple layers such as the semiconductor layer 113a, the insulating layer 105a, and the conductive layer 115a can be shared between the transistor 43 and the transistor 41, the manufacturing process of the semiconductor device can be simplified accordingly.

[0328] <Structural example 17 of semiconductor device> Figure 15C 、 Figure 24A and Figure 24B FIG. 10 shows a structural example of a semiconductor device 10 according to an aspect of the present invention, which is different from the structure described above. Figure 15C FIG. 11 is a plan view showing a structural example of a part of the semiconductor device 10. Figure 24A FIG. 12 is a cross-sectional view taken along the dotted line A1-A2 shown in Figure 15C FIG. 12, and Figure 24B FIG. 13 is a cross-sectional view taken along the dotted line A3-A4 shown in Figure 15C FIG. 13.

[0329] Figure 15C 、 Figure 24A and Figure 24B The semiconductor device 10 shown in FIG. 10 is different from the semiconductor device 10 shown in FIGS. 14 and 15 in that the conductive layer 112a, which serves as the other of the source electrode and the drain electrode of the transistor 41, is electrically connected to the conductive layer 141, which serves as the other electrode of the capacitor 51. Figure 16A and Figure 16B FIG. 15.

[0330] In Figure 15C 、 Figure 24A and Figure 24B FIG. 10, the top surface of the conductive layer 115a included in the transistor 41, the topmost surface of the insulating layer 105a, the topmost surface of the semiconductor layer 113a, the top surface of the conductive layer 112a, the topmost surface of the insulating layer 107a, and the top surface of the insulating layer 131 are substantially at the same height relative to the substrate surface. On the other hand, the bottom surface of the conductive layer 143 included in the capacitor 51, the lowermost surface of the insulating layer 135, and the bottom surface of the conductive layer 141 are substantially at the same height relative to the substrate surface. The top surface of the conductive layer 112a and the bottom surface of the conductive layer 141 have a contact area with each other.

[0331] Figure 15C 、 Figure 24A and Figure 24B By having the above structure, the semiconductor device 10 shown in FIG. 10 can provide the same potential to the conductive layer 112a and the conductive layer 141. As described above, the conductive layer 112a serves as the wiring 35, and the conductive layer 141 serves as the wiring 36. Therefore, by making the semiconductor device 10 have the above structure, the number of wirings can be reduced, and thus the manufacturing process can be simplified.

[0332] In Figure 15C 、Figure 24A and Figure 24B In the semiconductor device 10 shown, other than the above differences, reference may be made to Figure 16A and Figure 16B the description of the semiconductor device 10 shown.

[0333] <Structural example of a display device> One aspect of the present invention can also be used for a display device. Figure 25A is a block diagram showing a structural example of a display device 70 of one aspect of the present invention. The display device 70 includes a display unit 80, a scan line drive circuit 71, a signal line drive circuit 73, a power supply circuit 75, and a reference potential generation circuit 77. The display unit 80 includes a plurality of pixels 81 arranged in a matrix. In addition, the power supply circuit 75 may also be provided outside the display device 70.

[0334] The scan line drive circuit 71 is electrically connected to the pixels 81 through wirings 31 (wirings 31a, 31b, and 31c). The wiring 31 extends, for example, in the row direction of the above matrix.

[0335] The signal line drive circuit 73 is electrically connected to the pixels 81 through a wiring 33. The wiring 33 extends, for example, in the column direction of the above matrix.

[0336] The power supply circuit 75 is electrically connected to the pixels 81 through a wiring 35. The wiring 35 extends, for example, in the row direction of the above matrix.

[0337] The reference potential generation circuit 77 is electrically connected to the pixels 81 through a wiring 38. The wiring 38 extends, for example, in the column direction of the above matrix.

[0338] The pixel 81 includes a display element (also referred to as a display device), and an image can be displayed on the display unit 80 through the display element. As the display element, for example, a light-emitting element (also referred to as a light-emitting device) can be used, and specifically, an organic EL element can be used. In addition, a liquid crystal element (also referred to as a liquid crystal device) can be used as the display element.

[0339] The scan line drive circuit 71 has, for example, a function of selecting the pixels 81 to which image data is to be written row by row. Specifically, the scan line drive circuit 71 can select the pixels 81 to which image data is to be written by outputting a signal to the wiring 31. Here, in the scan line drive circuit 71, for example, after outputting the above signal to the wiring 31 of the first row, the above signal is output to the wiring 31 of the second row, and the above signal is sequentially output until the wiring 31 of the last row, whereby all the pixels 81 can be selected. Thus, the signal output by the scan line drive circuit 71 to the wiring 31 is a scan signal, and it can be said that the wiring 31 provided in the display device 70 is a scan line.

[0340] The signal line driving circuit 73 has a function of generating image data. The image data is supplied to the pixels 81 through the wiring 33. For example, the image data can be written to all the pixels 81 included in the row selected by the scan line driving circuit 71. Here, the image data can be represented as a signal (image signal). Therefore, the wiring 33 provided in the display device 70 can be said to be a signal line.

[0341] The power supply circuit 75 has a function of generating a power supply potential and supplying it to the wiring 35. The power supply circuit 75 has, for example, a function of generating a high power supply potential (hereinafter, simply referred to as "high potential" or "VDD") and supplying it to the wiring 35. In addition, the power supply circuit 75 may also have a function of generating a low power supply potential (hereinafter, simply referred to as "low potential" or "VSS"). As described above, the wiring 35 is used as a power supply line.

[0342] The reference potential generation circuit 77 has a function of generating a reference potential and supplying it to the wiring 38. Since the potential of the wiring 38 is the reference potential, the wiring 38 can be called a reference potential line. In addition, the electrical characteristics of each pixel can be read out to the reference potential generation circuit 77 outside the pixel through the wiring 38. In other words, the reference potential generation circuit 77 may also have a function of sensing the electrical characteristics of each pixel. The electrical characteristics of each pixel can be read by the reference potential generation circuit 77 to sense deterioration, unevenness, etc. of the elements (transistors, light-emitting elements, etc.) in each pixel. Moreover, the deterioration and unevenness of the image quality can be corrected by feeding back the read characteristics to the video signal.

[0343] Figure 25B is a plan view showing an example of the structure of the pixel 81. The pixel 81 may include a plurality of sub-pixels 83. Figure 25B shows an example in which the pixel 81 includes the sub-pixels 83R, 83G, and 83B as sub-pixels 83. Here, when the pixel 81 includes a light-emitting element as a display element, for example, Figure 25B the top surface shape of the sub-pixel shown corresponds to the top surface shape of the light-emitting area of the light-emitting element. Note that in Figure 25B it is shown that the aperture ratios (which may also be referred to as sizes or the sizes of the light-emitting areas) of the sub-pixels 83R, 83G, and 83B are equal or approximately equal, but one embodiment of the present invention is not limited to this. The aperture ratios of the sub-pixels 83R, 83G, and 83B can be appropriately determined respectively. The aperture ratios of the sub-pixels 83R, 83G, and 83B may be different from each other, or two or more of them may be equal or approximately equal.

[0344] Figure 25BIn the pixel 81 shown, the stripe arrangement is adopted as the arrangement method of the sub-pixels 83. In addition, as the arrangement method of the sub-pixels 83, the S-stripe arrangement, the matrix arrangement, the Delta arrangement, the Bayer arrangement, the Pentile arrangement, etc. can also be adopted.

[0345] The sub-pixel 83R, the sub-pixel 83G, and the sub-pixel 83B emit light of different colors. As the sub-pixel 83R, the sub-pixel 83G, and the sub-pixel 83B, three-color sub-pixels of red (R), green (G), and blue (B) and three-color sub-pixels of yellow (Y), cyan (C), and magenta (M) can be cited, etc. In addition, four or more sub-pixels 83 can also be provided in the pixel 81. For example, four-color sub-pixels of R, G, B, and white (W) can also be provided in the pixel 81. Thus, in the display device 70, the pixel 81 includes a plurality of sub-pixels 83 that emit light of different colors, and a full-color image can be displayed on the display unit 80. In addition, sub-pixels of R, G, B, and infrared light (IR) can also be provided in the pixel 81, for example.

[0346] In addition, a sensor can also be provided in the display unit 80. For example, a sensor can also be provided in the pixel 81. For example, the display unit 80 can also be used as a fingerprint sensor. For example, the display unit 80 can also be used as an optical or ultrasonic fingerprint sensor.

[0347] Figure 25C is a circuit diagram showing Figure 25A an example of the structure of the sub-pixel 83 included in the pixel 81 shown. Figure 25C The sub-pixel 83 shown includes a pixel circuit 90 and a light-emitting element 91.

[0348] The pixel circuit 90 includes a transistor 41, a transistor 42, a transistor 43, a transistor 53, a capacitor 51, and a capacitor 58. That is to say, the pixel circuit 90 is a 4Tr2C type pixel circuit.

[0349] In the pixel circuit 90, one of the source and drain of the transistor 42 is electrically connected to the wiring 33. The other of the source and drain of the transistor 42 is electrically connected to one electrode of the capacitor 51 and the gate of the transistor 41. The gate of the transistor 42 is electrically connected to the wiring 31a. One of the source and drain of the transistor 41 is electrically connected to one of the source and drain of the transistor 43. The other of the source and drain of the transistor 43 is electrically connected to the wiring 35. The gate of the transistor 43 is electrically connected to the wiring 31c. One electrode of the capacitor 58 is electrically connected to the other of the source and drain of the transistor 41, one of the source and drain of the transistor 53, the other electrode of the capacitor 51, and one electrode of the light-emitting element 91. The other electrode of the capacitor 58 is electrically connected to the wiring 35. The other of the source and drain of the transistor 53 is electrically connected to the wiring 38. The gate of the transistor 53 is electrically connected to the wiring 31b. The other electrode of the light-emitting element 91 is electrically connected to the wiring 37.

[0350] The transistor 43 is used as a switch and has a function of controlling the conduction state or non-conduction state between the wiring 35 and one of the source and drain of the transistor 41 according to the potential of the wiring 31c.

[0351] By turning on the transistor 43, for example, a current corresponding to the magnitude of the gate potential of the transistor 41 flows from the wiring 35 to the wiring 37. Thus, the light-emitting element 91 emits light having a luminance corresponding to the gate potential of the transistor 41. On the other hand, by turning off the transistor 43, current can be prevented from flowing through the light-emitting element 91, and thus the light-emitting element 91 can be prevented from emitting light.

[0352] As the transistors 41, 42, and 43, it is preferable to use OS transistors. The OS transistor has a higher field-effect mobility, for example, compared to a transistor using amorphous silicon. Thus, by using OS transistors as the transistors 41 and 42, the display device 70 can be driven at high speed.

[0353] As described above, the off-state current of the OS transistor is significantly small. Thus, by using the OS transistor as the transistor 42, the charge stored in the capacitor 51 can be retained for a long time. Thus, since the image data written to the sub-pixel 83 can be retained for a long time, the frequency of the refresh operation (rewriting the image data to the sub-pixel 83) can be reduced. Therefore, the power consumption of the display device 70 can be reduced.

[0354] Here, when increasing the emission luminance of the light-emitting element 91, it is necessary to increase the current flowing through the light-emitting element 91. Accordingly, it is necessary to increase the source-drain voltage of the transistor 41 of the driving transistor. Since the breakdown voltage between the source and the drain of the OS transistor is higher than that of the Si transistor, a high voltage can be applied between the source and the drain of the OS transistor. Accordingly, by using the OS transistor as the transistor 41, the current flowing through the light-emitting element 91 can be increased to increase the emission luminance of the light-emitting element 91.

[0355] As the light-emitting element 91, for example, an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode) is preferably used. Examples of the light-emitting substance included in the light-emitting element 91 include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and an inorganic compound (for example, a quantum dot material). In addition, as the light-emitting element 91, an LED such as a micro LED (Light Emitting Diode) can also be used.

[0356] <Structural example 18 of semiconductor device> The structural examples of the plurality of memory cells 21 will be described below. Specifically, the structural example of the four-row four-column memory cells 21 will be described with reference to the plan view. Note that some symbols may be omitted in this plan view.

[0357] Figure 26A is a diagram showing Figure 4A a plan view of a structural example in which the memory cells 21 shown are arranged in a matrix. Figure 26B is a plan view in which the transistors 42 and 43 in the structure shown in Figure 26A are omitted.

[0358] As shown in Figure 26A and Figure 26BAs shown, the conductive layer 111c serving as the wiring 33R and the conductive layer 112a serving as the wiring 35 both have regions extending in the Y direction and are shared by the memory cells 21 arranged in the Y direction. That is, the memory cells 21 in the same column share the same conductive layer 111c and conductive layer 112a. Thus, when reading the data held in the memory cells 21, it is possible to prevent current from flowing through one wiring 35 serving as a power supply line from multiple wirings 33R serving as read bit lines. Therefore, the current flowing through the wiring 35 can be reduced. Here, due to Ohm's law, the voltage drop ΔV of the wiring becomes the product of the wiring resistance R and the current I (ΔV = R×I). Therefore, by reducing the current flowing through the wiring 35, especially in the memory cells 21, for example, where the wiring distance from Figure 1A the power supply circuit 15 shown is long, it is possible to suppress the potential drop of the potential supplied as the power supply potential. Thus, for example, it is possible to suppress the inability to accurately read the data held in the memory cells 21. Therefore, it is possible to provide a memory cell and a semiconductor device with high read accuracy.

[0359] In addition, in Figure 26A the example shown, the conductive layer 115b serving as the wiring 31W has a region extending in the X direction and is shared by the memory cells 21 arranged in the X direction. That is, the memory cells 21 in the same row share the same conductive layer 115b. In addition, the conductive layer 112b serving as the wiring 33W has a region extending in the Y direction and is shared by the memory cells 21 arranged in the Y direction. That is, the memory cells 21 in the same column share the same conductive layer 112b.

[0360] Figure 27 and Figure 28 is Figure 26A a cross-sectional view of the 4-row and 4-column memory cells 21 shown in the plan view. Figure 27 is a cross-sectional view along the XZ plane, Figure 28 is a cross-sectional view along the YZ plane. As Figure 26A the plan view and Figure 27 and Figure 28 the cross-sectional views shown, a semiconductor device according to one embodiment of the present invention can be configured with high density in the XY plane with memory cells 21 having a structure in which three transistors with source electrodes and drain electrodes provided at different heights with respect to the substrate surface are stacked. Thus, not only can the occupied area of each memory cell be reduced when viewed from the plane, but also a semiconductor device with high integration of multiple memory cells can be realized.

[0361] Note that, as described later Figure 57 and the like, a semiconductor device according to one embodiment of the present invention may have a structure in which memory cells 21 are stacked not only in the XY plane but also in the Z direction. By adopting this structure, further high integration of the semiconductor layer device can be achieved.

[0362] Figure 29A and Figure 29B are respectively Figure 26A and Figure 26B Examples of modifications of the structure shown, showing an example in which the conductive layer 112a used as the wiring 35 is shared by the storage cells 21 in two adjacent columns. By sharing the conductive layer 112a among the storage cells 21 in multiple columns, the storage cells 21 can be arranged in a high density.

[0363] Figure 30A and Figure 30B are respectively Figure 26A and Figure 26B Examples of modifications of the structure shown, the conductive layer 112a of the wiring 35 used as the power supply line has a region extending in the X direction and a region extending in the Y direction. And, the conductive layer 112a includes an opening 121a in a region where the region extending in the X direction intersects with the region extending in the Y direction. By adopting such a shape for the conductive layer 112a, for example, compared with Figure 26A and Figure 26B the structure shown, the wiring resistance of the conductive layer 112a can be reduced. On the other hand, in Figure 30A and Figure 30B the example shown, for example, the conductive layer 112a included in all the storage cells 21 are electrically connected to each other. Therefore, when reading the data held in the storage cell 21, for example, current flows from all the wirings 33R through one conductive layer 112a. In addition, in Figure 30B the example shown, the conductive layer 112a includes an opening 122 surrounded by four storage cells 21.

[0364] Figure 31A and Figure 31B are respectively Figure 30A and Figure 30B Examples of modifications of the structure shown, showing an example in which the conductive layer 112a does not include the opening 122. In Figure 31A and Figure 31B the example shown, in a storage section where the storage cells 21 are arranged in a matrix, the following structure can be adopted: the shape of the conductive layer 112a is quadrilateral and an opening 121a is provided in the quadrilateral conductive layer 112a.

[0365] Figure 32A and Figure 32B are respectively Figure 26A and Figure 26B Examples of modifications of the structure shown, the conductive layer 112a used as the wiring 35 has a region extending in the X direction, showing an example of being shared by the storage cells 21 arranged in the X direction. That is, in Figure 32A and Figure 32B the example shown, the storage cells 21 in the same row share the same conductive layer 112a.

[0366] Figure 33A and Figure 33B are respectively Figure 32A and Figure 32B The modified examples of the structures shown, showing an example where the memory cells 21 in adjacent two rows share the conductive layer 112a. By sharing the conductive layer 112a among the memory cells 21 in multiple rows, the memory cells 21 can be arranged in a high density.

[0367] <Constituent Materials of Semiconductor Devices> Hereinafter, the constituent materials applicable to semiconductor devices will be described.

[0368] [Substrate] As the substrate for forming the transistors 41, 42, 43 and the capacitor 51, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As the insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., yttrium-stabilized zirconia substrate) and a resin substrate etc. can be cited. In addition, as the semiconductor substrate, for example, a semiconductor substrate made of silicon, germanium etc., or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide etc. can be cited. And, a semiconductor substrate having an insulator region inside the above semiconductor substrate can also be cited, for example, an SOI (Silicon On Insulator; silicon-on-insulator) substrate. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate and a conductive resin substrate etc. can be cited. Or, a substrate containing a metal nitride, a substrate containing a metal oxide etc. can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator etc. can be cited. Or, a substrate provided with elements on these substrates can also be used.

[0369] [Insulator] As the insulator, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides and metal nitrides etc. having insulation properties.

[0370] For example, when miniaturizing and highly integrating transistors, due to the thinning of the gate insulating layer, problems such as leakage current sometimes occur. By using a high-k material as the insulator used for the gate insulating layer, low voltage operation of the transistor can be achieved while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator used for the gate insulating layer can be reduced. On the other hand, by using a material with a relatively low relative permittivity for the insulator used for the interlayer insulating layer, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulator. In addition, a material with a relatively low relative permittivity is also a material with a large dielectric strength.

[0371] As materials with a relatively high relative permittivity (high-k), for example, alumina, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium can be cited.

[0372] As materials with a low relative permittivity, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate, and acrylic resin can be cited. In addition, as other inorganic insulating materials with a low relative permittivity, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, for example, silicon oxide with pores can be cited. Note that these silicon oxides can also contain nitrogen. In addition, silicon oxide can be formed using an organosilane such as tetraethoxysilane (TEOS), for example.

[0373] In addition, by surrounding a transistor using a metal oxide with an insulator having a function of suppressing the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the permeation of impurities and oxygen, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. Specifically, as an insulator having a function of suppressing the permeation of impurities and oxygen, metal oxides such as alumina, magnesia, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0374] In addition, an insulator in contact with a semiconductor layer such as a gate insulating layer or an insulator provided near the semiconductor layer is preferably an insulator having a region containing excess oxygen. For example, by bringing an insulator having a region containing excess oxygen into contact with the semiconductor layer or providing it near the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. As an insulator in which a region containing excess oxygen is easily formed, silicon oxide, silicon oxynitride, or silicon oxide with pores can be cited.

[0375] In addition, as an insulator having oxygen barrier properties, oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesia, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride can be cited. In addition, as oxides containing one or both of aluminum and hafnium, alumina, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) can be cited.

[0376] In addition, examples of the insulator having hydrogen barrier properties include alumina, magnesia, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride.

[0377] The insulator having oxygen barrier properties and the insulator having hydrogen barrier properties can be said to be insulators having barrier properties against one or both of oxygen and hydrogen.

[0378] In addition, examples of the insulator having the function of capturing or fixing hydrogen include oxides containing magnesium or oxides containing one or both of aluminum and hafnium. Additionally, these oxides preferably have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds and sometimes have the property of capturing or fixing hydrogen by these dangling bonds. These metal oxides preferably have an amorphous structure, and a part thereof may also form a crystalline region.

[0379] Note that in this specification and the like, the barrier insulating film refers to an insulating film having barrier properties. In addition, the barrier property refers to the property that the corresponding substance is not easily diffused (also referred to as the property that the corresponding substance is not easily permeated, the property that the permeability of the corresponding substance is low, or the function of suppressing the diffusion of the corresponding substance). Furthermore, the function of capturing or fixing (also referred to as gettering) the corresponding substance can also be referred to as the barrier property. Note that hydrogen described as the corresponding substance, for example, refers to at least one of hydrogen atoms, hydrogen molecules, water molecules, and substances hydrogen-bonded such as OH - and the like. In addition, unless otherwise specified, the impurities described as the corresponding substances refer to impurities in the channel formation region or the semiconductor layer, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, and the like. In addition, oxygen described as the corresponding substance, for example, refers to at least one of oxygen atoms and oxygen molecules. Specifically, the oxygen barrier property refers to the property that at least one of oxygen atoms and oxygen molecules is not easily diffused.

[0380] [Conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal element as a component, or an alloy combining the above metal elements. As the alloy containing the above metal element as a component, a nitride or an oxide of the alloy can also be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like. In addition, a semiconductor having a high conductivity represented by polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0381] In addition, nitrogen-containing conductive materials such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, or titanium and aluminum nitride, ruthenium oxide, oxygen-containing conductive materials such as strontium and ruthenium oxide or lanthanum and nickel oxide, materials containing metal elements such as titanium, tantalum or ruthenium are conductive materials that are not easily oxidized, conductive materials with the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Note that as oxygen-containing conductive materials, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide added with silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide can be cited. In this specification and the like, oxygen-containing conductive materials are sometimes referred to as oxide conductors.

[0382] In addition, conductive materials mainly composed of tungsten, copper or aluminum have high conductivity, so they are preferred.

[0383] In addition, a plurality of conductors formed of the above materials can be laminated. For example, a laminated structure combining a material containing the above metal element and an oxygen-containing conductive material can be adopted. In addition, a laminated structure combining a material containing the above metal element and a nitrogen-containing conductive material can be adopted. In addition, a laminated structure combining a material containing the above metal element, an oxygen-containing conductive material, and a nitrogen-containing conductive material can be adopted.

[0384] In addition, when a metal oxide is used for the channel formation region of a transistor, a laminated structure combining a material containing the above metal element and an oxygen-containing conductive material is preferably used as the conductor used as the gate electrode. In this case, it is preferable to dispose the oxygen-containing conductive material on the channel formation region side. By disposing the oxygen-containing conductive material on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0385] In particular, as the conductor used as the gate electrode, a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel is preferably used. In addition, a conductive material containing the above metal element and nitrogen can also be used. For example, a nitrogen-containing conductive material such as titanium nitride or tantalum nitride can be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, sometimes the hydrogen contained in the metal oxide forming the channel can be captured. Or sometimes the hydrogen mixed in from an external insulator or the like can be captured.

[0386] [Metal Oxide] Metal oxides sometimes have lattice defects. As lattice defects, there are point defects such as atomic vacancies and strange atoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. In addition, as the causes of lattice defect formation, there are deviations in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms) and impurities, etc.

[0387] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause generation or capture of carriers, etc. Therefore, when a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, it is preferable that the lattice defects in the metal oxide used for the semiconductor layer of a transistor are few.

[0388] In a transistor using a metal oxide for the semiconductor layer, especially, if there are oxygen vacancies (V O ) and impurities in the metal oxide in the channel formation region, the electrical characteristics are likely to vary and the reliability may sometimes decrease. In addition, hydrogen near the oxygen vacancy forms V O H and may generate electrons that become carriers. Therefore, when the metal oxide in the channel formation region contains oxygen vacancies, the transistor has a normally-on characteristic (a characteristic in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Thus, in the metal oxide in the channel formation region, it is preferable to minimize oxygen vacancies and impurities as much as possible. In other words, it is preferable that the carrier concentration in the metal oxide in the channel formation region is reduced and it is i-type (intrinsic) or substantially i-type.

[0389] The types of lattice defects that are likely to exist in a metal oxide and the amount of lattice defects present vary depending on the structure of the metal oxide or the deposition method of the metal oxide, etc.

[0390] The structure of a metal oxide is classified into a single crystal structure and other structures (non-single crystal structures). As non-single crystal structures, for example, there are CAAC structures, polycrystalline structures, nc structures, amorphous-like (a-like) structures, and amorphous structures, etc. The a-like structure has a structure intermediate between the nc structure and the amorphous structure.

[0391] In addition, voids or low-density regions exist in the metal oxides having an a-like structure and the metal oxides having an amorphous structure. In other words, the crystallinity of the metal oxides having an a-like structure and the metal oxides having an amorphous structure is lower than that of the metal oxides having an nc structure and the metal oxides having a CAAC structure. In addition, the hydrogen concentration in the metal oxides having an a-like structure is higher than that in the metal oxides having an nc structure and the metal oxides having a CAAC structure. Therefore, lattice defects are likely to be generated in the metal oxides having an a-like structure and the metal oxides having an amorphous structure.

[0392] Therefore, it is preferable to use a metal oxide having high crystallinity for the semiconductor layer of the transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a single crystal structure. By using this metal oxide for the semiconductor layer of the transistor, a transistor having good electrical characteristics can be realized. In addition, a transistor having high reliability can be realized.

[0393] In addition, it is preferable to use, for the channel formation region of the transistor, a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is only necessary to increase the mobility of the metal oxide used for the transistor. In order to increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce the scattering factors that affect the transport of carriers. The carriers flow from the source electrode to the drain electrode through the channel formation region. Therefore, by providing a channel formation region in which carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0394] Here, it is preferable to use, as the metal oxide having a channel formation region, a metal oxide having high crystallinity. Furthermore, the crystal preferably has a crystal structure in which a plurality of layers (for example, a first layer, a second layer, and a third layer) are stacked. In other words, the crystal has a layered crystal structure (also referred to as a layered crystal or a layered structure). At this time, the c-axis direction of the crystal is the direction in which a plurality of layers are stacked. The metal oxide having such a crystal includes, for example, a single crystal oxide semiconductor and a CAAC-OS.

[0395] In addition, the c-axis of the above-described crystal is preferably oriented in the normal direction of the formation surface or the film surface of the metal oxide. As a result, the plurality of layers are arranged in parallel or substantially parallel to the formation surface or the film surface of the metal oxide. That is, the plurality of layers extend in the channel length direction.

[0396] For example, the above-described three-layered crystal structure has the following structure. The first layer has an atomic coordination structure of an oxygen octahedron with the metal contained in the first layer at the center. The second layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal contained in the second layer at the center. The third layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal contained in the third layer at the center.

[0397] As the crystal structure of the above-described crystal, for example, there are YbFe2O4-type structures, Yb2Fe3O7-type structures, and modified structures thereof.

[0398] Furthermore, preferably, the first to third layers are each composed of one metal element or multiple metal elements having the same valence, and oxygen. Preferably, the valence of one or more metal elements constituting the first layer is the same as the valence of one or more metal elements constituting the second layer. Additionally, the first layer and the second layer may also contain the same metal element. Additionally, preferably, the valence of one or more metal elements constituting the first layer is different from the valence of one or more metal elements constituting the third layer.

[0399] By adopting the above structure, the crystallinity of the metal oxide can be improved, thereby improving the mobility of the metal oxide. Thus, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.

[0400] As the metal oxide according to one aspect of the present invention, for example, indium oxide, gallium oxide, and zinc oxide can be cited. The metal oxide according to one aspect of the present invention preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than with indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony, etc. can be cited. Element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. When element M contained in the metal oxide is gallium, the metal oxide according to one aspect of the present invention preferably contains any one or more selected from indium, gallium, and zinc. Note that in this specification, etc., sometimes metal elements and metalloid elements are collectively referred to as "metal elements", and sometimes the "metal elements" described in this specification, etc. include metalloid elements.

[0401] As a metal oxide of one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. may be used. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. may be cited.

[0402] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0403] The metal oxide may also contain one or more metal elements with a large period number instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large period number in addition to indium. The metal oxide has a tendency that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by containing a metal element with a large period number, the field-effect mobility of the transistor can sometimes be increased. As the metal element with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period, etc. may be cited. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, etc. may be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0404] The metal oxide may also contain one or more non-metal elements. By the metal oxide containing non-metal elements, the field-effect mobility of the transistor can sometimes be increased. As the non-metal element, for example, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, hydrogen, etc. may be cited.

[0405] In addition, by increasing the atomic number ratio of zinc to the total number of atoms of all metal elements contained in the metal oxide, the crystallinity of the metal oxide is improved, whereby the diffusion of impurities in the metal oxide can be suppressed. Thereby, the variation in the electrical characteristics of the transistor is suppressed, and the reliability can be improved.

[0406] In addition, by increasing the atomic number ratio of element M to the total number of atomic numbers of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, and thus a transistor with a small off-state current can be realized. In addition, variations in the electrical characteristics of the transistor are suppressed, and thus the reliability can be improved.

[0407] In addition, by increasing the atomic number ratio of In to the sum of the atomic numbers of all metal elements in the metal oxide, a transistor with a large on-state current and high frequency characteristics can be obtained.

[0408] In the present embodiment, an example in which the metal oxide is an In-Ga-Zn oxide may be described.

[0409] In order to form the above-described metal oxide having a layered crystal structure, it is preferable to deposit atoms layer by layer. By using the ALD method, it is easy to form a metal oxide having the above-described layered crystal structure.

[0410] Examples of the ALD method include a thermal ALD (Thermal ALD) method in which only heat energy is used to react a precursor and a reactant, and a plasma ALD (PEALD: Plasma Enhanced ALD) method in which a reactant excited by plasma is used.

[0411] The ALD method can deposit atoms layer by layer, and thus has effects such as being able to deposit extremely thinly, being able to deposit on a structure with a high aspect ratio, being able to deposit with few defects such as pinholes, being able to perform highly covering deposition, and being able to deposit at a low temperature. Since plasma is used, deposition can be performed at a lower temperature, so the PEALD method is sometimes preferable. The precursor used in the ALD method sometimes contains elements such as carbon or chlorine. Therefore, the film formed by the ALD method sometimes contains more elements such as carbon or chlorine than the film formed by other deposition methods. In addition, the quantification of the above elements can be performed using XPS or SIMS.

[0412] When the ALD method is used as the deposition method of the metal oxide, by adopting one or both of the conditions of a high substrate temperature during deposition and an impurity removal treatment, the amounts of carbon and chlorine in the film can be reduced compared to the case where the ALD method is used without adopting these conditions.

[0413] For example, when depositing a metal oxide, it is preferable to intermittently perform an impurity removal treatment in an oxygen-containing atmosphere. In addition, after depositing the metal oxide, it is preferable to perform an impurity removal treatment in an oxygen-containing atmosphere. By performing the impurity removal treatment in one or both of the deposition and after-deposition of the metal oxide, impurities in the film can be removed. Thereby, impurities (such as hydrogen, carbon, and nitrogen) contained in raw materials such as precursors can be inhibited from remaining in the metal oxide. Therefore, the impurity concentration in the metal oxide can be reduced. In addition, the crystallinity of the metal oxide can be improved.

[0414] As the impurity removal treatment, for example, plasma treatment, microwave treatment, and heat treatment can be cited.

[0415] When performing plasma treatment or microwave treatment, the substrate temperature is preferably 25°C or higher and 500°C or lower, 100°C or higher and 500°C or lower, 200°C or higher and 500°C or lower, 300°C or higher and 500°C or lower, 400°C or higher and 500°C or lower, or 400°C or higher and 450°C or lower. In addition, the temperature of the heat treatment is preferably 100°C or higher and 450°C or lower, 200°C or higher and 450°C or lower, 300°C or higher and 450°C or lower, or 400°C or higher and 450°C or lower.

[0416] In particular, by setting the temperature in the impurity removal treatment to a temperature below the highest temperature in the manufacturing process of the transistor or semiconductor device, the impurity content of the metal oxide can be reduced without a decrease in productivity, so it is preferable. For example, by setting the highest temperature in the manufacturing of the semiconductor device according to one embodiment of the present invention to 500°C or lower, preferably 450°C or lower, the productivity of the transistor or semiconductor device can be improved.

[0417] Here, the microwave treatment is, for example, a treatment using a device including a power source that generates high-density plasma with microwaves. In addition, in this specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz or higher and 300 GHz or lower.

[0418] The microwave treatment preferably uses, for example, a microwave treatment device including a power source that generates high-density plasma with microwaves. Here, the frequency of the microwave treatment device is preferably set to 300 MHz or higher and 300 GHz or lower, more preferably 2.4 GHz or higher and 2.5 GHz or lower, and can be 2.45 GHz, for example. By using high-density plasma, high-density oxygen radicals can be generated. In addition, the power of the power source that applies microwaves in the microwave treatment device is preferably 1000 W or higher and 10000 W or lower, preferably 2000 W or higher and 5000 W or lower. In addition, the microwave treatment device may also include a power source that applies RF to the substrate side. In addition, by applying RF to the substrate side, oxygen ions generated from the high-density plasma can be efficiently introduced into the film.

[0419] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, more preferably 300 Pa or more and 700 Pa or less. In addition, the treatment temperature is preferably room temperature (25 °C) or more and 750 °C or less, more preferably 300 °C or more and 500 °C or less, and further preferably 400 °C or more and 450 °C or less.

[0420] In addition, after the microwave treatment or the oxygen plasma treatment, heat treatment can be continuously carried out without exposure to external air. The temperature of the heat treatment is, for example, preferably 100 °C or more and 750 °C or less, more preferably 300 °C or more and 500 °C or less, and further preferably 400 °C or more and 450 °C or less.

[0421] For example, the above microwave treatment can be carried out using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2 + Ar)) is greater than 0% and 100% or less. Preferably, the oxygen flow ratio (O2 / (O2 + Ar)) is greater than 0% and 50% or less. More preferably, the oxygen flow ratio (O2 / (O2 + Ar)) is 10% or more and 40% or less. Further preferably, the oxygen flow ratio (O2 / (O2 + Ar)) is 10% or more and 30% or less.

[0422] The heat treatment is carried out in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas is preferably set to about 20%. The heat treatment can also be carried out under reduced pressure. Alternatively, it can be carried out in a nitrogen gas or inert gas atmosphere, and then in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to replenish the oxygen that has escaped. The heat treatment can be carried out in an ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, and more preferably 10 ppb or less) atmosphere.

[0423] By carrying out the heat treatment in this way, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. And while removing the above impurities, metal atoms and oxygen atoms are rearranged, so the crystallinity can be improved. Thereby, a metal oxide having a highly crystalline layered crystal structure, particularly the above-mentioned CAAC structure metal oxide, can be formed.

[0424] For example, different from deposition methods such as deposition by particles released from a target or the like, the ALD method is a deposition method in which a film is formed by reaction on the surface of an object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, since the ALD method has good step coverage and thickness uniformity, the ALD method is suitable, for example, for forming a film that covers the surface of an opening with a high aspect ratio. However, since the deposition rate of the ALD method is relatively slow, it is sometimes preferable to use it in combination with other deposition methods such as a sputtering method or a CVD method with a high deposition rate. For example, a method of depositing a first metal oxide by a sputtering method and depositing a second metal oxide on the first metal oxide by the ALD method can be cited. For example, when the above-mentioned first metal oxide has a crystalline part, crystal growth sometimes occurs in the second metal oxide with the crystalline part as a nucleus.

[0425] The ALD method can control the composition of the obtained film according to the introduction amount of the source gas. For example, in the ALD method, by adjusting the introduction amount of the source gas, the number of introductions (also referred to as the number of pulses), and the time required for one pulse (also referred to as the pulse time), etc., a film with an arbitrary composition can be deposited. In addition, for example, when using the ALD method, a film with a continuously changing composition can be deposited by changing the source gas while performing deposition. When depositing while changing the source gas, since the time required for transfer and pressure adjustment is not required, the deposition time can be shortened compared to the case of depositing using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0426] [[Transistor including metal oxide]] Next, the case of using a metal oxide (oxide semiconductor) for a transistor will be described. Hereinafter, a transistor using an oxide semiconductor for a semiconductor layer is called an OS transistor, and a transistor using silicon for an active layer is called a Si transistor.

[0427] By using the metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with a high field-effect mobility can be realized. In addition, a transistor with high reliability can be realized. In addition, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.

[0428] It is preferable to use an oxide semiconductor with a low carrier concentration for the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Hereinafter, it is preferably 1×10 17 cm -3 Hereinafter, it is more preferably 1×10 15 cm -3Hereinafter, it is further preferably 1×10 13 cm -3 Hereinafter, it is also preferably 1×10 11 cm -3 Hereinafter, it is even more preferably less than 1×10 10 cm -3 and is 1×10 -9 cm -3 or more. When aiming to reduce the carrier concentration of the oxide semiconductor film, it is preferable to reduce the impurity concentration of the oxide semiconductor film to reduce the density of defect states. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as highly pure intrinsic or substantially highly pure intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0429] Since a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film has a low density of defect states, it is possible to have a low density of trap states.

[0430] In addition, it takes a long time for the charge trapped in the trap states of the oxide semiconductor to disappear and sometimes behaves like a fixed charge. Therefore, the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states are sometimes unstable.

[0431] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in the oxide semiconductor refer to elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity.

[0432] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. By using an oxide semiconductor with a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0433] For example, in Si transistors, as the miniaturization of the transistors progresses, the short channel effect (Short Channel Effect: also referred to as SCE) appears. Therefore, it is difficult to miniaturize Si transistors. One of the reasons for the appearance of the short channel effect can be cited as the relatively small band gap of silicon. On the other hand, in OS transistors, an oxide semiconductor with a large band gap is used as the semiconductor material, so the short channel effect can be suppressed. In other words, OS transistors are transistors without or with very little short channel effect.

[0434] The short-channel effect refers to the degradation of electrical characteristics that occurs as transistors are miniaturized (reduction of channel length). Specific examples of the short-channel effect include a decrease in the threshold voltage, an increase in the subthreshold swing value (sometimes denoted as the S value), and an increase in the leakage current. Here, the S value refers to the change in the gate voltage in the subthreshold region when the drain current value changes by one order of magnitude with a fixed drain voltage.

[0435] As an index of the tolerance to the short-channel effect, the characteristic length is widely used. The characteristic length is an index of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist the short-channel effect is high.

[0436] OS transistors are accumulation-mode transistors, and Si transistors are inversion-mode transistors. Therefore, compared with Si transistors, the characteristic lengths between the source region and the channel formation region and between the drain region and the channel formation region in OS transistors are smaller. Therefore, the ability of OS transistors to resist the short-channel effect is higher than that of Si transistors. That is to say, when wanting to fabricate transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0437] Even when the carrier concentration of the oxide semiconductor is reduced to the extent that the channel formation region is i-type or substantially i-type, in short-channel transistors, due to the Conduction-Band-Lowering (CBL) effect, the conduction band bottom of the channel formation region also becomes lower. Therefore, the energy difference between the conduction band bottoms of the source region or the drain region and the channel formation region may be reduced to more than 0.1 eV and less than 0.2 eV. Thus, OS transistors can be regarded as having an n + / n - / n + accumulation-mode junction-less transistor structure or an n + / n - / n + accumulation-mode non-junction transistor structure, where the channel formation region is an n - -type region, and the source region and the drain region are n + -type regions.

[0438] When the above structure is adopted as an OS transistor, good electrical characteristics can be achieved even when the semiconductor device is miniaturized or highly integrated. For example, even when the channel length or gate length of the OS transistor is 1 nm or more and 20 nm or less, 3 nm or more and 15 nm or less, 5 nm or more and 10 nm or less, 5 nm or more and 7 nm or less, or 5 nm or more and 6 nm or less, good electrical characteristics can be obtained. On the other hand, in a Si transistor, it is sometimes difficult to have a gate length of 20 nm or less or 15 nm or less because of the short-channel effect. Therefore, compared with a Si transistor, an OS transistor is more suitable for use as a transistor with a small channel length. Note that the gate length refers to the length of the gate electrode in the direction in which carriers migrate in the channel formation region during transistor operation.

[0439] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cut-off frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cut-off frequency of the transistor can be 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more.

[0440] As described above, the OS transistor has excellent effects compared with the Si transistor, such as a small off-state current and the ability to fabricate a transistor with a small channel length.

[0441] [Impurities in Metal Oxide] Here, the effects of various impurities in the metal oxide (oxide semiconductor) are described.

[0442] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 3×10 19 atoms / cm 3 or less, further preferably 1×10 19 atoms / cm 3 or less, still preferably 3×10 18 atoms / cm 3 or less, even more preferably 1×10 18 atoms / cm 3 or less. In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3Hereinafter, preferably 5×10 19 atoms / cm 3 Hereinafter, more preferably 3×10 19 atoms / cm 3 Hereinafter, further preferably 1×10 19 atoms / cm 3 Hereinafter, still preferably 3×10 18 atoms / cm 3 Hereinafter, even more preferably 1×10 18 atoms / cm 3 Hereinafter.

[0443] When the oxide semiconductor contains nitrogen, electrons are generated as carriers, increasing the carrier concentration and making it easy to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen in the semiconductor layer tends to have a normally-on characteristic. Or, when the oxide semiconductor contains nitrogen, trap states may be formed. As a result, the electrical characteristics of the transistor may sometimes be unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Hereinafter, preferably 5×10 19 atoms / cm 3 Hereinafter, more preferably 1×10 19 atoms / cm 3 Hereinafter, further preferably 5×10 18 atoms / cm 3 Hereinafter, still further preferably 1×10 18 atoms / cm 3 Hereinafter, even more preferably 5×10 17 atoms / cm 3 Hereinafter.

[0444] Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, so oxygen vacancies may sometimes be formed. When hydrogen enters the oxygen vacancies, electrons may sometimes be generated as carriers. In addition, sometimes electrons are generated as carriers because a part of hydrogen bonds with oxygen bonded to metal atoms. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Thus, it is preferable to minimize hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration measured by SIMS is set to be less than 1×10 20 atoms / cm 3 and preferably less than 5×10 19 atoms / cm 3 and more preferably less than 1×1019 atoms / cm 3 , and more preferably less than 5×10 18 atoms / cm 3 , and still more preferably less than 1×10 18 atoms / cm 3 .

[0445] In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are sometimes formed to form carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal easily has a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0446] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of the transistor, the transistor can have stable electrical characteristics.

[0447] [Other semiconductor materials] The semiconductor layer 113 can be alternatively referred to as a semiconductor layer including the channel formation region of the transistor. The semiconductor materials that can be used for the semiconductor layer are not limited to the above metal oxides. As the semiconductor layer, a semiconductor material having a bandgap (a semiconductor material that is not a zero-bandgap semiconductor) can also be used. For example, it is preferable to use a single-element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) as the semiconductor material.

[0448] Here, in this specification, etc., the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by a bond weaker than covalent bonds and ionic bonds such as van der Waals forces. The layered material has high conductivity in the unit layer, that is, has high two-dimensional conductivity. By using a material that is used as a semiconductor and has high two-dimensional conductivity for the channel formation region, a transistor with a large on-state current can be provided.

[0449] Examples of the single-element semiconductor that can be used for the semiconductor material include silicon and germanium. Examples of the silicon that can be used for the semiconductor layer include single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon).

[0450] As compound semiconductors that can be used for semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, boron arsenide, etc. can be cited. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably includes crystals having a cubic crystal structure.

[0451] As layered materials, for example, graphene, silicene, boron carbonitride, chalcogenides, etc. can be cited. In boron carbonitride as a layered material, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. In addition, chalcogen elements are the general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited.

[0452] As the semiconductor layer, for example, transition metal chalcogenides used as semiconductors are preferably used. Specifically, as transition metal chalcogenides that can be used for the semiconductor layer, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited. By using the above transition metal chalcogenides for the semiconductor layer, a semiconductor device with a large on-state current can be provided.

[0453] This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.

[0454] (Embodiment 2) In this embodiment, an example of a method for manufacturing a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0455] <Example of a method for manufacturing a semiconductor device> Next, as an example of a method for manufacturing a semiconductor device according to one aspect of the present invention, Figures 4A to 4C an example of a method for manufacturing the semiconductor device shown will be described.

[0456] Each of the drawings A shows a plan view. In addition, B in each drawing is a cross-sectional view showing a part along the dotted line A1 - A2 in each drawing A. In addition, each drawing C is a cross-sectional view of a part along the dotted line A3 - A4 in each drawing A. For clarity, some constituent elements are omitted in the plan views of each drawing A.

[0457] Hereinafter, a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method can be appropriately used to deposit an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor.

[0458] Note that as the sputtering method, an RF sputtering method using a high-frequency power source for the sputtering power source, a DC sputtering method using a DC power source, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner can be cited. The RF sputtering method is mainly used when depositing an insulating film, and the DC sputtering method is mainly used when depositing a metal conductive film. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, or carbides by a reactive sputtering method.

[0459] The CVD method can be classified into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be classified into a metal CVD (MCVD: Metal CVD) method and a metalorganic CVD (MOCVD: MetalOrganic CVD) method according to the source gas used.

[0460] By using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since the thermal CVD method does not use plasma, the object to be processed is not damaged by the plasma. For example, wirings, electrodes, and elements (such as transistors and capacitors) included in a semiconductor device sometimes generate charge accumulation due to receiving charges from the plasma. At this time, the wirings, electrodes, or elements included in the semiconductor device may be damaged due to the accumulated charges. On the other hand, since the above-mentioned plasma damage does not occur in the thermal CVD method that does not use plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage does not occur during deposition, so a film with fewer defects can be obtained.

[0461] As the ALD method, a thermal ALD method that uses only heat energy to react a precursor and a reactant, a PEALD method that uses a reactant excited by plasma, etc. are adopted.

[0462] The CVD method and the ALD method are different from the sputtering method in which particles released from a target are deposited. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, since the ALD method has high step coverage and thickness uniformity, the ALD method is suitable, for example, for covering the surface of an opening with a high aspect ratio. However, since the deposition rate of the ALD method is relatively slow, it is sometimes preferably used in combination with other deposition methods such as the CVD method with a high deposition rate.

[0463] In addition, when using the CVD method, a film with any composition can be deposited according to the flow rate ratio of the source gases. For example, when using the CVD method, a film with a continuously changing composition can be deposited by changing the flow rate ratio of the source gases while performing the deposition. When depositing while changing the flow rate ratio of the source gases, since there is no need for the time required for transferring and adjusting the pressure, the deposition time can be shortened compared to the case of depositing using multiple deposition chambers. Therefore, sometimes the productivity of the semiconductor device can be improved.

[0464] When using the ALD method, a film with any composition can be deposited by simultaneously introducing different types of precursors. Alternatively, when introducing different types of precursors, a film with any composition can be deposited by controlling the number of cycles of each precursor.

[0465] First, a substrate (not shown) is prepared, and an insulating layer 101 ( Figures 34A to 34C ) is formed on the substrate. The insulating layer 101 can appropriately use the above-mentioned insulating materials. The insulating layer 101 can be appropriately formed by deposition methods such as sputtering, CVD, MBE, PLD, or ALD.

[0466] Next, a conductive layer 111c ( Figures 34A to 34C ) is formed on the insulating layer 101. For example, the conductive layer 111c can be formed by forming a conductive film that becomes the conductive layer 111c and processing the conductive film. The conductive film that becomes the conductive layer 111c can appropriately use the conductive materials that can be used for the above-mentioned conductive layer 111.

[0467] The formation of the conductive film that becomes the conductive layer 111c can be appropriately performed by deposition methods such as sputtering, CVD, MBE, PLD, or ALD. For example, as the conductive film that becomes the conductive layer 111c, a laminated film formed by sequentially depositing tungsten and titanium nitride can be formed using the CVD method. After forming the conductive film that becomes the conductive layer 111c, for example, a pattern can be formed by photolithography and the above-mentioned conductive film can be processed according to the pattern using dry etching or wet etching methods to form the conductive layer 111c. Here, since fine processing can be performed by processing the conductive film using the dry etching method, it is preferred.

[0468] Note that in photolithography, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Thus, a pattern is formed.

[0469] For example, a resist mask can be formed by exposing a resist using a KrF excimer laser, an ArF excimer laser, EUV light, etc. In addition, a liquid immersion technique in which exposure is performed in a state where a liquid (e.g., water) is filled between a substrate and a projection lens can also be used. In addition, an electron beam or an ion beam can be used instead of the above-mentioned light. Note that when using an electron beam or an ion beam, a mask is not required. In addition, the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after performing a dry etching process, or performing a dry etching process after performing a wet etching process.

[0470] Next, an etching process is performed through this resist mask. Thereby, a conductive layer, a semiconductor layer, an insulating layer, etc. can be processed into a desired shape.

[0471] When performing a dry etching process as the above-mentioned etching process, an etching gas containing a halogen can be used. Specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. As the etching gas, for example, a mixed gas of one or more of C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, NF3 gas, CHF3 gas, Cl2 gas, BCl3 gas, SiCl4 gas, CCl4 gas, and BBr3 gas, etc. can be used. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas, etc. can be appropriately added to the above-mentioned etching gas. The etching conditions can be appropriately set according to the object to be etched.

[0472] As a dry etching apparatus, for example, a capacitively coupled plasma (CCP) etching apparatus including parallel plate electrodes can be used. A capacitively coupled plasma etching apparatus including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Or, a structure in which different multiple high-frequency voltages are applied to one of the parallel plate electrodes can also be adopted. Or, a structure in which high-frequency voltages having the same frequency are applied to each of the parallel plate electrodes can also be adopted. Or, a structure in which high-frequency voltages having different frequencies are applied to each of the parallel plate electrodes can also be adopted. Or, a dry etching apparatus having a high-density plasma source can be used. For example, as a dry etching apparatus having a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus, etc. can be used.

[0473] Next, an insulating layer 103c_1 serving as an interlayer insulating layer is formed on the insulating layer 101 and on the conductive layer 111c ( Figures 35A to 35C)。The insulating layer 103c_1 can appropriately use the above-mentioned insulating materials. The insulating layer 103c_1 can be appropriately formed by deposition methods such as sputtering method, CVD method, MBE method, PLD method, or ALD method. For example, as the insulating layer 103c_1, a silicon oxide film is deposited by sputtering method. In addition, the insulating layer 103c_1 is preferably subjected to chemical mechanical polishing (CMP: Chemical Mechanical Polishing) treatment after deposition to flatten its top surface. By performing the flattening treatment of the insulating layer 103c_1, a conductive layer 115c used as a wiring can be smoothly formed in subsequent processes. In addition, for example, after depositing aluminum oxide on the insulating layer 103c_1 by sputtering method until the insulating layer 103c_1 is exposed, CMP treatment can be performed. By performing this CMP treatment, the surface of the insulating layer 103c_1 can be flattened and smoothed. By disposing this aluminum oxide on the insulating layer 103c_1 and performing CMP treatment, the end point of the CMP treatment can be easily detected.

[0474] In addition, sometimes CMP treatment is not required. At this time, the top surface of the insulating layer 103c_1 has a convex curved surface shape. By not performing the flattening treatment, the manufacturing cost can be reduced and the yield can be improved.

[0475] Next, a conductive layer 115c is formed on the insulating layer 103c_1( Figures 36A to 36C )。For example, a conductive film that becomes the conductive layer 115c can be formed and the conductive film can be processed to form the conductive layer 115c. The conductive film that becomes the conductive layer 115c can appropriately use the conductive materials that can be used for the above-mentioned conductive layer 115. The formation of the conductive film that becomes the conductive layer 115c can be appropriately performed by deposition methods such as sputtering method, CVD method, MBE method, PLD method, or ALD method.

[0476] After forming the conductive film that becomes the conductive layer 115c, for example, a pattern can be formed by photolithography and the above-mentioned conductive film can be processed according to the pattern by dry etching method or wet etching method, etc. to form the conductive layer 115c. Here, since fine processing can be performed by processing the conductive film by dry etching method, it is preferred.

[0477] Next, an insulating layer 103c_2 used as an interlayer insulating layer is formed on the insulating layer 103c_1 and the conductive layer 115c( Figures 37A to 37C )。The insulating layer 103c_2 can be formed using the same materials and formation methods as the above-mentioned insulating layer 103c_1. In addition, the insulating layer 103c_2 is preferably subjected to CMP treatment after deposition to flatten its top surface.

[0478] Here, since the total thickness of the insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2 corresponds to the channel length of the transistor 43, the thicknesses of the insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2 can be appropriately set according to the design value of the channel length of the transistor 43.

[0479] Next, a part of the insulating layer 103c_2, a part of the conductive layer 115c, and a part of the insulating layer 103c_1 are processed to form an opening 121c reaching the conductive layer 111c ( Figures 38A to 38C ). The formation of the opening 121c can be performed, for example, by a photolithography method and an etching method.

[0480] Here, it is preferable that the side wall of the opening 121c is perpendicular to the top surface of the conductive layer 111c. By adopting this structure, miniaturization or high integration of the semiconductor device can be achieved. In addition, the side wall of the opening 121c may have a tapered shape. By making the side wall of the opening 121c have a tapered shape, for example, the coverage of a metal oxide film or the like that becomes the semiconductor layer 113c described later can be improved, and thus defects such as voids can be reduced.

[0481] The maximum width of the opening 121c (when viewed from the plane, the diameter when the opening 121c is circular) is preferably small. For example, the maximum width of the opening 121c is preferably 1 nm or more and 60 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 40 nm or less, 1 nm or more and 30 nm or less, 1 nm or more and 20 nm or less, or 5 nm or more and 20 nm or less.

[0482] Since the aspect ratio of the opening 121c is high, it is preferable to process a part of the insulating layer 103c_2, a part of the conductive layer 115c, and a part of the insulating layer 103c_1 by anisotropic etching. In particular, processing by a dry etching method is suitable for microfabrication and is therefore preferable. In addition, this processing can be performed under different conditions. Note that, depending on the processing conditions of a part of the insulating layer 103c_2, a part of the conductive layer 115c, and a part of the insulating layer 103c_1, the inclination of the side surface of the insulating layer 103c_2 in the opening 121c, the inclination of the side surface of the conductive layer 115c in the opening 121c, and the inclination of the side surface of the insulating layer 103c_1 in the opening 121c may be different from each other.

[0483] Next, heat treatment can also be performed. The heat treatment is carried out at 250°C or higher and 650°C or lower, preferably at 300°C or higher and 500°C or lower, and more preferably at 320°C or higher and 450°C or lower. In addition, the heat treatment is carried out, for example, in a nitrogen gas or inert gas atmosphere. The heat treatment can also be carried out under reduced pressure. By performing the above heat treatment, impurities such as water in the insulating layer 103c_1 and the insulating layer 103c_2 can be reduced before depositing the metal oxide film that will become the semiconductor layer 113c later.

[0484] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the moisture content of the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for the heat treatment, for example, it is possible to prevent moisture from being absorbed by the insulating layer 103c_1 and the insulating layer 103c_2 as much as possible.

[0485] Next, an insulating film 105C that will later become the insulating layer 105c is formed in contact with the top surface of the insulating layer 103c_2, the side surface of the insulating layer 103c_2, the side surface of the conductive layer 115c, the side surface of the insulating layer 103c_1, and the top surface of the conductive layer 111c ( Figures 39A to 39C ). The insulating film 105C can appropriately use the above insulating materials. The insulating film 105C can be appropriately formed by deposition methods such as sputtering, CVD, MBE, PLD, or ALD. Here, the insulating film 105C is preferably formed in contact with the bottom and side walls of the opening 121c having a large aspect ratio. Therefore, the insulating film 105C is preferably deposited by a deposition method with good coverage, and more preferably by CVD or ALD. For example, as the insulating film 105C, silicon oxide is deposited by ALD.

[0486] Note that when the side wall of the opening 121c is conical, the deposition method of the insulating film 105C is not limited to CVD or ALD. For example, sputtering can also be used.

[0487] Next, the insulating film 105C is processed to expose the top surface of the insulating layer 103c_2 and the top surface of the conductive layer 111c to form an insulating layer 105c in contact with the side surface of the insulating layer 103c_1, the side surface of the conductive layer 115c, and the side surface of the insulating layer 103c_2 ( Figures 40A to 40C ). The upper end portion of the insulating layer 105c has a curved shape.

[0488] The processing of the insulating film 105C is preferably performed using anisotropic etching. By processing the insulating film 105C using anisotropic etching, it is possible to selectively remove only the region of the insulating film 105C in the opening 121c with a large aspect ratio that contacts the bottom of the opening 121c. Thereby, an insulating layer 105c that contacts the sidewalls in the opening 121c can be formed with high precision.

[0489] Next, a metal oxide film 113C that will later become the semiconductor layer 113c is formed so as to contact the top surface of the conductive layer 111c, the side surface of the insulating layer 105c, the bent portion of the insulating layer 105c, and the top surface of the insulating layer 103c_2 ( Figures 41A to 41C ). The metal oxide film 113C can be appropriately a metal oxide that can be used for the above-mentioned semiconductor layer 113. The metal oxide film 113C can be appropriately formed using a deposition method such as sputtering, CVD method, MBE method, PLD method, or ALD method. Here, the metal oxide film 113C is preferably formed so as to contact the side surface of the insulating layer 105c and the top surface of the conductive layer 111c in the opening 121c with a large aspect ratio. Therefore, it is preferable to form the metal oxide film 113C using a deposition method with good coverage, and more preferably using the CVD method or ALD method, etc. For example, In-Ga-Zn oxide is deposited as the metal oxide film 113C using the ALD method. Alternatively, In-Al-Zn oxide can also be deposited as the metal oxide film 113C.

[0490] Note that when the sidewalls of the opening 121c are in a tapered shape, the deposition method of the metal oxide film 113C is not limited to the CVD method or ALD method. For example, the sputtering method can also be used.

[0491] In addition, when the semiconductor layer 113c has a stacked structure, the deposition methods of the respective layers in the semiconductor layer 113c can be the same or different. For example, when the semiconductor layer 113c has a two-layer stacked structure, the lower layer of the metal oxide film 113C can be deposited using the sputtering method and the upper layer of the metal oxide film 113C can be deposited using the ALD method. The metal oxide film deposited using the sputtering method easily has crystallinity. Then, by providing a metal oxide film with crystallinity as the lower layer of the metal oxide film 113C, the crystallinity of the upper layer of the metal oxide film 113C can be improved. In addition, even if pinholes or disconnections are formed in the lower layer of the metal oxide film 113C deposited using the sputtering method, the upper layer of the metal oxide film 113C deposited using the ALD method with good coverage can be used for filling.

[0492] Here, the metal oxide film 113C is preferably formed in contact with the top surface of the conductive layer 111a in the opening 121c, the side surface of the insulating layer 105c in the opening 121c, the bent portion of the insulating layer 105c, and the top surface of the insulating layer 103c_2. By forming the metal oxide film in contact with the conductive layer 111c, the conductive layer 111c can be used as one of the source electrode and the drain electrode of the transistor 43.

[0493] Next, a heat treatment is preferably performed. The heat treatment may be performed within a temperature range that does not cause the metal oxide film 113C to polycrystallize, and may be performed at 250°C or higher and 650°C or lower, preferably 400°C or higher and 600°C or lower. Details of the heat treatment can be referred to the above description.

[0494] Here, it is preferable to perform the above heat treatment on the metal oxide film 113C in a state of being in contact with the insulating layer 103c_2 containing excess oxygen. By performing the heat treatment in this way, oxygen can be supplied from the insulating layer 103c_2 to the metal oxide film 113C, thereby reducing oxygen defects and VoH in the semiconductor layer 113c formed later.

[0495] Note that although the heat treatment is performed after depositing the metal oxide film 113C in the above description...

Claims

1. A semiconductor device, comprising: a first transistor, a second transistor, a third transistor, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring, wherein source and drain electrodes of the first transistor, the second transistor, and the third transistor are disposed at different heights with respect to a substrate surface, the second transistor is disposed on the first transistor so as to overlap the first transistor, the third transistor is disposed on the second transistor so as to overlap the second transistor, a gate of the first transistor is electrically connected to the first wiring, one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, the other of the source and the drain of the first transistor is electrically connected to the second wiring, one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, the other of the source and the drain of the second transistor is electrically connected to the third wiring, a gate of the third transistor is electrically connected to the fourth wiring, and the other of the source and the drain of the third transistor is electrically connected to the fifth wiring.

2. The semiconductor device according to claim 1, wherein at least one of the first transistor, the second transistor, and the third transistor contains a metal oxide.

3. The semiconductor device according to claim 1 or 2, further comprising: a node electrically connecting one of a source and a drain of the first transistor to a gate of the second transistor, wherein the first transistor has a function of writing data corresponding to a potential provided by the second wiring into the node when a first potential is provided from the first wiring, and has a function of holding the data in the node when a second potential is provided from the first wiring, the second transistor and the third transistor have a function of reading the data held in the node when a third potential is provided to the third wiring, a fourth potential is provided to the fifth wiring, and a fifth potential is provided to the fourth wiring, the first potential is a potential at which the first transistor becomes in an on state, the second potential is a potential at which the first transistor becomes in an off state, the fourth potential is a potential higher than the third potential, and the fifth potential is a potential at which the third transistor becomes in an on state.

4. A semiconductor device, comprising: a first transistor, a second transistor, a third transistor, a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring, wherein source and drain electrodes of the first transistor, the second transistor, and the third transistor are disposed at different heights with respect to a substrate surface, the second transistor is disposed on the first transistor so as to overlap the first transistor, the third transistor is disposed on the second transistor so as to overlap the second transistor, the first transistor is disposed such that a gate surrounds a semiconductor layer when viewed in a plane, the second transistor is disposed such that a semiconductor layer surrounds a gate when viewed in a plane, The third transistor is arranged such that the semiconductor layer surrounds the gate when viewed from the plane. The gate of the first transistor is electrically connected to the first wiring. One of the source and drain of the first transistor is electrically connected to the gate of the second transistor. The other of the source and drain of the first transistor is electrically connected to the second wiring. One of the source and drain of the second transistor is electrically connected to one of the source and drain of the third transistor. The other of the source and drain of the second transistor is electrically connected to the third wiring. The gate of the third transistor is electrically connected to the fourth wiring. And the other of the source and drain of the third transistor is electrically connected to the fifth wiring.

5. The semiconductor device according to claim 4, wherein the semiconductor layer in at least one of the first transistor, the second transistor, and the third transistor contains a metal oxide.

6. The semiconductor device according to claim 4 or 5, further comprising: a node electrically connecting one of the source and drain of the first transistor to the gate of the second transistor, wherein the first transistor has a function of writing data corresponding to the potential provided by the second wiring to the node when a first potential is provided from the first wiring, and has a function of holding the data at the node when a second potential is provided from the first wiring, the second transistor and the third transistor have a function of reading the data held at the node when a third potential is provided to the third wiring, a fourth potential is provided to the fifth wiring, and a fifth potential is provided to the fourth wiring, the first potential is a potential at which the first transistor becomes in an on state, the second potential is a potential at which the first transistor becomes in an off state, the fourth potential is a potential higher than the third potential, and the fifth potential is a potential at which the third transistor becomes in an on state.

7. A semiconductor device, comprising: a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, wherein the first transistor, the second transistor, and the third transistor are stacked in this order, the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fifth insulating layer, and a first semiconductor layer, the first insulating layer, the third conductive layer, and the second insulating layer are sequentially stacked on the first conductive layer, a first opening reaching the first conductive layer is provided in the first insulating layer, the third conductive layer, and the second insulating layer, the fifth insulating layer is arranged to contact the sidewall of the first opening, the first semiconductor layer is arranged to contact the top surface of the first conductive layer in the first opening, the side surface of the fifth insulating layer in the first opening, and the top surface of the second insulating layer, the second conductive layer is arranged to contact the top surface of the first semiconductor layer and have a region overlapping with the first conductive layer, the second transistor includes the second conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth insulating layer, and a second semiconductor layer, The third insulating layer and the fourth conductive layer are sequentially stacked on the second conductive layer, a second opening reaching the second conductive layer is provided in the third insulating layer and the fourth conductive layer, the second semiconductor layer is disposed in contact with the top surface of the second conductive layer in the second opening, the side surface of the third insulating layer in the second opening, the side surface of the fourth conductive layer in the second opening, and the top surface of the fourth conductive layer, the sixth insulating layer is disposed in contact with the top surface of the second semiconductor layer, the side surface of the second semiconductor layer, the top surface of the fourth conductive layer, the side surface of the fourth conductive layer, and the top surface of the third insulating layer, the fifth conductive layer is disposed on the sixth insulating layer in contact therewith and filling the second opening, the third transistor includes a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a seventh insulating layer, and a third semiconductor layer, the sixth conductive layer is disposed in contact with the top surface of the fifth conductive layer, the fourth insulating layer and the seventh conductive layer are sequentially stacked on the sixth conductive layer, a third opening reaching the sixth conductive layer is provided in the fourth insulating layer and the seventh conductive layer, the third semiconductor layer is disposed in contact with the top surface of the sixth conductive layer in the third opening, the side surface of the fourth insulating layer in the third opening, the side surface of the seventh conductive layer in the third opening, and the top surface of the seventh conductive layer, the seventh insulating layer is disposed in contact with the top surface of the third semiconductor layer, the side surface of the third semiconductor layer, the top surface of the seventh conductive layer, the side surface of the seventh conductive layer, and the top surface of the fourth insulating layer, and the eighth conductive layer is disposed on the seventh insulating layer in contact therewith and filling the third opening.

8. The semiconductor device according to claim 7, wherein at least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer contains a metal oxide.

9. The semiconductor device according to claim 7 or 8, wherein the second conductive layer includes a ninth conductive layer and a tenth conductive layer, the ninth conductive layer is disposed in contact with the top surface of the first semiconductor layer and having a region overlapping with the first conductive layer, the tenth conductive layer is disposed in contact with the top surface of the ninth conductive layer and having a region overlapping with the first conductive layer, and the second semiconductor layer is disposed in contact with the top surface of the tenth conductive layer.

10. The semiconductor device according to claim 7 or 8, wherein the second conductive layer includes a ninth conductive layer, a tenth conductive layer, and an eleventh conductive layer, the ninth conductive layer is disposed in contact with the top surface of the first semiconductor layer and having a region overlapping with the first conductive layer, the tenth conductive layer is disposed in contact with the top surface of the ninth conductive layer, the eleventh conductive layer is disposed in contact with the top surface of the tenth conductive layer and having a region overlapping with the first conductive layer, And the second semiconductor layer is disposed in contact with the top surface of the eleventh conductive layer.

11. The semiconductor device according to claim 7 or 8, wherein there is a capacitor between the first transistor and the second transistor, the first transistor, the second transistor, the capacitor, and the third transistor are stacked in this order, the capacitor includes a ninth conductive layer, a tenth conductive layer, and an eighth insulating layer, the eighth insulating layer has a region in contact with the side surface of the ninth conductive layer, the tenth conductive layer covers at least a part of the side surface of the ninth conductive layer with the eighth insulating layer therebetween, the ninth conductive layer is disposed in contact with the top surface of the fifth conductive layer, and the sixth conductive layer is disposed in contact with the top surface of the ninth conductive layer.

12. A semiconductor device, comprising: a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, wherein the first transistor, the second transistor, and the third transistor are stacked in this order, the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fifth insulating layer, and a first semiconductor layer, the first insulating layer, the third conductive layer, and the second insulating layer are stacked in sequence on the first conductive layer, a first opening reaching the first conductive layer is provided in the first insulating layer, the third conductive layer, and the second insulating layer, the fifth insulating layer is disposed in contact with the side wall of the first opening, the first semiconductor layer is disposed in contact with the top surface of the first conductive layer in the first opening, the side surface of the fifth insulating layer in the first opening, and the top surface of the second insulating layer, the second conductive layer is disposed in contact with the top surface of the first semiconductor layer and has a region overlapping with the first conductive layer, the third conductive layer is disposed so as to surround the first semiconductor layer with the fifth insulating layer therebetween when viewed in plan, the second transistor includes the second conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth insulating layer, and a second semiconductor layer, the third insulating layer and the fourth conductive layer are stacked in sequence on the second conductive layer, a second opening reaching the second conductive layer is provided in the third insulating layer and the fourth conductive layer, the second semiconductor layer is disposed in contact with the top surface of the second conductive layer in the second opening, the side surface of the third insulating layer in the second opening, the side surface of the fourth conductive layer in the second opening, and the top surface of the fourth conductive layer and surrounds the fifth conductive layer with the sixth insulating layer therebetween when viewed in plan, the sixth insulating layer is disposed in contact with the top surface of the second semiconductor layer, the side surface of the second semiconductor layer, the top surface of the fourth conductive layer, the side surface of the fourth conductive layer, and the top surface of the third insulating layer, the fifth conductive layer is disposed on the sixth insulating layer in contact therewith and filling the second opening, the third transistor includes a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a seventh insulating layer, and a third semiconductor layer, The sixth conductive layer is disposed in contact with the top surface of the fifth conductive layer. The fourth insulating layer and the seventh conductive layer are sequentially stacked on the sixth conductive layer. A third opening reaching the sixth conductive layer is provided in the fourth insulating layer and the seventh conductive layer. The third semiconductor layer is disposed in contact with the top surface of the sixth conductive layer within the third opening, the side surface of the fourth insulating layer within the third opening, the side surface of the seventh conductive layer within the third opening, and the top surface of the seventh conductive layer, and is disposed so as to surround the eighth conductive layer with the seventh insulating layer therebetween when viewed in plan. The seventh insulating layer is disposed in contact with the top surface of the third semiconductor layer, the side surface of the third semiconductor layer, the top surface of the seventh conductive layer, the side surface of the seventh conductive layer, and the top surface of the fourth insulating layer. Moreover, the eighth conductive layer is disposed on the seventh insulating layer in contact therewith and filling the third opening.

13. The semiconductor device according to claim 12, wherein at least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer contains a metal oxide.

14. The semiconductor device according to claim 12 or 13, wherein the second conductive layer includes a ninth conductive layer and a tenth conductive layer. The ninth conductive layer is disposed in contact with the top surface of the first semiconductor layer and has a region overlapping with the first conductive layer. The tenth conductive layer is disposed in contact with the top surface of the ninth conductive layer and has a region overlapping with the first conductive layer. And the second semiconductor layer is disposed in contact with the top surface of the tenth conductive layer.

15. The semiconductor device according to claim 12 or 13, wherein the second conductive layer includes a ninth conductive layer, a tenth conductive layer, and an eleventh conductive layer. The ninth conductive layer is disposed in contact with the top surface of the first semiconductor layer and has a region overlapping with the first conductive layer. The tenth conductive layer is disposed in contact with the top surface of the ninth conductive layer. The eleventh conductive layer is disposed in contact with the top surface of the tenth conductive layer and has a region overlapping with the first conductive layer. And the second semiconductor layer is disposed in contact with the top surface of the eleventh conductive layer.

16. The semiconductor device according to claim 12 or 13, wherein there is a capacitor between the first transistor and the second transistor. The first transistor, the second transistor, the capacitor, and the third transistor are stacked in this order. The capacitor includes a ninth conductive layer, a tenth conductive layer, and an eighth insulating layer. The eighth insulating layer has a region in contact with the side surface of the ninth conductive layer. The tenth conductive layer covers at least a part of the side surface of the ninth conductive layer with the eighth insulating layer therebetween. The ninth conductive layer is disposed in contact with the top surface of the fifth conductive layer. And the sixth conductive layer is disposed in contact with the top surface of the ninth conductive layer.

17. A method for manufacturing a semiconductor device, comprising the following steps: Forming a first conductive layer; Form a first insulating layer on the first conductive layer; Form a second conductive layer on the first insulating layer; Form a second insulating layer on the first insulating layer and on the second conductive layer; Process the second conductive layer and the second insulating layer to form a first opening reaching the first conductive layer, Form a first insulating film that contacts the top surface of the first conductive layer within the first opening, the side surfaces of the first insulating layer within the first opening, the side surfaces of the second conductive layer within the first opening, the side surfaces of the second insulating layer within the first opening, and the top surface of the second insulating layer; Process the first insulating film to expose the top surface of the first conductive layer within the first opening and the top surface of the second insulating layer, and form a third insulating layer that contacts the side surfaces of the first insulating layer within the first opening, the side surfaces of the second conductive layer within the first opening, and the side surfaces of the second insulating layer within the first opening; Form a first metal oxide film that contacts the top surface of the first conductive layer, the side surfaces of the third insulating layer, the top surface of the third insulating layer, and the top surface of the second insulating layer; Process the first metal oxide film to form a first semiconductor layer having a region overlapping with the first opening; Form a third conductive layer that contacts the top surface of the first semiconductor layer; Form a fourth insulating layer on the third conductive layer and on the second insulating layer; Form a first conductive film on the fourth insulating layer; Process the first conductive film and the fourth insulating layer to form a second opening reaching the third conductive layer; Form a second metal oxide film that contacts the top surface of the third conductive layer within the second opening, the side surfaces of the fourth insulating layer within the second opening, the side surfaces of the first conductive film within the second opening, and the top surface of the first conductive film; Process the second metal oxide film to form a second semiconductor layer having a region overlapping with the second opening; Process the first conductive film to form a fourth conductive layer having a region overlapping with the third conductive layer; Form a fifth insulating layer on the second semiconductor layer, on the fourth conductive layer, and on the fourth insulating layer; Form a second conductive film on the fifth insulating layer; Process the second conductive film to form a fifth conductive layer having a region overlapping with the second semiconductor layer; Form a sixth insulating layer on the fifth conductive layer and on the fifth insulating layer; Process the top surface of the sixth insulating layer and the top surface of the fifth conductive layer so that their heights relative to the substrate surface are substantially the same; Form a sixth conductive layer that contacts the top surface of the fifth conductive layer; Form a seventh insulating layer on the fifth conductive layer and on the sixth insulating layer; Form a third conductive film on the seventh insulating layer; Process the third conductive film and the seventh insulating layer to form a third opening reaching the sixth conductive layer; Form a third metal oxide film that contacts the top surface of the sixth conductive layer within the third opening, the side surface of the seventh insulating layer within the third opening, the side surface of the third conductive film within the third opening, and the top surface of the third conductive film; Process the third metal oxide film to form a third semiconductor layer having a region overlapping with the third opening; Process the third conductive film to form a seventh conductive layer having a region overlapping with the sixth conductive layer; Form an eighth insulating layer on the third semiconductor layer, on the seventh conductive layer, and on the seventh insulating layer; Form a fourth conductive film on the eighth insulating layer; Process the fourth conductive film to form an eighth conductive layer having a region overlapping with the third semiconductor layer.

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