Semiconductor device

Abstract

Provided is a semiconductor device that is easy to miniaturize. The semiconductor device includes a transistor, a first insulating layer and a second insulating layer. The transistor includes first to third conductive layers, a semiconductor layer, and a third insulating layer. The first insulating layer is over the first conductive layer and includes an opening to the first conductive layer. The semiconductor layer has a portion in contact with a top surface of the first conductive layer in the opening, a portion along a side surface of the first insulating layer in the opening, and a portion on the first insulating layer. The third insulating layer covers the semiconductor layer in the opening. The third conductive layer covers the third insulating layer in the opening. The second insulating layer covers the third conductive layer. The second conductive layer has a portion on the third conductive layer via the second insulating layer and a portion in contact with a portion of the semiconductor layer on the first insulating layer.

Description

Technical Field

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a storage device, a display device, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As examples of the technical field of one aspect of the present invention disclosed in this specification and the like, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices, input / output devices, driving methods of these devices, or manufacturing methods of these devices can be cited. A semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. Background Art

[0003] In recent years, semiconductor devices have been developed, and CPUs, memories, or LSIs other than these are mainly used in semiconductor devices. A CPU is an aggregate of semiconductor elements including a semiconductor integrated circuit formed by processing a semiconductor wafer to form a chip (including at least a transistor and a memory) and having electrodes as connection terminals formed thereon.

[0004] The semiconductor circuits (IC chips) of CPUs, memories, or LSIs other than these are mounted on a circuit board, for example, a printed wiring board, and are used as one of the components of various electronic devices.

[0005] In addition, a technique of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. This transistor is widely used in electronic devices such as integrated circuits and image display devices (simply referred to as display devices). As a semiconductor thin film that can be applied to a transistor, silicon-based semiconductor materials are widely known, and as other materials, oxide semiconductors have attracted attention.

[0006] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in the non-conducting state. For example, Patent Document 1 discloses a low-power CPU and the like that utilize the characteristic of a small leakage current. In addition, for example, Patent Document 2 discloses a storage device and the like that achieve long-term retention of stored contents.

[0007] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high density of integrated circuits has increased. In addition, it is required to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique in which a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film are stacked, and a plurality of storage units are overlapped to increase the density of the integrated circuit. In addition, Patent Document 4 discloses a vertical transistor in which a gate electrode covers the side surface of an oxide semiconductor with a gate insulator interposed therebetween. [Prior Art Documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Laid-Open No. 2013-211537 [Non-Patent Documents]

[0009] [Non-Patent Document 1] M.Oota et.al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech.Dig., 2019, pp.50-53 Summary of the Invention Technical Problem to be Solved by the Invention

[0010] One of the objects of one aspect of the present invention is to provide a semiconductor device that is easy to miniaturize. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device that can achieve high integration. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device that reduces parasitic capacitance. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device that reduces wiring load. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device with high reliability. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device having good electrical characteristics. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device with a high operating speed.

[0011] One of the objects of one aspect of the present invention is to provide a semiconductor device, a storage device, a display device, or an electronic device having a novel structure. One of the objects of one aspect of the present invention is to at least alleviate at least one of the problems of the prior art.

[0012] Note that the description of these objects does not preclude the existence of other objects. Note that one aspect of the present invention does not need to achieve all of the above objects. In addition, objects other than the above can be extracted from the descriptions of the specification, drawings, claims, etc. Means for Solving the Technical Problem

[0013] One aspect of the present invention is a semiconductor device including a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is located above the first conductive layer and includes an opening reaching the first conductive layer. The semiconductor layer has a portion in contact with the top surface of the first conductive layer in the opening, a portion along the side surface of the first insulating layer in the opening, and a portion located on the first insulating layer. The third insulating layer covers the semiconductor layer within the opening. The third conductive layer covers the third insulating layer within the opening. The second insulating layer covers the third conductive layer. The second conductive layer has a portion located above the third conductive layer with the second insulating layer therebetween and a portion in contact with the portion of the semiconductor layer located on the first insulating layer.

[0014] In addition, in the above, the second conductive layer preferably has a portion extending in a first direction. Further, the third conductive layer preferably has a portion extending in a second direction intersecting the first direction. At this time, the second conductive layer and the third conductive layer preferably intersect in a region overlapping the opening.

[0015] In addition, in the above, it preferably further includes a fourth insulating layer and a fifth insulating layer located inside the opening. Preferably, the fourth insulating layer is provided between the semiconductor layer and the first insulating layer and contains a material in which hydrogen is less likely to diffuse compared to the first insulating layer. Further, preferably, the fifth insulating layer is provided between the semiconductor layer and the fourth insulating layer and has a function of capturing or fixing hydrogen.

[0016] In addition, it preferably further includes a sixth insulating layer located inside the opening. At this time, preferably, the sixth insulating layer is provided between the semiconductor layer and the fifth insulating layer and contains an oxide.

[0017] In addition, in the above, the diameter of the opening is preferably larger than the height of the opening. In particular, the diameter of the opening is more preferably twice or more the height of the opening.

[0018] In addition, in the above, at least one of the first conductive layer and the second conductive layer preferably contains ruthenium. Advantages of the Invention

[0019] According to one aspect of the present invention, a semiconductor device that is easy to miniaturize can be provided. In addition, according to one aspect of the present invention, a semiconductor device capable of achieving high integration can be provided. In addition, according to one aspect of the present invention, a semiconductor device with reduced parasitic capacitance can be provided. In addition, according to one aspect of the present invention, a semiconductor device with reduced wiring load can be provided. In addition, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device with a high operating speed can be provided.

[0020] According to one aspect of the present invention, a semiconductor device, a storage device, a display device, or an electronic device having a novel structure can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be alleviated at least.

[0021] Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not need to have all of the above effects. In addition, effects other than the above can be extracted from the descriptions in the specification, the drawings, the claims, and the like. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A and Figure 1B are structural examples of a semiconductor device. FIG. 2A to FIG. 2C are structural examples of a semiconductor device. Figure 3A and Figure 3B are structural examples of a semiconductor device. 4A to 4D are structural examples of a semiconductor device. FIG. 5A to FIG. 5D are structural examples of a semiconductor device. FIG. 6A to FIG. 6D are structural examples of a semiconductor device. FIG. 7A to FIG. 7D are structural examples of a semiconductor device. FIG. 8A to FIG. 8D are structural examples of a semiconductor device. 9A to 9D are diagrams illustrating examples of manufacturing methods of a semiconductor device. FIG. 10A to FIG. 10C are diagrams illustrating examples of manufacturing methods of a semiconductor device. FIG. 11A to FIG. 11C are diagrams illustrating examples of manufacturing methods of a semiconductor device. FIG. 12A to FIG. 12C are diagrams illustrating examples of manufacturing methods of a semiconductor device. FIG. 13A to FIG. 13C are structural examples of a storage device. FIG. 14A to FIG. 14C are structural examples of a storage device. Fig.15A and Fig. 15B are structural examples of a storage device. Fig.16A and Fig. 16B are structural examples of a storage device. Fig.17A and Fig. 17B are structural examples of a storage device. Fig.18This is an example of the structure of a storage device. Fig.19 This is an example of the structure of a storage device. Fig. 20A And Fig. 20B This is an example of the structure of a storage device. FIG. 21A to FIG. 21D This is an example of the structure of a storage device. Fig. 22 This is an example of the structure of a storage device. Fig.23A And Fig. 23B This is an example of the structure of a display device. Fig.24 This is an example of the structure of a display device. Fig.25 This is an example of the structure of a display device. Fig.26 This is an example of the structure of a display device. FIG. 27A to FIG. 27C This is an example of the structure of a display device. Fig.28A And Fig.28B This is an example of the structure of a display device. FIG. 29A to FIG. 29D This is an example of the structure of an electronic device. FIG. 30A to FIG. 30F This is an example of the structure of an electronic device. FIG. 31A to FIG. 31G This is an example of the structure of an electronic device. Fig.32A And Fig.32B This is an example of the structure of an electronic component. FIG. 33A to FIG. 33C This is an example of the structure of a mainframe computer. Fig.34A This is an example of the structure of a space device. Fig.34B This is an example of the structure of a storage system. Modes for Carrying Out the Invention

[0023] Next, embodiments will be described with reference to the accompanying drawings. However, those of ordinary skill in the art can easily understand the fact that the embodiments can be implemented in many different forms, and the ways and details thereof can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following embodiments.

[0024] Note that in the structures of the invention described below, the same symbols are used in common between different drawings to denote the same parts or parts having the same functions, and repeated descriptions thereof are omitted. In addition, when denoting parts having the same functions, the same hatching is sometimes used without particularly attaching symbols.

[0025] Note that in the respective drawings described in this specification, sometimes for clarity, the sizes of the respective components, the thicknesses of the layers, or the regions are exaggerated. Therefore, the present invention is not limited to the dimensions in the drawings.

[0026] Note that ordinal numbers such as "first" and "second" used in this specification and the like are attached to avoid confusion of the components, and are not for limiting in terms of the number.

[0027] A transistor is a type of semiconductor device, and can perform functions such as amplifying current or voltage, and switching operations for controlling conduction or non - conduction. The transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin - film transistors (TFTs: Thin Film Transistors).

[0028] In addition, in cases where transistors with different polarities are used or the direction of the current in the circuit operation changes, etc., the functions of the "source electrode" and the "drain electrode" are sometimes swapped with each other. Therefore, in this specification, the "source electrode" and the "drain electrode" can be used interchangeably.

[0029] In addition, in this specification and the like, "electrically connected" includes cases where connection is made through "elements having a certain electrical function". Here, there is no particular limitation on the "elements having a certain electrical function" as long as they can transmit and receive electrical signals between the connection objects. For example, the "elements having a certain electrical function" include switching elements such as transistors, resistors, coils, capacitors, and other elements having various functions in addition to electrodes or wirings.

[0030] Note that in this specification and the like, the top - surface shape of a component refers to the contour shape of the component when viewed from a plane. In addition, viewing from a plane means viewing from the normal direction of the surface of the formation surface of the component or the support (e.g., a substrate) on which the component is formed.

[0031] Note that in this specification and the like, "substantially the same top - surface shape" means that at least a part of the contours of each layer in the stack overlap. For example, it includes cases where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern. However, strictly speaking, there are cases where the contours do not overlap and the upper layer is inside the lower layer or the upper layer is outside the lower layer, and such cases can sometimes be said to have "substantially the same top - surface shape".

[0032] Note that hereinafter, expressions of directions such as "up" and "down" are basically used according to the directions in the accompanying drawings. However, for the sake of simplicity, the directions indicated by "up" or "down" in the specification are sometimes inconsistent with those in the accompanying drawings. For example, when explaining the stacking order (or formation order) of a laminate or the like, even if the surface (formed surface, support surface, bonding surface, flat surface, etc.) on the side where the laminate is provided in the accompanying drawings is located on the upper side of the laminate, the direction may sometimes be described as "down" and the opposite direction may be described as "up", etc.

[0033] Note that in this specification and the like, the channel length direction of a transistor refers to one of the directions parallel to the straight line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of the current flowing through the semiconductor layer when the transistor is in the on state. In addition, the channel width direction refers to the direction orthogonal to the channel length direction. Note that depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be limited to one direction.

[0034] In addition, in this specification and the like, "film" and "layer" can be interchanged with each other. For example, sometimes "insulating layer" and "insulating film" can be interchanged with each other.

[0035] (Embodiment 1) In this embodiment, an example of the structure and a manufacturing method example of a semiconductor device of one aspect of the present invention will be described. Hereinafter, a transistor and a storage device using the transistor will be described as an example of the semiconductor device.

[0036] The source electrode and the drain electrode of a transistor of one aspect of the present invention are located at different heights (for example, the heights in the direction perpendicular to the substrate surface or the insulating plane on which the transistor is provided), so the current flowing through the semiconductor layer flows in the height direction. That is to say, the channel length direction has a component in the height direction (vertical direction), so a transistor of one aspect of the present invention can be called a vertical transistor, a vertical channel transistor, etc.

[0037] More specifically, a first insulating layer serving as a first spacer is provided so as to cover the lower electrode of one of the source electrode and the drain electrode of the transistor, and a semiconductor layer that contacts the top surface of the lower electrode and forms a channel along the side surface of the first insulating layer is provided inside the opening provided in the first insulating layer. Another part of the semiconductor layer is provided along the top surface of the first insulating layer outside the opening. In addition, a gate insulating layer is provided along the semiconductor layer inside the opening, and a gate electrode is provided so as to overlap the semiconductor layer with the gate insulating layer interposed therebetween. Furthermore, a second insulating layer serving as a second spacer is provided to cover the gate electrode, and an upper electrode of the other of the source electrode and the drain electrode is provided on the second insulating layer. The semiconductor layer contacts the upper electrode in a region not covered by the second insulating layer.

[0038] Both the gate electrode and the upper electrode can be used as wirings. At this time, in a region overlapping with an opening provided in the first insulating layer, the gate electrode and the upper electrode can cross each other through the second insulating layer. Thereby, the crossing portion of the two wirings can be arranged to overlap with the transistor, and compared with the case where they are arranged separately, the occupied area can be significantly reduced.

[0039] In addition, by using an insulating film having a thickness larger than that of the gate insulating layer as the second insulating layer between the gate electrode and the upper electrode, the parasitic capacitance generated between the gate electrode and the upper electrode can be reduced. Furthermore, as the second insulating layer, it is more preferable to use a material having a dielectric constant lower than that of the gate insulating layer.

[0040] It is preferable to use an oxide semiconductor for the semiconductor layer. For example, when using silicon, which is a typical semiconductor material, in order to form the source region and the drain region, it is necessary to dope impurities serving as donors or acceptors into this region. However, in the vertical transistor according to one embodiment of the present invention, since the heights of the source and drain are different and the channel formation region is in the longitudinal direction with respect to the substrate surface or the like, it is sometimes difficult to dope impurities into the semiconductor layer with high precision. On the other hand, even without doping the above-mentioned impurities, the oxide semiconductor can form a low-resistance region and can connect the source electrode and the drain electrode well. Therefore, a transistor having a three-dimensional structure according to one embodiment of the present invention can be manufactured with a high yield.

[0041] In the opening of the first insulating layer, the semiconductor layer can be provided in contact with the side surface of the first insulating layer. At this time, when using an oxide semiconductor for the semiconductor layer, it is preferable to use an oxide insulating film for the first insulating layer in contact with the semiconductor layer. At this time, in order to reduce the hydrogen concentration in the semiconductor layer, the lower the hydrogen concentration in the first insulating layer, the more preferable.

[0042] Alternatively, it may include a barrier layer having a function of preventing hydrogen diffusion between the first insulating layer and the semiconductor layer. And it is preferable to provide a layer having a function of capturing or fixing hydrogen between the barrier layer and the semiconductor layer. Thereby, hydrogen contained in the first insulating layer can be prevented from diffusing into the semiconductor layer, and the hydrogen concentration in the semiconductor layer can be reduced. Therefore, a highly reliable semiconductor device can be realized. Note that it may also have an insulating layer including an oxide insulating film provided between the semiconductor layer and the layer for capturing or fixing hydrogen, and a structure in which this insulating layer is in contact with the semiconductor layer may also be adopted.

[0043] Here, the channel length of the transistor can be precisely controlled according to the thickness of the first insulating layer serving as the first spacer, so the channel length non-uniformity can be significantly reduced compared with the planar transistor. Furthermore, by thinning the first insulating layer, transistors with an extremely short channel length can also be manufactured. For example, transistors with a channel length of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less and 5 nm or more, 7 nm or more, or 10 nm or more can be manufactured. Thus, transistors with an extremely small channel length that cannot be achieved by mass-production exposure apparatuses can be realized. In addition, transistors with a channel length of less than 10 nm can be realized without using the very expensive exposure apparatuses used in the state-of-the-art LSI technology.

[0044] Since the channel length can be controlled according to the thickness of the first insulating layer, it is preferable that the thickness of the first insulating layer is as small as possible. For example, when the diameter of the opening of the first insulating layer is denoted as D and the thickness of the first insulating layer is denoted as H, H is preferably smaller than D, and more preferably H is half or less of D. In addition, the thickness of H is preferably as small as possible, but the thickness of H is preferably larger than one or both of the semiconductor layer and the gate insulating layer, and more preferably larger than the sum of the thicknesses of the semiconductor layer and the gate insulating layer.

[0045] The transistor according to one embodiment of the present invention can have an extremely small channel length, reduce the occupied area, allow a large current to flow, reduce parasitic capacitance, and operate at high speed. The transistor according to one embodiment of the present invention can be applied to various semiconductor devices. For example, it can be applied to storage devices, arithmetic devices, display devices, imaging devices, etc.

[0046] Hereinafter, more specific examples will be described with reference to the drawings.

[0047] [Structural Example] Figure 1A 、 Figure 1B are perspective views of the transistor 10. In each drawing, the X direction, Y direction, and Z direction are indicated by arrows. Figure 1A is a perspective view including a cross section perpendicular to the Y direction, Figure 1B is a perspective view including a cross section perpendicular to the X direction.

[0048] Figure 2A is a plan view of the transistor 10, Figure 2B 、 Figure 2C are respectively schematic cross-sectional views along the Figure 2A cutting lines A1 - A2, B1 - B2. Note that some constituent elements (insulating layers, etc.) are omitted in Figure 2A .

[0049] The transistor 10 is disposed on an insulating layer 11, and the insulating layer 11 is disposed on a substrate (not shown). The transistor 10 includes a conductive layer 31 serving as one of a source electrode and a drain electrode, a semiconductor layer 21, an insulating layer 22 serving as a gate insulating layer, a conductive layer 23 serving as a gate electrode, and a conductive layer 32 serving as the other of the source electrode and the drain electrode. The conductive layer 23, the conductive layer 31, and the conductive layer 32 are all used as wirings.

[0050] The conductive layer 31 is disposed on the insulating layer 11, and an insulating layer 41a, an insulating layer 41b, and an insulating layer 41c (hereinafter, also collectively referred to as the insulating layer 41) are disposed on the conductive layer 31. The insulating layer 41 has an opening 20a reaching the conductive layer 31. The semiconductor layer 21 is disposed along the inner wall (also referred to as a side surface, a side wall) of the opening 20a of the insulating layer 41 and contacts the top surface of the conductive layer 31. The insulating layer 22 has a portion located inside the opening 20a and covers the semiconductor layer 21. The conductive layer 23 covers the insulating layer 22 inside the opening 20a. Here, an example is shown in which a part of the conductive layer 23 fills the opening 20a and another part extends in the Y direction and is used as a wiring. Further, the insulating layer 42 covers the top surface and the side surface of the conductive layer 23, and the conductive layer 32 is disposed on the insulating layer 42. The conductive layer 32 contacts the semiconductor layer 21 in a region not overlapping with the conductive layer 23, the insulating layer 22, and the insulating layer 42.

[0051] The conductive layer 31 is embedded in the insulating layer 44, and the top surfaces of the conductive layer 31 and the insulating layer 44 are planarized, so that the height of the top surface of the conductive layer 31 is substantially the same as that of the insulating layer 44. By adopting the above structure, the influence of the step can be eliminated or reduced, so it is preferable. The insulating layer 44 is used as an interlayer insulating layer. For example, an inorganic insulating material having a low dielectric constant such as silicon oxide or silicon oxynitride is preferably used.

[0052] The conductive layer 23 and the conductive layer 32 overlap each other with the insulating layer 42 therebetween. Here, the conductive layer 23 extends in the Y direction, the conductive layer 32 extends in the X direction, and the conductive layer 23 and the conductive layer 32 cross each other in a region overlapping with the opening 20a.

[0053] The source and drain electrodes of the transistor 10 having the above structure are located at different heights, so the current flowing through the semiconductor flows in the height direction. That is to say, the channel length direction can have a component in the height direction (vertical direction), so the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc. In the transistor 10, the source electrode, the semiconductor, and the drain electrode can be overlapped, so compared with the so-called planar transistor (which can also be called a lateral transistor, an LFET (Lateral FET), etc.) in which the semiconductor is arranged on a plane, the occupied area can be significantly reduced. In addition, the above vertical transistor can also be called a CFET (Columnar Field Effect Transistor) according to its shape.

[0054] In addition, the channel length of the transistor 10 can be precisely controlled according to the thickness of the insulating layer 41 used as a spacer, so the channel length non-uniformity can be significantly reduced compared with the planar transistor. Furthermore, by thinning the insulating layer 41, a transistor with an extremely short channel length can also be manufactured. For example, a transistor with a channel length of 50 nm or less, 30 nm or less, or 20 nm or less and 5 nm or more, 7 nm or more, or 10 nm or more can be manufactured. Therefore, even if an existing mass-production exposure device is used instead of the very expensive exposure device used in the most advanced LSI technology, a transistor with a channel length less than 10 nm can be realized.

[0055] The semiconductor layer 21 can use various semiconductor materials, and it is particularly preferable to use an oxide semiconductor including a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor with both a high on-state current and an extremely low off-state current can be realized at low cost. Hereinafter, without special emphasis, a preferred structural example of the case where an oxide semiconductor is used as the semiconductor layer 21 will be described.

[0056] The top surface of the conductive layer 31 is in contact with the semiconductor layer 21. Therefore, when an oxide semiconductor is used as the semiconductor layer 21, due to the influence of the deposition process of the semiconductor film that will become the semiconductor layer 21 or subsequent heating, etc., the exposed surface of the conductive layer 31 is oxidized and an insulating oxide film is formed between the conductive layer 31 and the semiconductor layer 21, so the contact resistance sometimes increases. Thus, at least the uppermost part of the conductive layer 31 preferably uses an oxide conductor containing a conductive oxide. Thereby, an increase in the contact resistance due to the surface oxidation of the conductive layer 31 can be prevented. The conductive layer 31 can also be called an oxide layer, a metal oxide layer, an oxide conductor layer, etc.

[0057] In addition, the conductive layer 32 is in contact with the top surface of the semiconductor layer 21. Therefore, since the conductive layer 32 is not affected by the heat generated during the formation process of the semiconductor layer 21, a conductive material such as metal can be used as the conductive layer 32. In addition, when heat treatment is performed in a state where the conductive layer 32 is in contact with the semiconductor layer 21, depending on the material of the conductive layer 32, it may react with the material contained in the semiconductor layer 21 and oxidize. Therefore, an oxide conductor similar to the conductive layer 31 can also be used.

[0058] The conductive layer 31 can be used as one of the source wiring and the drain wiring. In addition, the conductive layer 32 can be used as the other of the source wiring and the drain wiring. In this way, when one or both of the conductive layer 31 and the conductive layer 32 are used as wiring, it is preferable that the resistance is low. For this purpose, it is preferable to use a material with higher conductivity than an oxide conductor, such as metal, alloy, or nitride thereof. In particular, one or both of the conductive layer 31 and the conductive layer 32 preferably have a laminated structure including a layer made of the material with high conductivity, and at least the portion in contact with the semiconductor layer 21 uses the above-mentioned oxide conductor.

[0059] Here, the transistor 10 is provided at the intersection of the conductive layer 23 serving as the gate wiring and the conductive layer 32 serving as the source wiring or the drain wiring. As a result, a parasitic capacitance is generated in the overlapping portion of the conductive layer 23 and the conductive layer 32 at their intersection. Therefore, it is more preferable that the thickness of the insulating layer 42 provided between the conductive layer 23 and the conductive layer 32 is larger, and it is more preferable that its dielectric constant is lower. The thickness of the insulating layer 42 is preferably at least larger than that of the insulating layer 22. And the insulating layer 42 preferably contains a material whose dielectric constant is at least lower than that of the insulating layer 22. Thereby, the capacitance between the conductive layer 23 and the conductive layer 32 can be effectively reduced. In addition, Figure 1A 、 Figure 1B etc. show a case where the thickness of the insulating layer 42 is larger than that of the conductive layer 32, but it is not limited thereto. By making the thickness of the insulating layer 42 larger than one or both of the conductive layer 32 and the conductive layer 23, the conductive layer 32 and the conductive layer 23 can be relatively separated, and the parasitic capacitance can be effectively reduced.

[0060] In Figure 2B and Figure 2C shows a case where a laminated film of the insulating layer 41a, the insulating layer 41b, and the insulating layer 41c is used as the Figure 1A and Figure 1B insulating layer 41. In addition, Figure 3A is an enlarged view of Figure 2B .

[0061] An insulating layer 15 is provided between the insulating layer 41b and the semiconductor layer 21. In addition, an insulating layer 16 is provided between the semiconductor layer 21 and the insulating layer 15. In addition, an insulating layer 17 is provided between the semiconductor layer 21 and the insulating layer 16. The insulating layers 15, 16 and 17 are all located in the opening 20a and along the side surface of the insulating layer 41a.

[0062] The insulating layer 41b is used as an interlayer insulating layer. The thickness of the insulating layer 41b is larger than that of other insulating layers (such as the insulating layer 41a, the insulating layer 41c, etc.), so it is preferably formed by a deposition method with a high deposition rate. In addition, the insulating layer 41b has a structure surrounded by the insulating layer 41a, the insulating layer 41c and the insulating layer 15 and not in contact with the semiconductor layer 21 and the conductive layers 31 and 32 overlapping the semiconductor layer 21. The insulating layers 41a, 41c and 15 preferably have hydrogen barrier properties. Thereby, it is possible to prevent hydrogen contained in the insulating layer 41b from directly or indirectly diffusing into the semiconductor layer 21 through the conductive layer. Thereby, a semiconductor device with good electrical characteristics and high reliability can be realized.

[0063] The insulating layer 16 has a gettering (adsorbing, absorbing, capturing or fixing) function for hydrogen. For example, by performing a heat treatment after forming the insulating layer 17 in contact with the insulating layer 16, the insulating layer 16 captures and fixes the hydrogen contained in the insulating layer 17, thereby reducing the hydrogen concentration in the insulating layer 17.

[0064] In addition, as an insulator having a gettering function for hydrogen, an oxide containing magnesium or an oxide containing one or both of aluminum and hafnium can be cited. In addition, the above-mentioned oxide preferably has an amorphous structure. In an oxide having an amorphous structure, sometimes oxygen atoms have dangling bonds, and hydrogen is captured or fixed by these dangling bonds. Note that the above-mentioned metal oxide preferably has an amorphous structure, but a crystalline region may be formed in a part thereof.

[0065] As the insulating layer 16, magnesium oxide, aluminum oxide, hafnium oxide, etc. can be used. In addition, for example, as the insulating layer 16, a laminated film of aluminum oxide and silicon nitride can also be used.

[0066] As the insulating layer 17 in contact with the semiconductor layer 21, an oxide insulating film is preferably used. For example, inorganic insulating films such as silicon oxide and silicon oxynitride can be used. In addition, the insulating layer 17 preferably uses an oxide insulating film containing excess oxygen to the extent that oxygen is released by heating. When the insulating layer 17 containing excess oxygen and having a reduced hydrogen concentration is provided in contact with the semiconductor layer 21, the oxygen vacancies in the semiconductor layer 21 are reduced and the hydrogen concentration is reduced, thereby enabling a highly reliable transistor 10.

[0067] The portion of the semiconductor layer 21 in contact with the insulating layer 17 is a region where oxygen vacancies are reduced, which can be said to be an i-type region. On the other hand, the portion not in contact with the insulating layer 17 is preferably an n-type region containing a large number of carriers. That is to say, the portion of the semiconductor layer 21 in contact with the insulating layer 17 can be called a channel formation region, and the outer region thereof can be called a low-resistance region (also referred to as a source region or a drain region). In Figure 3A different hatching lines are attached to the channel formation region 21i and the low-resistance region 21n of the semiconductor layer 21. Here, an example is shown in which the portion of the semiconductor layer 21 in contact with the insulating layer 41c, the insulating layer 15, or the conductive layer 31 is the low-resistance region 21n.

[0068] As Figure 3A shown, the channel length L of the transistor 10 can be said to be the length of the portion in contact with the insulating layer 17 on the path of the shortest distance connecting the portion in contact with the conductive layer 31 and the portion in contact with the conductive layer 32 in the semiconductor layer 21. In Figure 3A the example shown, the channel formation region has an L-shaped cross-sectional shape.

[0069] On the other hand, the channel width W of the transistor 10 depends on the shape of the opening 20a and the thickness of each insulating layer located in the opening 20a, etc. Figure 3B is a plan view when looking at the cross-section along the Figure 3A cutting line C1-C2 in

[0070] which is at the height where the insulating layer 41b is provided. Here, the case where the opening 20a has a cylindrical shape is shown. Inside the opening 20a, the insulating layer 15, the insulating layer 16, the insulating layer 17, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are sequentially provided in concentric circles from the outside.

[0071] Since the insulating layers 15, 16, 17, the semiconductor layer 21, and the insulating layer 22 are sequentially formed along the inner wall of the opening 20a of the insulating layer 41, the thickness of this portion may sometimes be reduced depending on the deposition method. For example, in deposition methods such as sputtering or plasma CVD, the thickness of a film deposited on a surface inclined or perpendicular to the substrate surface tends to be thinner than that of a film deposited on a surface parallel to the substrate surface. On the other hand, when using deposition methods such as atomic layer deposition (ALD) or thermal CVD, a film with a uniform thickness can be deposited regardless of the angle of the surface to be formed. For example, when the angle θ is 75 degrees or more, 80 degrees or more, or 85 degrees or more, it is preferable to form the insulating layers 15, 16, 17, the semiconductor layer 21, and the insulating layer 22 using the ALD method.

[0072] Here, the insulating layer 15 has an L-shaped cross-sectional shape such that a part of it is located between the bottom surface of the insulating layer 16 and the top surface of the conductive layer 31. For example, after successively forming the insulating film that becomes the insulating layer 15 and the insulating film that becomes the insulating layer 16, a part of these films is removed by etching to form the above shape.

[0073] As Figure 3A shown, let the thickness of the insulating layer 41 (insulating layers 41a, 41b, and 41c) be H, and as Figure 3B shown, let the diameter of the opening 20a in the insulating layer 41a be D. At this time, D is preferably greater than H, and more preferably more than twice H. As described above, the channel length L of the transistor 10 depends on the thickness of the insulating layer 41. Therefore, the smaller the thickness of the insulating layer 41, the shorter the channel length can be, and a large current can flow. Also, the channel width W with respect to the channel length L can be increased, so a transistor that can allow a larger current to flow can be realized.

[0074] [Constituent elements] [Substrate] As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. As the insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), a resin substrate, etc. can be cited. In addition, as the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, etc. can be cited. Further, a semiconductor substrate having an insulator region inside the above semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. can be cited. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Or, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can also be used. In addition, an insulator substrate provided with a conductive layer or a semiconductor layer, a semiconductor substrate provided with a conductive layer or an insulating layer, a conductor substrate provided with a semiconductor layer or an insulating layer, etc. can be cited. Or, a substrate having an element provided thereon can also be used. As the element provided on the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a storage element, etc. can be cited.

[0075] <Semiconductor layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0076] As the metal oxide that can be used for the semiconductor layer 21, for example, In oxide, Ga oxide, and Zn oxide can be cited. The metal oxide preferably contains at least In or Zn. In addition, the metal oxide preferably contains two or three selected from In, element M, and Zn. Note that element M is a metal element or a semi-metal element having a high bond energy with oxygen, for example, a metal element or a semi-metal element having a higher bond energy with oxygen than In. As element M, specifically, Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb, etc. can be cited. The element M contained in the metal oxide is preferably one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, and more preferably Ga. Note that hereinafter, the metal oxide containing In, M, and Zn is sometimes referred to as an In-M-Zn oxide. Note that in this specification, etc., a metal element and a semi-metal element are sometimes collectively referred to as a "metal element", and the "metal element" described in this specification, etc. sometimes includes a semi-metal element.

[0077] When using In-M-Zn oxide as the metal oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, as the atomic ratios of the metal elements in such In-M-Zn oxide, there can be mentioned In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions near them, etc. Note that the compositions near them include the range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be improved, etc.

[0078] The atomic ratio of In in the In-M-Zn oxide can also be less than the atomic ratio of M. For example, as the atomic ratios of the metal elements in such In-M-Zn oxide, there can be mentioned In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or compositions near them, etc. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0079] The semiconductor layer 21 can use, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, etc. In addition, Ga-Zn oxide can also be used.

[0080] In addition, the metal oxide can also replace indium or contain one or more metal elements with a large period number in addition to indium. There is a tendency that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, when a metal element with a large period number is included, the field-effect mobility of the transistor can sometimes be improved. As the metal elements with a large period number, there can be mentioned metal elements belonging to the 5th period and metal elements belonging to the 6th period, etc. As such metal elements, specifically, there can be mentioned Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu, etc. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0081] In addition, the metal oxide may also contain one or more non-metal elements. When the metal oxide contains non-metal elements, the field-effect mobility of the transistor can sometimes be improved. Examples of the non-metal elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0082] The metal oxide can be appropriately formed by a sputtering method or an atomic layer deposition (ALD: Atomic Layer Deposition) method. In particular, the metal oxide is preferably deposited by ALD with excellent coverage. Note that when the metal oxide is formed by the sputtering method, the composition of the deposited metal oxide is sometimes different from the composition of the target material. In particular, the content rate of zinc in the deposited metal oxide sometimes decreases to about 50% of the content rate of zinc in the target material.

[0083] In this specification and the like, the content rate of a certain metal element in the metal oxide refers to the ratio of the number of atoms of the element to the total number of atoms of the metal elements contained in the metal oxide. For example, when the metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide are A X , A Y , A Z respectively, the content rate of metal element X can be expressed as A X / (A X + A Y + A Z ). In addition, when the ratio of the number of atoms (atomic ratio) of metal element X, metal element Y, and metal element Z in the metal oxide is expressed as B X : B Y : B Z , the content rate of metal element X can be expressed as B X / (B X + B Y + B Z ).

[0084] For example, when using a metal oxide containing In, by increasing the content rate of In, a transistor with a large on-state current can be realized.

[0085] By using a metal oxide that does not contain Ga or has a low Ga content rate in the semiconductor layer 21, a transistor with high reliability for positive bias application can be realized. That is, a transistor with a small variation in the threshold voltage in the PBTS (Positive Bias Temperature Stress) test can be realized. In addition, when using a metal oxide containing Ga, the Ga content rate is preferably lower than the In content rate. Thus, a transistor with high mobility and high reliability can be realized.

[0086] On the other hand, by increasing the Ga content rate, a transistor with high reliability against light can be realized. That is, a transistor with a small variation in threshold voltage in the NBTIS (Negative Bias Temperature Illumination Stress) test can be realized. Specifically, the bandgap of a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In is larger, and the variation in threshold voltage in the NBTIS test of the transistor can be reduced.

[0087] In addition, by increasing the zinc content rate, a metal oxide with high crystallinity can be obtained, and impurity diffusion in the metal oxide can be suppressed. As a result, the variation in the electrical characteristics of the transistor is suppressed, and the reliability can be improved.

[0088] The semiconductor layer 21 may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 21 may be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, it can be formed using the same sputtering target, so the manufacturing cost can be reduced. Note that a stacked structure of two or more oxide semiconductor layers with different compositions may also be adopted. In addition, by using the ALD method, a metal oxide layer with a continuously varying composition in the thickness direction can be formed. As a result, compared with the case of using a film with a predetermined composition, not only can the design selection range be expanded, but also the generation of interface states and the like generated between two layers with different compositions can be prevented, so the electrical characteristics and reliability can be improved.

[0089] In the case where the semiconductor layer 21 has a two-layer structure, it is preferable to use a material (a material with high conductivity) with a higher mobility than the first layer in the second layer, that is, the layer closer to the gate electrode. As a result, a normally-off transistor with a large on-state current can be formed. Therefore, low power consumption and high performance can be achieved at the same time. In addition, a material with a higher mobility than the second layer may also be used in the first layer, that is, the layer in contact with the source electrode and the drain electrode. As a result, the contact resistance between the semiconductor layer 21 and the source electrode or the drain electrode can be reduced, the parasitic resistance can be reduced, and a transistor with a large on-state current can be formed.

[0090] In addition, in the case where the semiconductor layer 21 has a three-layer structure, it is preferable to use a material with a higher mobility than the first layer and the third layer in the second layer. As a result, a transistor with a high on-state current and high reliability can be realized.

[0091] For example, the above-described high or low mobility or high or low conductivity can be replaced with high or low indium content. In addition, the following factors also affect mobility and conductivity: the presence or absence of elements other than indium that contribute to improving conductivity, their content, and the like. As an example of a high-mobility material, materials such as In:Ga:Zn = 4:3:2 [atomic ratio] and those near it, In:Zn = 1:1 [atomic ratio] and those near it, In:Zn = 4:1 [atomic ratio] and those near it, In:Sn:Zn = 40:X:10 [atomic ratio] (X is 0.1 or more and 5 or less, typically X = 1) and those near it can be cited. On the other hand, as materials having a mobility or conductivity lower than the above materials, materials such as In:Ga:Zn = 1:3:2 [atomic ratio] and those near it, In:Ga:Zn = 1:3:4 [atomic ratio] and those near it, In:Ga:Zn = 2:2:1 [atomic ratio] and those near it, In:Ga:Zn = 1:1:1 [atomic ratio] and those near it, In:Ga:Zn = 1:1:2 [atomic ratio] and those near it can be cited.

[0092] As the semiconductor layer 21, a metal oxide layer having crystallinity is preferably used. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a microcrystalline (nc: nano-crystal) structure, or the like can be used. By using a metal oxide layer having crystallinity for the semiconductor layer 21, the density of defect states in the semiconductor layer 21 can be reduced, and thus a highly reliable semiconductor device can be realized.

[0093] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer having low crystallinity, a transistor capable of allowing a large current to flow can be realized.

[0094] Compared with a transistor using amorphous silicon, the field-effect mobility of a transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) is very high. In addition, the leakage current between the source and the drain in the off state of the OS transistor (hereinafter, also referred to as the off-state current) is extremely low, and the charge stored in a capacitor connected in series with the transistor can be maintained for a long period. In addition, by using an OS transistor, the power consumption of the semiconductor device can be reduced.

[0095] One embodiment of the semiconductor device of the present invention can be applied to, for example, a display device. When increasing the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. For this purpose, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since the breakdown voltage between the source and drain of an OS transistor is higher than that of a transistor using silicon (hereinafter referred to as an Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Thus, by using an OS transistor as the driving transistor included in the pixel circuit, the amount of current flowing through the light-emitting device can be increased to increase the emission luminance of the light-emitting device.

[0096] When a transistor operates in the saturation region, compared with an Si transistor, an OS transistor can make the change in the source-drain current for a change in the gate-source voltage small. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. Thus, the number of gray levels of the pixel circuit can be increased. In addition, even if there are variations in the electrical characteristics (e.g., resistance) of the light-emitting device or non-uniformity in the electrical characteristics, a stable current can flow.

[0097] As described above, by using an OS transistor as the driving transistor included in the pixel circuit, "suppression of black blurring", "increase in emission luminance", "multi-gradation", "suppression of the influence of manufacturing non-uniformity of the light-emitting device", etc. can be achieved.

[0098] The change in the electrical characteristics of an OS transistor due to irradiation with radiation is small, that is, the tolerance to radiation is high. Therefore, it can be appropriately used even in an environment where radiation may be incident. The OS transistor can also be said to have high reliability for radiation. For example, an OS transistor can be appropriately used as a pixel circuit of an X-ray flat panel detector. In addition, an OS transistor can be appropriately used for a semiconductor device used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and γ-rays) and particle radiation (e.g., α-rays, β-rays, proton radiation, and neutron radiation).

[0099] Note that the semiconductor material that can be used for the semiconductor layer 21 is not limited to an oxide semiconductor. For example, a semiconductor composed of a single element or a compound semiconductor can be used. Examples of the semiconductor composed of a single element include silicon (including single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon) or germanium. Examples of the compound semiconductor include gallium arsenide and silicon germanium. Examples of the compound semiconductor include an organic semiconductor, a nitride semiconductor, or an oxide semiconductor. Note that these semiconductor materials can also contain impurities as dopants.

[0100] Alternatively, the semiconductor layer 21 may also have a layered material serving as a semiconductor. The layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds weaker than covalent bonds and ionic bonds such as van der Waals bonding. The layered material has high conductivity in the unit layer, that is, has high two-dimensional conductivity. By using a material that serves as a semiconductor and has high two-dimensional conductivity for the channel formation region, a transistor with a large on-state current can be provided.

[0101] As the above-mentioned layered material, for example, graphene, silicene, chalcogenide, etc. can be cited. Chalcogenide is a compound containing a chalcogen element (an element belonging to Group 16). In addition, as chalcogenide, transition metal chalcogenide, Group 13 chalcogenide, etc. can be cited. As the transition metal chalcogenide that can be used as the semiconductor layer of a transistor, specifically, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited.

[0102] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 21, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than single crystal (polycrystalline semiconductor, microcrystalline semiconductor, or a semiconductor having a crystal region in a part thereof) can be used. When using a semiconductor having crystallinity, deterioration of the transistor characteristics can be suppressed, so it is preferred.

[0103] <Gate insulating layer> The insulating layer 22 is used as the gate insulating layer of the transistor and is also used as the dielectric layer of the capacitor. When an oxide semiconductor is used for the semiconductor layer 21, an oxide insulating film is preferably used as at least the film in the insulating layer 22 that contacts the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used. In addition to this, nitride insulating films such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride can also be used as the insulating layer 22. In addition, the insulating layer 22 may have a stacked structure, for example, may have a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0104] Note that in this specification, etc., oxynitride refers to a material containing more oxygen than nitrogen. Nitroxide refers to a material containing more nitrogen than oxygen.

[0105] In addition, the insulating layer 22 is preferably formed by laminating an insulating material made of a high-k material, and a laminated structure of a material having a high relative permittivity (high-k) and a material having a dielectric strength greater than that of the high-k material is preferably used. For example, as the insulating layer 22, an insulating film (also referred to as ZAZ) in which zirconia, alumina, and zirconia are laminated in sequence can be used. In addition, for example, an insulating film (also referred to as ZAZA) in which zirconia, alumina, zirconia, and alumina are laminated in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina are laminated in sequence can be used. By laminating an insulator having a relatively large dielectric strength such as alumina and using it, the dielectric strength can be increased and electrostatic breakdown of the capacitor can be suppressed.

[0106] In addition, a ferroelectric material can also be used as the insulating layer 22. Examples of the ferroelectric material include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO X (X is a real number greater than 0).

[0107] <Conductive layer> The conductive layer 31 and the conductive layer 32 are in contact with the semiconductor layer 21. Here, when an oxide semiconductor is used as the semiconductor layer 21, when a metal such as aluminum that is easily oxidized is used for a portion of the conductive layer 31 or the conductive layer 32 that is in contact with the semiconductor layer 21, an insulating oxide (such as alumina) may be formed between the conductive layer 31 or the conductive layer 32 and the semiconductor layer 21, which may hinder conduction between them. Therefore, at least a portion of the conductive layer 31 and the conductive layer 32 that is in contact with the semiconductor layer 21 is preferably made of a conductive material that is not easily oxidized, a conductive material that maintains a low resistance even when oxidized, or an oxide conductive material.

[0108] As the conductive layer 31 and the conductive layer 32, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like. They are conductive materials that are not easily oxidized or materials that maintain conductivity even when oxidized, so they are preferable.

[0109] Alternatively, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. In particular, a conductive oxide containing indium is preferably used because of its high conductivity. In addition, oxide materials such as In-Ga-Zn oxide that can be applied to the above-mentioned semiconductor layer 21 can also be used for the conductive layer by increasing the carrier concentration.

[0110] For example, as the conductive layer 31 and the conductive layer 32, a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure formed by sequentially laminating a titanium nitride film, a tungsten film, and a titanium nitride film, a two-layer structure formed by laminating a ruthenium film or a ruthenium oxide film on tungsten, a two-layer structure formed by laminating a ruthenium film or a ruthenium oxide film on the above-mentioned conductive oxide film, a two-layer structure formed by laminating the above-mentioned conductive oxide film on a ruthenium film or a ruthenium oxide film, etc. may be used. Note that ruthenium is a material that is difficult to etch, so the smaller its thickness, the more preferable it is. For example, it is preferably used with a thickness of 0.1 nm or more and 2 nm or less.

[0111] The conductive layer 23 is used as a gate electrode, and various conductive materials can be used. As the conductive layer 23, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., and an alloy containing the metal element as a component are preferably used. In addition, nitrides of the above-mentioned metals or alloys or oxides of the above-mentioned metals or alloys may also be used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. In addition, a semiconductor with high conductivity represented by polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide may also be used.

[0112] In addition, the conductive layer 23 may also use the nitrides and oxides that can be used for the conductive layer 31 and the conductive layer 32 described above.

[0113] Since the conductive layer 23, the conductive layer 31, and the conductive layer 32 are also used as wirings, it is preferable to stack and use conductive materials with low resistance.

[0114] <Insulating layer> The insulating layer 17 has a portion in contact with the semiconductor layer 21. When an oxide semiconductor is used for the semiconductor layer 21, in order to improve the interface characteristics between the semiconductor layer 21 and the insulating layer 17, at least the portion of the insulating layer 17 in contact with the semiconductor layer 21 preferably uses an oxide. For example, silicon oxide or silicon oxynitride can be appropriately used. The insulating layer 17 can be formed by a deposition method such as ALD method, sputtering method, plasma CVD method, etc. In particular, the insulating layer 17 is preferably formed by the ALD method.

[0115] In addition, the insulating layer 17 more preferably uses a film that releases oxygen by heating. Thereby, oxygen can be supplied to the semiconductor layer 21 by the heat applied in the manufacturing process of the transistor 10, the oxygen vacancies in the semiconductor layer 21 can be reduced, and the reliability can be improved. As a method of supplying oxygen to the insulating layer 17, heat treatment in an oxygen atmosphere, plasma treatment in an oxygen atmosphere, etc. can be cited.

[0116] The insulating layer 41b, the insulating layer 42, and the insulating layer 44 can be used as an interlayer insulating film. For example, it is preferably formed by a deposition method such as sputtering or plasma CVD method. In particular, by depositing using a deposition method that does not use hydrogen gas as a deposition gas by sputtering, a film with extremely low hydrogen content can be formed. Thereby, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0117] In addition, since the insulating layer 41b, the insulating layer 42, and the insulating layer 44 are used as an interlayer insulating layer, it is preferable to use a deposition method that can deposit at a higher deposition rate compared to other insulating layers. For example, as the insulating layer 41b, the insulating layer 42, and the insulating layer 44, a TEOS (Tetra-Ethyl-Ortho-Silicate: tetraethoxysilane, chemical formula: Si(OC2H5)4) film formed by plasma CVD method can be used. Thereby, the production rate can be increased.

[0118] As the insulating layer 41a, the insulating layer 41c, and the insulating layer 15, a film with low hydrogen diffusivity is preferably used. The insulating layer 41b is sandwiched between the insulating layer 41a and the insulating layer 41c with low hydrogen diffusivity, and the insulating layer 15 is provided on the side surface of the insulating layer 41b, thereby closing the hydrogen contained in the insulating layer 41b. Thereby, the hydrogen that may diffuse into the semiconductor layer 21 can be effectively reduced.

[0119] As the insulating layer 41a, the insulating layer 41c, and the insulating layer 15, for example, one or more of silicon nitride, silicon oxynitride, oxynitride silicon, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. In particular, silicon nitride and silicon oxynitride have the characteristics of rarely releasing impurities (such as water and hydrogen) and not easily allowing oxygen and hydrogen to permeate, so they can be suitably used as the insulating layer 41a, the insulating layer 41c, and the insulating layer 15.

[0120] [Modification Example] Examples in which a part is different from the above structural example will be described below. Note that the description of parts that overlap with the above may sometimes be omitted.

[0121] <Modification Example 1> Figure 4A and Figure 4B is a cross-sectional schematic view of the transistor 10a. Figure 4A is the same as Figure 2B a cross-sectional view of a cross-section parallel to the extending direction of the conductive layer 32, Figure 4B is the same as Figure 2C a cross-sectional view of a cross-section parallel to the extending direction of the conductive layer 23. The main difference between the transistor 10a and the above transistor 10 lies in the shape of the insulating layer 15.

[0122] In the transistor 10a, the cross-sectional shape of the insulating layer 15 is linear instead of L-shaped. Thus, the bottom surface of the insulating layer 16 contacts the conductive layer 31. By adopting the above structure, the contact area between the insulating layer 17 and the insulating layer 16 increases, and the hydrogen concentration in the insulating layer 17 can be reduced more effectively.

[0123] <Modified Example 2> Figure 4C 、 Figure 4D The transistor 10b shown in the figure shows the following structural example: The cross-sectional shapes of both the insulating layer 15 and the insulating layer 16 are L-shaped. The bottom surface of the insulating layer 16 is provided on the protruding portion of the insulating layer 15, and the bottom surface of the insulating layer 17 is provided on the protruding portion of the insulating layer 16. By adopting the above structure, when forming the insulating layer 15, the insulating layer 16, and the insulating layer 17, the three insulating films can be etched at one time after continuously depositing the three insulating films.

[0124] In addition, a part of the insulating layer 15 contacts the lower part of the semiconductor layer 21. The part of the semiconductor layer 21 that contacts the conductive layer 31 does not contact the insulating layer 17. Therefore, the carrier concentration in this part becomes high, and an n-type region is easily formed. Therefore, the current in the transistor 10b in the on state can be increased.

[0125] <Modified Example 3> Figure 5A 、 Figure 5B The difference between the transistor 10c shown in the figure and the above-mentioned transistor 10 is that the transistor 10c does not include the insulating layer 17.

[0126] Since the insulating layer 17 is not included, the insulating layer 16 is provided in contact with the semiconductor layer 21. Therefore, the insulating layer 16 can directly get the hydrogen in the semiconductor layer 21 to be gettering, so that the hydrogen concentration in the semiconductor layer 21 can be effectively reduced. Thus, a transistor with higher reliability can be realized. In addition, by not providing the insulating layer 17, the manufacturing process can be reduced, and the production rate can be increased.

[0127] In addition, Figure 5C 、 Figure 5D The transistor 10d shown in the figure is an example of the case where the insulating layer 17 in the structure of the above-mentioned transistor 10a is omitted.

[0128] <Modified Example 4> Fig. 6A 、 Figure 6B The main difference between the transistor 10e shown in the figure and the above-mentioned transistor 10 is that the transistor 10e includes a conductive layer 26.

[0129] The conductive layer 26 is provided in a region surrounded by the insulating layer 41a, the insulating layer 41b, the insulating layer 41c, and the insulating layer 15. It can also be said that the conductive layer 26 is embedded in the insulating layer 41b. The conductive layer 26 is disposed opposite to the semiconductor layer 21 with the insulating layer 15, the insulating layer 16, and the insulating layer 17 therebetween.

[0130] The conductive layer 26 is used as a second gate electrode (or a back gate electrode). In addition, the insulating layer 15, the insulating layer 16, and the insulating layer 17 are located between the conductive layer 26 and the semiconductor layer 21 and are used as a second gate insulating layer (or a back gate insulating layer). The conductive layer 26 can be supplied with a fixed potential or an arbitrary signal. By providing the conductive layer 26 and supplying an appropriate potential to the conductive layer 26, the potential on the back-channel side of the semiconductor layer 21 can be fixed, thereby reducing the non-uniformity of electrical characteristics. In addition, the conductive layer 26 can also be electrically connected to any one of the conductive layer 31, the conductive layer 32, and the conductive layer 23 to be supplied with the same potential.

[0131] Note that an example is shown here in which the conductive layer 26 extends in the same direction as the extension direction of the conductive layer 23, but it is not limited thereto. The conductive layer 26 can also extend in the same direction as the extension direction of the conductive layer 32 or in a direction different from the extension directions of the conductive layer 23 and the conductive layer 32.

[0132] In addition, Figure 6C 、 Fig.6D The transistor 10f shown is an example of the case where the above-mentioned transistor 10c further includes the conductive layer 26.

[0133] <Modification Example 5> Fig. 7A 、 Figure 7B The transistor 10g shown is an example of the case where the insulating layer 15, the insulating layer 16, and the insulating layer 17 in the above-mentioned transistor 10 are omitted.

[0134] The semiconductor layer 21 is provided in contact with the inner wall in the opening 20a of the insulating layer 41b. At this time, the insulating layer 41b preferably uses an oxide insulating film. In particular, an oxide insulating film that releases oxygen by heating is preferably used. At this time, the insulating layer 41b is clamped by the oxygen-barrier insulating layers 41a and 41c, so that the oxygen contained in the insulating layer 41b can be enclosed in the region surrounded by the insulating layer 41a, the insulating layer 41c, and the semiconductor layer 21. Thereby, the oxygen in the insulating layer 41b can be prevented from escaping during the process and reduced, and the oxygen can be efficiently supplied to the semiconductor layer 21.

[0135] The portion of the semiconductor layer 21 in contact with the insulating layer 41b is a region where oxygen vacancies are reduced, which can be said to be an i-type region. On the other hand, the portion not in contact with the insulating layer 41b is preferably an n-type region containing a large number of carriers. That is to say, the portion of the semiconductor layer 21 in contact with the insulating layer 41b can be called a channel formation region, and the outer region thereof can be called a low-resistance region (also referred to as a source region or a drain region).

[0136] In addition, the hydrogen concentration of the insulating layer 41b is preferably sufficiently low. For example, it is preferable to use an oxide insulating film deposited by a deposition method in which the gas used during deposition does not contain hydrogen. It is preferable to use an oxide insulating film such as silicon oxide or silicon oxynitride formed by a sputtering method. Thus, without using the insulating layer 16 having a gettering function for hydrogen and the insulating layer 17 having a hydrogen barrier property, etc., not only can the hydrogen concentration in the semiconductor layer 21 be reduced, but also a large amount of oxygen can be supplied to the semiconductor layer 21, thereby enabling a highly reliable transistor to be realized.

[0137] <Modification Example 6> Figure 7C 、 Fig.7D The main difference between the transistor 10h shown and the above-mentioned transistor 10g lies in the structures of the insulating layer 42 and the insulating layer 22.

[0138] The insulating layer 42 and the insulating layer 22 respectively cover the insulating layer 41c and the semiconductor layer 21 on the insulating layer 41c. In other words, it can also be said that the insulating layer 22 and the insulating layer 42 cover the ends of the semiconductor layer 21. In addition, the insulating layer 42 and the insulating layer 22 are provided with openings reaching the semiconductor layer 21 in the region overlapping with the insulating layer 41c. The conductive layer 32 is electrically connected to the semiconductor layer 21 through this opening.

[0139] Thus, when adopting the structure in which the semiconductor layer 21 is covered by the insulating layer 22 and the insulating layer 42, it is possible to prevent impurities from diffusing from the exposed portion of the semiconductor layer 21 during the manufacturing process of the transistor, thereby enabling a highly reliable transistor to be realized.

[0140] The structure in which the ends of the semiconductor layer 21 are covered by the insulating layer 22, the insulating layer 42, or both of the above-mentioned insulating layers can be applied to other structural examples in addition to the structure of the transistor 10h. That is to say, this structure can be applied to a structure including at least one of the insulating layer 15, the insulating layer 16, and the insulating layer 17.

[0141] <Modification Example 7> Fig. 8A 、 Figure 8B The main difference between the transistor 10i shown and the above-mentioned transistor 10g lies in the shape of the conductive layer 31.

[0142] The conductive layer 31 is provided with a recess, and a semiconductor layer 21, an insulating layer 22, and a conductive layer 23 are provided along the recess. At this time, the height of the lower end of the conductive layer 23 is preferably lower than the height of the top surface of the conductive layer 31.

[0143] In the transistor 10i, the portion of the semiconductor layer 21 in contact with the conductive layer 31 is a region having a lower resistance than the channel formation region. Therefore, by making the height of the lower end of the conductive layer 23 lower than the top surface of the conductive layer 31, a gate electric field can be uniformly applied to the entire channel formation region of the semiconductor layer 21, thereby preventing the formation of a high-resistance region (biased region) due to the difficulty of applying the gate electric field in the semiconductor layer 21. Therefore, a transistor with an increased on-state current can be realized. To achieve such a structure, for example, the thickness of the conductive layer 31 is preferably at least thicker than the sum of the thicknesses of the semiconductor layer 21 and the insulating layer 22.

[0144] Note that the structure of the conductive layer 31 having a recess can be applied to other structural examples in addition to the structure of the transistor 10i. That is, this structure can be applied to a structure including at least one of the insulating layer 15, the insulating layer 16, and the insulating layer 17.

[0145] <Modification Example 8> Figure 8C 、 Fig.8D The transistor 10j shown is an example of the case where the side wall of the opening 20a has a tapered shape. In the transistor 10j, the diameter (opening diameter) of the upper end of the opening 20a is larger than the diameter (opening diameter) of the lower end.

[0146] By having the side wall of the opening 20a with a tapered shape, the coverage of the semiconductor layer 21, the insulating layer 22, etc. is improved, and even when using a deposition method such as sputtering, the generation of defects such as low-density regions in the film can be suppressed. For example, the angle θ can be 45 degrees or more and 90 degrees or less, 60 degrees or more and less than 90 degrees, or 70 degrees or more and less than 90 degrees. In addition, when using a deposition method with extremely high coverage such as the ALD method, the angle θ can also be greater than 90 degrees (i.e., it can also have an inverted tapered shape).

[0147] When the side wall of the opening 20a has a tapered shape, the diameter of the opening 20a corresponding to the channel width of the transistor 10j increases from the side of the conductive layer 31 to the side of the conductive layer 32. At this time, the magnitude of the current flowing through the transistor 10j is limited by the portion with the smallest diameter. Therefore, the channel width of the transistor 10j can be regarded as the perimeter of the portion with the smallest diameter. Therefore, by having the side wall of the opening 20a with a tapered shape, a transistor with a channel width smaller than the diameter of the upper end of the opening 20a can be manufactured.

[0148] In addition, the structure in which the side wall of the opening 20a has a conical shape can be applied to other structural examples in addition to the structure of the transistor 10j. That is to say, this structure can be applied to a structure including at least one of the insulating layer 15, the insulating layer 16, and the insulating layer 17.

[0149] The above is the description of the modification examples.

[0150] [Examples of manufacturing method] Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Here, an example of the manufacturing method of the above-described transistor 10 will be described.

[0151] 9A to 12C are cross-sectional schematic views in each process of the manufacturing method of the semiconductor device shown below. In each drawing, they are arranged on the left and right sides respectively to show the cross-sections corresponding to Figure 2B and Figure 2C of.

[0152] Hereinafter, an insulating material for forming an insulating layer, a conductive material for forming a conductive layer, or a semiconductor material for forming a semiconductor layer can be appropriately deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0153] In addition, as the sputtering method, an RF sputtering method using a high-frequency power source for the sputtering power source, a DC sputtering method using a DC power source, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner can be cited. The RF sputtering method is mainly used when depositing an insulating film, and the DC sputtering method is mainly used when depositing a metal conductive film. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using a reactive sputtering method.

[0154] Note that the CVD method can be classified into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be classified into a metal CVD (MCVD: Metal CVD) method and a metalorganic CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0155] By using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used in the thermal CVD method, plasma damage to the object to be processed can be reduced. In addition, in the thermal CVD method, plasma damage during deposition does not occur, so a film with fewer defects can be obtained.

[0156] As the ALD method, there are a thermal ALD method that uses only thermal energy to react precursors and reactants, a PEALD method that uses reactants excited by plasma, etc.

[0157] The CVD method and the ALD method are different from the sputtering method. The CVD method and the ALD method are deposition methods with good step coverage and are not easily affected by the shape of the object to be processed. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of openings with a high aspect ratio, etc. However, since the deposition rate of the ALD method is relatively slow, it is sometimes preferable to use it in combination with other deposition methods such as the CVD method with a high deposition rate.

[0158] In addition, when using the CVD method, a film with an arbitrary composition can be deposited according to the flow rate ratio of the source gases. For example, when using the CVD method, a film with a continuously changing composition can be deposited by changing the flow rate ratio of the source gases while performing deposition. When depositing while changing the flow rate ratio of the source gases, since the time required for transferring or adjusting the pressure is not required, the deposition time can be shortened compared to the case of depositing using multiple deposition chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0159] When using the ALD method, a film with an arbitrary composition can be deposited by simultaneously introducing different types of precursors. Or, when introducing different types of precursors, a film with an arbitrary composition can be deposited by controlling the number of cycles of each precursor. In addition, similar to the CVD method, a film with a continuously changing composition can be deposited.

[0160] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate. As the insulating layer 11, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. The deposition of the insulating layer 11 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. When the formed surface of the insulating layer 11 is uneven, it is preferable to perform a planarization process after depositing the insulating layer 11 so that the top surface of the insulating layer 11 becomes flat.

[0161] Next, a conductive film that will become the conductive layer 31 is formed on the insulating layer 11. Next, a resist mask is formed on the conductive film by photolithography or the like, and the portion of the conductive film not covered by the resist mask is removed by etching, and then the resist mask is removed. Thus, the conductive layer 31 can be formed. Next, by depositing an insulating film that will become the insulating layer 44 and removing the portion overlapping with the conductive layer 31, the insulating layer 44 and the conductive layer 31 embedded in the insulating layer 44 can be formed ( Fig. 9A)。The processing of the insulating film that will become the insulating layer 44 is preferably carried out by CMP (Chemical Mechanical Polishing) method. For example, by processing the insulating film until the top surface of the conductive layer 31 is exposed, the insulating layer 44 as shown in Fig. 9A can be formed.

[0162] In addition, it is also possible to first form the insulating film that will become the insulating layer 44, then form an opening in the insulating film, and form a conductive film in such a way as to fill the opening, and perform polishing treatment (planarization treatment) by CMP method until the top surface of the insulating film is exposed, thereby forming the insulating layer 44 and the conductive layer 31.

[0163] By performing planarization treatment so that the heights of the top surfaces of the insulating layer 44 and the conductive layer 31 are the same, the top surface of the insulating layer 41 formed later can be made flat. Note that the insulating layer 41 can also be provided to cover the conductive layer 31 without providing the insulating layer 44. In this case, it is preferable to perform planarization treatment on the top surface of the insulating layer 41 by CMP method to make the top surface flat.

[0164] Next, an insulating layer 41a, an insulating layer 41b, and an insulating layer 41c (hereinafter sometimes collectively referred to as the insulating layer 41) are formed on the conductive layer 31 and the insulating layer 44 ( Fig. 9B ). The insulating layer 41a, the insulating layer 41b, and the insulating layer 41c can be formed appropriately by sputtering method, CVD method, MBE method, PLD method, ALD method, etc.

[0165] Here, since the thickness of the insulating layer 41 affects the channel length of the transistor, it is very important that the thickness of the insulating layer 41 does not show non-uniformity.

[0166] Note that when the insulating layer 41b is in contact with the semiconductor layer 21, by depositing the insulating layer 41b by sputtering method in an oxygen-containing atmosphere, an insulating layer 41b containing a large amount of oxygen can be formed. In addition, by using a sputtering method that does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in the insulating layer 41b can be reduced. In this way, by depositing the insulating layer 41b, oxygen is supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0167] Next, an opening 20a reaching the conductive layer 31 is formed in the insulating layer 41 ( Fig. 9C ).

[0168] The side wall of the opening 20a is preferably as perpendicular as possible to the top surface of the conductive layer 31. By adopting this structure, a transistor with a small occupied area can be manufactured. Alternatively, the side wall of the opening 20a can also have a tapered shape. By having a tapered shape, the coverage of the film formed inside the opening 20a can be improved.

[0169] The maximum width of the opening 20a (in the case where the opening 20a is circular when viewed from the plane, the maximum diameter of the opening 20a) is preferably as fine as possible. For example, the maximum width of the opening 20a is preferably 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 150 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less and 5 nm or more. In particular, in order to perform fine processing on the opening 20a, it is preferable to use a lithography technique using light with a short wavelength such as EUV light or an electron beam.

[0170] The opening 20a is preferably formed by anisotropic etching. Since processing using a dry etching method is suitable for fine processing, it is particularly preferable. In addition, the etching conditions for this processing can also be different in each of the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a. In addition, the angles of the side walls of the opening 20a can also be different in each of the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a.

[0171] When etching the insulating layer 41, sometimes a part of the upper portion of the conductive layer 31 is etched, and the thickness of the conductive layer 31 at the bottom of the opening 20a becomes thin. Alternatively, after forming the opening 20a, a part of the upper portion of the conductive layer 31 can be etched to thin the thickness of the conductive layer 31.

[0172] Next, a heat treatment can also be performed. The heat treatment can be carried out at 250 °C or higher and 650 °C or lower, preferably at 300 °C or higher and 500 °C or lower, and more preferably at 320 °C or higher and 450 °C or lower. In addition, the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas can be set to about 20%. The heat treatment can also be carried out under a reduced pressure state. Alternatively, the heat treatment can be carried out in an atmosphere of nitrogen gas or an inert gas, and then, in order to fill the escaped oxygen, the heat treatment can be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above heat treatment, water, hydrogen, and other impurities contained in the insulating layer 41 and the like can be reduced before depositing the oxide semiconductor film that will become the semiconductor layer.

[0173] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment can be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed by the insulating layer 41 and the like as much as possible.

[0174] Next, an insulating film 15f and an insulating film 16f are formed so as to cover the insulating layer 41c, the opening 20a, the conductive layer 31, etc. Fig.9D The insulating film 15f is a film that will become the insulating layer 15 later, and the insulating film 16f is a film that will become the insulating layer 16 later.

[0175] The insulating film 15f and the insulating film 16f can be appropriately formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In particular, it is preferable to form them by an ALD method with high coverage. The insulating film 15f and the insulating film 16f are preferably formed by the same deposition method, and more preferably continuously formed without exposing them to the atmosphere. More specifically, it is preferable to continuously form the insulating film 15f and the insulating film 16f in a vacuum by using an ALD apparatus.

[0176] Next, the insulating film 15f and the insulating film 16f are anisotropically etched so as to expose the top surfaces of the insulating layer 41c and the conductive layer 31, whereby the insulating layer 15 and the insulating layer 16 can be formed inside the opening 20a. Fig. 10A )

[0177] Next, an insulating film 17f is formed so as to cover the insulating layer 41c, the opening 20a, the insulating layer 15, the insulating layer 16, the conductive layer 31, etc. Fig. 10B ) The insulating film 17f is a film that will become the insulating layer 17 later.

[0178] The insulating film 17f can be formed by the same deposition method as the insulating film 15f and the insulating film 16f.

[0179] When depositing the insulating film 17f or after depositing the insulating film 17f, a treatment of supplying oxygen to the insulating film 17f can also be performed. For example, a heat treatment in an oxygen atmosphere or a plasma treatment in an oxygen atmosphere, etc., can be cited.

[0180] Next, the insulating film 17f is anisotropically etched so as to expose the top surfaces of the insulating layer 41c and the conductive layer 31, whereby the insulating layer 17 can be formed inside the opening 20a. Fig. 10C )

[0181] Next, the impurities such as water and hydrogen contained in the insulating layer 17, etc., can also be reduced by performing a heat treatment. The method of the heat treatment can refer to the above description.

[0182] Next, a semiconductor film 21f that becomes the semiconductor layer 21 is deposited so as to cover the insulating layer 41, the conductive layer 31, the opening 20a, the insulating layer 15, the insulating layer 16, the insulating layer 17, etc. Fig.11A ) Then, unnecessary portions of the semiconductor film 21f are removed by etching, whereby the semiconductor layer 21 is formed.

[0183] An oxide semiconductor film can be used as the semiconductor film 21f. The oxide semiconductor film can be deposited by appropriately using a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Here, the oxide semiconductor film is preferably formed so as to be in contact with the bottom and side walls of the opening 20a having a high aspect ratio. Therefore, when depositing the oxide semiconductor film, a deposition method with good coverage is preferably used, and a CVD method or an ALD method is more preferably used. For example, In-Ga-Zn oxide can be deposited as the oxide semiconductor film by an ALD method. In addition, when the opening 20a has a tapered shape, the oxide semiconductor film can be deposited by a sputtering method.

[0184] In addition, it is preferable to perform microwave treatment in an oxygen-containing atmosphere during or after depositing the oxide semiconductor film to reduce the impurity concentration in the oxide semiconductor film. Hydrogen and carbon can be cited as impurities in particular. In addition, by performing microwave treatment, the crystallinity of the oxide semiconductor film can sometimes be improved. Here, microwave treatment refers to, for example, a treatment using a device including a power source for generating high-density plasma using microwaves.

[0185] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be made into plasma using microwaves or high frequencies such as RF and the oxygen plasma can act. In addition, as the oxygen acting on the oxide semiconductor, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having unpaired electrons, also called O radicals). In addition, the oxygen acting on the oxide semiconductor can be one or more of the above forms, and oxygen radicals are particularly preferred.

[0186] In addition, it is preferable to heat the substrate when performing microwave treatment in an atmosphere containing the above-mentioned oxygen, as it can further reduce the impurity concentration in the oxide semiconductor film. The heating of the substrate can be carried out at 100 °C or higher and 650 °C or lower, preferably at 200 °C or higher and 600 °C or lower, and more preferably at 300 °C or higher and 450 °C or lower.

[0187] By heating the substrate when performing microwave treatment in an atmosphere containing the above-mentioned oxygen, the carbon concentration in the oxide semiconductor film measured by SIMS can be made lower than 1×10 20 atoms / cm 3 , preferably lower than 1×10 19 atoms / cm 3 , and further preferably lower than 1×10 18 atoms / cm 3 .

[0188] Note that the above shows an example of microwave treatment of an oxide semiconductor film in an oxygen-containing atmosphere, but is not limited thereto. For example, the insulating film near the oxide semiconductor film may be microwave-treated in an oxygen-containing atmosphere. More specifically, the silicon oxide film may be microwave-treated. Thereby, hydrogen contained in the silicon oxide film can be released to the outside as H2O. By releasing hydrogen from the silicon oxide film near the oxide semiconductor film, a highly reliable semiconductor device can be provided. For example, the insulating layer 22 to be formed later may be microwave-treated in an oxygen-containing atmosphere.

[0189] In addition, when the semiconductor layer 21 has a stacked structure, the deposition methods of the respective layers may be the same or different. For example, when the semiconductor layer 21 has a two-layer stacked structure, the lower oxide semiconductor film may be deposited by sputtering and the upper oxide semiconductor film may be deposited by ALD. The oxide semiconductor film deposited by sputtering easily has crystallinity. Then, by providing an oxide semiconductor film with crystallinity as the lower oxide semiconductor film, the crystallinity of the upper oxide semiconductor film can be improved. In addition, even if pinholes or disconnections are formed in the lower oxide semiconductor film deposited by sputtering, the portions overlapping with the above pinholes or disconnections can be blocked by the upper oxide semiconductor film deposited by ALD with good coverage.

[0190] After depositing the oxide semiconductor film, a heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the above oxide semiconductor film does not undergo polycrystallization, and may be performed at 250 °C or higher and 650 °C or lower, preferably 400 °C or higher and 600 °C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas may be set to about 20%. The heat treatment may also be performed under a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then, in order to replenish the oxygen that has escaped, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more.

[0191] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed by the above oxide semiconductor film and the like as much as possible.

[0192] Here, it is preferable to perform the above heating treatment in a state where the semiconductor film is in contact with the insulating layer 17 containing a large amount of oxygen. Thereby, oxygen can be supplied from the insulating layer 17 to the portion of the semiconductor film that will become the channel formation region to reduce oxygen vacancies.

[0193] Note that the heating treatment is performed after depositing the above oxide semiconductor film, but the present invention is not limited thereto. Furthermore, the heating treatment may also be performed in a subsequent process.

[0194] Next, an insulating layer 22 is formed so as to cover the semiconductor layer 21 and the insulating layer 41c ( Fig. 11B ). When depositing the insulating layer 22, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be appropriately used.

[0195] The insulating layer 22 is preferably provided with as uniform a thickness as possible on the side surface of the semiconductor layer 21 within the opening 20a. Therefore, it is particularly preferable to form the insulating layer 22 by the ALD method, which is a deposition method with very excellent coverage. Note that when the side wall of the opening 20a has a tapered shape, a deposition method such as a sputtering method can be used to deposit the insulating layer 22.

[0196] Next, a conductive film is deposited so as to cover the insulating layer 22 and fill the opening 20a, and etching is performed to remove unnecessary portions, thereby forming a conductive layer 23 ( Fig. 11C ). At this time, it is formed such that the width in the direction orthogonal to the extending direction of the conductive layer 23 is smaller than the width of the semiconductor layer 21. That is, in the semiconductor layer 21, there is a portion that is not covered by the conductive layer 23.

[0197] Next, an insulating layer 42 is formed so as to cover the insulating layer 22 and the conductive layer 23 ( Fig. 12A ). The insulating layer 42 preferably uses a material having a dielectric constant lower than that of at least the insulating layer 22. In addition, the thickness of the insulating layer 42 is preferably at least larger than that of the insulating layer 22. For example, the insulating layer 22 can be formed by a deposition method such as a sputtering method or a plasma CVD method.

[0198] Next, a part of the insulating layer 42 and the insulating layer 22 is removed by etching to expose a part of the top surface of the semiconductor layer 21 ( Fig. 12B ). At this time, the insulating layer 42 is etched in a region where the conductive layer 23 is not provided so that the conductive layer 23 is surrounded by the insulating layer 42 and the insulating layer 22.

[0199] Note, Fig. 12BAn example of etching the insulating layer 44 and the insulating layer 22 is shown in such a manner that the end portion of the semiconductor layer 21 is exposed, but it is not limited thereto, and etching may also be performed in such a manner that the insulating layer 22 and the insulating layer 44 cover the end portion of the semiconductor layer 21. In this case, the insulating layer 41c is not exposed and is covered by the insulating layer 22.

[0200] Next, after depositing a conductive film so as to cover the insulating layer 42, the semiconductor layer 21, etc., unnecessary portions are removed by etching, thereby forming a conductive layer 32( Fig. 12C ). The conductive layer 32 has a portion in contact with the semiconductor layer 21 in a region not overlapping with the conductive layer 23.

[0201] Through the above steps, the transistor 10 can be manufactured.

[0202] By the manufacturing method according to one aspect of the present invention, the hydrogen concentration in the channel formation region can be effectively reduced, so that a highly reliable transistor can be realized. In addition, since a thick interlayer insulating layer can be provided between the gate electrode and the upper electrode, the parasitic capacitance therebetween is reduced, and thus a transistor that can be used in a circuit requiring high-speed operation can be realized.

[0203] The above is the description of the example of the manufacturing method.

[0204] [Application Example] The structure of a storage device using a transistor and a capacitor will be described below.

[0205] Fig.13A is a circuit diagram of the storage cell 30. The storage cell 30 is composed of one transistor Tr1 and one capacitor C, and may also be denoted as 1Tr1C. The gate of the transistor Tr1 is connected to the wiring WL, one of the source and the drain is connected to the wiring BL, and the other is connected to one electrode of the capacitor C. The other electrode of the capacitor C is connected to the wiring PL.

[0206] The storage cell 30 stores the data potential input from the wiring BL through the transistor Tr1 in the capacitor C, thereby storing data. In addition, by making the transistor Tr1 in the non-conductive state, the data can be held. In addition, by making the transistor Tr1 in the conductive state, the potential corresponding to the held data is output to the wiring BL, thereby reading out the data. The wiring WL is supplied with a signal for controlling the conduction and non-conduction of the transistor Tr1. In addition, the wiring PL is supplied with a specified potential (for example, a fixed potential).

[0207] Fig. 13B and Fig. 13C is a cross-sectional view of the storage cell 30. Fig. 13B is a cross-sectional view along the extending direction of the conductive layer 32 and the conductive layer 34, Fig. 13CIt is a sectional view along the extending direction of the conductive layer 23. The storage cell 30 has a structure in which a transistor 10 is stacked on a capacitor 50. The transistor 10 and the capacitor 50 respectively correspond to the above-mentioned transistor Tr1 and the above-mentioned capacitor C.

[0208] Regarding the structure of the transistor 10, reference can be made to the above description, and thus the description is omitted here. Here, an example of the case of using the transistor 10 is shown, but it is not limited to the transistor 10 and can be replaced with various transistors described above.

[0209] The capacitor 50 includes a conductive layer 51, a conductive layer 52, and an insulating layer 53 sandwiched therebetween. The capacitor 50 constitutes a so-called MIM (Metal-Insulator-Metal) capacitor.

[0210] The capacitor 50 is provided on the insulating layer 11. A conductive layer 34 and an insulating layer 47 on the conductive layer 34 are provided on the insulating layer 11. An opening 20b reaching the conductive layer 34 is provided in the insulating layer 47. The conductive layer 51 is provided inside the opening 20b in contact with the side surface of the insulating layer 47 and the top surface of the conductive layer 34. In addition, the insulating layer 53 is provided to cover the insulating layer 47 and the conductive layer 51. An insulating layer 48 is provided on the insulating layer 53. The conductive layer 52 is provided in a manner of being embedded in the insulating layer 48 and the opening 20b.

[0211] The top surfaces of the conductive layer 52 and the insulating layer 48 are flattened, and their top surface heights are substantially the same. An insulating layer 44 and a conductive layer 31 are provided on the conductive layer 52 and the insulating layer 48. The conductive layer 31 is provided in contact with the top surface of the conductive layer 52.

[0212] In Fig. 14B and Fig. 14C , the conductive layer 32 corresponds to the wiring BL, the conductive layer 23 corresponds to the wiring WL, and the conductive layer 34 corresponds to the above-mentioned wiring PL.

[0213] As the conductive layer 34, the conductive layer 51, and the conductive layer 52, a low-resistance conductive material can be used. For example, the material that can be used for the above-mentioned conductive layer 23 can be used.

[0214] The insulating layer 53 is used as the dielectric layer of the capacitor 50. The thinner the thickness of the insulating layer 53 and the higher the relative dielectric constant, the more the capacitance of the capacitor 50 increases. For example, it is preferable to use a high-k material that can be used for the above-mentioned insulating layer 22.

[0215] Fig.14AThis is the circuit diagram of the memory cell 30a. The memory cell 30a includes a transistor Tr2 instead of the capacitor C of the memory cell 30. In the transistor Tr2, the gate is connected to the other of the source and drain of the transistor Tr1, and one of the source and drain is connected to the wiring SL and the other is connected to the wiring RL.

[0216] The memory cell 30a holds the data potential input from the wiring BL through the transistor Tr1 at the node connected to the gate of the transistor Tr2, whereby data can be stored. In addition, by making the transistor Tr1 non-conductive, the data can be held. Further, in the transistor Tr2, the conduction state between the wiring SL and the wiring RL changes according to the potential held at the gate. For example, data can be read out according to the magnitude of the potential or current output to the other of the wiring SL and the wiring RL when a signal is supplied to one of them. Therefore, the memory cell 30a can be used as a memory capable of non-destructive readout.

[0217] In addition, a capacitor C can also be provided in Fig.14A the memory cell 30a shown. More specifically, the following structure can also be adopted: One electrode of the capacitor C is connected to the node connected to the other of the source and drain of the transistor Tr1 and the gate of the transistor Tr2. At this time, the other electrode of the capacitor C can be connected to the above-mentioned wiring PL. The capacitor C can have the same structure as the above-mentioned capacitor 50, or various MIM capacitors such as a parallel plate type, a cylindrical type, and a column type can be used.

[0218] Fig. 14B 、 Fig. 14C This is the cross-sectional view of the memory cell 30a. The memory cell 30a has a structure in which a transistor 10 is stacked on a transistor 70. The structure of the transistor 10 is the same as that of the above-mentioned memory cell 30.

[0219] The transistor 70 includes a conductive layer 74, a semiconductor layer 71, an insulating layer 72, a conductive layer 73, a conductive layer 75, etc. The transistor 70 is a vertical transistor provided in the region overlapping the opening 20c in the conductive layer 75, the insulating layers 47a, 47b, and 47c. The main difference between the transistor 70 and the transistor 10 lies in the structure of the upper electrode. Except for this, the transistor 70 can refer to the description of the transistor 10.

[0220] A conductive layer 74 is provided on the insulating layer 11, and insulating layers 47a, 47b, and 47c are stacked on the conductive layer 74. A conductive layer 75 is provided on the insulating layer 47c. The semiconductor layer 71 and the insulating layer 72 are provided along the inner wall of the opening 20c in the conductive layer 75, insulating layer 47a, insulating layer 47b, and insulating layer 47c. The semiconductor layer 71 is provided in contact with the top surface and side surface of the conductive layer 75, the side surfaces of the insulating layers 47a, 47b, and 47c, and the top surface of the conductive layer 74. The conductive layer 73 is provided to fill the insulating layer 48 and the opening 20c.

[0221] In Fig. 14B , Fig. 14C , the conductive layer 31 and the conductive layer 73 correspond to the gate of the transistor Tr2, the conductive layer 75 corresponds to one of the wirings SL and RL, and the conductive layer 74 corresponds to the other of the wirings SL and RL.

[0222] Fig.15A And Fig. 15B show an example of a storage device in which two storage units 30 are connected to the same wiring. Fig.15A is a top view schematic diagram of the storage device, Fig. 15B is along Fig.15A in the cross-sectional schematic diagram of the cut line A3 - A4.

[0223] The conductive layer 23 serving as the wiring WL is provided in two storage units 30 respectively. The conductive layer 32 serving as the wiring BL is provided in a manner shared by two storage units 30.

[0224] In addition, the conductive layer 32 serving as the wiring BL is embedded in each interlayer insulating layer and is electrically connected to the conductive layers 61 and 62 serving as plugs (also called connection electrodes). The conductive layer 61 can also be electrically connected to a sense amplifier (not shown) provided below the insulating layer 11. In addition, the conductive layer 61 can also be electrically connected to the conductive layer 32 of the storage unit stacked above the insulating layer 65.

[0225] The insulating layer 65 is used as a barrier layer and has a function of preventing impurities such as water and hydrogen from diffusing into the storage device from the outside.

[0226] In addition, by arranging the storage units 30 in a three-dimensional matrix, a storage unit array can be formed. As an example of the storage unit array, Fig.16A And Fig. 16B show an example of a storage device in which 4 × 2 × 4 storage units 30 are arranged in the X direction, Y direction, and Z direction. Fig.16A is a plan view of the storage device, Fig. 16B is along Fig.16A in the cross-sectional view of the cut line A3 - A4.

[0227] A group of four memory cells 30 may be referred to as a memory unit 60 . Fig.16A , Fig. 16B Eight memory cells (memory cell 60 [1, 1] to memory cell 60 [2, 4]) are shown. In memory cell 60 [a, b] (a, b are each a positive integer), a represents an address in the Y direction, and b represents an address in the Z direction.

[0228] The memory cell 60 is centered on the conductive layer 61 or the conductive layer 62, and each two memory cells 30 are arranged at symmetrical positions. The conductive layers 32 of each memory cell 60 stacked in the Z direction are electrically connected to each other through the conductive layer 62. In this way, by stacking a plurality of memory cells 60, the storage capacity per unit area can be increased, and a storage device capable of miniaturization or high integration can be provided.

[0229] Fig.17A and Fig. 17B An example is shown in which the connection portion is arranged at the end of the memory cell. Fig.17A is a plan view of the storage device, Fig. 17B is a cross-sectional view of a memory device. Here, as an example of a memory cell array, an example of a memory device configured with 3×3×m (m is an integer greater than or equal to 2) memory cells 30 is shown. Among the layers including the memory cells 30, the first layer is represented as layer 80[1], and the mth layer (uppermost layer) is represented as layer 80[m].

[0230] Conductive layer 63 is provided outside the memory cell. Conductive layer 63 may also be connected to wiring in a layer above layer 80 including conductive layer 63. For example, conductive layer 63 provided in layer 80[1] is electrically connected to wiring provided in layer 80[2]. In addition, without limitation thereto, conductive layer 63 may also be electrically connected to wiring in layer 80 below layer 80 including conductive layer 63.

[0231] Fig.18 An example of a cross-sectional structure of a memory device is shown in which a layer including the memory cell 30 is stacked on a layer provided with a driver circuit including a sense amplifier.

[0232] Fig.18 An example is shown in which a capacitor 50 is stacked above a transistor 90 and a transistor 10 thereon. The transistor 90 is one of the transistors in the sense amplifier.

[0233] By providing the sense amplifier so as to overlap with the memory cell 30, the bit line can be shortened. Thus, the load on the bit line can be reduced, and the read sensitivity of the sense amplifier can be improved. Therefore, the storage capacitance of the memory cell can be reduced.

[0234] A transistor 90 is disposed on a substrate 91 and includes a conductive layer 94 serving as a gate, an insulating layer 93 serving as a gate insulating layer, a semiconductor region 92 formed of a part of the substrate 91, and low-resistance regions 95a and 95b serving as a source region or a drain region. The transistor 90 can be a p-channel type or an n-channel type.

[0235] Here, in Fig.18 the illustrated transistor 90, the semiconductor region 92 (a part of the substrate 91) forming a channel has a convex shape. Further, the conductive layer 94 is disposed so as to cover side surfaces and a top surface of the semiconductor region 92 with the insulating layer 93 therebetween. Since the convex portion of the semiconductor substrate is utilized, such a transistor 90 is also referred to as a FIN type transistor.

[0236] Preferably, there is a structure in which an interlayer insulating layer and a wiring layer are alternately stacked (also referred to as a multilayer wiring layer) between the layer in which the transistor 90 is disposed and the layer in which the storage unit 30 is disposed. Fig.18 An example is shown in which the low-resistance region 95b of the transistor 90 is electrically connected to a conductive layer 32 serving as a bit line of the storage unit 30 through wiring and a plug.

[0237] At least a part of the present embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0238] (Embodiment 2) In the present embodiment, with reference to Figures 19 to 22 a storage device according to one aspect of the present invention will be described. In the present embodiment, a structural example of a storage device in which a layer including a storage unit is stacked on a layer including a driving circuit including a sense amplifier will be described.

[0239] <Structural Example of Storage Device> Fig.19 is a block diagram showing a structural example of a storage device 480 according to one aspect of the present invention. Fig.19 The illustrated storage device 480 includes a layer 420 and a stacked layer 470.

[0240] The layer 420 is a layer including Si transistors. In the layer 470, element layers 430[1] to 430[m] (m is an integer of 2 or more) are stacked. The element layers 430[1] to 430[m] are layers including OS transistors. The layer 470 in which the layers including OS transistors are stacked can be stacked on the layer 420.

[0241] Elements such as OS transistors and capacitors included in the element layers 430[1] to 430[m] constitute storage units. Fig.19An example is shown in which the element layers 430[1] to 430[m] include a plurality of memory cells 432 arranged in a matrix configuration of m rows and n columns (n is an integer of 2 or more).

[0242] In Fig.19 , the memory cell 432 in the first row and first column is represented as the memory cell 432[1, 1], and the memory cell 432 in the m-th row and n-th column is represented as the memory cell 432[m, n]. In addition, in the present embodiment and the like, an arbitrary row may sometimes be denoted as "the i-th row". In addition, an arbitrary column may sometimes be denoted as "the j-th column". Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less. In addition, in the present embodiment and the like, the memory cell 432 in the i-th row and j-th column is represented as the memory cell 432[i, j]. Note that in the present embodiment and the like, when expressed as "i + α" (α is a positive integer or a negative integer), "i + α" is not less than 1 and not greater than m. Similarly, when expressed as "j + α", "j + α" is not less than 1 and not greater than n.

[0243] In addition, as an example, Fig.19 m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction are shown. In the present embodiment and the like, the first (the first row) provided wiring WL is represented as the wiring WL[1], and the m-th (the m-th row) provided wiring WL is represented as the wiring WL[m]. Similarly, the first (the first row) provided wiring PL is represented as the wiring PL[1], and the m-th (the m-th row) provided wiring PL is represented as the wiring PL[m]. Similarly, the first (the first column) provided wiring BL is represented as the wiring BL[1], and the n-th (the n-th column) provided wiring BL is represented as the wiring BL[n]. Note that the number of layers of the element layers 430[1] to 430[m] and the number of wirings WL (and wirings PL) may also be different.

[0244] The plurality of memory cells 432 provided in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 432 provided in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0245] The wiring BL is used as a bit line for writing and reading data. The wiring WL is used as a word line for controlling the on or off (conductive state or non-conductive state) of an access transistor serving as a switch. The wiring PL is used as a constant potential line connected to a capacitor. In addition, a wiring for transmitting a back gate potential may be provided separately.

[0246] The memory cells 432 included in the element layers 430[1] to 430[m] are respectively connected to the sense amplifier 446 via the wiring BL. The wiring BL can be configured in a direction parallel or perpendicular to the substrate surface on which the layer 420 is provided. By forming the wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] with the wiring configured in the direction parallel to the substrate surface and the wiring configured in the direction perpendicular to the substrate surface, the wiring length between the element layer 430 and the sense amplifier 446 can be shortened. Since the signal transmission distance between the memory cell and the sense amplifier can be shortened and the resistance and parasitic capacitance of the bit line can be significantly reduced, power consumption and signal delay can be reduced. Thus, reduction of power consumption and signal delay of the storage device 480 can be achieved. In addition, it can operate even when the capacitance of the capacitor included in the memory cell 432 is reduced. Thus, miniaturization of the storage device 480 can be achieved.

[0247] The layer 420 includes the PSW 471 (power switch), the PSW 472, and the peripheral circuit 422. The peripheral circuit 422 includes the drive circuit 440, the control circuit 473 (Control Circuit), and the voltage generation circuit 474. Note that each circuit included in the layer 420 is a circuit including Si transistors.

[0248] In the storage device 480, each circuit, each signal, and each voltage can be appropriately selected or discarded as needed. Alternatively, other circuits or other signals can also be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and the signal RDA is a signal output to the outside. The signal CLK is a clock signal.

[0249] In addition, the signals BW, CE, and GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are signals for power gating control. In addition, the signals PON1 and PON2 can also be generated in the control circuit 473.

[0250] The control circuit 473 is a logic circuit having a function of controlling the overall operation of the storage device 480. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode of the storage device 480 (e.g., write operation, read operation). Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 to execute the above operation mode.

[0251] The voltage generation circuit 474 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 474. For example, when the signal WAKE is supplied with an H-level signal, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0252] The drive circuit 440 is a circuit for writing and reading data to and from the memory cell 432. The drive circuit 440 includes the above-mentioned sense amplifier 446 in addition to a row decoder 442 (Row Decoder), a column decoder 444 (Column Decoder), a row driver 443 (Row Driver), a column driver 445 (Column Driver), an input circuit 447 (Input Cir.), and an output circuit 448 (Output Cir.).

[0253] The row decoder 442 and the column decoder 444 have a function of decoding the signal ADDR. The row decoder 442 is a circuit for specifying the row to be accessed, and the column decoder 444 is a circuit for specifying the column to be accessed. The row driver 443 has a function of selecting the wiring WL specified by the row decoder 442. The column driver 445 has the following functions: a function of writing data to the memory cell 432; a function of reading data from the memory cell 432; a function of holding the read data, etc.

[0254] The input circuit 447 has a function of holding the signal WDA. The data held in the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is the data (Din) written to the memory cell 432. The data (Dout) read from the memory cell 432 by the column driver 445 is output to the output circuit 448. The output circuit 448 has a function of holding Dout. In addition, the output circuit 448 has a function of outputting Dout to the outside of the storage device 480. The data output from the output circuit 448 is the signal RDA.

[0255] The PSW 471 has a function of controlling the supply of VDD to the peripheral circuit 422. The PSW 472 has a function of controlling the supply of VHM to the row driver 443. Here, the high power supply voltage of the storage device 480 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high level, which is higher than VDD. The on and off of the PSW 471 are controlled by the signal PON1, and the on and off of the PSW 472 are controlled by the signal PON2. In Fig.19 In, the number of power supply domains supplied with VDD in the peripheral circuit 422 is 1, but it can also be multiple. At this time, a power switch can be set for each power supply domain.

[0256] The element layers 430[1] to 430[m] can be overlapped and arranged on the layer 420. Fig. 20A FIG. 480 is a perspective view of a storage device 480 showing a case where five (m = 5) element layers 430[1] to 430[5] are stacked on the layer 420.

[0257] In Fig. 20A , the element layer 430 provided in the first layer is denoted as the element layer 430[1], the element layer 430 provided in the second layer is denoted as the element layer 430[2], and the element layer 430 provided in the fifth layer is denoted as the element layer 430[5]. In addition, Fig. 20A FIG. 480 shows a wiring WL and a wiring PL extending in the X direction, and a wiring BL and a wiring BLB extending in the Y direction and the Z direction (a direction perpendicular to the surface of the substrate on which the drive circuit is provided). The wiring BLB is an inverted bit line. Note that, in order to make the drawings easier to understand, a part of the wiring WL and the wiring PL included in each of the element layers 430 is not shown.

[0258] Fig. 20B is an explanatory Fig. 20A FIG. 480 is a schematic diagram showing a structural example of a sense amplifier 446 connected to the wiring BL and the wiring BLB and a memory cell 432 included in the element layers 430[1] to 430[5] connected to the wiring BL and the wiring BLB. In addition, a structure in which a plurality of memory cells (memory cells 432) are electrically connected to one wiring BL and one wiring BLB is also referred to as a "memory string".

[0259] Fig. 20B FIG. 480 shows an example of the circuit structure of the memory cell 432 connected to the wiring BLB. The memory cell 432 includes a transistor 437 and a capacitor 438. Regarding the transistor 437, the capacitor 438, and each wiring (such as the wiring BL and the wiring WL), for example, the wiring BL[1] and the wiring WL[1] may be referred to as the wiring BL and the wiring WL, etc. As the memory cell 432, for example, the memory cell 30 shown in the above embodiment can be used. That is, as the transistor 437, the transistor 10 can be used, and as the capacitor 438, the capacitor 50 can be used. In addition, as the transistor included in the sense amplifier 446, the transistor 90 can be used (refer to Fig.18 ).

[0260] In the memory cell 432, one of the source and the drain of the transistor 437 is connected to the wiring BL. The other of the source and the drain of the transistor 437 is connected to one electrode of the capacitor 438. The other electrode of the capacitor 438 is connected to the wiring PL. The gate of the transistor 437 is connected to the wiring WL.

[0261] The wiring PL is a wiring for supplying a constant potential for maintaining the potential of the capacitor 438. By connecting a plurality of wirings PL and using them as one wiring, the number of wirings can be reduced.

[0262] In one aspect of the present invention, while the OS transistor is stacked, the wiring serving as the bit line is arranged in a direction perpendicular to the substrate surface on which the layer 420 is provided. Further, the transistors 437 and the capacitors 438 included in the memory cell 432 are arranged in a direction perpendicular to the substrate surface on which the layer 420 is provided. By arranging each element and each wiring in a direction perpendicular to the substrate surface, the wiring length between the element layers can be shortened, and the element density provided per unit area can be increased. Thereby, a memory device excellent in terms of reducing the storage capacity and power consumption can be realized.

[0263] [Structural examples of the memory cell 432 and the sense amplifier 446] Fig.21A and Fig.21B are a circuit diagram corresponding to the above-described memory cell 432 and a circuit block diagram corresponding to the circuit diagram. As Fig.21A and Fig.21B shown, the memory cell 432 is sometimes shown as a block in the drawings and the like. Further, in the case where the wiring BL shown in Fig.21A and Fig.21B is replaced with the wiring BLB, it can be similarly shown.

[0264] Further, Fig. 21C and Fig.21D are a circuit diagram corresponding to the above-described sense amplifier 446 and a circuit block diagram corresponding to the circuit diagram. In the sense amplifier 446, a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplifier circuit 485 are shown. Further, in addition to the wirings BL and BLB, wirings SA_OUT and SA_OUTB for outputting the read signal are also shown.

[0265] As Fig. 21C shown, the switch circuit 482 includes, for example, n-channel transistors 482_1 and 482_2. The transistors 482_1 and 482_2 switch the conduction states of the wiring pair of the wirings SA_OUT and SA_OUTB and the wiring pair of the wirings BL and BLB according to the signal CSEL.

[0266] As Fig. 21C shown, the precharge circuit 483 is composed of n-channel transistors 483_1 to 483_3. The precharge circuit 483 is a circuit for precharging the wirings BL and BLB to an intermediate potential VPRE equivalent to the potential VDD / 2 according to the signal EQ.

[0267] As Fig. 21CAs shown, the precharge circuit 484 is composed of p-channel transistors 484_1 to 484_3. The precharge circuit 484 is a circuit for precharging the wirings BL and BLB to an intermediate potential VPRE equivalent to VDD / 2 according to the signal EQB.

[0268] As Fig. 21C shown, the amplifier circuit 485 is composed of p-channel transistors 485_1, 485_2 connected to the wiring SAP or SAN and n-channel transistors 485_3, 485_4. The wiring SAP or SAN is a wiring having the function of supplying VDD or VSS. The transistors 485_1 to 485_4 are transistors constituting an inverter loop.

[0269] In addition, Fig.21D is a circuit block diagram corresponding to Fig. 21C the sense amplifier 446 described in etc. As Fig.21D shown, the sense amplifier 446 is sometimes shown as a block in the drawings or the like.

[0270] Fig. 22 is Fig.19 the circuit diagram of the storage device 480 of Fig. 22 In FIG. 21A to FIG. 21D the circuit blocks described in are used.

[0271] As Fig. 22 shown, the layer 470 having the element layer 430[m] includes the memory cells 432. As an example, Fig. 22 the memory cells 432 shown are connected to the paired wirings BL[1] and BLB[1] or the wirings BL[2] and BLB[2]. The memory cells 432 connected to the wiring BL are memory cells for writing or reading data.

[0272] The wirings BL[1] and BLB[1] are connected to the sense amplifier 446[1], and the wirings BL[2] and BLB[2] are connected to the sense amplifier 446[2]. The sense amplifiers 446[1] and 446[2] can read data according to Fig. 21C the various signals described in.

[0273] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0274] (Embodiment 3) In this embodiment, a structural example of a display device using a transistor according to one aspect of the present invention will be described.

[0275] The transistor according to one embodiment of the present invention can be formed to be extremely miniaturized, so a display device using the transistor according to one embodiment of the present invention can be a display device with extremely high definition. For example, a display device according to one embodiment of the present invention can be used for a display unit of information terminal devices (wearable devices) such as a watch type and a bracelet type, and a display unit of devices that can be worn on the head such as a VR device like a head-mounted display and a glasses-type AR device (HMD: Head Mounted Display).

[0276] [Display module] Fig.23A A perspective view showing the display module 280 is presented. The display module 280 includes a display device 200A and an FPC 290. Note that the display device included in the display module 280 is not limited to the display device 200A, and it can also be the display device 200B or the display device 200C which will be described later.

[0277] The display module 280 includes a substrate 291 and a substrate 292. The display module 280 includes a display unit 281. The display unit 281 is an area for displaying an image.

[0278] Fig. 23B A perspective schematic view showing the structure on the side of the substrate 291 is presented. A circuit unit 282 is laminated on the substrate 291, a pixel circuit unit 283 is on the circuit unit 282, and a pixel unit 284 is on the pixel circuit unit 283. In addition, a terminal unit 285 for connecting to the FPC 290 is provided on a portion of the substrate 291 that does not overlap with the pixel unit 284. The terminal unit 285 and the circuit unit 282 are electrically connected through a wiring portion 286 composed of a plurality of wirings.

[0279] The pixel unit 284 includes a plurality of pixels 284a arranged periodically. Fig. 23B An enlarged view of one pixel 284a is shown on the right side. The pixel 284a includes a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0280] The pixel circuit unit 283 includes a plurality of pixel circuits 283a arranged periodically. One pixel circuit 283a controls the light emission of three light-emitting elements included in one pixel 284a. One pixel circuit 283a may also include three circuits for controlling the light emission of one light-emitting element. For example, the pixel circuit 283a can adopt a structure having at least one selection transistor, one current control transistor (driving transistor), and a capacitor for one light-emitting element. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. Thus, an active matrix type display panel can be realized.

[0281] The circuit section 282 includes a circuit for driving each pixel circuit 283a of the pixel circuit section 283. For example, it preferably includes one or both of a gate line driving circuit and a source line driving circuit. In addition, it may also have at least one of an arithmetic circuit, a storage circuit, a power supply circuit, etc. In addition, the transistors provided in the circuit section 282 may also form part of the pixel circuit 283a. That is to say, the pixel circuit 283a may also be constituted by the transistors included in the pixel circuit section 283 and the transistors included in the circuit section 282.

[0282] The FPC 290 is used as a wiring for supplying a video signal, a power supply potential, etc. from the outside to the circuit section 282. In addition, an IC may also be mounted on the FPC 290.

[0283] The display module 280 may adopt a structure in which one or both of the pixel circuit section 283 and the circuit section 282 are overlapped and provided on the lower side of the pixel section 284, so the display section 281 can have an extremely high aperture ratio (effective display area ratio). For example, the aperture ratio of the display section 281 may be 40% or more and less than 100%, preferably 50% or more and 95% or less, more preferably 60% or more and 95% or less. In addition, the pixels 284a can be arranged with extremely high density, whereby the display section 281 can have extremely high definition. For example, the display section 281 preferably arranges the pixels 284a with a definition of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, further preferably 6000 ppi or more and 20000 ppi or less or 30000 ppi or less.

[0284] Such a display module 280 is very clear, so it is suitable for VR devices such as head-mounted displays or glasses-type AR devices. For example, because the display module 280 has a display section 281 with extremely high definition, in the structure of viewing the display section of the display module 280 through a lens, even if the display section is magnified by the lens, no pixels can be seen, whereby a display with a high sense of immersion can be realized. In addition, the display module 280 is not limited to this, and it can also be suitable for electronic devices with a relatively small display section. For example, it is suitable for the display section of wearable electronic devices such as watch-type devices.

[0285] [Display device 200A] Fig.24 The shown display device 200A includes a substrate 331, a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitor 240, and a transistor 320.

[0286] The substrate 331 corresponds to Fig.23A the substrate 291 in

[0287] The transistor 320 is a vertical-channel transistor using an oxide semiconductor in a semiconductor layer where a channel is formed. The transistor 320 includes a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a conductive layer 325, a conductive layer 326, etc.

[0288] The transistor 320 can use various transistors shown in Embodiment 1.

[0289] An insulating layer 332 is provided on a substrate 331. The insulating layer 332 is used as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from escaping from the semiconductor layer 321 to the insulating layer 332 side. As the insulating layer 332, for example, a film such as an alumina film, a hafnium oxide film, or a silicon nitride film, in which hydrogen or oxygen is less likely to diffuse compared to a silicon oxide film, can be used.

[0290] A conductive layer 327 is provided on the insulating layer 332, and a conductive layer 325 is provided on the conductive layer 327. A conductive layer 326 is provided on the conductive layer 325. An insulating layer 334 is provided on the conductive layer 326. An opening is provided in the insulating layer 334, and the semiconductor layer 321 and the insulating layer 323 are provided in the opening. A conductive layer 324 is provided on the insulating layer 323, and an insulating layer 328 is provided so as to cover the top surface and the side surfaces of the conductive layer 324. A conductive layer 326 is provided on the insulating layer 328 and the semiconductor layer 321. In addition, an insulating layer 264 is provided so as to cover the conductive layer 326.

[0291] The insulating layer 264 is used as an interlayer insulating layer. A barrier layer that prevents impurities such as water or hydrogen in the insulating layer 264, etc. from diffusing to the transistor 320 may also be provided between the insulating layer 264 and the insulating layer 254. As the barrier layer, the same insulating film as the insulating layer 332 can be used.

[0292] A plug 274 electrically connected to one of the conductive layers 326 is embedded in the insulating layer 264. Here, the plug 274 preferably includes a conductive layer 274a that covers the side surface of the opening of the insulating layer 264 and a part of the top surface of the conductive layer 326, and a conductive layer 274b that contacts the top surface of the conductive layer 274a. At this time, as the conductive layer 274a, a conductive material in which hydrogen and oxygen are less likely to diffuse is preferably used.

[0293] In addition, a capacitor 240 is provided on the insulating layer 264. The capacitor 240 includes a conductive layer 241, a conductive layer 245, and an insulating layer 243 located between them. The conductive layer 241 is used as one electrode of the capacitor 240, the conductive layer 245 is used as the other electrode of the capacitor 240, and the insulating layer 243 is used as the dielectric of the capacitor 240.

[0294] The conductive layer 241 is disposed on the insulating layer 264 and embedded in the insulating layer 254. The conductive layer 241 is electrically connected to the conductive layer 326 of the transistor 320 through the plug 274. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is disposed in a region overlapping with the conductive layer 241 with the insulating layer 243 therebetween.

[0295] An insulating layer 255a is provided to cover the capacitor 240. An insulating layer 255b is provided on the insulating layer 255a, and an insulating layer 255c is provided on the insulating layer 255b.

[0296] For the insulating layer 255a, the insulating layer 255b, and the insulating layer 255c, an inorganic insulating film can be appropriately used. For example, preferably, a silicon oxide film is used as the insulating layer 255a and the insulating layer 255c, and a silicon nitride film is used as the insulating layer 255b. Thereby, the insulating layer 255b can be used as an etching protection film. Although an example in which a part of the insulating layer 255c is etched to form a recess is shown in the present embodiment, a recess may not be provided in the insulating layer 255c.

[0297] A light-emitting element 110R, a light-emitting element 110G, and a light-emitting element 110B are provided on the insulating layer 255c.

[0298] The light-emitting element 110R includes a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G includes a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B includes a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are commonly provided in the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0299] The organic layer 112R included in the light-emitting element 110R contains at least a light-emitting organic compound that emits red light. The organic layer 112G included in the light-emitting element 110G contains at least a light-emitting organic compound that emits green light. The organic layer 112B included in the light-emitting element 110B contains at least a light-emitting organic compound that emits blue light. Each of the organic layer 112R, the organic layer 112G, and the organic layer 112B may also be referred to as an EL layer and includes at least a layer (light-emitting layer) containing a light-emitting organic compound.

[0300] Since the display device 200A forms light-emitting devices for each light-emitting color, the chromaticity change between low-luminance light emission and high-luminance light emission is small. In addition, since the organic layers 112R, 112G, and 112B are separated from each other, crosstalk between adjacent sub-pixels can be suppressed even when a high-definition display panel is used. Therefore, a display device with high definition and high display quality can be realized.

[0301] An insulating layer 125, a resin layer 126, and a layer 128 are provided in the region between adjacent light-emitting elements.

[0302] The pixel electrodes 111R, 111G, and 111B of the light-emitting elements are electrically connected to the conductive layer 326 of the transistor 320 through plugs 256 embedded in the insulating layers 255a, 255b, and 255c, a conductive layer 241 embedded in the insulating layer 254, and a plug 274. The height of the top surface of the insulating layer 255c is the same as or substantially the same as the height of the top surface of the plug 256. Various conductive materials can be used as the plug.

[0303] In addition, a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B. A substrate 170 is bonded to the protective layer 121 by an adhesive layer 171.

[0304] No insulating layer covering the top end portion of the pixel electrode 111 is provided between two adjacent pixel electrodes 111. Therefore, the interval between adjacent light-emitting elements can be made very small. Therefore, a display device with high definition or high resolution can be realized.

[0305] [Display device 200B] Hereinafter, a display device having a partial structure different from the above example will be described. Note that the same parts as those in the above example are referred to the above description, and the description may be omitted sometimes.

[0306] Fig.25 The shown display device 200B shows an example in which a transistor 320A, which is a planar transistor formed as a semiconductor layer on a plane, and a transistor 320B, which is a vertical channel transistor, are stacked. The transistor 320B has the same structure as the transistor 320 in the above display device 200A.

[0307] The transistor 320A includes a semiconductor layer 351, an insulating layer 353, a conductive layer 354, a pair of conductive layers 355, an insulating layer 356, and a conductive layer 357.

[0308] An insulating layer 352 is provided on the substrate 331. The insulating layer 352 is used as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from escaping from the semiconductor layer 351 to the insulating layer 352 side. As the insulating layer 352, for example, a film such as an alumina film, a hafnium oxide film, or a silicon nitride film, in which hydrogen or oxygen is less likely to diffuse compared to a silicon oxide film, can be used.

[0309] A conductive layer 357 is provided on an insulating layer 352, and an insulating layer 356 is provided so as to cover the conductive layer 357. The conductive layer 357 is used as a first gate electrode of a transistor 320A, and a part of the insulating layer 356 is used as a first gate insulating layer. At least a portion of the insulating layer 356 that contacts the semiconductor layer 351 is preferably an oxide insulating film such as a silicon oxide film. The top surface of the insulating layer 356 is preferably planarized.

[0310] A semiconductor layer 351 is provided on the insulating layer 356. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film that exhibits semiconductor characteristics. A pair of conductive layers 355 contact the semiconductor layer 351 and are used as source and drain electrodes.

[0311] An insulating layer 358 and an insulating layer 350 are provided so as to cover the top and side surfaces of the pair of conductive layers 355 and the side surface of the semiconductor layer 351. The insulating layer 358 is used as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and prevents oxygen from escaping from the semiconductor layer 351. As the insulating layer 358, the same insulating film as the above-mentioned insulating layer 352 can be used.

[0312] An opening reaching the semiconductor layer 351 is provided in the insulating layer 358 and the insulating layer 350. An insulating layer 353 that contacts the top surface of the semiconductor layer 351 and a conductive layer 354 are embedded inside the opening. The conductive layer 354 is used as a second gate electrode, and the insulating layer 353 is used as a second gate insulating layer.

[0313] The top surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are planarized so that their heights are the same or substantially the same, and an insulating layer 359 is provided so as to cover them. The insulating layer 359 is used as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 320. The insulating layer 359 can use the same insulating film as the above-mentioned insulating layer 352.

[0314] As the transistor 320, a structure in which two gates sandwich a semiconductor layer forming a channel is adopted. In addition, the transistor can also be driven by connecting the two gates and supplying the same signal to the two gates. Alternatively, the threshold voltage of the transistor can be controlled by supplying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0315] [Display device 200C] Fig.26 The shown display device 200C has a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a transistor 320 of a vertical channel transistor.

[0316] The transistor 310 is a transistor having a channel formation region in a substrate 301. As the substrate 301, for example, a semiconductor substrate such as a single crystal silicon substrate can be used. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 is used as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and is used as a gate insulating layer. The low-resistance region 312 is a region in the substrate 301 doped with impurities and is used as one of a source and a drain. The insulating layer 314 covers the side surfaces of the conductive layer 311.

[0317] In addition, between two adjacent transistors 310, an element isolation layer 315 is provided in a manner of being embedded in the substrate 301.

[0318] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0319] (Embodiment 4) In this embodiment, a structural example of a display device that can be used for manufacturing a transistor for one mode of using the present invention is described. The display device shown below can be used for the pixel portion 284 of the above-described Embodiment 3 and the like.

[0320] One mode of the present invention is a display device including a light-emitting element (also referred to as a light-emitting device). The display device includes two or more pixels having different light-emitting colors. Each pixel includes a light-emitting element. Each light-emitting element includes a pair of electrodes and an EL layer therebetween. The light-emitting element is preferably an organic EL element (organic electroluminescent element). Two or more light-emitting elements having different light-emitting colors each include an EL layer containing different light-emitting materials. For example, by including three light-emitting elements that respectively emit red (R), green (G), or blue (B) light, a full-color display device can be realized.

[0321] When manufacturing a display device including a plurality of light-emitting elements having different emission colors, it is necessary to form at least a layer containing a light-emitting material (light-emitting layer) into an island shape respectively. When forming a part or all of the EL layer respectively, there is known a method of forming an island-shaped organic film by an evaporation method using a shadow mask such as a metal mask. However, due to various influences such as the accuracy of the metal mask, the misalignment between the metal mask and the substrate, the flexure of the metal mask, and the vapor scattering, etc., the shape and position of the island-shaped organic film deviate from the shape and position at the design time, and it is difficult to achieve high definition and high aperture ratio of the display device. In addition, during evaporation, sometimes the thickness of the end portion becomes smaller due to the blurred contour of the layer. That is to say, sometimes the thickness of the island-shaped light-emitting layer is different depending on the position. In addition, when manufacturing a large-sized, high-resolution or high-definition display device, there is a concern as follows: due to the low dimensional accuracy of the metal mask and the deformation caused by heat, etc., the manufacturing yield decreases. Therefore, the following measures have been taken: by adopting a special pixel arrangement such as Pentile arrangement, the definition (also referred to as pixel density) is improved analogously.

[0322] Note that in this specification, etc., an island shape means a state in which two or more layers made of the same material formed in the same process are physically separated. For example, an island-shaped light-emitting layer means a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0323] In one aspect of the present invention, instead of using a shadow mask such as a fine metal mask (FMM), the EL layer is processed into a fine pattern by a photolithography method. Therefore, a display device having high definition and high aperture ratio, which has been difficult to achieve at present, can be realized. In addition, since the EL layer can be manufactured separately, a display device having a very vivid and high-contrast display quality can be realized. In addition, for example, both a metal mask and a photolithography method can also be used to process the EL layer into a fine pattern.

[0324] In addition, a part or all of the EL layer can be physically separated. Thereby, the leakage current between the light-emitting elements via a layer (also referred to as a common layer) shared by adjacent light-emitting elements can be suppressed. Therefore, the unintended light emission caused by crosstalk can be suppressed, and thus a display device having a very high contrast can be realized. In particular, a display device having a high current efficiency at low brightness can be realized.

[0325] One aspect of the present invention can also implement a display device that combines a light-emitting element that emits white light and a color filter. In this case, light-emitting elements having the same structure can be used as the light-emitting elements in pixels (sub-pixels) that emit different colors of light, and all layers in each light-emitting element can be common layers. Furthermore, a part or all of each EL layer can be cut using photolithography. Thereby, leakage current via the common layer can be suppressed, and a display device with high contrast can be realized. In particular, in an element having a tandem structure in which a plurality of light-emitting layers are stacked with an intermediate layer having high conductivity therebetween, leakage current via the intermediate layer can be effectively prevented, so a display device having high brightness, high definition, and high contrast can be realized.

[0326] When processing the EL layer using photolithography, sometimes deterioration occurs due to a part of the light-emitting layer being exposed. Therefore, it is preferable to provide an insulating layer that covers at least the side surfaces of the island-shaped light-emitting layer. This insulating layer can also cover a part of the top surface of the island-shaped EL layer. This insulating layer preferably uses a material that has a barrier property against water and oxygen. For example, an inorganic insulating film that does not easily allow water or oxygen to diffuse can be used. Thereby, deterioration of the EL layer can be suppressed, and a display device with high reliability can be realized.

[0327] In addition, there is a region (recess) between two adjacent light-emitting elements where the EL layer of each light-emitting element is not provided. When a common electrode or a common electrode and a common layer are formed so as to cover this recess, sometimes the common electrode is disconnected due to a step at the end of the EL layer (also referred to as disconnection), resulting in insulation of the common electrode on the EL layer. Thus, it is preferable to adopt a structure in which a resin layer used as a planarization film fills the local steps between two adjacent light-emitting elements (also referred to as LFP: Local Filling Planarization). This resin layer is used as a planarization film. Thereby, disconnection of the common layer or the common electrode can be suppressed, and a display device with high reliability can be realized.

[0328] Hereinafter, a more specific structural example of the display device according to one aspect of the present invention will be described with reference to the drawings.

[0329] [Structural Example 1] Fig.27A A plan view showing a display device 100 according to one aspect of the present invention is shown. The display device 100 includes a plurality of light-emitting elements 110R that emit red, a plurality of light-emitting elements 110G that emit green, and a plurality of light-emitting elements 110B that emit blue on a substrate 101. In Fig.27A In order to facilitate distinction between the light-emitting elements, symbols R, G, and B are attached in the light-emitting regions of the light-emitting elements.

[0330] The light-emitting elements 110R, 110G, and 110B are all arranged in a matrix. Fig.27AThe so-called stripe arrangement is shown in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light-emitting elements is not limited to this, and an S-stripe arrangement, a Delta arrangement, a Bayer arrangement, a zigzag arrangement, a Pentile arrangement, a Diamond arrangement, etc. can also be used.

[0331] As the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, for example, OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode) is preferably used. As the light-emitting substance contained in the EL element, for example, a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material) can be cited. As the light-emitting substance contained in the EL element, an inorganic compound (quantum dot material, etc.) can also be used in addition to an organic compound.

[0332] also, Fig.27A The connection electrode 111C is shown to be electrically connected to the common electrode 113. The connection electrode 111C is supplied with a potential (for example, an anode potential or a cathode potential) for supplying the common electrode 113. The connection electrode 111C is provided outside the display region where the light emitting elements 110R and the like are arranged.

[0333] The connection electrode 111C may be disposed along the periphery of the display region. For example, it may be disposed along one edge of the periphery of the display region, or it may be disposed across two or more edges of the periphery of the display region. That is, when the top surface of the display region is rectangular, the top surface of the connection electrode 111C may be in a strip shape (rectangle), L shape, "冂" shape (square bracket shape), or quadrilateral shape.

[0334] Fig.27B , Fig.27C They correspond to Fig.27A Schematic cross-sectional view of the dot-dashed line A1-A2 and the dot-dashed line A3-A4. Fig.27B Schematic cross-sectional view showing the light emitting element 110R, the light emitting element 110G and the light emitting element 110B, Fig.27C A schematic cross-sectional view of the connection portion 140 connecting the connection electrode 111C to the common electrode 113 is shown.

[0335] The light-emitting element 110R includes a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G includes a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B includes a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are commonly provided in the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0336] The organic layer 112R included in the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G included in the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B included in the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B may each also be referred to as an EL layer and at least include a layer (light-emitting layer) containing a light-emitting organic compound.

[0337] Hereinafter, when describing the common content among the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, it is sometimes described as the light-emitting element 110. Similarly, when describing the common content among the components distinguished by letters such as the organic layer 112R, the organic layer 112G, and the organic layer 112B, it is sometimes described using symbols omitting the letters.

[0338] The organic layer 112 and the common layer 114 may each independently include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the organic layer 112 has a stacked structure in which a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer are stacked from the pixel electrode 111 side, and the common layer 114 includes an electron injection layer.

[0339] The pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B are provided in each light-emitting element. In addition, the common electrode 113 and the common layer 114 are provided as a layer shared by the light-emitting elements. A conductive film having light transmittance to visible light is used for either the pixel electrodes or the common electrode 113, and a reflective conductive film is used for the other. By making each pixel electrode have light transmittance and making the common electrode 113 have reflectivity, a bottom-emission type (bottom-emission structure) display device can be realized. On the contrary, by making each pixel electrode have reflectivity and making the common electrode 113 have light transmittance, a top-emission type (top-emission structure) display device can be realized. In addition, by making both the pixel electrodes and the common electrode 113 have light transmittance, a double-sided emission type (double-sided emission structure) display device can also be realized.

[0340] A protective layer 121 is provided on the common electrode 113 so as to cover the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B. The protective layer 121 has a function of preventing impurities such as water from diffusing from above to each light-emitting element.

[0341] The end portion of the pixel electrode 111 preferably has a tapered shape. When the end portion of the pixel electrode 111 has a tapered shape, the organic layer 112 provided along the end portion of the pixel electrode 111 may also have a tapered shape. By making the side surface of the pixel electrode 111 have a tapered shape, the coverage of the organic layer 112 provided across the end portion of the pixel electrode 111 can be improved. In addition, by making the side surface of the pixel electrode 111 have a tapered shape, foreign matters (for example, dust or fine particles, etc.) in the manufacturing process can be easily removed by a washing process or the like, so it is preferable.

[0342] Note that in this specification, etc., the tapered shape means a shape in which at least a part of the side surface of a constituent element is inclined with respect to the substrate surface. For example, it preferably has a region where the angle (also referred to as the taper angle) formed by the inclined side surface and the substrate surface is less than 90°.

[0343] The organic layer 112 is processed into an island shape by photolithography. Therefore, the organic layer 112 has a shape in which the angle formed by the top surface and the side surface at its end portion is nearly 90 degrees. On the other hand, the thickness of the organic film formed using an FMM (Fine Metal Mask) or the like has a tendency to become thinner as it approaches the end portion. For example, the top surface in the range of 1 μm or more and 10 μm or less from the end portion is formed in a sloped shape, so it is difficult to distinguish the top surface from the side surface.

[0344] An insulating layer 125, a resin layer 126, and a layer 128 are provided between two adjacent light-emitting elements.

[0345] Between two adjacent light-emitting elements, the side surfaces of the respective organic layers 112 face each other across the resin layer 126. The resin layer 126 is located between two adjacent light-emitting elements and is provided so as to fill the end portions of the respective organic layers 112 and the region between the two organic layers 112. The top surface of the resin layer 126 has a smooth convex shape, and the common layer 114 and the common electrode 113 are provided so as to cover the top surface of the resin layer 126.

[0346] The resin layer 126 is used as a planarization film for filling the steps located between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent the common electrode 113 from being insulated on the organic layer 112 due to the phenomenon (also referred to as disconnection) in which the common electrode on the organic layer 112 is disconnected due to the steps at the end portions of the organic layer 112. The resin layer 126 may also be referred to as an LFP (Local Filling Planarization) layer.

[0347] As the resin layer 126, an insulating layer containing an organic material can be suitably used. For example, as the resin layer 126, an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimide amide resin, a silicone resin, a siloxane resin, a benzocyclobutene resin, a phenolic resin, or a precursor of the above resins can be used. In addition, as the resin layer 126, an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used.

[0348] In addition, as the resin layer 126, a photosensitive resin can also be used. As the photosensitive resin, a photoresist can also be used. The photosensitive resin can be a positive-type material or a negative-type material.

[0349] The resin layer 126 can also contain a material that absorbs visible light. For example, the resin layer 126 itself can be composed of a material that absorbs visible light, and the resin layer 126 can also contain a pigment that absorbs visible light. As the resin layer 126, for example, the following resins can be used: a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light; or a resin that contains carbon black as a pigment and is used as a black matrix; etc.

[0350] The insulating layer 125 is in side contact with the organic layer 112. In addition, the insulating layer 125 covers the upper end portion of the organic layer 112. In addition, a part of the insulating layer 125 is in contact with the top surface of the substrate 101.

[0351] The insulating layer 125 is located between the resin layer 126 and the organic layer 112 and is used as a protective film that prevents the resin layer 126 from contacting the organic layer 112. When the organic layer 112 is in contact with the resin layer 126, there is a possibility that the organic layer 112 is dissolved due to an organic solvent or the like used when forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, the side surface of the organic layer 112 can be protected.

[0352] The insulating layer 125 can be an insulating layer containing an inorganic material. As the insulating layer 125, for example, inorganic insulating films such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitrogen oxide insulating film can be used. The insulating layer 125 can have a single-layer structure or a laminated structure. As the oxide insulating film, examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. As the nitride insulating film, examples include a silicon nitride film and an aluminum nitride film. As the oxynitride insulating film, examples include a silicon oxynitride film and an aluminum oxynitride film. As the nitrogen oxide insulating film, examples include a silicon nitrogen oxide film and an aluminum nitrogen oxide film. In particular, by using a metal oxide film such as an aluminum oxide film or a hafnium oxide film formed by ALD method or an inorganic insulating film such as a silicon oxide film for the insulating layer 125, an insulating layer 125 with few pinholes and excellent function of protecting the EL layer can be formed.

[0353] Note that in this specification, etc., oxynitride refers to a material in which the oxygen content is more than the nitrogen content in its composition, while nitrogen oxide refers to a material in which the nitrogen content is more than the oxygen content in its composition. For example, when it is described as silicon oxynitride, it refers to a material in which the oxygen content is more than the nitrogen content in its composition, and when it is described as silicon nitrogen oxide, it refers to a material in which the nitrogen content is more than the oxygen content in its composition.

[0354] The insulating layer 125 can be formed by sputtering method, CVD method, PLD method, ALD method, etc. The insulating layer 125 is preferably formed by ALD method with good coverage.

[0355] In addition, by providing a reflective film (for example, a metal film containing one or more selected from silver, palladium, copper, titanium, and aluminum, etc.) between the insulating layer 125 and the resin layer 126, the light emitted from the light-emitting layer can be reflected by the reflective film. Thereby, the light extraction efficiency can be further improved.

[0356] The layer 128 is a part of the protective layer (also called mask layer, sacrificial layer) that remains to protect the organic layer 112 when etching the organic layer 112. The layer 128 can use the materials that can be used for the above insulating layer 125. In particular, it is preferable that both the layer 128 and the insulating layer 125 use the same material, so that the same processing devices, etc. can be used.

[0357] In particular, since metal oxide films such as aluminum oxide film and hafnium oxide film formed by ALD method and inorganic insulating films such as silicon oxide film are films with fewer pinholes and have excellent function of protecting the EL layer, they can be suitably used for the insulating layer 125 and the layer 128.

[0358] The protective layer 121 may, for example, have a single-layer structure or a laminated structure including at least an inorganic insulating film. As the inorganic insulating film, for example, oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film can be cited. Alternatively, semiconductor materials or conductive materials such as indium gallium oxide, indium zinc oxide, indium tin oxide, and indium gallium zinc oxide can also be used as the protective layer 121.

[0359] As the protective layer 121, a laminated film of an inorganic insulating film and an organic insulating film can also be used. For example, it is preferable to sandwich an organic insulating film between a pair of inorganic insulating films. In addition, the organic insulating film is preferably used as a planarization film. Therefore, the top surface of the organic insulating film can be made flat, so the coverage of the inorganic insulating film thereon is improved, and thus the barrier property can be improved. In addition, the top surface of the protective layer 121 becomes flat, so when a structure (for example, a color filter, an electrode of a touch sensor, or a lens array, etc.) is provided above the protective layer 121, the influence caused by the uneven shape of the underlying structure can be reduced, which is preferable.

[0360] Fig.27C A connection portion 140 showing the connection electrode 111C and the common electrode 113 being electrically connected is shown. In the connection portion 140, an opening is provided in the insulating layer 125 and the resin layer 126 on the connection electrode 111C. At this opening, the connection electrode 111C and the common electrode 113 are electrically connected.

[0361] Note that Fig.27C A connection portion 140 showing the connection electrode 111C and the common electrode 113 being electrically connected is shown, but the common electrode 113 can also be provided on the connection electrode 111C with the common layer 114 interposed therebetween. In particular, in the case where the carrier injection layer is used as the common layer 114, etc., the resistivity of the material for the common layer 114 is sufficiently low and its thickness is also very thin, so in many cases, there is no problem even if the common layer 114 is located in the connection portion 140. Thereby, the common electrode 113 and the common layer 114 can be formed using the same masking mask, so the manufacturing cost can be reduced.

[0362] [Structural Example 2] Hereinafter, a display device in which some structures are different from those in the above Structural Example 1 will be described. Note that the description of the parts that are the same as those in the above Structural Example 1 may be omitted with reference to the above Structural Example 1.

[0363] Fig.28A It is a cross-sectional schematic view of the display device 100a. The main differences between the display device 100a and the display device 100 are: the structure of the light-emitting element; and the former includes a coloring layer.

[0364] The display device 100a includes a light-emitting element 110W that emits white light. The light-emitting element 110W includes a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113. The organic layer 112W emits white light. For example, the organic layer 112W may include two or more light-emitting materials whose emission colors are in a complementary color relationship. For example, the organic layer 112W may include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. In addition, a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light may also be included.

[0365] Between two adjacent light-emitting elements 110W, the respective organic layers 112W are separated. Thereby, leakage current flowing between the adjacent light-emitting elements 110W through the organic layer 112W can be suppressed, and crosstalk due to the leakage current can be suppressed. Therefore, a display device with high contrast and color reproducibility can be realized.

[0366] An insulating layer 122 serving as a planarization film is provided on the protective layer 121, and a coloring layer 116R, a coloring layer 116G, and a coloring layer 116B are provided on the insulating layer 122.

[0367] As the insulating layer 122, an organic resin film or an inorganic insulating film whose top surface is planarized can be used. Since the insulating layer 122 is the surface on which the coloring layer 116R, the coloring layer 116G, and the coloring layer 116B are formed, the thickness of the coloring layer 116R etc. can be made uniform when the top surface of the insulating layer 122 is planar, thereby improving color purity. Note that when the thickness of the coloring layer 116R etc. is uneven, the light absorption amount varies depending on the region in the coloring layer 116R, which may cause a decrease in color purity.

[0368] [Structural Example 3] Fig.28B is a cross-sectional schematic view of the display device 100b.

[0369] The light-emitting element 110R includes a pixel electrode 111, a conductive layer 115R, an organic layer 112W, and a common electrode 113. The light-emitting element 110G includes a pixel electrode 111, a conductive layer 115G, an organic layer 112W, and a common electrode 113. The light-emitting element 110B includes a pixel electrode 111, a conductive layer 115B, an organic layer 112W, and a common electrode 113. The conductive layer 115R, the conductive layer 115G, and the conductive layer 115B all have light transmissivity and are used as optical adjustment layers.

[0370] A microcavity resonator (microcavity) structure can be achieved by using a film that reflects visible light as the pixel electrode 111 and a film that is both reflective and transmissive to visible light as the common electrode 113. At this time, by adjusting the thicknesses of the conductive layer 115R, the conductive layer 115G, and the conductive layer 115B in such a way as to achieve the most appropriate optical path length, even when using the organic layer 112 that emits white light, light of different wavelengths can be extracted from the light-emitting elements 110R, the light-emitting element 110G, and the light-emitting element 110B, and the enhanced light can be obtained.

[0371] Moreover, by providing the color filter layers 116R, the color filter layer 116G, and the color filter layer 116B on the optical paths of the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, respectively, light with high color purity can be extracted.

[0372] In addition, an insulating layer 123 that covers the ends of the pixel electrode 111 and the conductive layer 115 is provided. The end of the insulating layer 123 preferably has a tapered shape. By providing the insulating layer 123, the coverage of the organic layer 112W, the common electrode 113, the protective layer 121, etc. formed thereon can be improved.

[0373] The organic layer 112W and the common electrode 113 are provided as continuous films in each light-emitting element. By adopting such a structure, the manufacturing process of the display device can be greatly simplified, so it is preferable.

[0374] Here, the end of the pixel electrode 111 preferably has an almost vertical shape. As a result, a steeply inclined portion can be formed on the surface of the insulating layer 123, and a thin portion can be formed in a part of the organic layer 112W that covers this portion, or a part of the organic layer 112W can be separated. As a result, leakage current generated between adjacent light-emitting elements through the organic layer 112W can be suppressed without performing processing of the organic layer 112W using photolithography or the like.

[0375] The above describes an example of the structure of the display device.

[0376] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0377] (Embodiment 5) In this embodiment, an electronic device according to one aspect of the present invention is described with reference to FIGS. 29 to 31.

[0378] The electronic device of this embodiment includes a display panel (display device) using a transistor according to one aspect of the present invention in the display unit. The display device according to one aspect of the present invention can easily achieve high definition and high resolution, and in addition, high display quality can be achieved. Therefore, it can be used in the display units of various electronic devices.

[0379] As an electronic device, for example, in addition to electronic devices with a relatively large screen such as a television set, a desktop or notebook personal computer, a display for a computer or the like, a digital signage, a large game machine such as a pachinko machine, etc., a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproduction device, etc. can also be cited.

[0380] In particular, since the display panel according to one embodiment of the present invention can improve the clarity, it can be suitably used for an electronic device including a relatively small display unit. As such an electronic device, a watch-type and bracelet-type information terminal device (wearable device), a wearable device that can be worn on the head such as a VR device such as a head-mounted display, a glasses-type AR device, an MR device, etc. can be cited.

[0381] The display panel according to one embodiment of the present invention preferably has an extremely high resolution such as HD (number of pixels: 1280×720), FHD (number of pixels: 1920×1080), WQHD (number of pixels: 2560×1440), WQXGA (number of pixels: 2560×1600), 4K (number of pixels: 3840×2160), 8K (number of pixels: 7680×4320), etc. In particular, it is preferably set to a resolution of 4K, 8K or higher. In addition, the pixel density (clarity) in the display panel according to one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and further preferably 7000 ppi or more. By using the display panel having one or both of the above high resolution and high clarity, the sense of reality, the sense of depth, etc. can be further improved. In addition, there is no particular limitation on the screen ratio (aspect ratio) of the display panel according to one embodiment of the present invention. For example, the display panel can adapt to various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, etc.

[0382] The electronic device according to the present embodiment may also include a sensor (the sensor has a function of sensing, detecting, and measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays).

[0383] The electronic device of this embodiment can have various functions. For example, it can have the following functions: the function of displaying various information (static images, moving images, text images, etc.) on the display unit; the function of a touch panel; the function of displaying a calendar, date, time, etc.; the function of executing various software (programs); the function of performing wireless communication; the function of reading programs or data stored in a storage medium; etc.

[0384] Use FIG. 29A to FIG. 29D An example of a wearable device that can be worn on the head will be described. These wearable devices have one or both of the functions of displaying AR content and the function of displaying VR content. In addition, these wearable devices can also have the function of displaying content of SR or MR in addition to AR and VR. When the electronic device has the function of displaying at least one of the content of AR, VR, SR, and MR, etc., the immersion of the user can be improved.

[0385] Fig.29A The electronic device 700A shown and Fig.29B The electronic device 700B shown both include a pair of display panels 751, a pair of frames 721, a communication unit (not shown), a pair of mounting portions 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a bezel 757, and a pair of nose pads 758.

[0386] The display panel 751 can apply the display panel of one aspect of the present invention. Therefore, an electronic device capable of extremely high-definition display can be realized.

[0387] Both the electronic device 700A and the electronic device 700B can project the image displayed by the display panel 751 onto the display area 756 in the optical member 753. Since the optical member 753 has translucency, the user can see the image displayed in the display area overlapping with the transmitted image seen through the optical member 753. Therefore, both the electronic device 700A and the electronic device 700B are electronic devices capable of AR display.

[0388] In the electronic device 700A and the electronic device 700B, a camera capable of photographing the front can also be provided as the imaging unit. In addition, by providing an acceleration sensor such as a gyro sensor in the electronic device 700A and the electronic device 700B, the orientation of the user's head can be detected and the image corresponding to that direction can be displayed on the display area 756.

[0389] The communication unit has a wireless communication device, and an image signal, etc. can be supplied through this wireless communication device. In addition, instead of or in addition to the wireless communication device, a connector capable of connecting a cable for supplying an image signal and a power potential can be included.

[0390] In addition, the electronic device 700A and the electronic device 700B are provided with a battery and can be charged in one or both of a wireless manner and a wired manner.

[0391] The housing 721 may also be provided with a touch sensor module. The touch sensor module has a function of detecting whether the outer surface of the housing 721 is touched. Through the touch sensor module, various processes can be executed by detecting a tap operation or a swipe operation of the user, etc. For example, through a tap operation, processes such as temporarily stopping or restarting a moving image can be executed, and through a swipe operation, processes such as fast forward and rewind can be executed, etc. In addition, by providing a touch sensor module in each of the two housings 721, the operation range can be expanded.

[0392] As the touch sensor module, various touch sensors can be used. For example, various methods such as a capacitive method, a resistive film method, an infrared method, an electromagnetic induction method, a surface acoustic wave method, and an optical method can be adopted. In particular, it is preferable to apply a sensor of the capacitive method or the optical method to the touch sensor module.

[0393] When using an optical touch sensor, a photoelectric conversion device (also referred to as a photoelectric conversion element) can be used as a light receiving device (also referred to as a light receiving element). One or both of an inorganic semiconductor and an organic semiconductor can be used in the active layer of the photoelectric conversion device.

[0394] Fig.29C The illustrated electronic device 800A and Fig.29D the illustrated electronic device 800B both include a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0395] The display unit 820 can apply a display panel of one aspect of the present invention. Therefore, an electronic device capable of performing extremely clear display can be realized. Thus, the user can experience a high sense of immersion.

[0396] The display unit 820 is provided at a position inside the housing 821 where it can be seen through the lens 832. In addition, by displaying different images on each of the pair of display units 820, three-dimensional display using parallax can be performed.

[0397] Both the electronic device 800A and the electronic device 800B can be referred to as VR electronic devices. A user wearing the electronic device 800A or the electronic device 800B can see the image displayed on the display unit 820 through the lens 832.

[0398] The electronic device 800A and the electronic device 800B preferably have a mechanism in which the left - right positions of the lens 832 and the display unit 820 can be adjusted so that the lens 832 and the display unit 820 are located at the most suitable positions according to the position of the user's eyes. In addition, it preferably has a mechanism in which the focus is adjusted by changing the distance between the lens 832 and the display unit 820.

[0399] The user can mount the electronic device 800A or the electronic device 800B on the head using the mounting part 823. Additionally, Fig.29C Examples in which the mounting part 823 has a shape such as the temple of glasses (also called temple wires, etc.) are shown, but it is not limited thereto. As long as the user can mount it, the mounting part 823 can have, for example, a helmet - type or band - type shape.

[0400] The imaging unit 825 has a function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras can also be provided to be able to correspond to various perspectives such as telephoto and wide - angle.

[0401] Note that an example including the imaging unit 825 is shown here, and a distance measurement sensor (hereinafter, also called a detection unit) capable of measuring the distance to an object may be provided. In other words, the imaging unit 825 is one form of the detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as a lidar (Light Detection and Ranging) can be used. By using the image acquired by the camera and the image acquired by the distance image sensor, more information can be obtained, and more accurate attitude operations can be achieved.

[0402] The electronic device 800A may also include a vibration mechanism used as a bone - conduction headphone. For example, as one or more of the display unit 820, the housing 821, and the mounting part 823, a structure including this vibration mechanism can be adopted. Thus, there is no need to separately provide audio devices such as over - the - ear headphones, earphones, or speakers, and the user can enjoy images and sounds just by mounting the electronic device 800A.

[0403] The electronic device 800A and the electronic device 800B may also both include input terminals. Cables for supplying video signals from video output devices, etc., and power for charging the battery provided in the electronic device can be connected to the input terminals.

[0404] The electronic device according to one aspect of the present invention may also have a function of wirelessly communicating with the headphone 750. The headphone 750 includes a communication unit (not shown) and has a wireless communication function. The headphone 750 can receive information (such as audio data) from the electronic device through the wireless communication function. For example, Fig.29A The illustrated electronic device 700A has a function of transmitting information to the earphone 750 through a wireless communication function. In addition, for example Fig.29C The illustrated electronic device 800A has a function of transmitting information to the earphone 750 through a wireless communication function.

[0405] In addition, the electronic device may also include an earphone unit. Fig.29B The illustrated electronic device 700B includes an earphone unit 727. For example, a structure in which the earphone unit 727 and the control unit are connected in a wired manner may be adopted. A part of the wiring connecting the earphone unit 727 and the control unit may also be arranged inside the housing 721 or the mounting portion 723.

[0406] Similarly, Fig.29D The illustrated electronic device 800B includes an earphone unit 827. For example, a structure in which the earphone unit 827 and the control unit 824 are connected in a wired manner may be adopted. A part of the wiring connecting the earphone unit 827 and the control unit 824 may also be arranged inside the housing 821 or the mounting portion 823. In addition, the earphone unit 827 and the mounting portion 823 may also include magnets. Thus, it is preferable because the earphone unit 827 can be fixed to the mounting portion 823 by magnetic force and storage becomes easy.

[0407] In addition, the electronic device may also include a sound output terminal that can be connected to an earphone or a headset, etc. In addition, the electronic device may also include one or both of a sound input terminal and a sound input mechanism. As the sound input mechanism, for example, a sound collection device such as a microphone may be used. By providing the sound input mechanism to the electronic device, the electronic device can have a so-called headset function.

[0408] Thus, as the electronic device according to one aspect of the present invention, both the glasses type (such as the electronic device 700A and the electronic device 700B) and the goggles type (such as the electronic device 800A and the electronic device 800B) are preferable.

[0409] Fig. 30A The illustrated electronic device 6500 is a portable information terminal device that can be used as a smart phone.

[0410] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, etc. The display unit 6502 has a touch panel function. In addition, the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one embodiment of the present invention can be used for the display unit 6502, the control device 6509, etc. By using a semiconductor device according to one embodiment of the present invention for the control device 6509, power consumption can be reduced, which is therefore preferable.

[0411] The display unit 6502 can use a display panel according to one embodiment of the present invention.

[0412] Fig. 30B It is a schematic cross-sectional view of an end on the microphone 6506 side including the housing 6501.

[0413] A protective member 6510 having translucency is provided on the display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are provided in a space surrounded by the housing 6501 and the protective member 6510.

[0414] The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 using an adhesive layer (not shown).

[0415] In a region outside the display unit 6502, a part of the display panel 6511 is folded, and an FPC 6515 is connected to the folded part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on the printed circuit board 6517.

[0416] The display panel 6511 can use a flexible display according to one embodiment of the present invention. Thereby, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while suppressing the thickness of the electronic device. In addition, by folding a part of the display panel 6511 to provide a connection portion with the FPC 6515 on the back surface of the pixel portion, a narrow-bezel electronic device can be realized.

[0417] Fig. 30C An example of a television device is shown. In the television device 7100, the display unit 7000 is assembled in the housing 7101. A structure in which the housing 7101 is supported by a bracket 7103 is shown here.

[0418] It can be performed by using operation switches provided in the housing 7101 and a separately provided remote controller 7111 Fig. 30C Operation of the television apparatus 7100 shown. Alternatively, a touch sensor may be provided in the display unit 7000, and the television apparatus 7100 may be operated by touching the display unit 7000 with a finger or the like. In addition, a display unit for displaying information output from the remote controller 7111 may be provided in the remote controller 7111. By using the operation keys or the touch panel provided in the remote controller 7111, channel and volume operations can be performed, and the image displayed on the display unit 7000 can be operated on.

[0419] In addition, the television apparatus 7100 includes a receiver, a modem, etc. General television broadcasts can be received by using the receiver. Furthermore, by connecting to a communication network in a wired or wireless manner through the modem, one-way (from the sender to the receiver) or two-way (between the sender and the receiver or between the receivers, etc.) information communication can be performed.

[0420] Fig.30D An example of a notebook personal computer is shown. The notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, etc. The display unit 7000 is assembled in the housing 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be used for the display unit 7000, the control device 7216, etc. By using a semiconductor device according to one aspect of the present invention for the control device 7216, power consumption can be reduced, which is therefore preferable.

[0421] Fig.30E and Fig.30F An example of a digital signage is shown.

[0422] Fig.30E The digital signage 7300 shown includes a housing 7301, a display unit 7000, a speaker 7303, etc. In addition, it may further include an LED lamp, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

[0423] Fig.30F A digital signage 7400 provided on a cylindrical column 7401 is shown. The digital signage 7400 includes a display unit 7000 provided along the curved surface of the column 7401.

[0424] The larger the display unit 7000 is, the more information can be provided at one time. The larger the display unit 7000 is, the more likely it is to attract people's attention, and for example, the advertising effect can be improved.

[0425] By using the touch panel for the display unit 7000, not only can static images or dynamic images be displayed on the display unit 7000, but also the user can intuitively operate it, so it is preferable. In addition, when used for providing information such as route information or traffic information, the usability can be improved by intuitive operations.

[0426] As Fig.30E and Fig.30F shown, the digital signage 7300 or the digital signage 7400 preferably can be linked with information terminal devices 7311 or 7411 such as smartphones carried by the user through wireless communication. For example, the advertisement information displayed on the display unit 7000 can be displayed on the screens of the information terminal devices 7311 or 7411. In addition, by operating the information terminal devices 7311 or 7411, the display of the display unit 7000 can be switched.

[0427] In addition, games can be executed on the digital signage 7300 or the digital signage 7400 with the screens of the information terminal devices 7311 or 7411 as the operation units (controllers). Thus, multiple unspecified users can participate in the game simultaneously and enjoy the fun of the game.

[0428] In FIG. 30C to FIG. 30F this case, the display panel of one mode of the present invention can be used for the display unit 7000.

[0429] FIG. 31A to FIG. 31G The electronic device shown includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, a sensor 9007 (the sensor has the function of sensing, detecting, or measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays), a microphone 9008, etc.

[0430] FIG. 31A to FIG. 31GThe electronic device shown has various functions. For example, it can have the following functions: a function of displaying various information (such as still images, moving images, and text images) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of controlling processing by using various software (programs); a function of performing wireless communication; a function of reading and processing programs or data stored in a storage medium; etc. Note that the functions of the electronic device are not limited to the above functions, but can have various functions. The electronic device may include a plurality of display units. In addition, a camera or the like may be provided in the electronic device so that it has the following functions: a function of capturing a still image or a moving image and storing the captured image in a storage medium (an external storage medium or a storage medium built in the camera); a function of displaying the captured image on the display unit; etc.

[0431] Next, a detailed description will be given of FIG. 31A to FIG. 31G the electronic device shown.

[0432] Fig.31A is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used as a smart phone, for example. Note that in the portable information terminal 9101, a speaker 9003, a connection terminal 9006, a sensor 9007, etc. may also be provided. In addition, as the portable information terminal 9101, text or image information can be displayed on its multiple faces. In Fig.31A an example of displaying three icons 9050 is shown. In addition, information 9051 shown by a dotted rectangle can also be displayed on other faces of the display unit 9001. As an example of the information 9051, information indicating receipt of an e-mail, SNS, or phone call, etc.; a title of an e-mail or SNS, etc.; a sender's name of an e-mail or SNS, etc.; a date; a time; a battery level; and a radio wave intensity, etc. can be cited. Alternatively, icons 9050, etc. may also be displayed at the position where the information 9051 is displayed.

[0433] Fig.31B is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on more than three faces of the display unit 9001. Here, an example of information 9052, information 9053, and information 9054 being displayed on different faces respectively is shown. For example, in a state where the portable information terminal 9102 is placed in an upper pocket, the user can confirm the information 9053 displayed at a position seen from above the portable information terminal 9102. For example, the user can confirm this display without taking out the portable information terminal 9102 from the pocket, and thus can determine whether to answer a call.

[0434] Fig.31CFIG. 0 is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 can execute various application programs such as a mobile phone, reading and editing of e-mails and articles, playing music, network communication, and computer games. The tablet terminal 9103 includes a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front surface of the housing 9000, operation keys 9005 serving as operation buttons on the left side surface of the housing 9000, and connection terminals 9006 on the bottom surface.

[0435] Fig.31D FIG. 4 is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can be used as, for example, a smart watch (registered trademark). In addition, the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. Further, the portable information terminal 9200 can perform hands-free calling by communicating with a headset capable of wireless communication, for example. Further, by using the connection terminals 9006, the portable information terminal 9200 can perform data transmission with other information terminals or can be charged. Further, charging can also be performed by wireless power supply.

[0436] FIG. 31E to FIG. 31G FIG. 8 is a perspective view showing a foldable portable information terminal 9201. Further, Fig.31E FIG. 10 is a perspective view of a state in which the portable information terminal 9201 is unfolded, Figure 31G FIG. 12 is a perspective view of a folded state, Fig.31F FIG. 14 is a perspective view of an intermediate state when converting from one of the state of Fig.31E and the state of Figure 31G to the other. The portable information terminal 9201 has good portability in the folded state, and has strong display browsability in the unfolded state because it has a seamless and spliced large display area. The display unit 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. The display unit 9001 can be bent, for example, in a range where the radius of curvature is 0.1 mm or more and 150 mm or less.

[0437] At least a part of the present embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0438] (Embodiment 6) In the present embodiment, an application example of a semiconductor device according to one aspect of the present invention will be described. For example, a semiconductor device according to one aspect of the present invention can be used for electronic components, electronic devices, mainframes, space devices, and data centers (also referred to as Data Center: DC). Electronic components, electronic devices, mainframes, space devices, and data centers using a semiconductor device according to one aspect of the present invention are effective for realizing high performance such as low power consumption.

[0439] The electronic components, etc. of the semiconductor device using one mode of the present invention can be applied to the electronic device shown in Embodiment 5.

[0440] [Electronic component] Fig.32A A perspective view showing a substrate (circuit board 704) on which an electronic component 700 is mounted is shown. Fig.32A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. In Fig.32A , a part of the electronic component 700 is omitted from the description to show its interior. The electronic component 700 includes lands 712 outside the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 through leads 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of the above-described electronic components and electrically connecting them to the printed circuit board 702 respectively, the circuit board 704 is completed.

[0441] In addition, the semiconductor device 710 includes a drive circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The stacked structure of the drive circuit layer 715 and the storage layer 716 can be a monolithic stacked structure. In the monolithic stacked structure, through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding are not required to connect between the layers. When the drive circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0442] In addition, by adopting the on-chip memory structure, compared with the technology using through-electrodes such as TSV, the size of connection wirings, etc. can be reduced, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, and thus the memory bandwidth (also referred to as memory bandwidth) can be increased.

[0443] In addition, preferably, OS transistors are used to form a plurality of memory cell arrays in the memory layer 716, and the plurality of memory cell arrays are stacked in a monolithic manner. When the plurality of memory cell arrays are monolithically stacked, one or both of the bandwidth of the memory and the access latency of the memory can be improved. Bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between access and the start of data exchange. When Si transistors are used in the memory layer 716, it is difficult to have a monolithic stacking structure compared with the case of using OS transistors. Therefore, in a monolithic stacking structure, OS transistors are superior to Si transistors.

[0444] In addition, the semiconductor device 710 may be referred to as a die. In the present specification and the like, a die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also referred to as a wafer) or the like in the manufacturing process of a semiconductor chip and cutting it into rectangular small pieces. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also referred to as a silicon wafer) is sometimes referred to as a silicon die.

[0445] Next, Fig.32B A perspective view of the electronic component 730 is shown. The electronic component 730 is an example of a SiP (System in Package) or an MCM (MultiChip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0446] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM: High Bandwidth Memory). In addition, the semiconductor device 735 can be used for integrated circuits such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0447] The package substrate 732 can use, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can use, for example, a silicon interposer or a resin interposer.

[0448] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are composed of a single layer or multiple layers. In addition, the interposer 731 functions to electrically connect the integrated circuits provided on the interposer 731 with the electrodes provided on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or an "intermediate substrate". In addition, sometimes the integrated circuit and the package substrate 732 are electrically connected by providing a through electrode in the interposer 731 and using this through electrode. In addition, in the case of using a silicon interposer, TSV can also be used as the through electrode.

[0449] In HBM, in order to achieve a wide memory bandwidth, many wirings need to be connected. For this purpose, it is required that fine wirings can be formed at a high density on the interposer on which HBM is installed. Therefore, a silicon interposer is preferably used as the interposer for installing HBM.

[0450] In addition, in SiP, MCM, etc. that use a silicon interposer, it is not easy to cause a decrease in reliability due to the difference in the coefficient of thermal expansion between the integrated circuit and the interposer. In addition, due to the high surface flatness of the silicon interposer, it is not easy to generate poor connections between the integrated circuits provided on the silicon interposer and the silicon interposer. It is particularly preferable to use a silicon interposer for a 2.5D package (2.5D mounting), in which multiple integrated circuits are arranged horizontally and disposed on the interposer.

[0451] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches by using a silicon interposer, TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when trying to reduce the size of the electronic component 730, the width of the above terminal pitch becomes a problem, and it is sometimes difficult to set multiple wirings required to achieve a wide memory bandwidth. Thus, as described above, it is preferable to adopt a monolithic stacked structure using OS transistors. In addition, a composite structure combining a memory cell array with TSV stacked and a memory cell array of a monolithic stacked structure can also be adopted.

[0452] In addition, a heat sink (heat dissipation plate) can also be provided overlapping the electronic component 730. In the case of providing a heat sink, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in the present embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0453] In order to mount the electronic component 730 on another substrate, electrodes 733 can also be provided at the bottom of the package substrate 732. Fig.32BAn example of forming the electrode 733 with solder balls is shown. By arranging solder balls in a matrix at the bottom of the package substrate 732, the installation of BGA (Ball Grid Array) can be achieved. In addition, the electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix at the bottom of the package substrate 732, the installation of PGA (Pin Grid Array) can be achieved.

[0454] The electronic component 730 can be installed on other substrates by various installation methods, not limited to BGA and PGA. As installation methods, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package) can be cited.

[0455] [Mainframe computer] Fig.33A A perspective view of the mainframe computer 5600 is shown. In the mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in the rack 5610. In addition, the mainframe computer 5600 can also be referred to as a supercomputer.

[0456] Figure 33B A perspective view showing an example of the computer 5620 is shown. The computer 5620 includes a motherboard 5630. A plurality of slots 5631 and a plurality of connection terminals are provided on the motherboard 5630. A personal computer card 5621 is inserted into the slot 5631. And, the personal computer card 5621 includes connection terminals 5623, 5624, 5625, which are connected to the motherboard 5630.

[0457] Figure 33C An example of the personal computer card 5621 is shown. The personal computer card 5621 is, for example, a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 includes a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and a connection terminal 5629, etc. mounted on the board 5622. In addition, Figure 33C Components other than the electronic components 5626, 5627, and 5628 are also shown.

[0458] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. For example, PCIe etc. can be cited as the specifications of the connection terminal 5629.

[0459] The connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for supplying power to the personal computer card 5621 or inputting signals etc. In addition, for example, it can be used as an interface for outputting signals calculated by the personal computer card 5621 etc. For example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. can be cited as the specifications of the connection terminals 5623, 5624, and 5625 respectively. In addition, when outputting a video signal from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark), etc. can be cited as the specifications for each.

[0460] The electronic component 5626 includes terminals (not shown) for inputting and outputting signals, and the electronic component 5626 can be electrically connected to the board 5622 by inserting these terminals into the socket (not shown) included in the board 5622.

[0461] The electronic components 5627 and 5628 include a plurality of terminals, and the electronic components 5627 and 5628 can be installed, for example, by soldering these terminals to the wiring included in the board 5622 by reflow soldering. For example, FPGA, GPU, CPU, etc. can be cited as the electronic component 5627. For example, the electronic component 730 can be used as the electronic component 5627. For example, a storage device etc. can be cited as the electronic component 5628. For example, the electronic component 700 can be used as the electronic component 5628.

[0462] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

[0463] [Space equipment] A semiconductor device according to one aspect of the present invention can be applied to space equipment.

[0464] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor has small changes in electrical characteristics caused by irradiation with radiation. In other words, it has high resistance to radiation, so it can be appropriately used even in an environment where radiation may enter. For example, the OS transistor can be appropriately used when used in space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, a satellite, or a space probe. As radiation, for example, X-rays and neutron rays can be cited. Note that space, for example, refers to a height of 100 km or more, but the space shown in this specification may also include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0465] In Figure 34A as an example of a space device, a satellite 6800 is shown. The satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In addition, Figure 34A an example where there is a planet 6804 in space is shown.

[0466] In addition, although Figure 34A not shown in the figure, a battery management system (also referred to as BMS) or a battery control circuit can also be provided in the secondary battery 6805. When the OS transistor is used in the above battery management system or battery control circuit, low power consumption can be achieved, and high reliability can be achieved even in space, so it is preferable.

[0467] In addition, space is an environment where the radiation dose is 100 times or more that of the ground. In addition, as radiation, for example, electromagnetic waves (electromagnetic radiation) typified by X-rays and γ-rays; and particle radiation typified by α-rays, β-rays, neutron rays, proton rays, heavy ion rays, meson rays, etc. can be cited.

[0468] When sunlight shines on the solar panel 6802, the electric power required for the satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar panel or when the amount of sunlight shining on the solar panel is small, the amount of generated electric power decreases. Therefore, it is possible that the electric power required for the satellite 6800 to operate is not generated. In order to make the satellite 6800 operate even when the generated electric power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. In addition, the solar panel is sometimes referred to as a solar cell module.

[0469] The artificial satellite 6800 can generate signals. The signals are transmitted through the antenna 6803 and can be received by, for example, a receiver on the ground or other artificial satellites. By receiving the signals transmitted by the artificial satellite 6800, the position of the receiver that receives the signals can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0470] In addition, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is constituted by, for example, one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, a semiconductor device including an OS transistor according to one aspect of the present invention is preferably used. Compared with Si transistors, the OS transistor has less change in electrical characteristics due to being irradiated with radiation. In other words, the OS transistor has high reliability and can be appropriately used even in an environment where radiation may enter.

[0471] In addition, the artificial satellite 6800 can include sensors. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected by an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays released from the earth's surface. Thus, the artificial satellite 6800 can be used as, for example, an earth observation satellite.

[0472] Note that in the present embodiment, an artificial satellite is shown as an example of a space device, but it is not limited thereto. For example, a semiconductor device according to one aspect of the present invention can be appropriately applied to space devices such as spacecrafts, space capsules, and space probes.

[0473] As described above, compared with Si transistors, the OS transistor has excellent effects such as enabling a wider memory bandwidth and high resistance to radiation.

[0474] [Data Center] For example, a semiconductor device according to one aspect of the present invention can be applied to a storage system adopted in a data center or the like. A data center is required to ensure data immutability and perform long-term management of data. When performing long-term management of data, it is necessary to make the facility large-scale, such as setting up storage and servers for storing a huge amount of data, ensuring stable power to maintain the data, or ensuring cooling equipment required during data retention.

[0475] By using a semiconductor device according to one aspect of the present invention for the storage system adopted in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, reduce the scale of the cooling equipment, etc. Thus, it is possible to save space in the data center.

[0476] In addition, the power consumption of the semiconductor device according to one embodiment of the present invention is low, so that the circuit heat generation can be reduced. As a result, the negative impacts on the circuit itself, the peripheral circuits, and the modules caused by such heat generation can be reduced. In addition, by using the semiconductor device according to one embodiment of the present invention, a data center that can operate stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0477] Figure 34B A storage system applicable to a data center is shown. Figure 34B The storage system 6000 shown includes a plurality of servers 6001sb as a host 6001 (illustrated as a main computer). In addition, a plurality of storage devices 6003md are included as a storage 6003 (illustrated as a storage). The form in which the host 6001 and the storage 6003 are connected through a storage area network 6004 (illustrated as a SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as a storage controller) is shown.

[0478] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 can also be connected to each other through a network.

[0479] In the storage 6003, by using a flash memory, the access speed of data is shortened, that is, the time required for storing and outputting data is shortened. However, this time is much longer than the time required for a DRAM that can be used as a cache memory in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 6003, a cache memory is generally provided in the storage to shorten the time required for storing and outputting data.

[0480] The above cache memory is used in the storage control circuit 6002 and the storage 6003. The data exchanged between the host 6001 and the storage 6003 is output to the host 6001 or the storage 6003 after being stored in the cache memory in the storage control circuit 6002 and the storage 6003.

[0481] When an OS transistor is used as a transistor for storing the data of the above cache memory to hold the potential corresponding to the data, the refresh frequency can be reduced to lower the power consumption. In addition, miniaturization can be achieved by stacking the memory cell arrays.

[0482] Note that by using the semiconductor device according to one embodiment of the present invention for one or more selected from electronic components, electronic devices, mainframe computers, space devices, and data centers, an effect of reducing power consumption can be expected. Therefore, although it is currently considered that the energy demand increases with the high performance or high integration of semiconductor devices, by using the semiconductor device according to one embodiment of the present invention, it is also possible to reduce the emissions of greenhouse gases represented by carbon dioxide (CO2). In addition, since the semiconductor device according to one embodiment of the present invention has low power consumption, it is also effective as a measure against global warming.

[0483] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification. [Symbol Explanation]

[0484] 10a: transistor, 10b: transistor, 10c: transistor, 10d: transistor, 10e: transistor, 10f: transistor, 10g: transistor, 10h: transistor, 10i: transistor, 10j: transistor, 10: transistor, 11: insulating layer, 15f: insulating film, 15: insulating layer, 16f: insulating film, 16: insulating layer, 17f: insulating film, 17: insulating layer, 20a: opening, 20b: opening, 20c: opening, 21f: semiconductor film, 21i: channel formation region, 21n: low resistance region, 21: semiconductor layer, 22: insulating layer, 23: conductive layer, 26: conductive layer, 30a: memory cell, 30: memory cell, 31: conductive layer, 32: conductive layer, 34: conductive layer, 41a: insulating layer, 41b: insulating layer, 41c: insulating layer, 41: insulating layer, 42: insulating layer, 44: insulating layer, 47a: insulating layer, 47b: insulating layer, 47c: insulating layer, 47: insulating layer, 48: insulating layer, 50: capacitor, 51: conductive layer, 52: conductive layer, 53: insulating layer, 60: memory unit, 60[a, b]: memory unit, 80[m]: layer, 61: conductive layer, 62: conductive layer, 63: conductive layer, 65: insulating layer, 70: transistor, 71: semiconductor layer, 72: insulating layer, 73: conductive layer, 74: conductive layer, 75: conductive layer, 80: layer, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region

Claims

1. A semiconductor device comprising: transistor; a first insulating layer; as well as The second insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer and a third insulating layer. The first insulating layer is located above the first conductive layer and includes an opening reaching the first conductive layer, The semiconductor layer has a portion in contact with a top surface of the first conductive layer in the opening, a portion along a side surface of the first insulating layer in the opening, and a portion located on the first insulating layer. The third insulating layer covers the semiconductor layer in the opening, The third conductive layer covers the third insulating layer in the opening, The second insulating layer covers the third conductive layer, Furthermore, the second conductive layer has a portion located on the third conductive layer via the second insulating layer and a portion in contact with a portion of the semiconductor layer located on the first insulating layer.

2. The semiconductor device according to claim 1, wherein the second conductive layer has a portion extending in the first direction, The third conductive layer has a portion extending in a second direction intersecting the first direction, And the second conductive layer and the third conductive layer intersect in a region overlapping the opening.

3. The semiconductor device according to claim 1, further comprising: a fourth insulating layer and a fifth insulating layer located inside the opening, wherein the fourth insulating layer is disposed between the semiconductor layer and the first insulating layer and comprises a material in which hydrogen is less likely to diffuse than the first insulating layer, And the fifth insulating layer is arranged between the semiconductor layer and the fourth insulating layer and has the function of capturing or fixing hydrogen.

4. The semiconductor device according to claim 3, further comprising: a sixth insulating layer located inside the opening, The sixth insulating layer is disposed between the semiconductor layer and the fifth insulating layer and comprises oxide.

5. The semiconductor device according to claim 1, The diameter of the opening is greater than the height of the opening.

6. The semiconductor device according to claim 1, The diameter of the opening is more than twice the height of the opening.

7. The semiconductor device according to claim 1, At least one of the first conductive layer and the second conductive layer contains ruthenium.

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