Semiconductor device

Abstract

Provided is a semiconductor device that achieves both high performance and high productivity. The semiconductor device includes a first transistor and a second transistor on a substrate. The first transistor sequentially includes a first conductive layer, a first insulating layer, and a second conductive layer, and in openings disposed in the first insulating layer and the second conductive layer, the first conductive layer sequentially includes a first semiconductor layer, a second insulating layer, and a third conductive layer. The second transistor includes a first insulating layer, a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, a second insulating layer, and a sixth conductive layer in this order. The second semiconductor layer has a region in contact with the second insulating layer and a region overlapping the second insulating layer via the fourth conductive layer or the fifth conductive layer. The second conductive layer, the fourth conductive layer, and the fifth conductive layer may be formed using the same film.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method of manufacturing the same. One aspect of the present invention relates to a transistor and a method of manufacturing the same. One aspect of the present invention relates to a display device including a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As an example of the technical field of one aspect of the present invention, there can be cited semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving methods or manufacturing methods of the above devices.

[0003] Note that in this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), and a device including such a circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips having integrated circuits, and electronic components in which chips are housed in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, and sometimes all include semiconductor devices. Background Art

[0004] Semiconductor devices including transistors are widely used in electronic devices. For example, in a display device, by reducing the occupied area of a transistor, the pixel size can be reduced, and thus the clarity can be improved. Therefore, micro-transistors are required.

[0005] As devices that require high-definition display devices, for example, the development of devices for virtual reality (VR: Virtual Reality), augmented reality (AR: Augmented Reality), substitutional reality (SR: Substitutional Reality), and mixed reality (MR: Mixed Reality) is active.

[0006] As a display device, for example, a light-emitting device including an organic EL (Electro Luminescence) element or a light-emitting diode (LED: Light Emitting Diode) is developed.

[0007] A high-definition display device using an organic EL element is disclosed in Patent Document 1.

[0008] [Prior Art Documents]

[0009] [Patent Documents]

[0010] [Patent Document 1] International Patent Application Publication No. WO 2016 / 038508 Summary of the Invention

[0011] Technical Problem to be Solved by the Invention

[0012] One of the objectives of one embodiment of the present invention is to provide a semiconductor device including a micro transistor. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device including a transistor with a short channel length. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device including a transistor with a large on-state current. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device including a transistor with a small off-state current. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device including a transistor with high reliability. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device including a transistor with excellent electrical characteristics. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device with a small occupied area. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device with high performance. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device with low power consumption. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device with high reliability. In addition, one of the objectives of one embodiment of the present invention is to provide a semiconductor device with high productivity. In addition, one of the objectives of one embodiment of the present invention is to provide a novel semiconductor device.

[0013] Note that the description of these objectives does not preclude the existence of other objectives. One embodiment of the present invention does not need to achieve all of the above objectives. Objectives other than the above can be extracted from the descriptions in the specification, drawings, and claims.

[0014] Means for Solving the Technical Problem

[0015] One aspect of the present invention is a first semiconductor device including a first transistor and a second transistor on a substrate. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a first semiconductor layer. The first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the first insulating layer and the second conductive layer have an opening reaching the first conductive layer, and the first semiconductor layer contacts the top surface of the first conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second conductive layer, and the top surface of the second conductive layer in the opening. The second insulating layer is located on the first semiconductor layer, and the third conductive layer is located on the first semiconductor layer with the second insulating layer therebetween. The second transistor includes a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a first insulating layer, a second insulating layer, and a second semiconductor layer. The fourth conductive layer and the fifth conductive layer are located on the first insulating layer, and the second semiconductor layer contacts the top surface of the fourth conductive layer, the side surfaces of the fourth conductive layer, the top surface of the first insulating layer, the side surfaces of the fifth conductive layer, and the top surface of the fifth conductive layer. The second insulating layer is located on the second semiconductor layer, and the sixth conductive layer is located on the second semiconductor layer with the second insulating layer therebetween.

[0016] In the first semiconductor device, the second conductive layer, the fourth conductive layer, and the fifth conductive layer preferably contain the same material.

[0017] In the first semiconductor device, the third conductive layer and the sixth conductive layer preferably contain the same material.

[0018] In the first semiconductor device, preferably, the second transistor includes a third insulating layer, the second semiconductor layer is located on the third insulating layer with the second insulating layer therebetween, and the oxygen concentration in the second insulating layer is higher than the oxygen concentration in the third insulating layer.

[0019] Further, one aspect of the present invention is a second semiconductor device including a first transistor and a second transistor on a substrate. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a first semiconductor layer. The first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the second insulating layer covers the top surface and side surfaces of the second conductive layer, the third conductive layer is located on the second insulating layer, the first insulating layer, the second insulating layer, and the third conductive layer have an opening reaching the first conductive layer, and the first semiconductor layer contacts the top surface of the first conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second insulating layer, the side surfaces of the third conductive layer, and the top surface of the third conductive layer in the opening. The third insulating layer is located on the first semiconductor layer, and the fourth conductive layer is located on the first semiconductor layer with the third insulating layer therebetween. The second transistor includes a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a second semiconductor layer. The first insulating layer is located on the fifth conductive layer, the second insulating layer is located on the first insulating layer, the sixth conductive layer and the seventh conductive layer are located on the second insulating layer, the second semiconductor layer contacts the top surface of the sixth conductive layer, the side surfaces of the sixth conductive layer, the top surface of the second insulating layer, the side surfaces of the seventh conductive layer, and the top surface of the seventh conductive layer. The third insulating layer is located on the second semiconductor layer, and the eighth conductive layer is located on the second semiconductor layer with the third insulating layer therebetween.

[0020] In the second semiconductor device, the third conductive layer, the sixth conductive layer, and the seventh conductive layer preferably contain the same material.

[0021] In the second semiconductor device, the first conductive layer and the fifth conductive layer preferably contain the same material.

[0022] In the second semiconductor device, preferably, the second transistor includes a fourth insulating layer, the second semiconductor layer is located on the fourth insulating layer with the third insulating layer therebetween, and the concentration of oxygen contained in the third insulating layer is higher than the concentration of oxygen contained in the fourth insulating layer.

[0023] In the first semiconductor device or the second semiconductor device, the first semiconductor layer and the second semiconductor layer preferably both contain a metal oxide.

[0024] In the first semiconductor device or the second semiconductor device, the first semiconductor layer and the second semiconductor layer preferably contain the same material.

[0025] Further, in the first semiconductor device or the second semiconductor device, the first semiconductor layer and the second semiconductor layer preferably contain different materials.

[0026] Advantages of the Invention

[0027] According to one aspect of the present invention, a semiconductor device including a micro transistor can be provided. Further, according to one aspect of the present invention, a semiconductor device including a transistor with a short channel length can be provided. Further, according to one aspect of the present invention, a semiconductor device including a transistor with a large on-state current can be provided. Further, according to one aspect of the present invention, a semiconductor device including a transistor with a small off-state current can be provided. Further, according to one aspect of the present invention, a semiconductor device including a transistor with high reliability can be provided. Further, according to one aspect of the present invention, a semiconductor device including a transistor with excellent electrical characteristics can be provided. Further, according to one aspect of the present invention, a semiconductor device with a small occupied area can be provided. Further, according to one aspect of the present invention, a semiconductor device with high performance can be provided. Further, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Further, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Further, according to one aspect of the present invention, a semiconductor device with high productivity can be provided. Further, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0028] Note that the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have all of the above effects. Effects other than the above can be extracted from the descriptions in the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A is a top view showing an example of the semiconductor device. Figure 1B and Figure 1C is a cross-sectional view showing an example of the semiconductor device.

[0030] Figure 2 is a perspective view showing an example of the semiconductor device.

[0031] Figure 3A and Figure 3B is a perspective view showing the structure of the semiconductor device.

[0032] Figure 4A is a top view showing an example of the semiconductor device. Figure 4B is a cross-sectional view showing an example of the semiconductor device.

[0033] Figure 5 is a cross-sectional view showing an example of the semiconductor device.

[0034] Figure 6A is a top view showing an example of the semiconductor device. Figure 6B is a cross-sectional view showing an example of the semiconductor device.

[0035] Figures 7A to 7C It is a cross-sectional view showing an example of a semiconductor device.

[0036] Figure 8A and Figure 8B It is a cross-sectional view showing an example of a semiconductor device.

[0037] Figure 9A It is a top view showing an example of a semiconductor device. Figure 9B and Figure 9C It is a cross-sectional view showing an example of a semiconductor device.

[0038] Figure 10 It is a perspective view showing an example of a semiconductor device.

[0039] Figure 11A and Figure 11B It is a perspective view showing the structure of a semiconductor device.

[0040] Figure 12A and Figure 12B It is a perspective view showing the structure of a semiconductor device.

[0041] Figure 13 It is a cross-sectional view showing an example of a semiconductor device.

[0042] Figure 14A It is a top view showing an example of a semiconductor device. Figure 14B It is a cross-sectional view showing an example of a semiconductor device.

[0043] Figure 15A and Figure 15B It is a cross-sectional view showing an example of a semiconductor device.

[0044] Figure 16A It is a top view showing an example of a semiconductor device. Figure 16B and Figure 16C It is a cross-sectional view showing an example of a semiconductor device.

[0045] Figures 17A to 17C It is a cross-sectional view showing an example of a semiconductor device.

[0046] Figure 18A and Figure 18B It is a cross-sectional view showing an example of a semiconductor device.

[0047] Figure 19A and Figure 19B It is a cross-sectional view showing an example of a semiconductor device.

[0048] Figure 20 It is a cross-sectional view showing an example of a semiconductor device.

[0049] Figure 21A is a top view showing an example of a semiconductor device. Figure 21B is a cross-sectional view showing an example of a semiconductor device.

[0050] Figure 22A and Figure 22B is a cross-sectional view showing an example of a semiconductor device.

[0051] Figure 23A and Figure 23B is a cross-sectional view showing an example of a semiconductor device.

[0052] Figure 24A is a top view showing an example of a semiconductor device. Figure 24B and Figure 24C is a cross-sectional view showing an example of a semiconductor device.

[0053] Figure 25A is a top view showing an example of a semiconductor device. Figure 25B and Figure 25C is a cross-sectional view showing an example of a semiconductor device.

[0054] Figure 26A and Figure 26B is a cross-sectional view showing an example of a semiconductor device.

[0055] Figures 27A to 27E is a cross-sectional view showing an example of a manufacturing method of a semiconductor device.

[0056] Figures 28A to 28D is a cross-sectional view showing an example of a manufacturing method of a semiconductor device.

[0057] Figures 29A to 29C is a cross-sectional view showing an example of a manufacturing method of a semiconductor device.

[0058] Figures 30A to 30C is a cross-sectional view showing an example of a manufacturing method of a semiconductor device.

[0059] Figure 31A is a perspective view showing an example of a display device. Figure 31B is a block diagram of a display device.

[0060] Figure 32A is a circuit diagram of a latch circuit. Figure 32B is a circuit diagram of an inverter circuit.

[0061] Figure 33A and Figure 33B is a circuit diagram of a pixel circuit. Figure 33C is a cross-sectional view showing an example of a pixel circuit.

[0062] Figure 34 It is a cross-sectional view showing an example of a display device.

[0063] Figure 35 It is a cross-sectional view showing an example of a display device.

[0064] Figure 36 It is a cross-sectional view showing an example of a display device.

[0065] Figures 37A to 37C It is a cross-sectional view showing an example of a display device.

[0066] Figure 38 It is a cross-sectional view showing an example of a display device.

[0067] Figure 39 It is a cross-sectional view showing an example of a display device.

[0068] Figure 40 It is a cross-sectional view showing an example of a display device.

[0069] Figures 41A to 41F It is a cross-sectional view showing an example of a manufacturing method of a display device.

[0070] Figures 42A to 42D It is a diagram showing an example of an electronic device.

[0071] Figures 43A to 43F It is a diagram showing an example of an electronic device.

[0072] Figures 44A to 44G It is a diagram showing an example of an electronic device.

[0073] Figure 45A and Figure 45B It is a diagram showing the electrical characteristics of the transistor of the embodiment.

[0074] Figure 46A and Figure 46B It is a diagram showing the electrical characteristics of the transistor of the embodiment.

[0075] Figure 47 It is a diagram showing the electrical characteristics of the transistor of the embodiment. Detailed Description of the Invention

[0076] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it is easily understandable to those of ordinary skill in the art that the manner and details thereof can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following embodiments.

[0077] Note that in the invention structure described below, the same symbols are used in different drawings to denote the same parts or parts having the same functions, and repeated descriptions are omitted. In addition, when denoting parts having the same functions, the same hatching is sometimes used without particularly attaching symbols.

[0078] In addition, for ease of understanding, the positions, sizes, ranges, etc. of the respective components shown in the drawings do not necessarily represent their actual positions, sizes, ranges, etc. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings.

[0079] Note that in this specification, etc., for convenience, ordinal numbers such as "first" and "second" are attached, but they do not limit the number of components or the order of components (e.g., process order or lamination order). In addition, the ordinal numbers attached to a component in a certain part of this specification may sometimes be inconsistent with the ordinal numbers attached to the same component in other parts of this specification or in the claims.

[0080] In addition, depending on the situation or state, "film" and "layer" can be interchanged with each other. For example, "conductive layer" can be changed to "conductive film". In addition, "insulating film" can be changed to "insulating layer".

[0081] A transistor is a type of semiconductor device and can perform functions such as amplifying current or voltage, and switching operations for controlling conduction or non-conduction. The transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs: Thin Film Transistors).

[0082] In cases where transistors with different polarities are used or the direction of the current flowing in the circuit changes, etc., the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be used interchangeably.

[0083] In this specification, etc., "electrically connected" includes cases where connection is made through "components having a certain electrical effect". Here, there are no particular limitations on the "components having a certain electrical effect" as long as they can transfer electrical signals between the connection targets. For example, the "components having a certain electrical effect" include switching elements such as transistors, resistance elements, coils, and other components having various functions in addition to electrodes or wirings.

[0084] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and the drain when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). Unless otherwise specified, in an n-channel transistor, the off state means that the voltage V between the gate and the source gs is lower than the threshold voltage V th (in a p-channel transistor, higher than V th ).

[0085] In this specification and the like, "substantially the same top surface shape" means that at least a part of the edges of each layer in the stack overlap. For example, it includes the case where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern. However, in practice, there are cases where the edges do not overlap, and sometimes the upper layer is inside the lower layer or the upper layer is outside the lower layer, and this case can also be said to have "substantially the same top surface shape". When the top surface shapes are the same or substantially the same, it can also be said that the ends are aligned or substantially aligned. Note that in this specification and the like, the top surface shape of a component refers to the contour shape of the component when viewed from a plane. In addition, viewing from a plane means viewing from the normal direction of the surface of the formation surface of the component or the support body (such as a substrate) on which the component is formed.

[0086] Note that in this specification and the like, the conical shape means a shape in which at least a part of the side surface of the component is inclined with respect to the substrate surface or the formation surface. For example, it preferably has a region where the angle (also referred to as the cone angle) formed by the inclined side surface and the substrate surface or the formation surface is less than 90 degrees. Here, the side surface of the component, the substrate surface, and the formation surface do not necessarily have to be completely flat, and may be an approximately planar shape with a small curvature or an approximately planar shape with fine irregularities.

[0087] In this specification and the like, a device manufactured using a metal mask or an FMM (Fine Metal Mask, high-precision metal mask) is sometimes referred to as a device having an MM (Metal Mask) structure. In addition, in this specification and the like, a device not manufactured using a metal mask or an FMM is sometimes referred to as a device having an MML (Metal Mask Less) structure.

[0088] In this specification and the like, a structure in which light-emitting layers are separately manufactured in light-emitting elements (also referred to as light-emitting devices) having different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. Since the SBS structure can optimize the materials and structures for each light-emitting element, the degree of freedom in material and structure selection is increased, and it is easy to achieve improvements in brightness and reliability.

[0089] In this specification and the like, a hole or an electron is sometimes referred to as a "carrier". Specifically, a hole injection layer or an electron injection layer is sometimes called a "carrier injection layer", a hole transport layer or an electron transport layer is called a "carrier transport layer", and a hole blocking layer or an electron blocking layer is called a "carrier blocking layer". Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer cannot sometimes be clearly distinguished. In addition, sometimes a layer has the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0090] In this specification and the like, a light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Here, as the layers included in the EL layer (also referred to as functional layers), a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer) can be cited. In this specification and the like, a light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, sometimes one of the pair of electrodes is referred to as a pixel electrode, and the other is referred to as a common electrode.

[0091] In this specification and the like, a sacrificial layer (which can also be called a mask layer) is at least located above the light-emitting layer (more specifically, the layer formed in an island shape among the layers constituting the EL layer), and has a function of protecting the light-emitting layer in the manufacturing process.

[0092] In this specification and the like, disconnection refers to a phenomenon in which a layer, film, or electrode is disconnected due to the shape of the formation surface (for example, a step, etc.).

[0093] (Embodiment 1)

[0094] In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 1 to 26.

[0095] <Structural Example 1>

[0096] A semiconductor device according to one aspect of the present invention will be described. Figure 1A A plan view (also referred to as a top view) of the semiconductor device 10 is shown. Figure 1B Shown along Figure 1A a cross-sectional view of the cross-section along the dotted line A1 - A2 shown, Figure 1C a cross-sectional view of the cross-section along the dotted lines B1 - B2 and B3 - B4 is shown. Figure 2 A perspective view of the semiconductor device 10 is shown. Figure 3A And Figure 3B A perspective view showing the constituent elements of a part of the semiconductor device 10 extracted. Note that in Figure 1AIn this figure, some components (such as the insulating layer) of the semiconductor device 10 are omitted. Regarding the top view of the semiconductor device, similar to Figure 1A similarly, some components are also omitted in the subsequent figures. In addition, in Figure 2 the insulating layer is shown in perspective, and its outline is represented by a dashed line.

[0097] The semiconductor device 10 includes a transistor 100 and a transistor 200. The transistor 100 and the transistor 200 have different structures, and they are both disposed on the substrate 102. In addition, the transistor 100 and the transistor 200 can be formed in a manner where some processes are the same.

[0098] The transistor 100 includes a conductive layer 112, an insulating layer 110, an insulating layer 120, a semiconductor layer 108, a conductive layer 109, an insulating layer 106, and a conductive layer 104. Each layer constituting the transistor 100 can have a single-layer structure or a laminated structure.

[0099] The conductive layer 112 is disposed on the substrate 102. The conductive layer 112 is used as one of the source electrode and the drain electrode of the transistor 100.

[0100] The insulating layer 110 is located on the conductive layer 112. The insulating layer 110 is disposed so as to cover the top surface and the side surfaces of the conductive layer 112.

[0101] The insulating layer 110 preferably has a laminated structure. Figure 1B etc. show an example of the laminated structure of the insulating layer 110 having an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b.

[0102] The insulating layer 110a is located on the conductive layer 112. The insulating layer 110a is disposed so as to cover the top surface and the side surfaces of the conductive layer 112.

[0103] The insulating layer 110b is disposed on the insulating layer 110a, and the insulating layer 110c is disposed on the insulating layer 110b. Furthermore, the insulating layer 120 is disposed on the insulating layer 110c. An opening 141 reaching the conductive layer 112 is provided in the insulating layer 110 and the insulating layer 120.

[0104] The conductive layer 109 is located on the insulating layer 120. An opening 143 overlapping the opening 141 is provided in the conductive layer 109. The conductive layer 109 is used as the other of the source electrode and the drain electrode of the transistor 100. The conductive layer 109 has a region overlapping the conductive layer 112 with the insulating layer 110 and the insulating layer 120 therebetween.

[0105] There is no limitation on the top surface shape of the openings 141 and 143. The openings 141 and 143 can be, for example, circular, elliptical, triangular, quadrangular (including rectangular, rhombic, square), pentagonal or other polygonal shapes or the rounded shapes of these polygonal shapes. The polygonal shape can also be a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As Figure 1A shown, etc., the top surface shapes of the openings 141 and 143 are preferably both circular. By making the top surface shape of the opening circular, the processing accuracy when forming the opening can be improved, and a fine opening can be formed. Note that in this specification, etc., the circle is not limited to a perfect circle.

[0106] In this specification, etc., the top surface shape of the opening 141 refers to the shape of the top surface end portion on the opening 141 side of the insulating layer located between the conductive layer 112 and the conductive layer 109. For example, in Figure 1B the structure shown, etc., the top surface shape of the opening 141 refers to the shape of the top surface end portion on the opening 141 side of the insulating layer 120. In addition, the top surface shape of the opening 143 refers to the shape of the bottom surface end portion on the opening 143 side of the conductive layer 109. In addition, the bottom surface shape of the opening 143 refers to the shape of the bottom surface end portion on the opening 143 side of the conductive layer 109.

[0107] As Figure 1A shown, the top surface shape of the opening 141 and the top surface shape of the opening 143 can be made the same or substantially the same. At this time, as Figure 1B and Figure 1C shown, the bottom surface end portion on the opening 143 side of the conductive layer 109 and the top surface end portion on the opening 141 side of the insulating layer 120 are preferably aligned or substantially aligned. The bottom surface of the conductive layer 109 refers to the surface on the insulating layer 120 side. The top surface of the insulating layer 120 refers to the surface on the conductive layer 109 side.

[0108] In addition, the top surface shape of the opening 141 and the top surface shape of the opening 143 can also be different. In addition, when the top surface shapes of the openings 141 and 143 are circular, the openings 141 and 143 can be either concentric or non - concentric.

[0109] The semiconductor layer 108 is in contact with the top surfaces of the conductive layer 112, the side surfaces of the insulating layer 110, the side surfaces of the insulating layer 120, and the top surface and side surfaces of the conductive layer 109. The semiconductor layer 108 is disposed so as to cover the openings 141 and 143. The semiconductor layer 108 is disposed in a manner of contacting the side surfaces on the opening 141 side in the insulating layer 110 and the insulating layer 120 and the end portions (which can also be said to be a part of the top surface and the side surfaces on the opening 143 side) on the opening 143 side in the conductive layer 109. The semiconductor layer 108 is in contact with the conductive layer 112 through the openings 141 and 143.

[0110] Figure 1B An example is shown in which the end of the semiconductor layer 108 contacts the top surface of the conductive layer 109, but the present invention is not limited thereto. The semiconductor layer 108 may also cover the end of the conductive layer 109 and the end of the semiconductor layer 108 may contact the top surface of the insulating layer 120.

[0111] The insulating layer 106 is located on the insulating layer 120, the semiconductor layer 108, and the conductive layer 109. The insulating layer 106 is provided so as to cover the openings 141 and 143 with the semiconductor layer 108 interposed therebetween. A part of the insulating layer 106 is used as the gate insulating layer of the transistor 100.

[0112] The conductive layer 104 is located on the insulating layer 106. The conductive layer 104 overlaps the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 is used as the gate electrode of the transistor 100.

[0113] The transistor 100 is a so-called top-gate type transistor having a gate electrode above the semiconductor layer 108. Furthermore, since the bottom surface of the semiconductor layer 108 contacts the source electrode and the drain electrode, it can be said to be a TGBC (Top Gate Bottom Contact) type transistor. In addition, in the transistor 100, the heights of the source electrode and the drain electrode with respect to the surface of the substrate 102 of the formed surface (for example, the height in the direction perpendicular to the surface of the substrate or the insulating plane on which the transistor is provided) are different from each other, and the drain current flows in the direction perpendicular to or substantially perpendicular to the surface of the substrate 102. It can also be said that in the transistor 100, the drain current flows in the longitudinal direction or the substantially longitudinal direction. Therefore, the transistor according to one embodiment of the present invention can be said to be a longitudinal channel type transistor or a VFET (Vertical Field Effect Transistor).

[0114] The channel length of the transistor 100 can be controlled by the thickness of the insulating layers (here, the insulating layer 110 and the insulating layer 120) provided between the conductive layer 112 and the conductive layer 109. Therefore, a transistor having a channel length shorter than the limit resolution of the exposure apparatus used to manufacture the transistor can be manufactured with high precision. In addition, the characteristic non-uniformity between the plurality of transistors 100 can be reduced. Therefore, the operation of the semiconductor device including the transistor 100 is stable, and the reliability can be improved. In addition, when the characteristic non-uniformity is reduced, the degree of freedom in circuit design is increased, and the maximum operating voltage can also be reduced. As a result, the power consumption of the semiconductor device can be reduced.

[0115] In the transistor 100, the source electrode, the semiconductor layer, and the drain electrode can be overlapped and provided, so that the occupied area can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0116] The conductive layer 112, the conductive layer 109, and the conductive layer 104 can all be used as wirings, and the transistor 100 can be provided in the region where these wirings overlap. That is, in a circuit including the transistor 100 and the wirings, the occupied area of the transistor 100 and the wirings can be reduced. Therefore, the occupied area of the circuit can be reduced to realize a small semiconductor device.

[0117] For example, when the semiconductor device according to one embodiment of the present invention is used for a pixel circuit of a display device, the occupied area of the pixel circuit can be reduced, and a high-definition display device can be realized. Further, for example, when the semiconductor device according to one embodiment of the present invention is used for a driving circuit of a display device (for example, one or both of a gate line driving circuit and a source line driving circuit), the occupied area of the driving circuit can be reduced, and thus a display device with a narrow border can be realized.

[0118] Figure 1B Examples in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the openings 141 and 143 are shown, but one embodiment of the present invention is not limited thereto. Further, a structure in which the insulating layer 110, the insulating layer 120, and the conductive layer 109 and the conductive layer 112 form a step, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step may also be employed.

[0119] The transistor 200 includes the insulating layer 110, the insulating layer 120, the semiconductor layer 208, the insulating layer 106, and the conductive layer 204. Each layer constituting the transistor 200 may have a single-layer structure or a stacked structure.

[0120] The insulating layer 110 is provided on the substrate 102, and the insulating layer 120 is provided on the insulating layer 110.

[0121] The conductive layer 209a and the conductive layer 209b are provided on the insulating layer 120. The conductive layer 209a is used as one of the source electrode and the drain electrode of the transistor 200, and the conductive layer 209b is used as the other of the source electrode and the drain electrode of the transistor 200. Further, the conductive layer 209a and the conductive layer 209b can be formed by the same process as the conductive layer 109. For example, by forming a conductive film that will become the conductive layer 109, the conductive layer 209a, and the conductive layer 209b and processing the conductive film, the conductive layer 209a and the conductive layer 209b can be formed. Figure 3A FIG. is a perspective view showing a structural example in which the conductive layer 109, the conductive layer 209a, and the conductive layer 209b are formed on the insulating layer 120 by the same process.

[0122] A semiconductor layer 208 is provided on the conductive layer 209a, the conductive layer 209b, and the insulating layer 120. The semiconductor layer 208 can use, for example, the same material as the semiconductor layer 108. Furthermore, the semiconductor layer 208 can be formed by the same process as the semiconductor layer 108. For example, by forming a semiconductor film that will become the semiconductor layer 108 and the semiconductor layer 208 and processing the semiconductor film, the semiconductor layer 108 and the semiconductor layer 208 can be formed. Figure 3B It is a perspective view showing a structural example in which the semiconductor layer 108 and the semiconductor layer 208 are formed by the same process.

[0123] An insulating layer 106 is provided on the insulating layer 120, the conductive layer 209a, the conductive layer 209b, and the semiconductor layer 208. A part of the insulating layer 106 is used as a gate insulating layer of the transistor 200. In addition, the insulating layer 106 has openings 147a and 147b that reach the semiconductor layer 208.

[0124] A conductive layer 204, a conductive layer 212a, and a conductive layer 212b are provided on the insulating layer 106. The conductive layer 204, the conductive layer 212a, and the conductive layer 212b can use, for example, the same material as the conductive layer 104. Furthermore, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed by the same process as the conductive layer 104. For example, by forming a conductive film that will become the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b and processing the conductive film, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed.

[0125] The conductive layer 204 has a region overlapping the semiconductor layer 208 with the insulating layer 106 therebetween and is used as a gate electrode of the transistor 200. The end portion of the conductive layer 204 is located inside the end portion of the insulating layer 106. It can also be said that the end portion of the conductive layer 204 contacts the top surface of the insulating layer 106. In addition, it can also be said that the insulating layer 106 has a portion that protrudes at least on the semiconductor layer 208 to the outside of the end portion of the conductive layer 204.

[0126] The conductive layer 212a is provided so as to cover at least a part of the opening 147a and contacts the semiconductor layer 208 through the opening 147a. In addition, the conductive layer 212b is provided so as to cover at least a part of the opening 147b and contacts the semiconductor layer 208 through the opening 147b. The conductive layer 212a is used as one of the source electrode and the drain electrode of the transistor 200, and the conductive layer 212b is used as the other of the source electrode and the drain electrode of the transistor 200.

[0127] In the semiconductor layer 208, the entire region overlapping with the gate electrode with the gate insulating layer interposed therebetween between the source electrode and the drain electrode is used as a channel formation region. The semiconductor layer 208 has a pair of regions 208L sandwiching the channel formation region and a pair of regions 208D outside thereof.

[0128] The region 208D can also be said to be a region having a carrier concentration higher than that of the channel formation region, a low-resistance region, or an n-type region. The region in the semiconductor layer 208 that contacts the conductive layer 212a and the region 208D adjacent thereto are used as one of the source region and the drain region. The region in the semiconductor layer 208 that contacts the conductive layer 212b and the region 208D adjacent thereto are used as the other of the source region and the drain region.

[0129] The region 208L can also be said to be a region having a resistance equal to or lower than that of the channel formation region, a carrier concentration equal to or higher than that of the channel formation region, an oxygen vacancy density equal to or higher than that of the channel formation region, or an impurity concentration equal to or higher than that of the channel formation region. Also, the region 208L can be said to be a region having a resistance equal to or higher than that of the region 208D, a carrier concentration equal to or lower than that of the region 208D, an oxygen vacancy density equal to or lower than that of the region 208D, or an impurity concentration equal to or lower than that of the region 208D.

[0130] The region 208L is used as a buffer region for alleviating the drain electric field. Since the region 208L does not overlap with the conductive layer 204, almost no channel is formed when a gate voltage is supplied to the conductive layer 204. The carrier concentration in the region 208L is preferably higher than that in the channel formation region. Thereby, the region 208L can be used as an LDD (Lightly Doped Drain) region. By providing the region 208L serving as an LDD region between the channel formation region and the region 208D, a transistor 200 having both high drain breakdown voltage and large on-state current and high reliability can be realized.

[0131] The carrier concentration of the semiconductor layer 208 preferably has the following distribution: the channel formation region is the lowest, and it increases in order of the region 208L and the region 208D. By providing the region 208L between the channel formation region and the region 208D, for example, even if impurities such as hydrogen diffuse from the region 208D in the manufacturing process, the carrier concentration in the channel formation region can be maintained extremely low.

[0132] Note that the carrier concentration in the region 208L may also be non-uniform and sometimes has a gradient that decreases from the region 208D side toward the channel formation region side. For example, it may have a gradient in which one or both of the hydrogen concentration and the oxygen vacancy concentration in the region 208L decrease from the region 208D side toward the channel formation region side.

[0133] For example, as Figure 1BAs shown, by providing regions in a part of the semiconductor layer 208 that overlap the insulating layer 120 with the conductive layer 209a or the conductive layer 209b interposed therebetween, the regions 208L and 208D can be formed. The regions 208L and 208D are regions in the semiconductor layer 208 that overlap the insulating layer 120 with the conductive layer 209a or the conductive layer 209b interposed therebetween. The region 208L is a region among the above regions that overlaps the insulating layer 106 and does not overlap the conductive layer 204.

[0134] Regions in the semiconductor layer 208 that are in contact with the insulating layer 120 can receive oxygen contained in the insulating layer 120. On the other hand, in regions in the semiconductor layer 208 that overlap the insulating layer 120 with the conductive layer 209a or the conductive layer 209b interposed therebetween, oxygen contained in the insulating layer 120 cannot be directly received. In addition, regions in the semiconductor layer 208 that overlap the insulating layer 120 with the conductive layer 209a or the conductive layer 209b interposed therebetween are regions in contact with the conductive layer 209a or the conductive layer 209b, and sometimes oxygen contained in the semiconductor layer 208 in these regions is taken away by the conductive layer 209a or the conductive layer 209b. Therefore, regions in the semiconductor layer 208 that overlap the insulating layer 120 with the conductive layer 209a or the conductive layer 209b interposed therebetween can be regions having a carrier concentration higher than that of the channel formation region, low-resistance regions, or n-type regions.

[0135] Alternatively, for example, after forming the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, by using these conductive layers as masks and adding impurity elements to the semiconductor layer 208, the regions 208L and 208D can be formed. The region 208L is a region in the semiconductor layer 208 that overlaps the insulating layer 106 and does not overlap the conductive layer 204. The region 208D is a region in the semiconductor layer 208 that does not overlap the insulating layer 106 and the conductive layer 204.

[0136] As Figure 1B and Figure 1C shown, the ends of a part of the conductive layer 212a and the conductive layer 212b are preferably located inside the openings 147a and 147b. In other words, in the openings 147a and 147b, the ends of a part of the conductive layer 212a and the conductive layer 212b are preferably in contact with the semiconductor layer 208. Thereby, a region in contact with the conductive layer 212a can be adjacent to one of the pair of regions 208D, and similarly, a region in contact with the conductive layer 212b can be adjacent to the other of the pair of regions 208D.

[0137] Note that there is no particular limitation on the top surface shape of the openings 147a and 147b. Figure 1AStructures are shown in which the top surface shapes of the openings 147a and 147b are different from those of the openings 141 and 143, but one embodiment of the present invention is not limited thereto. The top surface shapes of the openings 147a and 147b may also be the same as those of the openings 141 and 143.

[0138] Regions 208L and 208D are regions containing impurity elements. As such impurity elements, one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases can be used. As typical examples of noble gases, helium, neon, argon, krypton, and xenon can be cited. As impurity elements, one or more of boron, phosphorus, aluminum, magnesium, and silicon are particularly preferably used.

[0139] When adding impurity elements to the semiconductor layer 208 to form the regions 208L and 208D, the conductive layer 104 can also be used as a mask and the impurity elements can be supplied to the semiconductor layer 108 through the insulating layer 106. Thereby, a region 108L is formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104. Note that in the transistor 100, a region of the semiconductor layer 108 that contacts the conductive layer 109 is used as a source region or a drain region. The region 108L is formed in a part of the source region or the drain region. Additionally, the region 108L may not be formed. For example, when the conductive layer 104 extends and covers the end of the semiconductor layer 108, the entire semiconductor layer 108 is covered by the conductive layer 104, so the semiconductor layer 108 is not supplied with impurity elements and the region 108L is not formed.

[0140] The transistor 200 is a so-called top-gate type transistor including a gate electrode above the semiconductor layer 208. For example, by using the conductive layer 204 serving as a gate electrode as a mask and adding impurity elements to the semiconductor layer 208, regions 208D serving as source regions and drain regions can be formed in a self-aligned manner. The transistor 200 can be said to be a TGSA (Top Gate Self-Aligned) type transistor.

[0141] The transistor 200 can control the channel length by the length of the conductive layer 204. Thus, the channel length of the transistor 200 is a value equal to or greater than the limit resolution of the exposure apparatus used in the manufacture of the transistor. By increasing the channel length, a transistor with high saturation characteristics can be achieved.

[0142] As described above, the transistor 100 with a short channel length and the transistor 200 with a long channel length can be formed on the same substrate in a manner where a part of the processes is common. For example, by using the transistor 100 as a transistor that requires a large drain current and using the transistor 200 as a transistor that requires high saturation characteristics, a high-performance semiconductor device can be realized.

[0143] An insulating layer 195 is provided to cover the transistor 100 and the transistor 200. The insulating layer 195 is used as a protective layer for the transistor 100 and the transistor 200.

[0144] The detailed structures of the transistor 100 and the transistor 200 will be described.

[0145] First, with reference to Figure 4A and Figure 4B the channel length and the channel width of the transistor 100 will be described. Figure 4A is Figure 1A an enlarged view of the transistor 100 shown in Figure 4B is Figure 1B an enlarged view of the transistor 100 shown in

[0146] In the semiconductor layer 108, the region in contact with the conductive layer 112 is used as one of the source region and the drain region, the region in contact with the conductive layer 109 is used as the other of the source region and the drain region, and the region between the source region and the drain region is used as the channel formation region.

[0147] The channel length of the transistor 100 is the distance between the source region and the drain region. In Figure 4B the channel length L100 of the transistor 100 is indicated by a double-headed dashed arrow. The channel length L100 can be said to be the shortest distance between the region of the semiconductor layer 108 in contact with the conductive layer 112 and the region in contact with the conductive layer 109 when viewed in cross-section.

[0148] The channel length L100 of the transistor 100 corresponds to the length of the side of the opening 141 of the insulating layer sandwiched between the conductive layer 112 and the conductive layer 109 when viewed in cross-section. That is, the channel length L100 is determined by the thickness Tins of the insulating layer sandwiched between the conductive layer 112 and the conductive layer 109 (here, the sum of the thicknesses of the insulating layer 110 and the insulating layer 120) and the angle θins formed by the side of the opening 141 of these insulating layers and the formation surface (here, the top surface of the conductive layer 112). Therefore, for example, the channel length L100 can be set to a value smaller than the limit resolution of the exposure apparatus, and a micro transistor can be realized. Specifically, a transistor with an extremely short channel length that cannot be realized by an exposure apparatus used in the mass production of existing flat panel displays (for example, with a minimum line width of about 2 μm or 1.5 μm) can be realized. In addition, a transistor with a channel length less than 10 nm can be realized without using a very expensive exposure apparatus used in the most advanced LSI technology.

[0149] The channel length L100 can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 can be set to 100 nm or more and 1 μm or less.

[0150] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of operating at high speed can be manufactured. Furthermore, the occupied area of the circuit can be reduced. Therefore, a small semiconductor device can be realized. For example, when the semiconductor device according to one embodiment of the present invention is used in a large display device or a high-definition display device, signal delay of each wiring can be reduced even when the number of wirings increases, thereby suppressing display unevenness. In addition, since the occupied area of the circuit can be reduced, the bezel of the display device can be reduced.

[0151] By adjusting the thickness Tins and the angle θins, the channel length L100 can be controlled. Note that, in Figure 4B the thickness Tins is indicated by a dotted double arrow.

[0152] The thickness Tins can be, for example, 10 nm or more, 50 nm or more, 100 nm or more, 150 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more and less than 3.0 μm, 2.5 μm or less, 2.0 μm or less, 1.5 μm or less, 1.2 μm or less, 1.0 μm or less.

[0153] The side surfaces on the opening 141 side of the insulating layer 110 and the insulating layer 120 preferably have a tapered shape. The angle θins formed by the side surfaces on the opening 141 side of the insulating layer 110 and the insulating layer 120 and the formed surface of the insulating layer 110 (here, the top surface of the conductive layer 112) is preferably 90 degrees or less. By reducing the angle θins, the coverage of the layer provided on these insulating layers (for example, the semiconductor layer 108) can be improved. In addition, the smaller the angle θins, the longer the channel length L100 can be, and the larger the angle θins, the shorter the channel length L100 can be.

[0154] The angle θins can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more and 90 degrees or less, 85 degrees or less, or 80 degrees or less. The closer the angle θins is to 90 degrees, the smaller the setting area of the transistor 100 can be, which is advantageous for high density. Figure 5An example of the transistor 100 when the angle θins is 90 degrees is shown. In this case, the thickness Tins is consistent with the channel length L100.

[0155] Note that in Figure 4B etc., a structure is shown in which the shape of the side surface on the opening 141 side of the insulating layer 110 and the insulating layer 120 is a straight line when viewed from the cross section, but one embodiment of the present invention is not limited thereto. When viewed from the cross section, the shape of the side surface on the opening 141 side of the insulating layer 110 and the insulating layer 120 may also be a curve, or may have both a region where the shape of the side surface is a straight line and a region where the shape is a curve.

[0156] In Figure 4A and Figure 4B the width D143 of the opening 143 is indicated by a double-headed arrow with a double-dashed line. Figure 4A An example in which the top surface shapes of the opening 141 and the opening 143 are circular is shown. At this time, the width D143 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 corresponds to the length of the circumference of the circle. That is, the channel width W100 is π×D143. Thus, when the top surface shapes of the opening 141 and the opening 143 are circular, a transistor with a smaller channel width W100 can be realized compared with other shapes.

[0157] Note that the diameter of the opening 141 and the diameter of the opening 143 may sometimes be different. In addition, the diameter of the opening 141 and the diameter of the opening 143 may sometimes change in the depth direction. As the diameter of the opening, for example, the average value of the diameter at the highest position, the diameter at the lowest position, and the diameter at the midpoint position of the insulating layer 110 and the insulating layer 120 when viewed from the cross section can be used. Or, as the diameter of the opening, for example, any diameter among the diameter at the highest position, the diameter at the lowest position, and the diameter at the midpoint position of the insulating layer 110 and the insulating layer 120 when viewed from the cross section can also be used.

[0158] When forming the opening 143 by photolithography, the width D143 of the opening 143 is above the limit resolution of the exposure apparatus. The width D143 can be, for example, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more and less than 5.0 μm, 4.5 μm or less, 4.0 μm or less, 3.5 μm or less, 3.0 μm or less, 2.5 μm or less, 2.0 μm or less, 1.5 μm or less, or 1.0 μm or less.

[0159] Next, with reference to Figure 6A and Figure 6B the channel length and the channel width of the transistor 200 will be described. Figure 6A is a top view of the transistor 200, Figure 6B is Figure 1B an enlarged view of the transistor 200 shown.

[0160] In the semiconductor layer 208 , a pair of regions 208D are used as a source region and a drain region, and a region between the source region and the drain region is used as a channel formation region. The channel formation region includes a region overlapping with the conductive layer 204 with the insulating layer 106 interposed therebetween.

[0161] The channel length of transistor 200 is the length of the region where semiconductor layer 208 and conductive layer 204 overlap between a pair of regions 208D. Figure 6A and Figure 6B In the figure, the double-dotted arrow indicates the channel length L200 of the transistor 200. The channel length L200 of the transistor 200 is determined by the length of the conductive layer 204 and is a value greater than the limiting resolution of the exposure device used in the manufacture of the transistor. For example, the channel length L200 may be greater than 1.5 μm. By increasing the channel length, a transistor with high saturation characteristics can be realized.

[0162] The channel width of the transistor 200 is the width of the region where the semiconductor layer 208 and the conductive layer 204 overlap in a direction orthogonal to the channel length direction. Figure 6A and Figure 6B In FIG. 1 , the channel width W200 of the transistor 200 is represented by a solid double arrow.

[0163] As described above, the channel length L100 of the transistor 100 can be set to a value smaller than the limiting resolution of the exposure device, and the channel length L200 of the transistor 200 can be set to a value greater than the limiting resolution of the exposure device. For example, by using the transistor 100 as a transistor requiring a large on-state current and using the transistor 200 as a transistor requiring a high saturation characteristic, a high-performance semiconductor device 10 that takes advantage of the advantages of each transistor can be realized.

[0164] In the semiconductor device 10 of one embodiment of the present invention, the transistor 100 and the transistor 200 having different structures and channel lengths can be formed on the substrate 102 in a manner in which some processes are the same. Specifically, the conductive layer 109, the conductive layer 209a, and the conductive layer 209b can be formed by the same process. The semiconductor layer 108 and the semiconductor layer 208 can be formed by the same process. A portion of the insulating layer 106 is used as a gate insulating layer of the transistor 100, and the other portion of the insulating layer 106 is used as a gate insulating layer of the transistor 200. The conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed by the same process. Therefore, the productivity of the semiconductor device 10 can be improved and the manufacturing cost can be reduced.

[0165] Notice, Figure 6B The example in which the thickness of the semiconductor layer 208 is uniform at any position is shown in FIG. 1 , but one embodiment of the present invention is not limited to this.Figure 7A As shown, the thickness may also be different between the region of the semiconductor layer 208 that overlaps with the insulating layer 106 and the region that does not overlap with the insulating layer 106. For example, when forming the openings 147a and 147b, sometimes a part of the semiconductor layer 208 is removed, and the thickness of the region of the semiconductor layer 208 that does not overlap with the insulating layer 106 is smaller than the thickness of the region that overlaps with the insulating layer 106. Or, as Figure 7B shown, the thickness may also be different between the region of the semiconductor layer 208 that overlaps with any one of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b and the region that does not overlap with any one of them. For example, when forming the conductive layer 212a and the conductive layer 212b, sometimes a part of the semiconductor layer 208 is removed, and the thickness of the region of the semiconductor layer 208 that does not overlap with any one of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b is smaller than the thickness of the region that overlaps with any one of them. Or, as Figure 7C shown, the thickness may also be different between the region of the semiconductor layer 208 that overlaps with the insulating layer 106, the region that overlaps with any one of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b, and the region that does not overlap with any one of them.

[0166] Note that although Figure 6A and Figure 6B etc. show examples where the position of one end of the conductive layer 204 is aligned with the end of the conductive layer 209a and the position of the other end of the conductive layer 204 is aligned with the end of the conductive layer 209b, one aspect of the present invention is not limited thereto. As Figure 8A shown, one end of the conductive layer 204 may overlap with the conductive layer 209a, and the other end of the conductive layer 204 may overlap with the conductive layer 209b. Or, as Figure 8B shown, one end of the conductive layer 204 may be located at a distant position that does not overlap with the conductive layer 209a, and the other end of the conductive layer 204 may be located at a distant position that does not overlap with the conductive layer 209b.

[0167] The components included in the semiconductor device of the present embodiment will be described below.

[0168] [Semiconductor layer 108, Semiconductor layer 208]

[0169] There is no particular limitation on the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208. For example, a semiconductor composed of a single element or a compound semiconductor can be used. As the semiconductor composed of a single element, silicon and germanium can be cited, for example. As the compound semiconductor, gallium arsenide and silicon germanium can be cited, for example. In addition, as the compound semiconductor, an organic semiconductor, a nitride semiconductor, and an oxide semiconductor can be cited, for example. Note that these semiconductor materials may also contain impurities as dopants.

[0170] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a semiconductor having a crystal region in a part thereof) can be used. When a single crystal semiconductor or a semiconductor having crystallinity is used, deterioration of the transistor characteristics can be suppressed, so it is preferable.

[0171] The semiconductor layer 108 and the semiconductor layer 208 preferably contain a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.

[0172] The band gap of the metal oxide used for the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0173] As the metal oxide that can be used for the semiconductor layer 108 and the semiconductor layer 208, indium oxide, gallium oxide, and zinc oxide can be cited, for example. The metal oxide preferably contains at least indium or zinc. In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony can be cited. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. Note that in this specification and the like, a metal element and a metalloid element are sometimes collectively referred to as a "metal element", and the "metal element" described in this specification and the like sometimes includes a metalloid element.

[0174] The semiconductor layer 108 and the semiconductor layer 208 can be made of, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (also denoted as Ga-Zn oxide, GZO), aluminum zinc oxide (also denoted as Al-Zn oxide, AZO), indium aluminum zinc oxide (also denoted as In-Al-Zn oxide, IAZO), indium tin zinc oxide (also denoted as In-Sn-Zn oxide, ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (also denoted as In-Ga-Zn oxide, IGZO), indium gallium tin zinc oxide (also denoted as In-Ga-Sn-Zn oxide, IGZTO), indium gallium aluminum zinc oxide (also denoted as In-Ga-Al-Zn oxide, IGAZO, IGZAO or IAGZO), etc. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0175] When the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements in the metal oxide is increased, the field-effect mobility of the transistor can be increased. In addition, a transistor with a large on-state current can be realized.

[0176] Note that the metal oxide can also replace indium or contain one or more metal elements with a large period number in the periodic table in addition to indium. There is a tendency that the larger the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including metal elements with a large period number in the periodic table, the field-effect mobility of the transistor can sometimes be increased. As the metal elements with a large period number in the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period, etc. can be cited. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium, etc. can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0177] The metal oxide can also contain one or more non-metal elements. When the metal oxide contains non-metal elements, sometimes the carrier concentration increases or the band gap becomes narrow, etc., and the field-effect mobility of the transistor can be increased. As the non-metal element, for example, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen, etc. can be cited.

[0178] When the ratio of the number of atoms of zinc to the sum of the number of atoms of all metal elements in the metal oxide is increased, the metal oxide has high crystallinity, and diffusion of impurities in the metal oxide can be suppressed. Therefore, variations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0179] When the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements in the metal oxide is increased, formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, generation of carriers due to oxygen vacancies is suppressed, and a transistor with a small off-state current can be formed. In addition, variations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0180] The electrical characteristics and reliability of the transistor differ depending on the composition of the metal oxide used for the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide according to the required electrical characteristics and reliability of the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0181] In the composition analysis of the metal oxide, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES) can be used. Alternatively, multiple of the above methods can be combined for analysis. Note that elements with a low content rate may be affected by the analysis accuracy, and the actual content rate may differ from the content rate obtained by analysis. For example, when the content rate of element M is low, the content rate of element M obtained by analysis may be lower than the actual content rate. In addition, it may be difficult to quantify element M or element M may not be detected.

[0182] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of the atomic ratio of the metal elements in such an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, and compositions in their vicinity. In addition, the compositions in the vicinity include a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be improved, etc.

[0183] The atomic ratio of In in the In-M-Zn oxide can also be less than the atomic ratio of M. Examples of the atomic ratio of the metal elements in such an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, and compositions in their vicinity. By increasing the proportion of the number of atoms of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0184] Note that when multiple metal elements are included as element M, the total of the atomic ratios of the metal elements can be the atomic ratio of element M.

[0185] In this specification, etc., the ratio of the number of indium atoms to the sum of the numbers of atoms of all the contained metal elements is sometimes referred to as the indium content rate. The same applies to other metal elements.

[0186] The metal oxide can be appropriately formed by a sputtering method or an atomic layer deposition (ALD: Atomic Layer Deposition) method. Note that when the metal oxide is formed by the sputtering method, the composition of the deposited metal oxide is sometimes different from the composition of the target. In particular, the zinc content rate in the deposited metal oxide sometimes decreases to about 50% of the target.

[0187] The semiconductor layer 108 and the semiconductor layer 208 can also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 108 and the semiconductor layer 208 can also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, it can be formed using the same sputtering target, so the manufacturing cost can be reduced.

[0188] The compositions of the two or more metal oxide layers included in semiconductor layer 108 and semiconductor layer 208 may also be different from each other. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn = 1:3:4 [atomic ratio] or a composition near thereto and a second metal oxide layer having a composition of In:M:Zn = 1:1:1 [atomic ratio] or a composition near thereto provided on the first metal oxide layer may be appropriately used. In addition, gallium, aluminum, or tin is particularly preferably used as element M. For example, a stacked structure selected from any one of indium oxide, indium gallium oxide, and IGZO and any one of IAZO, IAGZO, and ITZO (registered trademark) may be used.

[0189] Semiconductor layer 108 and semiconductor layer 208 preferably include a metal oxide layer having crystallinity. As the structure of the metal oxide having crystallinity, for example, a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a microcrystalline (nc: nano-crystal) structure can be cited. By using a metal oxide layer having crystallinity for semiconductor layer 108, the density of defect states in semiconductor layer 108 can be reduced, and thus a highly reliable semiconductor device can be realized.

[0190] The higher the crystallinity of the metal oxide layer for semiconductor layer 108 and semiconductor layer 208, the more the density of defect states in semiconductor layer 108 can be reduced. On the other hand, by using a metal oxide layer having low crystallinity, a transistor capable of flowing a large current can be realized.

[0191] When forming the metal oxide layer, the higher the substrate temperature (stage temperature) during formation, the more a metal oxide layer having high crystallinity can be formed. In addition, the higher the flow rate ratio of oxygen gas to the entire deposition gas used during formation (hereinafter, also referred to as the oxygen flow ratio), the more a metal oxide layer having high crystallinity can be formed.

[0192] Semiconductor layer 108 and semiconductor layer 208 may also have a stacked structure of two or more metal oxide layers having different crystallinities. For example, it may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer may have a region having higher crystallinity than the first metal oxide layer. Or, the second metal oxide layer may have a region having lower crystallinity than the first metal oxide layer. At this time, the compositions of the first metal oxide layer and the second metal oxide layer may be different, the same, or substantially the same.

[0193] The thickness of the semiconductor layer 108 and the semiconductor layer 208 is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, still more preferably 5 nm or more and 100 nm or less, still more preferably 10 nm or more and 100 nm or less, still more preferably 10 nm or more and 70 nm or less, still more preferably 15 nm or more and 70 nm or less, still more preferably 15 nm or more and 50 nm or less, still more preferably 20 nm or more and 50 nm or less.

[0194] When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, sometimes hydrogen in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, and oxygen vacancies (V O ) are formed in the oxide semiconductor. Furthermore, sometimes hydrogen enters a defect in the oxygen vacancy (hereinafter denoted as V O H) and is used as a donor to generate electrons as carriers. In addition, sometimes electrons as carriers are generated because a part of hydrogen bonds to oxygen bonded to a metal atom. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen easily has a normally-on characteristic. In addition, since hydrogen in the oxide semiconductor easily moves due to the action of heat, an electric field, etc., when the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0195] When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to minimize V O H in the semiconductor layer 108 and the semiconductor layer 208 to make it highly pure intrinsic or substantially highly pure intrinsic. Thus, in order to obtain an oxide semiconductor in which V O H is sufficiently reduced, it is important to remove impurities such as water and hydrogen in the oxide semiconductor (sometimes referred to as dehydration and dehydrogenation treatment); and supply oxygen to the oxide semiconductor to repair oxygen vacancies. By using an oxide semiconductor in which impurities such as V O H are sufficiently reduced for the channel formation region of the transistor, stable electrical characteristics can be imparted. Note that the treatment of supplying oxygen to the oxide semiconductor to repair oxygen vacancies is sometimes referred to as oxidation treatment.

[0196] When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, the carrier concentration of the oxide semiconductor in the region used as the channel formation region is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 , still more preferably less than 1×10 16 cm -3 , more preferably less than 1×10 13 cm -3 , still more preferably less than 1×1012 cm -3 There is no particular limitation on the lower limit value of the carrier concentration of the oxide semiconductor in the region used as the channel formation region. For example, it can be set to 1×10 -9 cm -3 。

[0197] Compared with a transistor using amorphous silicon, the field-effect mobility of a transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) is very high. In addition, the off-state current of the OS transistor is extremely small, and the charge stored in the capacitor connected in series with the transistor can be maintained for a long time. Furthermore, by using the OS transistor, the power consumption of the semiconductor device can be reduced.

[0198] The change in electrical characteristics of the OS transistor caused by irradiation with radiation is small, that is, it has high tolerance to radiation. Therefore, it can be appropriately used in an environment where radiation may be incident. The OS transistor can also be said to have high reliability for radiation. For example, the OS transistor can be appropriately used for the pixel circuit of an X-ray flat panel detector. In addition, the OS transistor can be appropriately used for semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and γ-rays) and particle radiation (e.g., α-rays, β-rays, proton radiation, and neutron radiation).

[0199] Examples of silicon that can be used for the semiconductor layer 108 and the semiconductor layer 208 include single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon).

[0200] A transistor using amorphous silicon for the semiconductor layer 108 and the semiconductor layer 208 can be formed on a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 108 and the semiconductor layer 208 has a high field-effect mobility and can operate at high speed. In addition, a transistor using microcrystalline silicon for the semiconductor layer 108 and the semiconductor layer 208 has a high field-effect mobility compared with a transistor using amorphous silicon and can operate at high speed.

[0201] The semiconductor layer 108 and the semiconductor layer 208 may also include a layered material used as a semiconductor. The layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds weaker than covalent bonds and ionic bonds such as van der Waals bonds. The layered material has high conductivity in the unit layer, that is, it has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity for the channel formation region, a transistor with a large on-state current can be provided.

[0202] As the above-mentioned layered material, for example, graphene, silicene, chalcogenide, etc. can be cited. Chalcogenide is a compound containing chalcogen elements (belonging to Group 16 elements). In addition, as chalcogenide, transition metal chalcogenide, Group 13 chalcogenide, etc. can be cited. As the transition metal chalcogenide that can be used as the semiconductor layer of the transistor, specifically, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited.

[0203] In addition, the material included in the semiconductor layer 108 and the material included in the semiconductor layer 208 can be the same material among any of the above materials, or can be different materials among any of the above materials. For example, the semiconductor layer 108 can include silicon, and the semiconductor layer 208 can include a metal oxide. Or, for example, the semiconductor layer 108 can include a first metal oxide, and the semiconductor layer 208 can include a second metal oxide having a composition different from that of the first metal oxide.

[0204] As described above, when the material included in the semiconductor layer 108 and the material included in the semiconductor layer 208 are different from each other, the semiconductor layer 108 and the semiconductor layer 208 are formed by different processes. For example, the semiconductor layer 208 can be formed after the semiconductor layer 108 is formed. Or, the semiconductor layer 108 can also be formed after the semiconductor layer 208 is formed. In addition, the semiconductor layer 108 and the semiconductor layer 208 can also use the same material and be formed by different processes.

[0205] As described above, the electrical characteristics and reliability of transistors vary depending on the materials used for the semiconductor layers. For example, when the first metal oxide is used for the semiconductor layer 108 and the second metal oxide is used for the semiconductor layer 208, the indium content ratio of the first metal oxide can be made higher than that of the second metal oxide. Thereby, the on-state current of the transistor 100 can be increased. In addition, by making the indium content ratio of the second metal oxide lower than that of the first metal oxide, the saturation of the Id-Vd characteristics of the transistor 200 can be improved. More specifically, an In-Ga-Zn oxide with an atomic ratio of 4:2:3 or around it can be used as the first metal oxide, and an In-Ga-Zn oxide with an atomic ratio of 1:1:1 or around it can be used as the second metal oxide. Or, an In-Zn oxide with an atomic ratio of 1:1 or around it can be used as the first metal oxide, and an In-Ga-Zn oxide with an atomic ratio of 1:1:1 or around it can be used as the second metal oxide. Or, an In-Zn oxide with an atomic ratio of 4:1 or around it can be used as the first metal oxide, and an In-Ga-Zn oxide with an atomic ratio of 1:1:1 or around it can be used as the second metal oxide.

[0206] When the semiconductor device according to one embodiment of the present invention is used in a display device, the transistor 100 can be appropriately used for a drive circuit (for example, one or both of a gate line drive circuit and a source line drive circuit) that requires a large on-state current. The transistor 200 can be appropriately used for a pixel circuit that requires high saturation. For example, in a pixel circuit of a display device including a light-emitting device, a transistor (hereinafter, also referred to as a drive transistor) having a function of controlling the current flowing through the light-emitting device is required to have high saturation. The transistor 200 can be appropriately used for the drive transistor.

[0207] The indium content ratio of the second metal oxide can also be higher than that of the first metal oxide. Thereby, the on-state current of the transistor 200 can be increased. In addition, the saturation of the Id-Vd characteristics of the transistor 100 can be improved.

[0208] By adjusting the respective channel lengths and the materials for the semiconductor layers according to the electrical characteristics and reliability required for the transistor 100 and the transistor 200, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0209] The difference in indium content ratios between semiconductor layer 108 and semiconductor layer 208 can be confirmed using EDX, for example. In EDX, the ratio of the number of atoms of each element constituting the metal oxide can be calculated separately. By comparing the ratio (content ratio) of the number of indium atoms to the sum of the number of atoms of all metal elements calculated for semiconductor layer 108 and semiconductor layer 208, the difference in indium content ratios can be confirmed. Additionally, in EDX, the count (detection value) of characteristic X-rays corresponds to the ratio of the elements constituting the metal oxide. Therefore, the difference in indium content ratios can be confirmed by the height of the indium peaks of semiconductor layer 108 and semiconductor layer 208. For example, when the indium content ratio of semiconductor layer 208 is higher than that of semiconductor layer 108, the count of characteristic X-rays from indium in semiconductor layer 208 is higher than the count of characteristic X-rays from indium in semiconductor layer 108. Note that in EDX, the peak of a certain element refers to the point at which the count of that element reaches a maximum value in a spectrum where the horizontal axis represents the energy of characteristic X-rays and the vertical axis represents the count of characteristic X-rays. Alternatively, the difference in content ratios can also be confirmed by the count at the energy of the characteristic X-ray inherent to that element. For example, for indium, the count at 3.287 keV (In-Lα) can be used.

[0210] Here, the indium content ratio is taken as an example for explanation, but the content ratios of other elements are the same. Note that when confirming the difference in content ratios using the count at the energy of the characteristic X-ray inherent to the element, for example, for gallium, the count at 9.243 keV (Ga-Kα) can be used, and for zinc, the count at 8.632 keV (Zn-Kα) can be used.

[0211] [Insulating layer 110]

[0212] Each layer constituting insulating layer 110 preferably uses an inorganic insulating film. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxynitride insulating films, and nitrogen oxide insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of nitrogen oxide insulating films include silicon nitrogen oxide films and aluminum nitrogen oxide films.

[0213] In this specification and the like, oxynitride refers to a material in which the oxygen content in its composition is more than the nitrogen content. Nitrogen oxide refers to a material in which the nitrogen content in its composition is more than the oxygen content. For example, silicon oxynitride refers to a material in which the oxygen content in its composition is more than the nitrogen content, while silicon nitrogen oxide refers to a material in which the nitrogen content in its composition is more than the oxygen content.

[0214] For the compositional analysis, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), or energy dispersive X-ray spectroscopy (EDX) can be used. For example, when the content rate of the target element is high (e.g., 0.5 atomic % or more or 1 atomic % or more), XPS is very suitable. On the other hand, when the content rate of the target element is low (e.g., 0.5 atomic % or less or 1 atomic % or less), SIMS is very suitable. For the compositional analysis, it is preferable to use a plurality of analysis methods. For example, it is more preferable to perform a combined analysis using both SIMS and XPS.

[0215] The insulating layer 110 includes a portion in contact with the semiconductor layer 108. When an oxide semiconductor is used as the semiconductor layer 108, in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110, it is preferable to use an oxide in at least a part of the portion of the insulating layer 110 in contact with the semiconductor layer 108. Specifically, it is preferable to use an oxide in the portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108. The channel formation region is a high-resistance region with a low carrier concentration. It can be said that the channel formation region is i-type (intrinsic) or substantially i-type.

[0216] The insulating layer 110b preferably uses a layer containing oxygen. The insulating layer 110b preferably has a region with an oxygen content larger than that of at least one of the insulating layer 110a and the insulating layer 110c. In particular, the insulating layer 110b preferably has a region with an oxygen content larger than that of each of the insulating layer 110a and the insulating layer 110c.

[0217] The insulating layer 110b preferably uses one or more of the above-mentioned oxide insulating films and oxynitride insulating films. Specifically, the insulating layer 110b preferably uses one or both of a silicon oxide film and a silicon oxynitride film. When the oxygen content of the insulating layer 110b is large, an i-type region is likely to be formed in the region of the semiconductor layer 108 in contact with the insulating layer 110b and in the vicinity thereof.

[0218] The insulating layer 110b preferably uses a film that releases oxygen upon heating. Due to the heat applied during the manufacturing process of the transistor 100, the insulating layer 110b releases oxygen, so that oxygen can be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, especially to the channel formation region of the semiconductor layer 108, oxygen vacancies (V O ) and V O H in the semiconductor layer 108 can be reduced, and a transistor with excellent electrical characteristics and high reliability can be achieved.

[0219] For example, by performing a heat treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere, oxygen can be supplied to the insulating layer 110b. In addition, an oxide film can be deposited on the top surface of the insulating layer 110b by sputtering in an oxygen atmosphere to supply oxygen. Then, the oxide film can also be removed.

[0220] The insulating layer 110b is preferably formed by a deposition method such as sputtering or plasma enhanced chemical vapor deposition (PECVD: Plasma Enhanced Chemical Vapor Deposition). In particular, when using the sputtering method, hydrogen does not need to be used as the deposition gas, so that a film with extremely low hydrogen content can be achieved. Therefore, it is possible to suppress the supply of hydrogen to the semiconductor layer 108 and stabilize the electrical characteristics of the transistor 100.

[0221] As described above, the channel length L100 of the transistor 100 can be made extremely short. When the channel length L100 is short, the influence of oxygen vacancies (V O ) and V O H on the electrical characteristics and reliability of the channel formation region is particularly large. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, it is possible to suppress the increase of oxygen vacancies (V O ) and V O H at least in the region of the semiconductor layer 108 in contact with the insulating layer 110b. Therefore, a transistor with a short channel length having excellent electrical characteristics and high reliability can be achieved.

[0222] The insulating layer 110a and the insulating layer 110c preferably use a film that does not easily diffuse oxygen. Thereby, it is possible to prevent oxygen in the insulating layer 110b from passing through the substrate 102 side through the insulating layer 110a due to heating and through the insulating layer 106 side through the insulating layer 110c. In other words, by sandwiching the insulating layer 110b up and down with the insulating layer 110a and the insulating layer 110c that do not easily diffuse oxygen, the oxygen in the insulating layer 110b can be enclosed. Thereby, oxygen can be effectively supplied to the semiconductor layer 108.

[0223] The insulating layers 110a and 110c are preferably made of a film that does not easily diffuse hydrogen. Thereby, diffusion of hydrogen from the outside of the transistor through the insulating layers 110a and 110c into the semiconductor layer 108 can be suppressed.

[0224] The insulating layers 110a and 110c are preferably made of one or more of the above-described insulating oxide films, insulating nitride films, oxynitride insulating films, and oxynitride insulating films, and are preferably made of one or more of silicon nitride films, silicon oxynitride films, silicon oxynitride films, aluminum oxide films, aluminum oxynitride films, aluminum nitride films, hafnium oxide films, and hafnium aluminate films. In particular, silicon nitride films and silicon oxynitride films have the characteristics of releasing very little of their own impurities (e.g., water and hydrogen) and not easily allowing oxygen and hydrogen to pass through, and thus can be suitably used as the insulating layers 110a and 110c. Note that the insulating layers 110b and 110c may be made of the same material or different materials.

[0225] Note that in this specification and the like, different materials refer to materials having different constituent elements or materials having the same constituent elements but different compositions.

[0226] Here, due to oxygen in the insulating layer 110b, the conductive layers 112 and 109 are oxidized, and sometimes the resistance becomes high. By providing the insulating layer 110a between the insulating layer 110b and the conductive layer 112, oxidation of the conductive layer 112 and an increase in resistance can be suppressed. In addition, by providing the insulating layer 110c between the insulating layer 110b and the conductive layer 109, oxidation of the conductive layer 109 and an increase in resistance can be suppressed. At the same time, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 is increased, and oxygen vacancies in the semiconductor layer 108 can be reduced.

[0227] The thickness of the insulating layers 110a and 110c is preferably 5 nm or more and 150 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 70 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 10 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less. By setting the thickness of the insulating layers 110a and 110c within the above range, oxygen vacancies in the semiconductor layer 108, particularly in the channel formation region, can be reduced.

[0228] For example, the insulating layers 110a and 110c are preferably made of a silicon nitride film, and the insulating layer 110a is preferably made of a silicon oxynitride film.

[0229] Note that in this embodiment, a structure in which the insulating layer 110 has a four-layer stacked structure is shown, but one aspect of the present invention is not limited thereto. The insulating layer 110 may have a single-layer structure or a stacked structure of two, three, or five or more layers. The insulating layer 110 preferably includes at least the insulating layer 110b.

[0230] [Insulation layer 120]

[0231] The insulating layer 120 can use the material that can be used for the insulating layer 110. The insulating layer 120 that is in contact with the semiconductor layer 208 is preferably an insulating layer containing oxygen. The insulating layer 120 can use the material that can be used for the insulating layer 110b as appropriate. For example, silicon oxide or silicon oxynitride can be used as appropriate.

[0232] The insulating layer 120 in contact with the semiconductor layer 208 is preferably formed of a film that releases oxygen by heating, similarly to the insulating layer 110 b. Since the insulating layer 120 releases oxygen due to heat applied in the manufacturing process of the transistor 200, oxygen can be supplied to the semiconductor layer 208 in contact with the insulating layer 120. By supplying oxygen from the insulating layer 120 to the semiconductor layer 208, especially to the channel formation region of the semiconductor layer 208, oxygen vacancies (V O ) and V O H, a transistor with excellent electrical characteristics and high reliability can be realized.

[0233] The insulating layer 120 is preferably located on the insulating layer 110. When the insulating layer 110 including a film in which oxygen is not easily diffused is located between the insulating layer 120 and the substrate 102, oxygen released from the insulating layer 120 can be prevented from penetrating toward the substrate 102 side. Thus, oxygen can be effectively supplied to the semiconductor layer 208. The oxygen concentration in the insulating layer 120 is preferably higher than the oxygen concentration (atomic number concentration, at%) in a layer in which oxygen is not easily diffused, such as the insulating layer 110a or the insulating layer 110c. The oxygen concentration in the insulating layer 120 is preferably higher than the oxygen concentration in a layer in which oxygen is not easily diffused, such as the insulating layer 110a or the insulating layer 110c. In other words, when the semiconductor layer 208 is located on the insulating layer 110 via the insulating layer 120, the oxygen concentration contained in the insulating layer 120 is preferably higher than the oxygen concentration contained in the insulating layer 110. The oxygen concentration contained in the insulating layer 120 and the like can be measured by STEM-EDX analysis or the like.

[0234] Note that although the insulating layer 120 has a single-layer structure in this embodiment, one embodiment of the present invention is not limited thereto. The insulating layer 120 may have a stacked structure of two or more layers. Alternatively, a structure without the insulating layer 120 may be employed.

[0235] [Conductive layer 112, conductive layer 109, conductive layer 104, conductive layer 204, conductive layer 209a, conductive layer 209b, conductive layer 212a, conductive layer 212b]

[0236] The conductive layers 112, 109, 104, 204, 209a, 209b, 212a and 212b can have either a single-layer structure or a laminated structure of two or more layers. As materials that can be used for the conductive layers 112, 109, 104, 204, 209a, 209b, 212a and 212b, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, ruthenium and niobium, and alloys containing one or more of the above metals as components can be cited. A low-resistance conductive material containing one or more of copper, silver, gold and aluminum can be appropriately used for the conductive layers 112, 109, 104, 204, 209a, 209b, 212a and 212b. In particular, copper or aluminum has advantages in mass production and is therefore preferred.

[0237] The conductive layers 112, 109, 104, 204, 209a, 209b, 212a and 212b can use a metal oxide having conductivity (also referred to as an oxide conductor). As the oxide conductor (OC: Oxide Conductor), for example, indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also referred to as ITO containing silicon, ITSO), zinc oxide added with gallium, and In-Ga-Zn oxide can be cited. In particular, a conductive oxide containing indium is preferably used because of its high conductivity.

[0238] Oxygen vacancies are formed in a metal oxide having semiconductor characteristics, and hydrogen is added to the oxygen vacancies to form donor energy levels near the conduction band. As a result, the conductivity of the metal oxide increases and it becomes a conductor. The metal oxide that becomes a conductor can be referred to as an oxide conductor.

[0239] As the conductive layers 112, 109, 104, 204, 209a, 209b, 212a and 212b, a laminated structure of a conductive film containing the above oxide conductor (metal oxide) and a conductive film containing a metal or an alloy can also be adopted. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced.

[0240] As the conductive layers 112, 109, 104, 204, 209a, 209b, 212a, and 212b, a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be applied. By using the Cu-X alloy film, processing can be performed by a wet etching method, thereby suppressing manufacturing costs.

[0241] Note that all the materials for the conductive layers 112, 109, 104, 204, 209a, 209b, 212a, and 212b can be the same, or the materials of at least one of them can also be different.

[0242] The conductive layers 112 and 109 have regions in contact with the semiconductor layer 108. When an oxide semiconductor is used as the semiconductor layer 108, there is a concern that when a metal that is easily oxidized (for example, aluminum) is used as the conductive layer 112 or 109, an insulating oxide (for example, aluminum oxide) is formed between the conductive layer 112 or 109 and the semiconductor layer 108, hindering their conduction. Therefore, it is preferable to use a conductive material that is not easily oxidized or a conductive material that maintains a low resistance even when oxidized for the conductive layers 112 and 109.

[0243] The conductive layers 209a, 209b, 212a, or 212b have regions in contact with the semiconductor layer 208. When an oxide semiconductor is used as the semiconductor layer 208, there is a concern that when a metal that is easily oxidized (for example, aluminum) is used as the conductive layer 209a, 209b, 212a, or 212b, an insulating oxide (for example, aluminum oxide) is formed between the conductive layer 209a, 209b, 212a, or 212b and the semiconductor layer 208, hindering their conduction. Therefore, it is preferable to use a conductive material that is not easily oxidized or a conductive material that maintains a low resistance even when oxidized for the conductive layers 209a, 209b, 212a, or 212b.

[0244] For the conductive layers 112, 109, 209a, 209b, 212a, and 212b, it is preferable to use one or more of titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel, for example. Since these materials are conductive materials that are not easily oxidized or conductive materials that maintain a low resistance even when oxidized, they are preferable.

[0245] The conductive layers 112, 109, 209a, 209b, 212a, and 212b can use the above-mentioned oxide conductors. Specifically, one or more of indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide added with gallium can be used.

[0246] The conductive layers 112, 109, 209a, 209b, 212a, and 212b can also use nitride conductors. For example, one or more of tantalum nitride and titanium nitride can be used.

[0247] The conductive layers 112, 109, 209a, 209b, 212a, and 212b can also all have a stacked structure. When adopting a stacked structure, it is preferred that at least the side in contact with the semiconductor layer 108 uses a conductive material that is not easily oxidized or a conductive material that maintains a low resistance even when oxidized. For example, the conductive layer 112 can have a stacked structure of an aluminum film and a titanium film on the aluminum film. The titanium film has a region in contact with the semiconductor layer 108. In addition, the conductive layer 112 can have a stacked structure of a first titanium film, an aluminum film on the first titanium film, and a second titanium film on the aluminum film. The second titanium film has a region in contact with the semiconductor layer 108.

[0248] [Insulating layer 106]

[0249] The insulating layer 106 can have a single-layer structure or a stacked structure of two or more layers. The insulating layer 106 preferably includes one or more inorganic insulating films. As the inorganic insulating film, for example, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitrogen oxide insulating film can be cited. The insulating layer 106 can use the materials that can be used for the insulating layer 110.

[0250] The insulating layer 106 has regions in contact with the semiconductor layer 108 and the semiconductor layer 208. When the semiconductor layer 108 and the semiconductor layer 208 use an oxide semiconductor, at least the film in the film constituting the insulating layer 106 in contact with the semiconductor layer 108 and the semiconductor layer 208 preferably uses any one of the above-mentioned oxide insulating film and oxynitride insulating film. In addition, the insulating layer 106 more preferably uses a film that releases oxygen by heating.

[0251] Specifically, when the insulating layer 106 has a single-layer structure, the insulating layer 106 preferably uses a silicon oxide film or a silicon oxynitride film.

[0252] In addition, the insulating layer 106 may also have a stacked structure of an oxide insulating film or an oxynitride insulating film in contact with one side of the semiconductor layer 108 and the semiconductor layer 208 and a nitride insulating film or a nitrogen oxide insulating film in contact with one side of the conductive layer 104 and the conductive layer 204. As the oxide insulating film or the oxynitride insulating film, for example, a silicon oxide film or a silicon oxynitride film is preferably used. As the nitride insulating film or the nitrogen oxide insulating film, a silicon nitride film or a silicon nitride oxide film is preferably used.

[0253] The silicon nitride film and the silicon nitride oxide film have the characteristics of releasing very little amount of impurities (such as water and hydrogen) by themselves and not easily allowing oxygen and hydrogen to permeate, so they can be suitably used as the insulating layer 106. Since the diffusion of impurities from the insulating layer 106 to the semiconductor layer 108 and the semiconductor layer 208 is suppressed, excellent electrical characteristics of the transistor can be achieved and the reliability can be improved.

[0254] Note that in a micro transistor, when the thickness of the gate insulating layer is small, the leakage current sometimes increases. By using a material with a relatively high relative dielectric constant (also called a high-k material) for the gate insulating layer, low voltage operation of the transistor can be achieved while maintaining the physical thickness. As the high-k materials that can be used for the insulating layer 106, for example, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium can be cited.

[0255] [Insulating layer 195]

[0256] The insulating layer 195 used as the protective layer of the transistor 100 and the transistor 200 preferably uses a material in which impurities do not easily diffuse. By providing the insulating layer 195, the diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the display device. Examples of impurities include water and hydrogen.

[0257] The insulating layer 195 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, the insulating layer 195 can suitably use an inorganic material such as an oxide, an oxynitride, a nitrogen oxide, or a nitride. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. As the organic material, for example, one or more of an acrylic resin and a polyimide resin can be used. A photosensitive material can also be used as the organic material. In addition, two or more of the above insulating films can be laminated. The insulating layer 195 can also have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0258] [Substrate 102]

[0259] Although there is no particular limitation on the material of the substrate 102, it is at least required to have heat resistance capable of withstanding subsequent heat treatment. For example, a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. In addition, semiconductor elements may be provided on the substrate 102. Note that the shapes of the semiconductor substrate and the insulating substrate may be circular or angular.

[0260] As the substrate 102, a flexible substrate can also be used, and transistors 100 etc. can be directly formed on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the transistors 100 etc. By providing the release layer, after manufacturing a part or all of the semiconductor device on the release layer, it can be separated from the substrate 102 and transferred to another substrate. At this time, the transistors 100 etc. can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0261] Next, a structural example of a semiconductor device and a transistor in which a part of the structure is different from the above structural example 1 will be described. Hereinafter, the description of the parts overlapping with the above structural example 1 may be omitted. In addition, in the following drawings, the parts having the same functions as those in the above structural example 1 are shaded with the same hatching, and sometimes no reference numerals are added.

[0262] Next, a structural example of a semiconductor device and a transistor in which a part of the structure is different from the above structural example 1 will be described. Hereinafter, the description of the parts overlapping with the above structural example 1 may be omitted. In addition, in the following drawings, the parts having the same functions as those in the above structural example 1 are shaded with the same hatching, and sometimes no reference numerals are added.

[0263] <Structural Example 2>

[0264] A semiconductor device according to one embodiment of the present invention will be described. Figure 9A A top view (also referred to as a plan view) of the semiconductor device 10A is shown. Figure 9B Shows a cross-sectional view of the cross-section along the Figure 9A indicated dash-dotted line A1 - A2, Figure 9C and shows cross-sectional views of the cross-sections along the dash-dotted lines B1 - B2 and B3 - B4. Figure 10 A perspective view of the semiconductor device 10A is shown. Figures 11A to 12B A perspective view showing a part of the components of the semiconductor device 10A is shown. Note that in Figure 9A , a part of the components of the semiconductor device 10A (such as an insulating layer) is omitted. In addition, in Figures 10 to 12B , the insulating layer is shown in perspective, and its outline is indicated by a dotted line.

[0265] The semiconductor device 10A includes a transistor 100A and a transistor 200A. The transistor 100A and the transistor 200A have different structures and are both disposed on a substrate 102. In addition, the transistor 100A and the transistor 200A can be formed in a manner where some processes are the same.

[0266] Figure 13 Shown Figure 9B An enlarged view of the shown transistor 100A. The transistor 100A includes a conductive layer 112, a conductive layer 103, an insulating layer 107, an insulating layer 110, an insulating layer 120, a semiconductor layer 108, a conductive layer 109, an insulating layer 106, and a conductive layer 104. Each layer constituting the transistor 100A can have a single-layer structure or a stacked structure.

[0267] The conductive layer 112 is disposed on the substrate 102. The conductive layer 112 is used as one of the source electrode and the drain electrode of the transistor 100A.

[0268] The insulating layer 107 is located on the conductive layer 112. The insulating layer 107 is disposed so as to cover the top surface and the side surfaces of the conductive layer 112.

[0269] The conductive layer 103 is located on the insulating layer 107. The conductive layer 112 and the conductive layer 103 are electrically insulated from each other by the insulating layer 107. As Figure 9B , Figure 11A shown, etc., an opening 148 reaching the insulating layer 107 is provided in a region of the conductive layer 103 that overlaps the conductive layer 112.

[0270] The insulating layer 110 is disposed on the insulating layer 107 and the conductive layer 103. The insulating layer 110 is disposed so as to cover the top surface and the side surfaces of the conductive layer 103 and the top surface of the insulating layer 107.

[0271] The insulating layer 110 preferably has a stacked structure. Figure 9B Shown, etc., is an example of a stacked structure of the insulating layer 110 having an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b.

[0272] The insulating layer 110a is located on the insulating layer 107 and the conductive layer 103. The insulating layer 110a is disposed so as to cover the top surface and the side surfaces of the conductive layer 103. The insulating layer 110a is disposed so as to cover a part of the opening 148. The insulating layer 110a is in contact with the insulating layer 107 through the opening 148.

[0273] An insulating layer 110b is provided on the insulating layer 110a, and an insulating layer 110c is provided on the insulating layer 110b. Furthermore, an insulating layer 120 is provided on the insulating layer 110c. An opening 141 reaching the conductive layer 112 is provided in the insulating layer 107, the insulating layer 110, and the insulating layer 120.

[0274] The conductive layer 109 is located on the insulating layer 120. An opening 143 overlapping with the opening 141 is provided in the conductive layer 109. Note that in Figure 11B , the opening 141 is represented by a dotted line. The conductive layer 109 is used as the other of the source electrode and the drain electrode of the transistor 100A. The conductive layer 109 has a region overlapping with the conductive layer 112 with the insulating layer 107, the insulating layer 110, and the insulating layer 120 therebetween.

[0275] There is no limitation on the top surface shape of the opening 141, the opening 143, and the opening 148. The opening 141, the opening 143, and the opening 148 may be, for example, circular, elliptical, triangular, quadrangular (including rectangular, rhombic, square), pentagonal, or other polygonal shapes or shapes with rounded corners of these polygonal shapes. The polygonal shape may also be a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with interior angles all less than 180 degrees). As Figure 9A and so on show, it is preferable that the top surface shapes of the opening 141, the opening 143, and the opening 148 are all circular. By making the top surface shape of the opening circular, the processing accuracy when forming the opening can be improved, and a fine opening can be formed. Note that in this specification and so on, a circle is not limited to a perfect circle.

[0276] In this specification and so on, the top surface shape of the opening 148 refers to the shape of the top surface end portion or the bottom surface end portion on the opening 148 side of the conductive layer 103.

[0277] As Figure 9A shows, the top surface shape of the opening 141 and the top surface shape of the opening 143 can be made the same or substantially the same. At this time, as Figure 9B , Figure 9C and Figure 13 show, it is preferable that the bottom surface end portion on the opening 143 side of the conductive layer 109 is aligned or substantially aligned with the top surface end portion on the opening 141 side of the insulating layer 120. The bottom surface of the conductive layer 109 refers to the surface on the insulating layer 120 side. The top surface of the insulating layer 120 refers to the surface on the conductive layer 109 side.

[0278] In addition, the top surface shape of the opening 141 and the top surface shape of the opening 143 may also be different. Furthermore, when the top surface shapes of the opening 141 and the opening 143 are circular, the opening 141 and the opening 143 may or may not be concentric.

[0279] When the top surface shapes of the openings 141 and 148 are circular, the openings 141 and 148 are preferably concentric. Thus, when viewed in cross-section, the shortest distances between the semiconductor layer 108 and the conductive layer 103 on the left and right sides of the opening 141 can be made equal. In addition, the openings 141 and 148 may not be concentric.

[0280] The semiconductor layer 108 is in contact with the top surface of the conductive layer 112, the side surfaces of the insulating layer 107, the insulating layer 110, the insulating layer 120, and the top surface and side surfaces of the conductive layer 109. The semiconductor layer 108 is disposed so as to cover the opening 141 and the opening 143. The semiconductor layer 108 is disposed so as to be in contact with the side surfaces on the opening 141 side of the insulating layer 107, the insulating layer 110, and the insulating layer 120 and the end portions (which can also be said to be a part of the top surface and the side surfaces on the opening 143 side) of the conductive layer 109 on the opening 143 side. The semiconductor layer 108 is in contact with the conductive layer 112 through the opening 141 and the opening 143.

[0281] Figure 9B An example is shown in which the end portion of the semiconductor layer 108 is in contact with the top surface of the conductive layer 109, but the present invention is not limited thereto. The semiconductor layer 108 may also cover the end portion of the conductive layer 109 and the end portion of the semiconductor layer 108 may be in contact with the top surface of the insulating layer 120.

[0282] The insulating layer 106 is located on the insulating layer 120, the semiconductor layer 108, and the conductive layer 109. The insulating layer 106 is disposed so as to cover the opening 141 and the opening 143 with the semiconductor layer 108 interposed therebetween. A part of the insulating layer 106 is used as the gate insulating layer of the transistor 100A.

[0283] The conductive layer 104 is located on the insulating layer 106. The conductive layer 104 overlaps with the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 is used as the gate electrode of the transistor 100A.

[0284] In the transistor 100A, the semiconductor layer 108 has a region that overlaps with the conductive layer 104 with the insulating layer 106 interposed therebetween and overlaps with the conductive layer 103 with a part of the insulating layer 110 (in particular, the insulating layer 110a and the insulating layer 110b) interposed therebetween. In other words, in the semiconductor layer 108, there is a region that is clamped by the conductive layer 104 and the conductive layer 103 with a part of the insulating layer 106 and the insulating layer 110 (in particular, the insulating layer 110f and the insulating layer 110c) interposed therebetween.

[0285] The conductive layer 103 is used as the back gate electrode of the transistor 100A. In addition, a part of the insulating layer 110 and the insulating layer 120 is used as the back gate insulating layer of the transistor 100A. In addition, the conductive layer 103 may not be provided.

[0286] By providing a back gate electrode in the transistor 100A, the potential of the back gate side (also referred to as the back channel) of the semiconductor layer 108 can be fixed, and the saturation of the Id-Vd characteristics of the transistor 100A can be improved.

[0287] Note that in this specification and the like, the case where the current change in the saturation region of the Id-Vd characteristics of a transistor is small is sometimes expressed as "high saturation".

[0288] Since the transistor 100A includes a back gate electrode, the potential of the back gate side of the semiconductor layer 108 can be fixed, and the drift of the threshold voltage can be suppressed. Here, when the threshold voltage of a transistor drifts, the drain current flowing when the gate voltage is 0V (hereinafter, also referred to as the cut-off current) sometimes increases. By suppressing the drift of the threshold voltage of the transistor 100A, a transistor with a small cut-off current can be realized. Note that a small cut-off current is sometimes described as normally-off.

[0289] The transistor 100A is a so-called top gate type transistor having a gate electrode above the semiconductor layer 108. Furthermore, since the bottom surface of the semiconductor layer 108 is in contact with the source electrode and the drain electrode, it can be said to be a TGBC (Top Gate Bottom Contact) type transistor. In addition, in the transistor 100A, the heights of the source electrode and the drain electrode with respect to the surface of the substrate 102 of the formed surface (for example, the height in the direction perpendicular to the surface of the substrate or the insulating plane on which the transistor is provided) are different from each other, and the drain current flows in a direction perpendicular to or substantially perpendicular to the surface of the substrate 102. It can also be said that in the transistor 100A, the drain current flows in the longitudinal direction or the substantially longitudinal direction. Therefore, the transistor of one embodiment of the present invention can be said to be a longitudinal channel type transistor or a VFET (Vertical Field Effect Transistor).

[0290] In addition, an opening reaching the conductive layer 112 may be provided in the region of the insulating layer 107 that overlaps with the conductive layer 103 and the conductive layer 112. At this time, the conductive layer 103 is provided so as to cover the opening and is electrically connected to the conductive layer 112 through the opening. By electrically connecting the conductive layer 112 serving as the source electrode or the drain electrode and the conductive layer 103 serving as the back gate electrode, the source electrode or the drain electrode and the back gate electrode can have the same potential. For example, when the conductive layer 112 is used as the source electrode, the drift of the threshold voltage of the transistor can be suppressed. In addition, the reliability of the transistor can be improved.

[0291] The channel length of the transistor 100A can be controlled by the thickness of the insulating layers (here, insulating layer 107, insulating layer 110, and insulating layer 120) provided between the conductive layer 112 and the conductive layer 109. Therefore, a transistor having a channel length shorter than the limit resolution of the exposure apparatus used to manufacture the transistor can be manufactured with high precision. In addition, the characteristic non-uniformity between multiple transistors 100A can be reduced. Therefore, the operation of the semiconductor device including the transistor 100A is stable, and the reliability can be improved. In addition, when the characteristic non-uniformity is reduced, the degree of freedom in circuit design is increased, and the maximum operating voltage can also be reduced. Thereby, the power consumption of the semiconductor device can be reduced.

[0292] In the transistor 100A, the source electrode, the semiconductor layer, and the drain electrode can be overlapped and arranged, so that the occupied area can be significantly reduced compared with a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0293] The conductive layer 112, the conductive layer 109, and the conductive layer 104 can all be used as wirings, and the transistor 100A can be provided in the region where these wirings overlap. That is, in a circuit including the transistor 100A and the wirings, the occupied area of the transistor 100A and the wirings can be reduced. Therefore, the occupied area of the circuit can be reduced to realize a small semiconductor device.

[0294] For example, when the semiconductor device according to one embodiment of the present invention is used in a pixel circuit of a display device, the occupied area of the pixel circuit can be reduced, and a high-definition display device can be realized. In addition, for example, when the semiconductor device according to one embodiment of the present invention is used in a driving circuit of a display device (for example, one or both of a gate line driving circuit and a source line driving circuit), the occupied area of the driving circuit can be reduced, and therefore, a display device with a narrow border can be realized.

[0295] Figure 9B Examples in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the opening 141 and the opening 143 are shown, but one embodiment of the present invention is not limited thereto. In addition, a structure in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along the steps formed by the insulating layer 107, the insulating layer 110, the insulating layer 120, the conductive layer 109, and the conductive layer 112 can also be adopted.

[0296] The transistor 200A includes a conductive layer 202, an insulating layer 107, an insulating layer 110, an insulating layer 120, a conductive layer 209a, a conductive layer 209b, a semiconductor layer 208, an insulating layer 106, a conductive layer 212a, a conductive layer 212b, and a conductive layer 204. Each layer constituting the transistor 200A can have a single-layer structure or a laminated structure.

[0297] The conductive layer 202 is provided on the substrate 102. The conductive layer 202 is used as the back gate electrode of the transistor 200A. The conductive layer 202 can use, for example, the same material as the conductive layer 112. Furthermore, the conductive layer 202 can be formed by the same process as the conductive layer 112. For example, by forming a conductive film that will become the conductive layer 112 and the conductive layer 202 and processing the conductive film, the conductive layer 112 and the conductive layer 202 can be formed.

[0298] An insulating layer 107 is provided on the conductive layer 202, an insulating layer 110 is provided on the insulating layer 107, and an insulating layer 120 is provided on the insulating layer 110. A part of the insulating layer 107, the insulating layer 110, and the insulating layer 120 is used as the back gate insulating layer of the transistor 200A.

[0299] The conductive layer 209a and the conductive layer 209b are provided on the insulating layer 120. The conductive layer 209a is electrically connected to one of the source electrode and the drain electrode of the transistor 200A, and the conductive layer 209b is electrically connected to the other of the source electrode and the drain electrode of the transistor 200A. Furthermore, the conductive layer 209a and the conductive layer 209b can be formed by the same process as the conductive layer 109. For example, by forming a conductive film that will become the conductive layer 109, the conductive layer 209a, and the conductive layer 209b and processing the conductive film, the conductive layer 209a and the conductive layer 209b can be formed.

[0300] A semiconductor layer 208 is provided on the conductive layer 209a, the conductive layer 209b, and the insulating layer 120. The semiconductor layer 208 has a region that overlaps with the conductive layer 202 with the insulating layer 107, the insulating layer 110, and the insulating layer 120 interposed therebetween. The semiconductor layer 208 can use, for example, the same material as the semiconductor layer 108. Furthermore, the semiconductor layer 208 can be formed by the same process as the semiconductor layer 108. For example, by forming a semiconductor film that will become the semiconductor layer 108 and the semiconductor layer 208 and processing the semiconductor film, the semiconductor layer 108 and the semiconductor layer 208 can be formed.

[0301] An insulating layer 106 is provided on the insulating layer 120, the conductive layer 209a, the conductive layer 209b, and the semiconductor layer 208. A part of the insulating layer 106 is used as the gate insulating layer of the transistor 200A. In addition, the insulating layer 106 has openings 147a and 147b that reach the semiconductor layer 208.

[0302] A conductive layer 204, a conductive layer 212a, and a conductive layer 212b are provided on the insulating layer 106. The conductive layer 204, the conductive layer 212a, and the conductive layer 212b can use, for example, the same material as the conductive layer 104. Furthermore, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed by the same process as the conductive layer 104. For example, by forming a conductive film that will become the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b and processing the conductive film, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed. The conductive layer 212a has a portion that overlaps with the conductive layer 209a with the semiconductor layer 108 therebetween, and the conductive layer 212b has a portion that overlaps with the conductive layer 209b with the semiconductor layer 108 therebetween. In addition, the conductive layer 212a may have a portion in contact with the conductive layer 209a, and similarly, the conductive layer 212b may have a portion in contact with the conductive layer 209b. In other words, the semiconductor layer 108 has a region sandwiched between the conductive layer 209a and the conductive layer 212a and a region sandwiched between the conductive layer 209b and the conductive layer 212b.

[0303] The conductive layer 204 has a region that overlaps with the semiconductor layer 208 with the insulating layer 106 therebetween and is used as the gate electrode of the transistor 200A. The end of the conductive layer 204 is located inside the end of the insulating layer 106. It can also be said that the end of the conductive layer 204 is in contact with the top surface of the insulating layer 106. In addition, it can also be said that the insulating layer 106 has a portion that protrudes at least outside the end of the conductive layer 204 on the semiconductor layer 208.

[0304] The conductive layer 212a is provided so as to cover at least a part of the opening 147a and is in contact with the semiconductor layer 208 through the opening 147a. In addition, the conductive layer 212b is provided so as to cover at least a part of the opening 147b and is in contact with the semiconductor layer 208 through the opening 147b. The conductive layer 212a is used as one of the source electrode and the drain electrode of the transistor 200A, and the conductive layer 212b is used as the other of the source electrode and the drain electrode of the transistor 200A. In addition, the conductive layer 212a may also be in contact with the conductive layer 209a in the opening 147a. Similarly, the conductive layer 212b may also be in contact with the conductive layer 209b in the opening 147b.

[0305] In the semiconductor layer 208, the entire region that overlaps with the gate electrode with the gate insulating layer therebetween between the source electrode and the drain electrode is used as the channel formation region. The semiconductor layer 208 has a pair of regions 208L that sandwich the channel formation region and a pair of regions 208D outside thereof. For the description of the region 208L and the region 208D, reference can be made to Structural Example 1.

[0306] As Figure 9B and Figure 9CAs shown, the ends of a part of the conductive layer 212a and the conductive layer 212b are preferably located inside the openings 147a and 147b. In other words, in the openings 147a and 147b, the ends of a part of the conductive layer 212a and the conductive layer 212b are preferably in contact with the semiconductor layer 208. Thereby, the region in contact with the conductive layer 212a can be adjacent to one of the pair of regions 208D, and similarly, the region in contact with the conductive layer 212b can be adjacent to the other of the pair of regions 208D.

[0307] Note that there is no particular limitation on the top surface shape of the openings 147a and 147b. Figure 9A Structures such as those shown in which the top surface shapes of the openings 147a and 147b are different from the top surface shapes of the openings 141 and 143 are shown, but one aspect of the present invention is not limited thereto. The top surface shapes of the openings 147a and 147b may also be the same as the top surface shapes of the openings 141 and 143.

[0308] As Figure 9C shown, the conductive layer 204 can also be electrically connected to the conductive layer 202 through the opening 149 provided in the insulating layer 106, the insulating layer 120, the insulating layer 110, and the insulating layer 107. Thereby, the same potential can be supplied to the conductive layer 204 and the conductive layer 202. By supplying the same potential to the conductive layer 204 and the conductive layer 202, the current that can flow when the transistor 200A is in the on state can be increased.

[0309] Note that there is no particular limitation on the top surface shape of the opening 149. The top surface shape of the opening 149 can be, for example, circular or elliptical. The top surface shapes of the openings 149 can also all be polygonal shapes such as triangular, quadrangular (including rectangular, rhombic, square), pentagonal, etc., or shapes in which the corners of these polygonal shapes are rounded. The top surface shape of the opening 149 can be the same as or different from the top surface shapes of the openings 141, 143, and 148. In addition, the top surface shape of the opening 149 can be the same as or different from the top surface shapes of the openings 147a and 147b.

[0310] As Figure 9A and Figure 9C shown, it is preferable that the conductive layer 204 and the conductive layer 202 protrude outside the ends of the semiconductor layer 208 in the channel width direction of the transistor 200A. At this time, as Figure 9CAs shown, the entirety in the channel width direction of the semiconductor layer 208 is covered by the conductive layer 204 and the conductive layer 202 with the insulating layer 106, the insulating layer 110, the insulating layer 120, and the insulating layer 107 in between. By adopting such a structure, the semiconductor layer 208 can be surrounded by the electric field generated by a pair of gate electrodes. At this time, it is particularly preferable to supply the same potential to the conductive layer 204 and the conductive layer 202. Thereby, an electric field for causing a channel can be effectively applied to the semiconductor layer 208, and the on-state current of the transistor 200A can be increased. Therefore, a miniature transistor 200A can be realized.

[0311] In addition, the conductive layer 204 may not be connected to the conductive layer 202. At this time, a constant potential can be supplied to one of the pair of gate electrodes, and a signal for driving the transistor 200A can be supplied to the other. At this time, the threshold voltage when driving the transistor 200A with the other gate electrode can be controlled by using the potential supplied to one gate electrode.

[0312] The conductive layer 202 may also be electrically connected to the conductive layer 212a or the conductive layer 212b. At this time, a structure in which the conductive layer 212a or the conductive layer 212b is electrically connected to the conductive layer 202 through an opening provided in the insulating layer 106, the insulating layer 120, the insulating layer 110, and the insulating layer 107 may be adopted.

[0313] Note, Figure 9B and Figure 9C An example in which both the transistor 100A and the transistor 200A include the insulating layer 120 is shown, but the transistor 100A may not include the insulating layer 120. At this time, the transistor 200A may include an island-shaped insulating layer 120.

[0314] As described above, the transistor 100A with a short channel length and the transistor 200A with a long channel length can be formed on the same substrate in a manner where a part of the processes is common. For example, by using the transistor 100A as a transistor that requires a large on-state current and using the transistor 200A as a transistor that requires high saturation characteristics, a high-performance semiconductor device can be realized.

[0315] The insulating layer 195 is provided to cover the transistor 100A and the transistor 200A. The insulating layer 195 is used as a protective layer for the transistor 100A and the transistor 200A.

[0316] The detailed structures of the transistor 100A and the transistor 200A will be described.

[0317] First, with reference to Figure 14A and Figure 14B the channel length and the channel width of the transistor 100A will be described. Figure 14A is Figure 9A an enlarged view of the transistor 100A shown,Figure 14B is Figure 9B an enlarged view of the transistor 100A shown in

[0318] In the semiconductor layer 108, the region in contact with the conductive layer 112 is used as one of the source region and the drain region, the region in contact with the conductive layer 109 is used as the other of the source region and the drain region, and the region between the source region and the drain region is used as the channel formation region.

[0319] The channel length of the transistor 100A is the distance between the source region and the drain region. In Figure 14B it, the channel length L100 of the transistor 100A is indicated by a double-headed arrow in dashed lines. The channel length L100 can be said to be the shortest distance between the region of the semiconductor layer 108 in contact with the conductive layer 112 and the region in contact with the conductive layer 109 when viewed in cross section.

[0320] The channel length L100 of the transistor 100A corresponds to the length of the side on the opening 141 side of the insulating layer sandwiched between the conductive layer 112 and the conductive layer 109 when viewed in cross section. That is, the channel length L100 is determined by the thickness Tins of the insulating layer sandwiched between the conductive layer 112 and the conductive layer 109 (here, the sum of the thicknesses of the insulating layer 107, the insulating layer 110, and the insulating layer 120) and the angle θins formed by the side on the opening 141 side of these insulating layers and the formation surface (here, the top surface of the conductive layer 112). Therefore, for example, the channel length L100 can be set to a value smaller than the limit resolution of the exposure apparatus, and a micro transistor can be realized. Specifically, a transistor with an extremely short channel length that cannot be realized by an exposure apparatus (for example, with a minimum line width of about 2 μm or 1.5 μm) used in the mass production of existing flat panel displays can be realized. In addition, a transistor with a channel length less than 10 nm can be realized without using a very expensive exposure apparatus used in the most advanced LSI technology.

[0321] The channel length L100 can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 can be set to 100 nm or more and 1 μm or less.

[0322] By shortening the channel length L100, the on-state current of the transistor 100A can be increased. By using the transistor 100A, a circuit capable of operating at high speed can be fabricated. Furthermore, the occupied area of the circuit can be reduced. Accordingly, a small semiconductor device can be realized. For example, in the case where the semiconductor device according to one embodiment of the present invention is used for a large display device or a high-definition display device, even when the number of wirings increases, the signal delay of each wiring can be reduced, thereby suppressing display unevenness. In addition, since the occupied area of the circuit can be reduced, the bezel of the display device can be made smaller.

[0323] By adjusting the thickness Tins and the angle θins, the channel length L100 can be controlled. Note that, in Figure 14B the thickness Tins is indicated by a double-headed dotted line.

[0324] The thickness Tins can be, for example, 10 nm or more, 50 nm or more, 100 nm or more, 150 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more and less than 3.0 μm, 2.5 μm or less, 2.0 μm or less, 1.5 μm or less, 1.2 μm or less, 1.0 μm or less.

[0325] The side surfaces on the opening 141 side of the insulating layer 107, the insulating layer 110, and the insulating layer 120 preferably have a tapered shape. The angle θins formed by the side surfaces on the opening 141 side of the insulating layer 107, the insulating layer 110, and the insulating layer 120 and the formed surface of the insulating layer 110 (here, the top surface of the conductive layer 112) is preferably 90 degrees or less. By reducing the angle θins, the coverage of the layer provided on these insulating layers (for example, the semiconductor layer 108) can be improved. In addition, the smaller the angle θins, the longer the channel length L100 can be, and the larger the angle θins, the shorter the channel length L100 can be.

[0326] The angle θins can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more and 90 degrees or less, 85 degrees or less, or 80 degrees or less. The closer the angle θins is to 90 degrees, the smaller the installation area of the transistor 100 can be, which is advantageous for high density.

[0327] Note that, in Figure 14B etc., a structure is shown in which the side surfaces on the opening 141 side of the insulating layer 107, the insulating layer 110, and the insulating layer 120 are straight when viewed in cross section, but one embodiment of the present invention is not limited thereto. When viewed in cross section, the side surfaces on the opening 141 side of the insulating layer 107, the insulating layer 110, and the insulating layer 120 may be curved, or may have both a region where the side surface shape is straight and a region where the side surface shape is curved.

[0328] In Figure 14A and Figure 14B a double-headed arrow with a double dash line indicates the width D143 of the opening 143. Figure 14A An example is shown in which the top surfaces of the opening 141 and the opening 143 are circular. At this time, the width D143 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100A corresponds to the length of the circumference of the circle. That is, the channel width W100 is π×D143. In this way, when the top surfaces of the opening 141 and the opening 143 are circular, a transistor with a smaller channel width W100 can be realized compared with other shapes.

[0329] Note that the diameter of the opening 141 and the diameter of the opening 143 may sometimes be different. In addition, the diameters of the opening 141 and the opening 143 may sometimes change in the depth direction. As the diameter of the opening, for example, the average value of the diameters at the highest position, the lowest position, and the position of the midpoint of the insulating layer 107, the insulating layer 110, and the insulating layer 120 when viewed from the cross section can be used. Alternatively, as the diameter of the opening, for example, any one of the diameters at the highest position, the lowest position, and the position of the midpoint of the insulating layer 107, the insulating layer 110, and the insulating layer 120 when viewed from the cross section can also be used.

[0330] When the opening 143 is formed by photolithography, the width D143 of the opening 143 is above the limit resolution of the exposure apparatus. The width D143 can be, for example, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more and less than 5.0 μm, 4.5 μm or less, 4.0 μm or less, 3.5 μm or less, 3.0 μm or less, 2.5 μm or less, 2.0 μm or less, 1.5 μm or less, or 1.0 μm or less.

[0331] Next, with reference to Figure 14B the conductive layer 103 used as the back gate electrode of the transistor 100A will be described.

[0332] The thickness T103 of the conductive layer 103 is preferably 0.5 times or more, more preferably 1.0 times or more, further preferably more than 1.0 times, and preferably 2.0 times or less, more preferably 1.5 times or less, further preferably 1.2 times or less of the channel length L100. Thereby, the region in the semiconductor layer 108 that overlaps with the conductive layer 104 with the insulating layer 106 interposed therebetween and overlaps with the conductive layer 103 with the insulating layer 110 and the insulating layer 120 interposed therebetween can be sufficiently enlarged. Therefore, the potential on the back gate side of the semiconductor layer 108 can be controlled more reliably.

[0333] The thickness T103 of the conductive layer 103 may also be greater than the thickness Tins. Thereby, the potential on the back gate side of the semiconductor layer 108 can be fixed over a wide range between the source region and the drain region in the semiconductor layer 108.

[0334] The transistor 100A according to one embodiment of the present invention has a region in which a conductive layer 103, an insulating layer 110, an insulating layer 120, a semiconductor layer 108, an insulating layer 106, and a conductive layer 104 are sequentially overlapped in one direction, and no other layers are included therebetween. As this direction, a direction perpendicular to the channel length L100 can be cited. By expanding this region, the potential on the back gate side of the semiconductor layer 108 can be controlled more reliably.

[0335] The thickness T103 of the conductive layer 103 may be greater than the sum of the thickness of the portion in contact with the conductive layer 112 inside the opening 141 in the semiconductor layer 108 and the thickness of the insulating layer 106 in contact with this portion.

[0336] The shortest distance L11 between the conductive layer 103 and the semiconductor layer 108 when viewed in cross section is preferably smaller than the channel length L100, more preferably 0.5 times or less, and further preferably 0.1 times or less. The closer the distance between the conductive layer 103 and the semiconductor layer 108, the more the saturation in the Id-Vd characteristics of the transistor 100A can be improved.

[0337] Note that when viewed in cross section, the shortest distance between the conductive layer 103 and the semiconductor layer 108 on the left and right sides of the opening 141 may be different. In this case, it is preferable that the distance L11 on at least one of the left and right sides of the opening 141 satisfies the above range, and more preferably, the distances L11 on both the left and right sides of the opening 141 satisfy the above range. In any cross section, the shortest distance between the conductive layer 103 on the left side of the opening 141 and the semiconductor layer 108 is preferably 50% or more and 150% or less, more preferably 30% or more and 130% or less, and further preferably 10% or more and 110% or less of the shortest distance on the right side of the opening 141.

[0338] Note, Figure 14B etc. show examples where the thickness of the insulating layer 107 is uniform at any position, but one embodiment of the present invention is not limited thereto. The thickness of the region of the insulating layer 107 overlapping with the conductive layer 103 may also be different from the thickness of the region of the insulating layer 107 not overlapping with the conductive layer 103. For example, when forming the conductive layer 103, sometimes a part of the region of the insulating layer 107 not overlapping with the conductive layer 103 is removed, whereby its thickness is reduced. Therefore, as Figure 15A shown, sometimes the thickness of the region of the insulating layer 107 not overlapping with the conductive layer 103 is smaller than the thickness of the region of the insulating layer 107 overlapping with the conductive layer 103.

[0339] As Figure 15B shown, the insulating layer 107 in the region not overlapping with the conductive layer 103 can also be removed, and the insulating layer 110a has a region in contact with the conductive layer 112. For example, when forming the conductive layer 103, the insulating layer 107 in the region not overlapping with the conductive layer 103 can be removed. In the case where the insulating layer 107 in the region not overlapping with the conductive layer 103 is removed, the thickness Tins is the sum of the thicknesses of the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, and the insulating layer 120. The thickness Tins is preferably within the above range.

[0340] Next, refer to Figures 16A to 16C to describe the channel length and channel width of the transistor 200A. Figure 16A is a top view of the transistor 200A, Figure 16B and Figure 9B is an enlarged view of the transistor 200A shown in Figure 16C and Figure 9C is an enlarged view of the transistor 200A shown in

[0341] In the semiconductor layer 208, a pair of regions 208D are used as the source region and the drain region, and the region between the source region and the drain region is used as the channel formation region. The channel formation region includes a region overlapping with the conductive layer 204 with the insulating layer 106 therebetween.

[0342] The channel length of the transistor 200A is the length of the region where the semiconductor layer 208 and the conductive layer 204 overlap between the pair of regions 208D. In Figure 16A and Figure 16B , the channel length L200 of the transistor 200A is indicated by a double-headed dashed arrow. The channel length L200 of the transistor 200A is determined according to the length of the conductive layer 204 and is a value above the limit resolution of the exposure apparatus used in the manufacture of the transistor. For example, the channel length L200 can be 1.5 μm or more. By increasing the channel length, a transistor with high saturation characteristics can be realized.

[0343] The channel width of the transistor 200A is the width of the region where the semiconductor layer 208 and the conductive layer 204 overlap in the direction orthogonal to the channel length direction. In Figure 16A and Figure 16C , the channel width W200 of the transistor 200A is indicated by a double-headed solid arrow.

[0344] As described above, the channel length L100 of the transistor 100A can be set to a value smaller than the limit resolution of the exposure apparatus, and the channel length L200 of the transistor 200A can be set to a value equal to or greater than the limit resolution of the exposure apparatus. For example, by using the transistor 100A for a transistor that requires a large on-state current and using the transistor 200A for a transistor that requires high saturation characteristics, a high-performance semiconductor device 10A that exhibits the advantages of each transistor can be realized.

[0345] In the semiconductor device 10A according to one embodiment of the present invention, transistors 100A and 200A having different structures and channel lengths can be formed on the substrate 102 in the same partial process. Specifically, the conductive layer 112 and the conductive layer 202 can be formed by the same process. The semiconductor layer 108 and the semiconductor layer 208 can be formed by the same process. A part of the insulating layer 106 is used as the gate insulating layer of the transistor 100A, and another part of the insulating layer 106 is used as the gate insulating layer of the transistor 200A. The conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed by the same process. Therefore, the productivity of the semiconductor device 10A can be improved and the manufacturing cost can be reduced.

[0346] Note that Figure 16B etc. show an example in which the thickness of the semiconductor layer 208 is uniform at any position, but one embodiment of the present invention is not limited thereto. As Figure 17A shown, the thickness may also be different between the region of the semiconductor layer 208 that overlaps with the insulating layer 106 and the region that does not overlap with the insulating layer 106. For example, when forming the openings 147a and 147b, sometimes a part of the semiconductor layer 208 is removed, and the thickness of the region of the semiconductor layer 208 that does not overlap with the insulating layer 106 is smaller than the thickness of the region that overlaps with the insulating layer 106. Or, as Figure 17B shown, the thickness may also be different between the region of the semiconductor layer 208 that overlaps with any one of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b and the region that does not overlap with any one of them. For example, when forming the conductive layer 212a and the conductive layer 212b, sometimes a part of the semiconductor layer 208 is removed, and the thickness of the region of the semiconductor layer 208 that does not overlap with any one of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b is smaller than the thickness of the region that overlaps with any one of them. Or, as Figure 17C shown, the thickness may also be different between the region of the semiconductor layer 208 that overlaps with the insulating layer 106, the region that overlaps with any one of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b, and the region that does not overlap with any one of them.

[0347] The following description includes the components in the semiconductor device of the present embodiment. Note that for the semiconductor layer 108, semiconductor layer 208, insulating layer 110, insulating layer 120, conductive layer 112, conductive layer 109, conductive layer 104, conductive layer 204, conductive layer 212a, conductive layer 212b, insulating layer 106, insulating layer 195, and substrate 102, etc., reference can be made to the description of Structural Example 1.

[0348] [Insulating layer 107]

[0349] The insulating layer 107 can use the materials that can be used for the insulating layer 110. The insulating layer 107 in contact with the conductive layer 112 preferably uses a nitrogen-containing insulating layer. The insulating layer 107 can appropriately use the materials that can be used for the insulating layer 110a and insulating layer 110c. For example, the insulating layer 107 can appropriately use silicon nitride.

[0350] Note that in the present embodiment, the insulating layer 107 having a single-layer structure is shown, but one aspect of the present invention is not limited thereto. The insulating layer 107 can also have a stacked structure of two or more layers.

[0351] [Conductive layer 103, conductive layer 202]

[0352] The conductive layer 103 and the conductive layer 202 can have either a single-layer structure or a stacked structure of two or more layers. The conductive layer 103 and the conductive layer 202 can use the materials that can be used for the conductive layer 112, etc.

[0353] Next, a structural example of a semiconductor device and a transistor in which a part of the structure is different from the above Structural Example 1 or Structural Example 2 will be described. Hereinafter, the description of the parts that overlap with the above Structural Example 1 or Structural Example 2 may be omitted. In addition, in the following drawings, the parts having the same functions as those in the above Structural Example 2 are shaded with the same hatching, and sometimes no reference numerals are added.

[0354] <Structural Example 3>

[0355] Figure 18A and Figure 18B is a cross-sectional view of a semiconductor device 10B according to one aspect of the present invention. The top view of the semiconductor device 10B can be referred to Figure 9A . Figure 18A is a cross-sectional view of the cross-section along the dash-dot line A1 - A2 shown in Figure 9A , Figure 18B is a cross-sectional view of the cross-section along the dash-dot lines B1 - B2 and dash-dot line B3 - B4 shown in Figure 9A .

[0356] The semiconductor device 10B includes a transistor 100B and a transistor 200B. The transistor 100B is connected to Figure 9BThe main difference of the transistor 100A shown, etc., is that the transistor 100B does not include the insulating layer 120. The transistor 200B and Figure 9B The main difference of the transistor 200A shown, etc., is that in the transistor 200B, the shape of the insulating layer 120 is island-shaped.

[0357] Note that in this specification, etc., the island shape means a state where two or more layers formed in the same process and using the same material are physically separated.

[0358] In the transistor 100B, the conductive layer 109 is provided in contact with the insulating layer 110 (here, the insulating layer 110c). The semiconductor layer 108 is in contact with the top surface of the conductive layer 112, the side surface of the insulating layer 110, and the top surface and side surfaces of the conductive layer 109.

[0359] When the insulating layer 120 has a region in contact with the conductive layer 109, there is a concern that the conductive layer 109 may be oxidized by the oxygen released from the insulating layer 120, and thus the resistance of the conductive layer 109 becomes high. In the transistor 100B, by adopting a structure in which the insulating layer 120 does not have a region in contact with the conductive layer 109, an increase in the resistance of the conductive layer 109 can be suppressed.

[0360] Figure 19A Shown Figure 18A An enlarged view of the transistor 100B shown. The region of the semiconductor layer 108 in contact with the insulating layer 110 is used as a channel formation region. Figure 19A The channel length L100 of the transistor 100B is indicated by a double-headed arrow in dashed lines. The channel length L100 of the transistor 100B is determined by the thickness Tins of the insulating layer in contact with the channel formation region when viewed in cross-section (here, the sum of the thicknesses of the insulating layers 107 and 110) and the angle θins formed by the side surface on the opening 141 side of the insulating layer and the formed surface (here, the top surface of the conductive layer 112). The thickness Tins and the angle θins are preferably both within the above ranges.

[0361] Note that at least one of the regions of the semiconductor layer 108 in contact with the insulating layer 107, the region in contact with the insulating layer 110a, and the region in contact with the insulating layer 110c may also have a higher carrier concentration and lower resistance than the channel formation region. That is, sometimes the regions of the semiconductor layer 108 in contact with the insulating layer 107, the region in contact with the insulating layer 110a, and the region in contact with the insulating layer 110c are respectively used as a source region or a drain region.

[0362] For example, by using a material for the insulating layer 110c that releases impurities (e.g., water or hydrogen), the region of the semiconductor layer 108 in contact with the insulating layer 110c can be used as a source region or a drain region. The same applies to the insulating layers 107 and 110a.

[0363] As the insulating layer 107, insulating layer 110a, and insulating layer 110c, materials that release impurities (e.g., water or hydrogen) can also be used. Figure 19B A structure is shown in which the regions in contact with the insulating layer 107, the regions in contact with the insulating layer 110a, and the regions in contact with the insulating layer 110c are respectively used as source regions or drain regions. At this time, the region in contact with the insulating layer 110b in the semiconductor layer 108 is used as a channel formation region. The channel length L100 of the transistor 100B is determined by the thickness Tins of the insulating layer in contact with the channel formation region as viewed in cross section (here, the thickness of the insulating layer 110b) and the angle θins formed by the side surface of the opening 141 of the insulating layer 110b and the formed surface (here, the top surface of the insulating layer 110a). The thickness Tins is preferably within the above range. The angle θins is preferably within the range of the above angle θins.

[0364] The amount of impurities (e.g., water or hydrogen) released from the insulating layer 107, insulating layer 110a, and insulating layer 110c can also be different. For example, a material with a higher amount of impurity release than the insulating layer 110a can be used for the insulating layer 107. The insulating layer 107 preferably releases hydrogen from itself by the heat applied during the process. Hydrogen is supplied from the insulating layer 107 to the region in contact with the insulating layer 107 in the semiconductor layer 108, and the resistance of this region becomes low. This region (hereinafter, also referred to as a low-resistance region) can be used as a source region or a drain region. By providing a low-resistance region on the side of the conductive layer 112 in the semiconductor layer 108, the distance from the source region to the gate electrode and the distance from the drain region to the gate electrode can be further made uniform. As a result, the electric field applied to the gate electrode in the channel formation region can be further made uniform.

[0365] Figure 20 A structure is shown in which the regions in contact with the insulating layer 107 and the regions in contact with the insulating layer 110c in the semiconductor layer 108 are used as source regions or drain regions. The channel length L100 of the transistor 100B is determined by the thickness Tins of the insulating layer in contact with the channel formation region as viewed in cross section (here, the sum of the thicknesses of the insulating layer 110a and the insulating layer 110b) and the angle θins formed by the side surface of the opening 141 of the insulating layer 110a and the formed surface (here, the top surface of the insulating layer 107). The thickness Tins is preferably within the above range. The angle θins is preferably within the range of the above angle θins.

[0366] The insulating layer 110a preferably releases a small amount of impurities from itself and is not easily permeated by impurities. As a result, it is possible to suppress the diffusion of hydrogen to the channel formation region and its vicinity in the semiconductor layer 108 through the insulating layer 110a and the insulating layer 110b, and thus a transistor with excellent electrical characteristics and high reliability can be realized.

[0367] The insulating layer 107 preferably includes regions having a higher hydrogen content than the insulating layer 110a. In the analysis of the hydrogen content of the insulating layer 110 (the insulating layer 107, the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c), for example, secondary ion mass spectrometry (SIMS) can be used.

[0368] By making the deposition conditions of the insulating layer 107 different from those of the insulating layer 110a, the amount of hydrogen released can be adjusted. Specifically, one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow ratio, deposition temperature, and the distance between the substrate and the electrode during formation may be made different between the insulating layer 107 and the insulating layer 110a. For example, by making the deposition power density of the insulating layer 110a smaller than that of the insulating layer 107, the hydrogen content in the insulating layer 107 can be made higher than that in the insulating layer 110a. As a result, the amount of hydrogen released from the insulating layer 107 due to the heat applied thereto can be increased.

[0369] The hydrogen content in the deposition gas used to form the insulating layer 107 is preferably higher than that in the deposition gas used to form the insulating layer 110a. Specifically, when forming the insulating layer 110 by the PECVD method, the ratio of the flow rate of ammonia gas to the total deposition gas used to form the insulating layer 107 (hereinafter, also referred to as the ammonia flow ratio) is preferably higher than the ammonia flow ratio of the deposition gas used to form the insulating layer 110a. By forming the insulating layer 107 under conditions of a high ammonia flow ratio, the hydrogen content in the insulating layer 107 can be increased. In addition, the amount of hydrogen released from the insulating layer 107 due to the heat applied thereto can be increased.

[0370] The film density of the insulating layer 110a is preferably higher than that of the insulating layer 107. The evaluation of the film density can be performed, for example, by Rutherford Backscattering Spectrometry (RBS) or X-Ray Reflection (XRR). The difference in film density can sometimes be evaluated from a cross-sectional Transmission Electron Microscopy (TEM) image. In TEM observation, if the film density is high, the Transmission Electron (TE) image is dark, and if the film density is low, the TE image is light. Therefore, in the TE image, the insulating layer 110a sometimes appears darker than the insulating layer 107. Note that even if the insulating layer 107 and the insulating layer 110c are made of the same material, their film densities are different, so these boundaries can sometimes be observed as differences in contrast in the cross-sectional TEM image.

[0371] In the transistor 200B, the semiconductor layer 208 is provided on the insulating layer 120. As Figure 18A shown, etc., the insulating layer 120 is preferably provided in at least a region in contact with the channel formation region of the semiconductor layer 208. In addition, the insulating layer 120 may also have a region in contact with the bottom surface of the conductive layer 209a and the bottom surface of the conductive layer 209b. At this time, the semiconductor layer 208 has a region overlapping the insulating layer 120 with the conductive layer 209a or the conductive layer 209b interposed therebetween.

[0372] Here, the insulating layer 120 in contact with the semiconductor layer 208 more preferably uses a film that releases oxygen upon heating. Since the insulating layer 120 releases oxygen due to the heat applied in the manufacturing process of the transistor 200B, oxygen can be supplied to the semiconductor layer 208. By supplying oxygen from the insulating layer 120 to the semiconductor layer 208, particularly to the channel formation region of the semiconductor layer 208, oxygen vacancies in the semiconductor layer 208 can be reduced, thereby enabling a transistor with good electrical characteristics and high reliability to be realized. In addition, in the transistor 200B, when the semiconductor layer 208 has a region overlapping the insulating layer 120 with the conductive layer 209a or the conductive layer 209b interposed therebetween, the supply of oxygen from the insulating layer 120 to the semiconductor layer 208 can be restricted in this region. In other words, a decrease in conductivity in the region of the semiconductor layer 208 in contact with the source electrode or the drain electrode can be suppressed.

[0373] Note that the structure of the insulating layer 120 shown in <Structural Example 3> etc. can also be used for other structural examples.

[0374] <Structural Example 4>

[0375] Refer toFigure 21A and Figure 21B illustrate a transistor 100C having a structure different from that of the above-described transistor 100B. Figure 21A is a top view of the transistor 100C, Figure 21B and is Figure 21A a cross-sectional view of a cross-section along the dash-dotted line B1-B2 shown. For the cross-sectional view along the dash-dotted line A1-A2, reference can be made to Figure 18A the transistor 100B shown.

[0376] The main difference between the transistor 100C and Figure 18A the transistor 100B shown, etc., is that in the transistor 100C, the conductive layer 103 is electrically connected to the conductive layer 104.

[0377] As Figure 21B shown, openings 146 reaching the conductive layer 103 are provided in the insulating layer 110 and the insulating layer 106. The conductive layer 104 is provided so as to cover the openings 146 and is electrically connected to the conductive layer 103 through the openings 146. By electrically connecting the conductive layer 104 serving as a gate electrode to the conductive layer 103 serving as a back gate electrode, the back gate electrode and the gate electrode can have the same potential, and thus the on-state current of the transistor 100C can be increased.

[0378] Note that the structures of the conductive layer 103 and the conductive layer 104 shown in <Structural Example 4> can also be used for other structural examples.

[0379] <Structural Example 5>

[0380] Figure 22A and Figure 22B show a cross-sectional view of a semiconductor device 10C according to one embodiment of the present invention. For the top view of the semiconductor device 10C, reference can be made to Figure 9A . Figure 22A is a cross-sectional view of a cross-section along the dash-dotted line A1-A2 shown, Figure 9A and Figure 22B is a cross-sectional view of a cross-section along the dash-dotted lines B1-B2 and B3-B4 shown. Figure 9A

[0381] The semiconductor device 10C includes a transistor 100D and a transistor 200C. The main difference between the semiconductor device 10C and Figure 18A the semiconductor device 10B shown, etc., is that the semiconductor device 10C does not include the insulating layer 107.

[0382] The main difference between transistor 100D and the above-described transistor 100B is that transistor 100D does not include the insulating layer 107 between the conductive layer 112 and the conductive layer 103. The conductive layer 103 is arranged in contact with the conductive layer 112. In transistor 100D, the insulating layer 110 is arranged so as to cover the top surface and side surfaces of the conductive layer 103 and the top surface and side surfaces of the conductive layer 112. By electrically connecting the conductive layer 112 serving as the source electrode or the drain electrode and the conductive layer 103 serving as the back gate electrode, the source electrode or the drain electrode and the gate electrode can have the same potential.

[0383] In transistor 200C, the insulating layer 110 is arranged so as to cover the top surface and side surfaces of the conductive layer 202.

[0384] For example, a first conductive film that will become the conductive layer 112 and the conductive layer 202 can be formed. After forming the conductive layer 112 and the conductive layer 202 by processing the first conductive film, a second conductive film that will become the conductive layer 103 is formed and processed, whereby the conductive layer 103 can be formed. Or, for example, after forming the first conductive film that will become the conductive layer 112 and the conductive layer 202 and the second conductive film that will become the conductive layer 103, the conductive layer 103 is formed by processing the second conductive film, and then the first conductive film is processed, whereby the conductive layer 112 and the conductive layer 103 can be formed. The processing of the first conductive film and the second conductive film can use one or both of a wet etching method and a dry etching method. The first conductive film and the second conductive film are preferably made of different materials. Furthermore, in the processing of the second conductive film, it is preferable to use a material with a high selectivity ratio as the first conductive film. Thus, when processing the second conductive film, it is possible to suppress a decrease in the thickness of the conductive layer 112 and the conductive layer 202 or the first conductive film. Note that the processing method of the first conductive film and the processing method of the second conductive film can also be different. For example, a wet etching method can be used for the processing of the first conductive film and a dry etching method can be used for the processing of the second conductive film. In addition, the same processing method can be used for these processes, and different processing conditions can be adopted.

[0385] Note that the structure of the insulating layer 110, the conductive layer 103, and the conductive layer 112 shown in <Structural Example 5> can also be used in other structural examples.

[0386] <Structural Example 6>

[0387] Figure 23A and Figure 23B is a cross-sectional view of a semiconductor device 10D according to one embodiment of the present invention. The top view of the semiconductor device 10D can be referred to Figure 9A . Figure 23A is Figure 9A a cross-sectional view of a cross-section along the dotted line A1 - A2 shown in Figure 23B is alongFigure 9A Cross-sectional views of the cross-sections of the dash-dotted lines B1 - B2 and dash-dotted lines B3 - B4 shown.

[0388] The semiconductor device 10D includes a transistor 100B and a transistor 200D. The semiconductor device 10D is Figure 18A The main difference from the semiconductor device 10B shown, etc. is that in the semiconductor device 10D, a conductive layer 202 is provided between the insulating layer 107 and the insulating layer 110a.

[0389] Regarding the transistor 100B, reference can be made to the above description, so detailed description is omitted.

[0390] In the transistor 200D, a conductive layer 202 is provided on the insulating layer 107. The conductive layer 202 can use, for example, the same material as the conductive layer 103. Furthermore, the conductive layer 202 can be formed by the same process as the conductive layer 103. The insulating layer 110a is provided so as to cover the top surface and the side surface of the conductive layer 202.

[0391] For example, when a material with a higher conductivity than the conductive layer 112 is used as the conductive layer 103, by forming the conductive layer 202 by the same process as the conductive layer 103 and also using a material with a high conductivity for the conductive layer 202, the resistance of the conductive layer 202 can be reduced. In addition, in the transistor 200D, a part of the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, and the insulating layer 120 is used as a back gate insulating layer. By providing the conductive layer 202 between the insulating layer 107 and the insulating layer 110a, compared with the case where the conductive layer 202 is provided between the substrate 102 and the insulating layer 107, the thickness of the back gate insulating layer can be reduced. As a result, the electric field of the back gate electrode can be enhanced. In addition, the saturation of the Id - Vd characteristics of the transistor 200D can be improved. In addition, by suppressing the threshold voltage drift, a transistor 200D with a small cut-off current can be realized.

[0392] Note that the structure of the conductive layer 202 shown in <Structural Example 6> can also be used for other structural examples.

[0393] <Structural Example 7>

[0394] Figure 24A A top view of the semiconductor device 10E showing one embodiment of the present invention. Figure 24B Showing along Figure 24A A cross-sectional view of the cross-section along the dash-dotted line A1 - A2 shown, Figure 24C A cross-sectional view of the cross-section along the dash-dotted lines B1 - B2 and dash-dotted lines B3 - B4 shown.

[0395] The semiconductor device 10E includes a transistor 100E and a transistor 200E. The semiconductor device 10E is Figure 18AThe main difference of the semiconductor device 10B shown etc. is that the semiconductor device 10E includes an insulating layer 106a and an insulating layer 106b instead of the insulating layer 106.

[0396] The transistor 100E includes an insulating layer 106a between the conductive layer 104 and the semiconductor layer 108. The insulating layer 106a is used as the gate insulating layer of the transistor 100E. The insulating layer 106a is provided at least in the region where the conductive layer 104 and the semiconductor layer 108 overlap.

[0397] As Figure 24B and Figure 24C shown, the insulating layer 106a may also cover the end portion of the semiconductor layer 108. Furthermore, it may also cover the end portion of the conductive layer 109. Specifically, the insulating layer 106a contacts the top surface and the side surfaces of the semiconductor layer 108 and the top surface and the side surfaces of the conductive layer 109. The end portion of the insulating layer 106a contacts the top surface of the insulating layer 110. By covering the semiconductor layer 108 and the conductive layer 109 with the insulating layer 106a, for example, damage to the semiconductor layer 108 and the conductive layer 109 during the formation of the conductive layer 104 can be suppressed.

[0398] The transistor 200E includes an insulating layer 106b between the conductive layer 204 and the semiconductor layer 208. The insulating layer 106b is used as the gate insulating layer of the transistor 200E. The insulating layer 106b is provided at least in the region where the conductive layer 204 and the semiconductor layer 208 overlap. The end portion of the conductive layer 204 preferably contacts the top surface of the insulating layer 106b. The insulating layer 106b can be formed by the same process as the insulating layer 106a. For example, by forming an insulating film that will become the insulating layer 106a and the insulating layer 106b and processing the conductive film, the insulating layer 106a and the insulating layer 106b can be formed. The insulating layer 106a and the insulating layer 106b can use the materials that can be used for the insulating layer 106.

[0399] As Figure 24B shown, in the transistor 200E, the conductive layers 212a and 212b may also be provided so as to cover the side surface of the semiconductor layer 208. In addition, the conductive layers 212a and 212b may each have a region in contact with the conductive layers 209a and 209b.

[0400] Note that the structure of the insulating layer 106a and the insulating layer 106b shown in <Structural Example 7> etc. can also be used for other structural examples.

[0401] <Structural Example 8>

[0402] Figure 25A A top view of a semiconductor device 10F showing one aspect of the present invention. Figure 25B Showing along Figure 25ACross-sectional view of the cross-section of the dash-dotted line A1 - A2 shown Figure 25C Cross-sectional views showing cross-sections along the dash-dotted line B1 - B2 and the dash-dotted line B3 - B4.

[0403] The semiconductor device 10F includes a transistor 100F and a transistor 200F. The main difference between the semiconductor device 10F and Figure 18A the semiconductor device 10B shown, etc., lies in the different structures of the conductive layers 212a and 212b.

[0404] In the transistor 200F, the conductive layers 212a and 212b are disposed so as to cover the openings 147a and 147b provided in the insulating layer 106 and the insulating layer 195. The conductive layers 212a and 212b are formed by a process different from that of the conductive layers 104 and 204. In addition, the conductive layers 212a and 212b may use the same or different materials as the conductive layers 104 and 204.

[0405] For example, the conductive layer 204 can be formed on the insulating layer 106, the insulating layer 195 can be formed on the conductive layer 204, the openings 147a and 147b can be formed in the insulating layer 106 and the insulating layer 195, and the conductive layers 212a and 212b can be formed so as to cover the openings 147a and 147b. By disposing the conductive layers 212a and 212b on different surfaces from the conductive layer 204, the degree of freedom in layout can be improved.

[0406] A region 208D is provided in a region of the semiconductor layer 208 that does not overlap with the conductive layer 204. For example, after forming the conductive layer 204, by using the conductive layer 204 as a mask and adding impurity elements to the semiconductor layer 208, the region 208D can be formed. The impurity elements are added to the region of the semiconductor layer 208 that does not overlap with the conductive layer 204 through the insulating layer 106. The openings 147a and 147b are provided in a region overlapping with the region 208D, and in the openings 147a and 147b, the conductive layers 212a and 212b are in contact with the region 208D. Note that there is no particular limitation on the top surface shape of the openings 147a and 147b.

[0407] When adding impurity elements to the semiconductor layer 208 to form the region 208D, the conductive layer 104 can also be used as a mask to supply the impurity elements to the semiconductor layer 108 through the insulating layer 106. Thus, an impurity addition region similar to the region 208D is formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104.

[0408] Note that the structures of the conductive layers 212a and 212b shown in <Structural Example 8> can also be used for other structural examples.

[0409] <Structural Example 9>

[0410] Figure 26A and Figure 26B A cross-sectional view of the semiconductor device 10G showing one embodiment of the present invention. A top view of the semiconductor device 10G can be referred to Figure 9A . Figure 26A is a cross-sectional view of a cross-section along the dotted line A1 - A2 shown in Figure 9A , Figure 26B is a cross-sectional view of a cross-section along the dotted lines B1 - B2 and B3 - B4 shown in Figure 9A .

[0411] The semiconductor device 10G includes a transistor 100G and a transistor 200G. The main difference between the semiconductor device 10G and Figure 18A the semiconductor device 10B shown, etc., is that in the semiconductor device 10G, a conductive layer 202 is provided between the insulating layer 110 and the insulating layer 120.

[0412] In the transistor 200G, a conductive layer 202 is provided on the insulating layer 110. The conductive layer 202 can use, for example, the same material as the conductive layer 109. Furthermore, the conductive layer 202 can be formed by the same process as the conductive layer 109. The insulating layer 120 is provided so as to cover the top surface and the side surfaces of the conductive layer 202.

[0413] An insulating layer 106 is provided on the conductive layer 202. The insulating layer 106 is provided so as to cover the top surface and the side surfaces of the conductive layer 202. In the transistor 200G, a part of the insulating layer 106 is used as a gate insulating layer. By providing the conductive layer 202 between the insulating layer 110 and the insulating layer 120, the thickness of the back gate insulating layer of the transistor 200G can be reduced. Thereby, the electric field of the back gate electrode can be enhanced. In addition, the saturation of the Id - Vd characteristics of the transistor 200G can be improved. Also, by suppressing the threshold voltage drift, a transistor 200G with a small cut-off current can be realized.

[0414] The insulating layer 120 can also have a laminated structure.

[0415] In the case where the insulating layer 120 has a laminated structure including a first layer and a second layer, the first layer provided in contact with the conductive layer 202 preferably uses a material in which the metal elements contained in the conductive layer 202 do not easily diffuse. Thereby, the diffusion of the metal elements contained in the conductive layer 202 into the channel formation region and its vicinity of the semiconductor layer 108 and the semiconductor layer 208 can be suppressed. The first layer of the insulating layer 120 can appropriately use the materials that can be used for the insulating layer 110a and the insulating layer 110c. The first layer of the insulating layer 120 can appropriately use, for example, silicon nitride.

[0416] The second layer of the insulating layer 120 having a region in contact with the channel formation region of the semiconductor layer 208 preferably uses an insulating layer containing oxygen. The second layer of the insulating layer 120 can appropriately use the materials that can be used for the insulating layer 110c. For example, the second layer of the insulating layer 120 can appropriately use silicon oxide or silicon oxynitride.

[0417] Note that the insulating layer 120 can have a stacked structure of three or more layers or a single-layer structure.

[0418] Note that the structure of the conductive layer 202 shown in <Structural Example 13> etc. can also be used for other structural examples. The structure of the insulating layer 120 can also be used for other structural examples.

[0419] This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.

[0420] (Embodiment 2)

[0421] In this embodiment, a method for manufacturing a semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 27 to 30. Note that, regarding the materials and formation methods of each component, parts that are the same as those described in the above Embodiment 1 may sometimes be omitted.

[0422] The thin films (such as insulating films, semiconductor films, and conductive films) constituting the semiconductor device can be formed by sputtering, chemical vapor deposition (CVD: Chemical Vapor Deposition), vacuum evaporation, pulsed laser deposition (PLD: Pulsed Laser Deposition), ALD, etc. As the CVD method, there are PECVD and thermal CVD. In addition, as one of the thermal CVD methods, there is metal organic chemical vapor deposition (MOCVD: Metal Organic CVD).

[0423] The thin films (such as insulating films, semiconductor films, and conductive films) constituting the semiconductor device can be formed by wet deposition methods such as spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, doctor knife method, slot die coating, roll coating, curtain coating, or knife-over-edge coating.

[0424] When processing the thin films constituting the semiconductor device, photolithography or the like can be used. Alternatively, nanoimprinting, sandblasting, lift-off, etc. can be used to process the thin films. In addition, island-shaped thin films can be directly formed by a deposition method using a masking mask such as a metal mask.

[0425] Lithography typically has the following two methods. One is a method of forming a resist mask on a thin film to be processed, processing the thin film by etching or the like, and removing the resist mask. The other is a method of depositing a photosensitive thin film and then performing exposure and development to process the thin film into a desired shape.

[0426] In lithography, as the light used for exposure, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these lights can be used. In addition, ultraviolet light, KrF laser, ArF laser, etc. can also be used. Furthermore, immersion exposure technology can also be used for exposure. In addition, as the light used for exposure, extreme ultraviolet (EUV) light or X-rays can also be used. In addition, instead of the light used for exposure, an electron beam can also be used. When using extreme ultraviolet light, X-rays, or an electron beam, extremely fine processing can be performed, so it is preferred. Note that when performing exposure by scanning with a light beam such as an electron beam, a photomask is not required.

[0427] As an etching method for the thin film, a dry etching method, a wet etching method, a sandblasting method, etc. can be used.

[0428] <Example of manufacturing method 1>

[0429] Hereinafter, Figure 18A taking the semiconductor device 10B shown in

[0430] Figures 27A to 30C as an example, the manufacturing method will be described.

[0431] First, a conductive layer 112 and a conductive layer 202 are formed on a substrate 102, an insulating film 107f that will become an insulating layer 107 is formed on the conductive layer 112 and the conductive layer 202, and a conductive layer 103 ( Figure 27A ) is formed on the insulating film 107f. An opening 148 reaching the insulating film 107f is provided in the conductive layer 103.

[0432] For example, a conductive film that will become the conductive layer 112 and the conductive layer 202 and a conductive film that will become the conductive layer 103 can be appropriately formed by a sputtering method. A resist mask is formed on the conductive film by a lithography process, and then the conductive film is processed, whereby the conductive layer can be formed. The processing of the conductive film can use one or both of a wet etching method and a dry etching method.

[0433] In addition, in the formation of the conductive layer 103, either the process of processing the conductive film that will become the conductive layer 103 into a desired shape such as an island shape or the process of forming the opening 148 can be performed first, or these processes can be performed simultaneously.

[0434] Note that when processing the conductive film that will become the conductive layer 103, sometimes a part of the insulating film 107f is removed. Therefore, sometimes the thickness of the region of the insulating layer 107 that overlaps with the opening 148 is smaller than the thickness of the region that overlaps with the conductive layer 103 ( Figure 15A ). Alternatively, the insulating film 107f can also be processed when processing the conductive film that will become the conductive layer 103 to form Figure 15B the insulating layer 107 shown.

[0435] When forming the insulating film 107f, for example, the sputtering method or the PECVD method can be appropriately used.

[0436] The substrate temperature when forming the insulating film 107f is preferably 180 °C or higher and 450 °C or lower, more preferably 200 °C or higher and 450 °C or lower, more preferably 250 °C or higher and 450 °C or lower, more preferably 300 °C or higher and 450 °C or lower, more preferably 300 °C or higher and 400 °C or lower, more preferably 350 °C or higher and 400 °C or lower. By setting the substrate temperature when forming the insulating film 107f within the above range, the release of impurities (e.g., water and hydrogen) from the insulating film 107f itself can be reduced, and thus the diffusion of impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor with excellent electrical characteristics and high reliability can be achieved.

[0437] Next, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 103 and the insulating film 107f ( Figure 27B ).

[0438] When forming the insulating film 110af and the insulating film 110bf, for example, the sputtering method or the PECVD method can be appropriately used. It is preferable to continuously form the insulating film 110bf in a vacuum without exposing the surface of the insulating film 110af to the atmosphere after forming the insulating film 110af. By continuously forming the insulating film 110af and the insulating film 110bf, the attachment of impurities derived from the atmosphere to the surface of the insulating film 110af can be suppressed. Examples of such impurities include water and organic substances.

[0439] When forming the insulating films 110af and 110bf, the substrate temperature is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. By setting the substrate temperature within the above range when forming the insulating films 110af and 110bf, the release of impurities (e.g., water and hydrogen) from the insulating films 110af and 110bf themselves can be reduced, and thus the diffusion of impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor with excellent electrical characteristics and high reliability can be achieved.

[0440] After forming the insulating film 110bf, oxygen can also be supplied to the insulating film 110bf. As a method for supplying oxygen, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used. As the plasma treatment, a device for plasmaizing oxygen gas with high-frequency power can be appropriately used. As a device for plasmaizing a gas with high-frequency power, for example, a PECVD device, a plasma etching device, and a plasma ashing device can be cited. The plasma treatment is preferably performed in an oxygen-containing atmosphere. For example, it is preferably performed in an atmosphere containing one or more of oxygen, nitrous oxide (N2O), nitrogen dioxide (NO2), carbon monoxide, and carbon dioxide.

[0441] Note that the plasma treatment can also be continuously performed in a vacuum in such a manner that the surface of the insulating film 110bf is not exposed to the atmosphere. For example, when a PECVD device is used to form the insulating film 110bf, it is preferable to perform the plasma treatment using this PECVD device. Thereby, the productivity can be improved.

[0442] Next, a metal oxide layer 180 ( Figure 27C ) is preferably formed on the insulating film 110bf. By forming the metal oxide layer 180, oxygen can be supplied to the insulating film 110bf.

[0443] There is no limitation on the conductivity of the metal oxide layer 180. The metal oxide layer 180 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film. For example, the metal oxide layer 180 can be formed using alumina, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO).

[0444] As the metal oxide layer 180, an oxide material containing one or more elements the same as those in the semiconductor layer 108 and the semiconductor layer 208 is preferably used. In particular, an oxide semiconductor material applicable to the semiconductor layer 108 and the semiconductor layer 208 is preferably used.

[0445] When forming the metal oxide layer 180, the higher the ratio of the oxygen flow rate (oxygen flow ratio) in the total flow rate of the deposition gas introduced into the processing chamber of the deposition apparatus or the oxygen partial pressure in the processing chamber, the more the amount of oxygen supplied to the insulating film 110af can be increased. The oxygen flow ratio or the oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and still more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow ratio to 100% to make the oxygen partial pressure as close to 100% as possible.

[0446] Thus, by forming the metal oxide layer 180 by sputtering in an oxygen-containing atmosphere, it is possible to supply oxygen to the insulating film 110bf while preventing oxygen from escaping from the insulating film 110bf when forming the metal oxide layer 180. As a result, more oxygen can be enclosed in the insulating film 110bf. And, more oxygen can be supplied to the semiconductor layer 108 through a subsequent heat treatment. As a result, oxygen vacancies and V O H in the semiconductor layer 108 can be reduced, and a transistor having excellent electrical characteristics and high reliability can be realized.

[0447] A heat treatment can also be performed after forming the metal oxide layer 180. By performing a heat treatment after forming the metal oxide layer 180, oxygen can be effectively supplied from the metal oxide layer 180 to the insulating film 110bf.

[0448] The temperature of the heat treatment is preferably 150°C or more and lower than the strain point of the substrate, more preferably 200°C or more and 450°C or less, more preferably 250°C or more and 450°C or less, more preferably 300°C or more and 450°C or less, more preferably 300°C or more and 400°C or less, and more preferably 350°C or more and 400°C or less. The heat treatment can be performed in an atmosphere containing one or more of noble gases, nitrogen, and oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can also be used. Note that the content of hydrogen, water, etc. in this atmosphere is preferably as small as possible. As this atmosphere, a high-purity gas having a dew point of -60°C or lower, preferably -100°C or lower is preferably used. By using an atmosphere having as little content of hydrogen, water, etc. as possible, it is possible to prevent hydrogen, water, etc. from being absorbed by the insulating film 107f, the insulating film 110af, etc. as much as possible. This heat treatment can use an oven, a rapid thermal annealing (RTA) apparatus, etc. By using an RTA apparatus, the heat treatment time can be shortened.

[0449] After forming the metal oxide layer 180 or after the above heat treatment, oxygen may also be supplied to the insulating film 110bf through the metal oxide layer 180. As a method of supplying oxygen, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment may be used. Regarding the plasma treatment, reference may be made to the above description, so its detailed description is omitted.

[0450] Next, the metal oxide layer 180 is removed. Although there is no particular limitation on the method of removing the metal oxide layer 180, a wet etching method may be appropriately employed. By using the wet etching method, etching of the insulating film 110bf when removing the metal oxide layer 180 can be suppressed. Therefore, a decrease in the thickness of the insulating film 110bf can be suppressed, and the thickness of the insulating layer 110a can be made uniform.

[0451] The oxygen supply treatment for the insulating film 110bf is not limited to the above method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. are supplied to the insulating film 110bf by an ion doping method, an ion implantation method, a plasma treatment, etc. In addition, after forming a film that suppresses oxygen desorption on the insulating film 110bf, oxygen may be supplied to the insulating film 110bf through this film. It is preferable to remove this film after supplying oxygen. As the above film that suppresses oxygen desorption, a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten may be used.

[0452] Next, an insulating film 110cf that will become the insulating layer 110c and an insulating film 120f that will become the insulating layer 120 are formed on the insulating film 110bf( Figure 27D ). Thus, a stacked structure of the insulating film 107f, the insulating film 110af, the insulating film 110bf, and the insulating film 110cf is formed on the conductive layer 112 and the conductive layer 202.

[0453] When forming the insulating film 110cf and the insulating film 120f, for example, a sputtering method or a PECVD method may be appropriately used. It is preferable to continuously form the insulating film 120f in a vacuum in such a manner that the surface of the insulating film 110cf is not exposed to the atmosphere after forming the insulating film 110cf. By continuously forming the insulating film 110cf and the insulating film 120f, attachment of impurities derived from the atmosphere to the surface of the insulating film 110af can be suppressed. Examples of such impurities include water and organic substances.

[0454] Next, the insulating film 120f is processed to form the insulating layer 120( Figure 27E ). The insulating layer 120 is provided in the region where the semiconductor layer 208 is provided. When forming the insulating layer 120, one or both of a wet etching method and a dry etching method may be used. In particular, a dry etching method may be appropriately used.

[0455] Without processing the insulating film 120f in the portion overlapping with the region of the transistor 100B, the transistors 100A and 200A as shown in Figure 9B etc. can be formed.

[0456] Next, a conductive film 109f that will become the conductive layer 109 is formed on the insulating film 110cf and the insulating layer 120 ( Figure 28A ). The formation of the conductive film 109f can be appropriately carried out by, for example, sputtering.

[0457] Next, the conductive film 109f is processed to form the conductive layer 109p, the conductive layer 209a, and the conductive layer 209b ( Figure 28B ). The conductive layer 109p will become the conductive layer 109 later. The formation of the conductive layer 109p, the conductive layer 209a, and the conductive layer 209b can be appropriately carried out by, for example, wet etching.

[0458] Next, a part of the conductive layer 109p is removed to form the conductive layer 109 having an opening 143. The opening 143 is provided in the region overlapping with the opening 148. When forming the conductive layer 109, one or both of wet etching and dry etching can be used. In particular, wet etching can be appropriately used.

[0459] Next, a part of the insulating film 107f, the insulating film 110af, the insulating film 110bf, and the insulating film 110cf is removed to form the insulating layer 107 and the insulating layer 110 having an opening 141 ( Figure 28C ). The opening 141 is provided in the region overlapping with the opening 143. In addition, the opening 141 is provided in the region overlapping with the opening 148, and by forming the opening 141, the conductive layer 112 is exposed. When forming the insulating layer 110, one or both of wet etching and dry etching can be used. In particular, dry etching can be appropriately used.

[0460] The opening 143 can be formed, for example, using the resist mask used for the formation of the opening 141. Specifically, a resist mask can be formed on the conductive layer 109p, and a part of the conductive layer 109p can be removed using this resist mask to form the opening 143, and a part of the insulating film 107f, the insulating film 110af, the insulating film 110bf, and the insulating film 110cf can be removed using this resist mask to form the opening 141. The opening 143 can also be formed using a resist mask different from the resist mask used for the formation of the opening 141.

[0461] In addition, a part of the conductive layer 112 in the region overlapping the opening 141 may be removed when the opening 141 is formed or after the opening 141 is formed. By making the thickness of the region of the conductive layer 112 in contact with the bottom surface of the semiconductor layer 108 smaller than the thickness of the region not in contact with the semiconductor layer 108, the electric field of the gate electrode in the channel formation region near the conductive layer 112 can be enhanced, thereby increasing the on-state current of the transistor.

[0462] Next, a metal oxide film 108f that will become the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the opening 141 and the opening 143 ( Figure 28D ). The metal oxide film 108f is provided in contact with the top surfaces and side surfaces of the conductive layer 109, the conductive layer 209a, and the conductive layer 209b, the top surface and side surfaces of the insulating layer 120, the top surface and side surfaces of the insulating layer 110, and the top surface of the conductive layer 112.

[0463] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by an ALD method.

[0464] The metal oxide film 108f is preferably a dense film with as few defects as possible. In addition, the metal oxide film 108f is preferably a high-purity film in which impurities containing hydrogen elements are reduced as much as possible. In particular, a crystalline metal oxide film is preferably used as the metal oxide film 108f.

[0465] When forming the metal oxide film 108f, oxygen gas is preferably used. By using oxygen gas when forming the metal oxide film 108f, oxygen can be appropriately supplied to the insulating layer 110 and the insulating layer 120. For example, when the insulating layer 110b uses an oxide, oxygen can be appropriately supplied to the insulating layer 110b.

[0466] By supplying oxygen to the insulating layer 110b and supplying oxygen to the semiconductor layer 108 in a subsequent process, oxygen vacancies and V in the semiconductor layer 108 can be reduced. O H. Similarly, by supplying oxygen to the insulating layer 120 and supplying oxygen to the semiconductor layer 208 in a subsequent process, oxygen vacancies and V in the semiconductor layer 208 can be reduced. O H.

[0467] When forming the metal oxide film 108f, an oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) may be mixed. Note that the higher the ratio of the oxygen gas in the entire deposition gas when forming the metal oxide film (oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a transistor with high reliability can be achieved. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, and a transistor with a large on-state current can be achieved. For example, by varying the oxygen flow ratio, a stacked structure of two or more metal oxide layers with different crystallinities can be formed.

[0468] When the substrate temperature is relatively high when forming the metal oxide film, a metal oxide film with higher crystallinity and higher density can be formed. On the other hand, as the substrate temperature becomes lower, a metal oxide film with lower crystallinity and higher conductivity can be formed.

[0469] The substrate temperature when forming the metal oxide film 108f is preferably above room temperature and below 250 °C, more preferably above room temperature and below 200 °C, and further preferably above room temperature and below 140 °C. For example, the substrate temperature is preferably above room temperature and below 140 °C, whereby the productivity can be improved. In addition, by setting the substrate temperature to room temperature or forming the metal oxide film in a state where the substrate is not heated, the crystallinity can be reduced.

[0470] When using the ALD method when forming the metal oxide film 108f, deposition methods such as thermal ALD method or PEALD (Plasma Enhanced ALD) are preferably used. The thermal ALD method has extremely high step coverage, so it is preferred. In addition, the PEALD method not only has high step coverage but also can perform low-temperature deposition, so it is preferred.

[0471] The metal oxide film can be formed, for example, by using a precursor containing a constituent metal element and an oxidizing agent and using the ALD method.

[0472] For example, when forming In-Ga-Zn oxide, three precursors including a precursor containing indium, a precursor containing gallium, and a precursor containing zinc can be used. Alternatively, two precursors including a precursor containing indium and a precursor containing gallium and zinc can also be used.

[0473] Examples of the precursor containing indium include triethylindium, indium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0474] As a gallium-containing precursor, for example, trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionato)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride can be cited.

[0475] As a zinc-containing precursor, for example, dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionato)zinc, and zinc chloride can be cited.

[0476] As an oxidizing agent, for example, ozone, oxygen, and water can be cited.

[0477] As a method for controlling the composition of the obtained film, adjustment of one or more of the type of source gas, the flow rate ratio of the source gas, the time for flowing the source gas, and the order of flowing the source gas can be cited. By adjusting them, a film with a continuously changing composition can also be formed. In addition, two or more films with different compositions can be continuously deposited.

[0478] Note that in the case where the semiconductor layer 108 has a stacked structure, it is preferable that after depositing the lower metal oxide film, the upper metal oxide film is continuously deposited in such a manner that its surface is not exposed to the atmosphere.

[0479] Before depositing the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, etc. adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen to the insulating layer 110. For example, a heat treatment can be performed at a temperature of 70°C or higher and 200°C or lower in a reduced-pressure atmosphere. Or, a plasma treatment in an oxygen-containing atmosphere can be performed. Or, by performing a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O), oxygen can also be supplied to the insulating layer 110. When performing a plasma treatment containing nitrous oxide gas, the organic substances on the surface of the insulating layer 110 can be appropriately removed and oxygen can be supplied to the insulating layer 110. It is preferable that after such a treatment, the metal oxide film 108f is continuously deposited in such a manner that the surface of the insulating layer 110 is not exposed to the atmosphere.

[0480] Next, the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208( Figure 29A ).

[0481] When forming the semiconductor layer 108 and the semiconductor layer 208, one or both of a wet etching method and a dry etching method can be used. For example, it is preferable to use the wet etching method. At this time, sometimes a part of the conductive layer 109 in the area not overlapping with the semiconductor layer 108 is etched and its thickness becomes smaller. Similarly, sometimes a part of the conductive layer 209a and the conductive layer 209b in the area not overlapping with the semiconductor layer 208 is etched and its thickness becomes smaller. Similarly, sometimes a part of the insulating layer 110 in the area not overlapping with both the semiconductor layer 108 and the conductive layer 109 is etched and its thickness becomes smaller. Similarly, sometimes a part of the insulating layer 110 in the area not overlapping with the semiconductor layer 208, the conductive layer 209a, and the conductive layer 209b is etched and its thickness becomes smaller. For example, sometimes due to etching, the insulating layer 110c in the insulating layer 110 disappears and the surface of the insulating layer 110b is exposed. Note that in the etching of the metal oxide film 108f, by using a material with a high selectivity as the insulating layer 110c, the reduction in the thickness of the insulating layer 110c can be suppressed.

[0482] It is preferable to perform a heat treatment after depositing the metal oxide film 108f or after processing the metal oxide film 108f into the semiconductor layer 108 and the semiconductor layer 208. By the heat treatment, hydrogen or water contained in the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 or adsorbed on the surface of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 can be removed. In addition, by the heat treatment, sometimes the film quality of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 is improved (for example, reduction of defects or improvement of crystallinity).

[0483] By the heat treatment, oxygen can be supplied from the insulating layer 110b and the insulating layer 120 to the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208. At this time, it is more preferable to perform the heat treatment after forming the metal oxide film 108f and before processing it into the semiconductor layer 108. Thereby, the area of the region where the insulating layer 120 contacts the metal oxide film 108f can be increased, and oxygen can be effectively supplied from the insulating layer 120 to the metal oxide film 108f. Since the heat treatment can be referred to the above description, the detailed description is omitted.

[0484] Note that this heat treatment may not be performed. In addition, the heat treatment performed in a later process can be used as the heat treatment in this process without performing the heat treatment in this process. Sometimes, a treatment at a high temperature in a later process (for example, a deposition process) can be used as the heat treatment in this process.

[0485] Next, an insulating film 106f that will become the insulating layer 106 is formed so as to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 109, the conductive layer 209a, the conductive layer 209b, the insulating layer 120, and the insulating layer 110( Figure 29B ). When forming the insulating film 106f, for example, the PECVD method or the ALD method can be appropriately used.

[0486] When an oxide semiconductor is used for the semiconductor layer 108, it is preferable to use the insulating layer 106 as a barrier film for suppressing oxygen diffusion. By making the insulating layer 106 have a function of suppressing oxygen diffusion, oxygen can be prevented from diffusing from the upper side of the insulating layer 106 to the conductive layer 104 and oxidizing the conductive layer 104. As a result, a transistor with excellent electrical characteristics and high reliability can be achieved.

[0487] Note that in this specification and the like, a barrier film refers to a film having barrier properties. For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer. In this specification and the like, barrier properties refer to one or both of the function of suppressing the diffusion of the corresponding substance (it can also be said to have low permeability) and the function of capturing or fixing (also referred to as gettering) the corresponding substance.

[0488] By increasing the temperature when forming the insulating film 106f that will become the insulating layer 106 used as the gate insulating layer, an insulating layer with fewer defects can be formed. However, when the temperature during the formation of the insulating film 106f is high, oxygen dissociates from the semiconductor layer 108 and the semiconductor layer 208, and sometimes the oxygen vacancies and V O H in the semiconductor layer 108 and the semiconductor layer 208 increase. The substrate temperature during the formation of the insulating film 106f is preferably 180 °C or higher and 450 °C or lower, more preferably 200 °C or higher and 450 °C or lower, more preferably 250 °C or higher and 450 °C or lower, more preferably 300 °C or higher and 450 °C or lower, and more preferably 300 °C or higher and 400 °C or lower. By making the substrate temperature during the formation of the insulating film 106f within the above range, it is possible to suppress the dissociation of oxygen from the semiconductor layer 108 and the semiconductor layer 208 while reducing the defects of the insulating layer 106. Therefore, a transistor with excellent electrical characteristics and high reliability can be achieved.

[0489] Before forming the insulating film 106f, the surfaces of the semiconductor layer 108 and the semiconductor layer 208 may also be subjected to plasma treatment. By this plasma treatment, impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208 can be reduced. Therefore, impurities in the interfaces between the semiconductor layer 108 and the insulating layer 106 and between the semiconductor layer 208 and the insulating layer 106 can be reduced, so that a highly reliable transistor can be realized. In particular, when the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the atmosphere between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating layer 106, plasma treatment is preferably performed. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, etc. The plasma treatment and the deposition of the insulating film 106f are preferably continuously performed without exposure to the atmosphere.

[0490] Next, the insulating film 106f is processed to form the insulating layer 106( Figure 29C ). Openings 147a and 147b reaching the semiconductor layer 208 are provided in the insulating layer 106. When forming the insulating layer 106, one or both of a wet etching method and a dry etching method can be used. In particular, the dry etching method can be appropriately used.

[0491] Next, a conductive film 104f that will become the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b is formed on the insulating layer 106( Figure 30A ). The conductive film 104f is provided so as to cover the openings 147a and 147b. When forming the conductive film 104f, for example, a sputtering method or an ALD method can be appropriately used.

[0492] Next, the conductive film 104f is processed to form the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b( Figure 30B ). When forming the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, one or both of a wet etching method and a dry etching method can be used.

[0493] Next, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be used as a mask to supply (also referred to as add or implant) impurities to the semiconductor layer 208. Thereby, in the semiconductor layer 208, a region 208D is formed in a region that does not overlap with any of the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the insulating layer 106, and a region 208L is formed in a region that does not overlap with any of the conductive layer 204, the conductive layer 212a, and the conductive layer 212b and overlaps with the insulating layer 106( Figure 30C)。At this time, it is preferable to determine the impurity supply conditions according to the material and thickness of the conductive layer 204 serving as a mask in such a manner that impurities are not supplied as much as possible in the region of the semiconductor layer 208 overlapping with the conductive layer 204. Thereby, a channel formation region with a sufficiently reduced impurity concentration can be formed in the region of the semiconductor layer 208 overlapping with the conductive layer 204. Similarly, the semiconductor layer 108 can also be supplied with impurities using the conductive layer 104 as a mask. A region 108L is formed in the region of the semiconductor layer 108 that does not overlap with the conductive layer 104 and overlaps with the insulating layer 106.

[0494] For the supply of impurities, the plasma ion doping method or the ion implantation method can be appropriately used. In these methods, the concentration distribution in the depth direction can be controlled with high precision according to the ion acceleration voltage, dose, etc. By using the plasma ion doping method, the productivity can be improved. In addition, by using the ion implantation method utilizing mass separation, the purity of the supplied impurities can be improved.

[0495] In the supply of impurities, it is preferable to adjust the supply conditions such that the impurity concentration at the surface of the semiconductor layer 208 or a portion closer to the surface is the highest.

[0496] As a raw material for the supply of impurities, for example, a gas containing the above-mentioned impurity elements can be used. When supplying boron, typically one or more of B2H6 gas and BF3 gas can be used. In addition, when supplying phosphorus, typically PH3 gas can be used. In addition, a mixed gas obtained by diluting these source gases with noble gases can also be used.

[0497] As a raw material for the supply of impurities, for example, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and noble gases can be used. Note that the raw material is not limited to gases, and solids or liquids can also be heated to vaporize them.

[0498] By setting conditions such as the acceleration voltage and dose according to the composition, density, and thickness of the insulating layer 106 and the semiconductor layer 208, the addition of impurities can be controlled.

[0499] When adding boron using the ion implantation method or the plasma ion doping method, the acceleration voltage can be, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 70 kV or less, more preferably 10 kV or more and 50 kV or less. In addition, the dose can be, for example, 1×10 13 ions / cm 2 or more and 1×10 17 ions / cm 2 or less, preferably 1×10 14 ions / cm 2 or more and 5×1016 ions / cm 2 Hereinafter, it is more preferably 1×10 15 ions / cm 2 or more and 3×10 16 ions / cm 2 or less.

[0500] When adding phosphorus ions by ion implantation or plasma ion doping, the acceleration voltage can be, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, more preferably 40 kV or more and 80 kV or less. In addition, the dose can be, for example, 1×10 13 ions / cm 2 or more and 1×10 17 ions / cm 2 or less, preferably 1×10 14 ions / cm 2 or more and 5×10 16 ions / cm 2 or less, more preferably 1×10 15 ions / cm 2 or more and 3×10 16 ions / cm 2 or less.

[0501] Note that the method of supplying impurities is not limited to this. For example, plasma treatment or treatment using thermal diffusion caused by heating can also be performed. In the case of using the plasma treatment method, impurities can be added by first generating plasma in a gas atmosphere containing the added impurities and then performing plasma treatment. As the device for generating the above plasma, a dry etching device, an ashing device, a plasma CVD device, a high-density plasma CVD device, etc. can be used.

[0502] For example, by performing plasma treatment using a plasma CVD device in an atmosphere containing hydrogen gas, hydrogen can be supplied as an impurity to the semiconductor layer 208 in a region that does not overlap with the conductive layer 204. In addition, by using a plasma CVD device during the supply of impurities and the formation of the insulating layer 106, the supply of impurities and the formation of the insulating layer 106 can be continuously performed in the device, so the productivity can be improved.

[0503] In a semiconductor device according to one embodiment of the present invention, when the structure of a transistor including a conductive layer 209a and a conductive layer 209b as illustrated in FIG. 1 or the like is employed, a transistor with good electrical characteristics can be obtained even without the impurity supply to the semiconductor layer 208 described above. In other words, when the structure of a transistor including a conductive layer 209a and a conductive layer 209b as illustrated in FIG. 1 or the like is employed, a transistor with good electrical characteristics can be manufactured without using the process and the processing apparatus for supplying impurities to the semiconductor layer 208, so that the productivity can be improved. In addition, when the structure of a transistor including a conductive layer 209a and a conductive layer 209b as illustrated in FIG. 1 or the like is employed, a transistor with even better characteristics can be obtained by supplying impurities to the semiconductor layer 208 as described above.

[0504] Next, an insulating layer 195 is formed so as to cover the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, the insulating layer 106, and the semiconductor layer 208( Figure 18A ). The insulating layer 195 can be formed by appropriately using the PECVD method.

[0505] When the deposition temperature of the insulating layer 195 is too high, the impurities contained in the impurity addition regions such as the region 208D may diffuse into the semiconductor layer 108 and the peripheral portion of the semiconductor layer 208 including the channel formation region. In addition, the resistance of the impurity addition regions such as the region 208D may increase. Therefore, the deposition temperature of the insulating layer 195 can be determined in consideration of the diffusion of impurities.

[0506] The deposition temperature of the insulating layer 195 is preferably, for example, 150°C or higher and 400°C or lower, more preferably 180°C or higher and 360°C or lower, and still more preferably 200°C or higher and 250°C or lower. By depositing the insulating layer 195 at a low temperature, even a transistor with a short channel length can have excellent electrical characteristics.

[0507] In addition, a heat treatment may be performed after the formation of the insulating layer 195. By this heat treatment, the resistance of the impurity addition regions such as the region 208D can sometimes be further reduced. For example, by performing a heat treatment, it is possible to appropriately diffuse the impurities to form the impurity addition regions such as the region 208D having an ideal impurity concentration gradient. Since the heat treatment can be referred to the above description, the detailed description is omitted. Note that when the temperature of the heat treatment is too high (for example, 500°C or higher), the impurities diffuse into the channel formation region, which may cause deterioration of the electrical characteristics and reliability of the transistor.

[0508] Note that it is not necessarily required to perform this heat treatment. In addition, the heat treatment to be performed in a later process may be used as the heat treatment in this process without performing the heat treatment in this process. Sometimes, the heat treatment at a high temperature in a later process (for example, a deposition process, etc.) may be used as the heat treatment in this process.

[0509] Through the above process, the semiconductor device 10B can be manufactured.

[0510] This embodiment can be appropriately combined with other embodiments.

[0511] (Embodiment 3)

[0512] In this embodiment, a display device of a semiconductor device using one mode of the present invention will be described with reference to FIGS. 31 to 41.

[0513] The display device of this embodiment can be a high-resolution display device or a large display device. Therefore, for example, the display device of this embodiment can be used as a display unit of a device such as an electronic device having a large screen such as a television device, a desktop or notebook personal computer, a display for a computer, etc., a digital signage, and a large game machine such as a pachinko machine; a digital camera; a digital video camera; a digital photo frame; a mobile phone; a portable game machine; a portable information terminal; a sound reproduction device.

[0514] The display device of this embodiment can be a high-definition display device. Therefore, for example, the display device of this embodiment can be used as a display unit of information terminal devices (wearable devices) such as watch type and bracelet type, and a display unit of wearable devices that can be worn on the head such as VR devices such as head-mounted displays (HMD) and glasses type AR devices.

[0515] One mode of the semiconductor device of the present invention can be used for a display device or a module including the display device. As a module including the display device, there can be mentioned a module in which the display device is equipped with a connector such as a flexible printed circuit board (hereinafter referred to as FPC) or a TCP (Tape Carrier Package), a module in which an integrated circuit (IC) is mounted by a COG (Chip On Glass) method or a COF (Chip On Film) method, etc.

[0516] Figure 31A is a perspective view of the display device 50A.

[0517] The display device 50A has a structure in which the substrate 152 is bonded to the substrate 151. In Figure 31A the substrate 152 is shown by a dotted line.

[0518] The display device 50A includes a display unit 162, a connection unit 140, a peripheral circuit unit 164, a wiring 165, etc. Figure 31A An example in which the display device 50A is mounted with an IC 173 and an FPC 172 is shown. Therefore, it is also possible to Figure 31A call the structure shown a display module including the display device 50A, the IC, and the FPC.

[0519] The connection unit 140 is provided outside the display unit 162. The connection unit 140 may be provided along one or more sides of the display unit 162. The connection unit 140 may also be one or more. Figure 31A An example in which the connection unit 140 is provided so as to surround the four sides of the display unit is shown. In the connection unit 140, the common electrode of the display element is electrically connected to the conductive layer, and a potential can be supplied to the common electrode.

[0520] The peripheral circuit unit 164 includes, for example, a scan line driving circuit (also referred to as a gate driver). In addition, the peripheral circuit unit 164 may also include both a scan line driving circuit and a signal line driving circuit (also referred to as a source driver).

[0521] The wiring 165 has a function of supplying signals and power to the display unit 162 and the peripheral circuit unit 164. The signals and power are input to the wiring 165 from the outside via the FPC 172 or input to the wiring 165 from the IC 173.

[0522] Figure 31A An example in which the IC 173 is provided on the substrate 151 by a COG method, a COF method, etc. is shown. As the IC 173, for example, an IC including one or both of a scan line driving circuit and a signal line driving circuit can be used. Note that the display device 50A and the display module do not necessarily have to be provided with an IC. In addition, the IC can also be mounted on the FPC by a COF method or the like.

[0523] The transistor according to one aspect of the present invention can be used, for example, in one or both of the display unit 162 and the peripheral circuit unit 164 of the display device 50A.

[0524] The display unit 162 is an image display area in the display device 50A and includes a plurality of pixels 210 arranged periodically. Figure 31A An enlarged view of one pixel 210 is shown.

[0525] There is no particular limitation on the arrangement of the pixels in the display device of the present embodiment, and various methods can be adopted. As the arrangement of the pixels, for example, stripe arrangement, S stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement can be cited.

[0526] Figure 31A The pixel 210 shown includes a pixel 230R that presents red light, a pixel 230G that presents green light, and a pixel 230B that presents blue light. The pixels 230R, 230G, and 230B are all used as sub-pixels.

[0527] The pixels 230R, 230G, and 230B all include a display element and a circuit that controls the driving of the display element.

[0528] As the display element, various elements can be used. For example, a liquid crystal element and a light-emitting element can be cited. In addition, a MEMS (Micro Electro Mechanical Systems) element of a shutter method or a light interference method, a display element using a microcapsule method, an electrophoresis method, an electro-wetting method, or an electrophoretic ink (registered trademark) method, etc. can also be used. In addition, a QLED (Quantum-dot LED) using a light source and a color conversion technology using a quantum dot material can also be used.

[0529] As the liquid crystal element, for example, a transmissive liquid crystal element, a reflective liquid crystal element, and a transflective liquid crystal element can be cited.

[0530] As the light-emitting element, for example, a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), and a semiconductor laser can be cited. As the LED, for example, a small LED, a micro LED, etc. can be used.

[0531] As the light-emitting substance contained in the light-emitting element, for example, a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), a substance that presents thermally activated delayed fluorescence (Thermally activated delayed fluorescence: TADF material), and an inorganic compound (quantum dot material, etc.) can be cited.

[0532] The light-emitting color of the light-emitting element can be infrared, red, green, blue, cyan, magenta, yellow, white, etc. In addition, when the light-emitting element has a microcavity structure, the color purity can be further improved.

[0533] In a pair of electrodes included in the light-emitting element, one electrode is used as the anode and the other electrode is used as the cathode.

[0534] In the present embodiment, the case where a light-emitting element is used as the display element is mainly taken as an example for description.

[0535] Figure 31BIt is a block diagram showing the display device 50A. The display device 50A includes a display unit 162 and a peripheral circuit unit 164. The display unit 162 includes a plurality of pixels 230 arranged periodically. The peripheral circuit unit includes a first drive circuit unit 231 and a second drive circuit unit 232.

[0536] The circuits included in the first drive circuit unit 231 are used as, for example, a scan line drive circuit. The circuits included in the second drive circuit unit 232 are used as, for example, a signal line drive circuit. Note that a certain circuit may be provided at a position facing the first drive circuit unit 231 with the display unit 162 interposed therebetween. A certain circuit may be provided at a position facing the second drive circuit unit 232 with the display unit 162 interposed therebetween.

[0537] As the peripheral circuit unit 164, various circuits such as a shift register circuit, a level converter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit can be used. Transistors and capacitor elements can be used in the peripheral circuit unit 164. In addition, the transistors included in the peripheral circuit unit 164 can be formed by the same process as the transistors included in the pixels 230.

[0538] The display device 50A includes wirings 236 and 238 arranged substantially in parallel. The potential of the wiring 236 is controlled by the circuits included in the first drive circuit unit 231, and the potential of the wiring 238 is controlled by the circuits included in the second drive circuit unit 232. In Figure 31B an example is shown in which the wirings 236 and 238 are connected to the pixel 230. However, the wirings 236 and 238 are merely an example, and the wirings connected to the pixel 230 are not limited to the wirings 236 and 238.

[0539] <Structural Example of Peripheral Drive Circuit>

[0540] As a circuit that can be used for the peripheral drive circuit, a structural example is described taking a latch circuit as an example.

[0541] Figure 32A It is a circuit diagram showing a structural example of the latch circuit LAT. Figure 32A The shown latch circuit LAT includes a transistor Tr31, a transistor Tr33, a transistor Tr35, a transistor Tr36, a capacitor C31, and an inverter circuit INV. In Figure 32A a node that electrically connects one of the source and drain of the transistor Tr33, the gate of the transistor Tr35, and one electrode of the capacitor C31 is referred to as a node N.

[0542] In Figure 32AIn the latch circuit LAT shown, when a high-potential signal is input to the terminal SMP, the transistor Tr33 becomes in an on state. Therefore, the potential of the node N becomes a potential corresponding to the potential of the terminal ROUT, and data corresponding to the signal input from the terminal ROUT to the latch circuit LAT is written into the latch circuit LAT. After writing data into the latch circuit LAT, by making the potential of the terminal SMP become low potential, the transistor Tr33 becomes in an off state. Therefore, the potential of the node N is held, and the data written into the latch circuit LAT is held. Specifically, for example, when the potential of the node N is low potential, the latch circuit LAT can hold data of "0", and when the potential of the node N is high potential, the latch circuit LAT can hold data of "1".

[0543] The transistor Tr33 preferably uses a transistor with a low off-state current. The transistor Tr33 can appropriately use an OS transistor. Therefore, the latch circuit LAT can hold data for a long time. Therefore, the frequency of writing data into the latch circuit LAT again can be reduced.

[0544] In this specification and the like, sometimes "writing data that makes the signal input from the terminal SP2 output to the terminal LIN into the latch circuit LAT" is simply referred to as "writing data into the latch circuit LAT". That is to say, for example, sometimes "writing data of '1' into the latch circuit LAT" is simply referred to as "writing data into the latch circuit LAT".

[0545] In the latch circuit LAT, a semiconductor device according to one aspect of the present invention can be appropriately used. For example, as one or more of the transistors Tr31, Tr33, Tr35, and Tr36, Figure 1B , Figure 9B transistors 100 and the like or transistors 200 and the like shown, etc. can be used.

[0546] Figure 32B The structural example of the inverter circuit INV is shown. The inverter circuit INV includes transistors Tr41, Tr43, Tr45, Tr47, and a capacitor C41.

[0547] When the latch circuit LAT has Figure 32A the structure shown and the inverter circuit INV has Figure 32B the structure shown, all the transistors in the latch circuit LAT adopt transistors with the same polarity, for example, n-channel transistors. Thus, for example, in addition to the transistor Tr33, the transistors Tr31, Tr35, Tr36, Tr41, Tr43, Tr45, and Tr47 can also be OS transistors. Therefore, all the transistors in the latch circuit LAT can be manufactured by the same process.

[0548] In the inverter circuit INV, a semiconductor device according to one aspect of the present invention can be appropriately used. For example, one or more of the transistors Tr41, Tr43, Tr45, and Tr47 can use Figure 1B , Figure 9B transistors 100 as shown, etc. or transistors 200 as shown, etc.

[0549] By using one or more of the transistors 100 to 100G, the occupied area can be reduced, and thus a display device with a narrow border can be realized. In addition, as a transistor required to have a large on-state current, one or more of the transistors 100 to 100G can be appropriately used. Furthermore, as a transistor required to have high saturation characteristics, one or more of the transistors 200 to 200G can be appropriately used. Thereby, a high-performance display device can be realized.

[0550] <Structural example of pixel circuit>

[0551] Figure 33A Shows a structural example of the pixel 230. The pixel 230 includes a pixel circuit 51 and a light-emitting device 61.

[0552] Figure 33A The pixel circuit 51 shown is a 2Tr1C type pixel circuit including a transistor 52A, a transistor 52B, and a capacitor 53.

[0553] In the transistor 52A, one of the source and the drain is electrically connected to the gate of the transistor 52B and one terminal of the capacitor 53, and the other of the source electrode and the drain electrode is electrically connected to the wiring SL. The gate of the transistor 52A is electrically connected to the wiring GL. One of the source electrode and the drain electrode of the transistor 52B and the other terminal of the capacitor 53 are electrically connected to the anode of the light-emitting device 61. The other of the source electrode and the drain electrode of the transistor 52B is electrically connected to the wiring ANO. The cathode of the light-emitting device 61 is electrically connected to the wiring VCOM.

[0554] The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238. The wiring VCOM is a wiring for supplying a potential for supplying current to the light-emitting device 61. The transistor 52A has a function of controlling the conduction state or non-conduction state between the wiring SL and the gate of the transistor 52B according to the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0555] The transistor 52B has a function of controlling the amount of electric current flowing through the light-emitting device 61. The capacitor 53 has a function of holding the gate potential of the transistor 52B. The intensity of the light emitted by the light-emitting device 61 is controlled according to the image signal supplied to the gate of the transistor 52B.

[0556] A part or all of the transistors included in the pixel circuit 51 may also be provided with a back gate electrode. Figure 33A The illustrated pixel circuit 51 shows a structure in which the transistor 52B includes a back gate electrode and the back gate electrode is electrically connected to one of the source electrode and the drain electrode of the transistor 52B. In addition, the back gate electrode of the transistor 52B may also be electrically connected to the gate electrode transistor 52 of the transistor 52B.

[0557] The above semiconductor device can be applied to the pixel circuit 51. For example, as the transistor 52A, Figure 1B 、 Figure 9B the transistor 100 shown etc. can be used, and as the transistor 52B, the transistor 200 etc. can be used.

[0558] Figure 33B Shows a structure example different from Figure 33A the pixel 230 shown. The pixel 230 includes the pixel circuit 51A and the light-emitting device 61.

[0559] Figure 33B The pixel circuit 51A shown is Figure 33A mainly different from the pixel circuit 51 shown in that the pixel circuit 51A includes the transistor 52C. The pixel circuit 51A is a 3Tr1C type pixel circuit including the transistor 52A, the transistor 52B, the transistor 52C, and the capacitor 53.

[0560] One of the source electrode and the drain electrode of the transistor 52C is electrically connected to one of the source electrode and the drain electrode of the transistor 52B. The other of the source electrode and the drain electrode of the transistor 52C is electrically connected to the wiring V0. For example, the wiring V0 is supplied with a reference potential.

[0561] The transistor 52C has a function of controlling the conduction state or non-conduction state between one of the source electrode and the drain electrode of the transistor 52B and the wiring V0 according to the potential of the wiring GL. The unevenness of the gate-source potential of the transistor 52B can be suppressed according to the reference potential of the wiring V0 supplied through the transistor 52C.

[0562] In addition, the wiring V0 can be used to obtain a current value that can be used for setting pixel parameters. Specifically, the wiring V0 can be used as a monitoring line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the outside.

[0563] The above semiconductor device can be applied to the pixel circuit 51A. For example, transistors 100 etc. shown as the transistor 52A and the transistor 52C can be used Figure 1B , Figure 9B etc., and transistors 200 etc. can be used as the transistor 52B.

[0564] Note that there is no particular limitation on the pixel circuit of the display device applicable to one embodiment of the present invention.

[0565] Figure 33C An example of the structure of the pixel circuit 51A is shown. Figure 33C It is a cross-sectional view of the pixel circuit 51A.

[0566] Figure 33C Shows the structure in which Figure 18A etc. the semiconductor device 10B is used for the pixel circuit 51A. Specifically, it shows the structure in which the transistor 100B is used for the transistor 52A and the transistor 52C and the transistor 200B is used for the transistor 52B.

[0567] Preferably, the saturation characteristics of the transistor 52B, which is used as a driving transistor for controlling the current flowing through the light-emitting device 61, are higher than those of the transistor 52A, which is used as a selection transistor for controlling the selection state of the pixel 230. By using the transistor 200B with a long channel length as the transistor 52B, a display device with high reliability can be realized. In addition, by using the transistor 100B as the transistor 52A and the transistor 52C, the occupied area of the pixel circuit 51A can be reduced, and thus a high-definition display device can be realized.

[0568] In addition, the transistor 100B can also be used as the transistor 52B. By using the transistor 100B with a short channel length as the transistor 52B, a display device with high brightness can be realized. In addition, the occupied area of the pixel circuit 51A can be reduced, and thus a high-definition display device can be realized.

[0569] The conductive layer 212a included in the transistor 52B is electrically connected to the conductive layer 202 through the opening 139 provided in the insulating layer 120 and the insulating layer 110. In addition, the conductive layer 212a is electrically connected to the conductive layer 109 included in the transistor 52C. Note that in Figure 33CIn [the structure], the transistor 52A and the transistor 52B are not electrically connected. For example, in the insulating layer 195, a first opening reaching the conductive layer 109 included in the transistor 52A and a second opening reaching the conductive layer 204 included in the transistor 52B are provided. By providing a first wiring on the insulating layer 195 so as to cover the first opening and the second opening, the conductive layer 109 included in the transistor 52A and the conductive layer 204 included in the transistor 52B can be electrically connected through the first wiring.

[0570] In Figure 33C [the structure], the capacitor 53 is omitted. The capacitor 53 can be formed, for example, in a region where an insulating layer 106 is sandwiched between the conductive layer 204 serving as the gate electrode of the transistor 52B and the conductive layer 109 serving as one of the gate electrode, source electrode, and drain electrode of the transistor 52C. In addition, the structure of the capacitor 53 is not particularly limited.

[0571] The insulating layer 195 is provided so as to cover the transistor 52A, the transistor 52B, the transistor 52C, and the capacitor 53, and the insulating layer 197 is provided so as to cover the insulating layer 195. A light-emitting device 61 can be provided on the insulating layer 197. Figure 33C The pixel electrode 111 serving as one electrode of the light-emitting device 61 is shown. The pixel electrode 111 is electrically connected to the conductive layer 109 included in the transistor 52C through an opening 135 provided in the insulating layer 195 and the insulating layer 197. The insulating layer 195 can be referred to the above description, so the detailed description is omitted. The insulating layer 197 has a function of reducing the unevenness caused by the transistor 52A, the transistor 52B, and the transistor 52C to make the formation surface of the light-emitting device 61 flatter. Note that in this specification and the like, the insulating layer 197 is sometimes referred to as a planarization layer.

[0572] As the insulating layer 197, an insulating layer containing an organic material can be appropriately used. As the organic material, a photosensitive resin is preferably used, and for example, a photosensitive resin composition including an acrylic resin is preferably used. Note that in this specification and the like, the acrylic resin does not only refer to polymethyl methacrylate or methacrylic resin, and sometimes also refers to the entire acrylic polymer in a broad sense.

[0573] As the insulating layer 197, an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimide amide resin, a silicone resin, a siloxane resin, a benzocyclobutene resin, a phenolic resin, and precursors of the above resins can also be used. In addition, as the insulating layer 197, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used. In addition, a photoresist can also be used as the photosensitive resin. As the photosensitive resin, a positive-type material or a negative-type material can be used.

[0574] The insulating layer 197 may also have a laminated structure of an organic insulating layer and an inorganic insulating layer. For example, the insulating layer 197 may have a laminated structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer. By providing an inorganic insulating layer on the outermost surface of the insulating layer 197, it can be used as an etching protection layer. Thereby, it is possible to suppress a part of the insulating layer 197 from being etched when the pixel electrode 111 is formed and a decrease in the flatness of the insulating layer 197.

[0575] The pixel electrode 111 is electrically connected to the conductive layer 109 through openings provided in the insulating layer 197, the insulating layer 195, and the insulating layer 106.

[0576] The display device according to one embodiment of the present invention may also adopt any one of the following structures: a top emission type that emits light in a direction opposite to the substrate on which the light-emitting device is formed, a bottom emission type that emits light toward the substrate side on which the light-emitting device is formed, and a dual emission type that emits light in both directions.

[0577] <Example 1 of the structure of the display device>

[0578] Figure 34 An example of a cross-section showing a part of the region including the FPC 172, a part of the peripheral circuit portion 164, a part of the display portion 162, a part of the connection portion 140, and a part of the region including the end portion of the display device 50A is shown.

[0579] Figure 34 The shown display device 50A includes transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, 130B, etc. between the substrate 151 and the substrate 152. The light-emitting element 130R is a display element included in the pixel 230R that emits red light, the light-emitting element 130G is a display element included in the pixel 230G that emits green light, and the light-emitting element 130B is a display element included in the pixel 230B that emits blue light.

[0580] The display device 50A adopts an SBS structure. In the SBS structure, it is possible to optimize the materials and structures of the respective light-emitting elements separately, the degree of freedom in the selection of materials and structures increases, and it becomes easy to improve the brightness and reliability.

[0581] The display device 50A adopts a top emission type. In the top emission type, transistors and the like can be arranged so as to overlap with the light-emitting region of the light-emitting element, so the aperture ratio of the pixel can be further improved compared with the bottom emission type.

[0582] The transistors 205D, 205R, 205G, and 205B are all formed on the substrate 151. These transistors can be manufactured using the same material and the same process.

[0583] OS transistors can be appropriately used as the transistors 205D, 205R, 205G, and 205B. As the transistors 205D, 205R, 205G, and 205B, transistors of one aspect of the present invention can be used. That is, in the display device 50A, both the display unit 162 and the peripheral circuit unit 164 include transistors of one aspect of the present invention. By using the transistors of one aspect of the present invention in the display unit 162, the pixel size can be reduced and the resolution can be improved. In addition, by using the transistors of one aspect of the present invention in the peripheral circuit unit 164, the occupied area of the peripheral circuit unit 164 can be reduced and the bezel can be narrowed. For the transistors of one aspect of the present invention, reference can be made to the description of the above embodiments.

[0584] Sometimes, the transistors provided in the peripheral circuit unit 164 need to have a larger on-state current than the transistors provided in the display unit 162. Transistors with a short channel length are preferably used in the peripheral circuit unit 164. For example, one or more of the above transistors 100 to 100G can be appropriately used in the peripheral circuit unit 164. By using one or more of the transistors 100 to 100G in the peripheral circuit unit 164, the occupied area can be reduced, and thus a display device with a narrow bezel can be realized. In addition, as the transistors provided in the display unit 162, one or more of the above transistors 200 to 200G can be appropriately used. Figure 34 A structure is shown in which the above transistor 100B is used as the transistor 205D, and the transistors 200B are used as the transistors 205R, 205G, and 205B. Note that one or more of the transistors 100 to 100G can also be used in the display unit 162, and one or more of the transistors 200 to 200G can also be used in the peripheral circuit unit 164.

[0585] Note that the transistors included in the display device in the present embodiment are not limited to the transistors of one aspect of the present invention. For example, the transistors of one aspect of the present invention and transistors of other structures can be combined. The display device of the present embodiment can include, for example, any one or more of planar transistors, staggered transistors, and anti-staggered transistors. The transistors included in the display device of the present embodiment can have any one of a top-gate type and a bottom-gate type structure. Alternatively, a gate can be provided above and below the semiconductor layer in which the channel is formed.

[0586] The display device according to this embodiment may also include a transistor (Si transistor) using silicon for the channel formation region. As the silicon, single-crystalline silicon, polycrystalline silicon, and amorphous silicon can be cited. In particular, a transistor including LTPS in the semiconductor layer (hereinafter, also referred to as an LTPS transistor) can be used. The LTPS transistor has a high field-effect mobility and good frequency characteristics.

[0587] When increasing the emission luminance of the light-emitting element included in the pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. For this purpose, it is necessary to increase the source-drain voltage of the driving transistor included in the pixel circuit. Since the breakdown voltage between the source and the drain of the OS transistor is higher than that of the Si transistor, a high voltage can be applied between the source and the drain of the OS transistor. Thus, by using the OS transistor as the driving transistor included in the pixel circuit, the amount of current flowing through the light-emitting element can be increased and the emission luminance of the light-emitting element can be increased.

[0588] When the transistor operates in the saturation region, compared with the Si transistor, the OS transistor can make the change in the source-drain current for the change in the gate-source voltage finer. Therefore, by using the OS transistor as the driving transistor included in the pixel circuit, the current flowing through the source-drain can be determined in detail according to the change in the gate-source voltage, so that the amount of current flowing through the light-emitting element can be controlled. Thus, the number of gray levels of the pixel circuit can be increased.

[0589] Regarding the saturation characteristics of the current flowing when the transistor operates in the saturation region, compared with the Si transistor, the OS transistor can make a stable current (saturation current) flow even when gradually increasing the source-drain voltage. Therefore, by using the OS transistor as the driving transistor, even if, for example, the current-voltage characteristics of the light-emitting element are uneven, a stable current can flow through the light-emitting element. That is, when the OS transistor operates in the saturation region, even if the source-drain voltage is changed, the source-drain current hardly changes, so that the emission luminance of the light-emitting element can be stabilized.

[0590] The transistors included in the peripheral circuit unit 164 and the transistors included in the display unit 162 may have the same structure or may have different structures. The plurality of transistors included in the peripheral circuit unit 164 may have the same structure or may have two or more different structures. Similarly, the plurality of transistors included in the display unit 162 may have the same structure or may have two or more different structures.

[0591] All the transistors included in the display unit 162 may be OS transistors, all the transistors included in the display unit 162 may be Si transistors, and some of the transistors included in the display unit 162 may be OS transistors and the remaining transistors may be Si transistors.

[0592] For example, by using both LTPS transistors and OS transistors in the display unit 162, a display device with low power consumption and high driving ability can be achieved. In addition, a structure combining LTPS transistors and OS transistors is sometimes referred to as LTPO. As a more preferable example, the following structure can be cited: using OS transistors for transistors such as switches that control conduction / non-conduction between control wirings and using LTPS transistors for transistors that control current, etc.

[0593] For example, one of the transistors included in the display unit 162 is used as a transistor that controls the current flowing through the light-emitting element and can also be referred to as a driving transistor. One of the source and drain of the driving transistor is electrically connected to the pixel electrode of the light-emitting element. An LTPS transistor is preferably used as the driving transistor. Thereby, the current flowing through the light-emitting element in the pixel circuit can be increased.

[0594] On the other hand, another one of the transistors included in the display unit 162 is used as a switch that controls the selection and non-selection of pixels and can also be referred to as a selection transistor. The gate of the selection transistor is electrically connected to the gate line, and one of the source and drain is electrically connected to the source line (signal line). An OS transistor is preferably used as the selection transistor. Therefore, even if the frame frequency is significantly low (e.g., 1 fps or less), the gray scale of the pixels can be maintained. Thus, by stopping the driver when displaying a static image, power consumption can be reduced.

[0595] An insulating layer 195 is provided so as to cover the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B, and an insulating layer 235 is provided on the insulating layer 195.

[0596] The insulating layer 235 is preferably used as a planarization layer, and an organic insulating film is suitable. As materials that can be used for the organic insulating film, for example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, silicone resin, benzocyclobutene resin, phenolic resin, and precursors of these resins can be cited. In addition, the insulating layer 235 can also adopt a laminated structure of an organic insulating film and an inorganic insulating film. The outermost surface layer of the insulating layer 235 is preferably used as an etching protection layer. Thereby, when processing the pixel electrodes 111R, 111G, 111B, etc., the formation of recesses in the insulating layer 235 can be suppressed. Or, recesses can also be provided in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, etc.

[0597] Light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 235.

[0598] The light-emitting element 130R includes a pixel electrode 111R on an insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. Figure 34 The illustrated light-emitting element 130R emits red light (R). The EL layer 113R includes a light-emitting layer that emits red light.

[0599] The light-emitting element 130G includes a pixel electrode 111G on an insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. Figure 34 The illustrated light-emitting element 130G emits green light (G). The EL layer 113G includes a light-emitting layer that emits green light.

[0600] The light-emitting element 130B includes a pixel electrode 111B on an insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. Figure 34 The illustrated light-emitting element 130B emits blue light (B). The EL layer 113B includes a light-emitting layer that emits blue light.

[0601] Note that in Figure 34 the EL layers 113R, 113G, and 113B are shown with the same thickness, but are not limited thereto. The respective thicknesses of the EL layers 113R, 113G, and 113B may also be different. For example, the thicknesses of the EL layers 113R, 113G, and 113B are preferably set to thicknesses that achieve an optical path of light that enhances the light emitted from the corresponding EL layers 113R, 113G, and 113B. Thereby, a microcavity structure can be realized to improve the color purity of the light emitted from each light-emitting element.

[0602] The pixel electrode 111R is electrically connected to a conductive layer 109 included in the transistor 205R through an opening provided in the insulating layers 195 and 235. Similarly, the pixel electrode 111G is electrically connected to the conductive layer 109 included in the transistor 205G, and the pixel electrode 111B is electrically connected to the conductive layer 109 included in the transistor 205B.

[0603] Each end of the pixel electrodes 111R, 111G, and 111B is covered by an insulating layer 237. The insulating layer 237 is used as a partition wall (also referred to as a bank, dam, or spacer). The insulating layer 237 can be provided as a single-layer structure or a stacked structure using one or both of an inorganic insulating material and an organic insulating material. The insulating layer 237 can be formed, for example, using a material that can be used for the insulating layer 235. The insulating layer 237 can electrically insulate the pixel electrode from the common electrode. In addition, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0604] The common electrode 115 is a continuous film shared by the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by a plurality of light-emitting elements is electrically connected to the conductive layer 123 provided in the connection portion 140. The conductive layer 123 preferably uses the same material as the pixel electrodes 111R, 111G, and 111B and is formed by the same process as the pixel electrodes 111R, 111G, and 111B.

[0605] In a display device according to one aspect of the present invention, a conductive film that transmits visible light is used as the electrode on the light extraction side of the pixel electrode and the common electrode. In addition, as the electrode on the non-light extraction side, a conductive film that reflects visible light is preferably used.

[0606] As the electrode on the non-light extraction side, a conductive film that transmits visible light may also be used. In this case, it is preferable to dispose this electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer can also be reflected by the reflective layer and extracted from the display device.

[0607] As the material for forming the pair of electrodes of the light-emitting element, metals, alloys, conductive compounds, and mixtures thereof can be appropriately used. Specifically, examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys obtained by appropriately combining them. In addition, as the material, indium tin oxide (also referred to as In-Sn oxide, ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide can be cited. In addition, as the material, aluminum-containing alloys (aluminum alloys) such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and silver-containing alloys such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (also denoted as Ag-Pd-Cu, APC) can be cited. In addition, as the material, elements belonging to Group 1 or Group 2 of the periodic table that are not listed above (for example, lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys obtained by appropriately combining them, and graphene can be cited.

[0608] The light-emitting element preferably has a microcavity resonator (microcavity) structure. Therefore, one of the pair of electrodes included in the light-emitting element preferably includes an electrode that is transmissive and reflective to visible light (semi-transmissive - semi-reflective electrode), and the other preferably includes an electrode that is reflective to visible light (reflective electrode). When the light-emitting element has a microcavity structure, light emission obtained from the light-emitting layer can be resonated between the two electrodes, and the light emitted from the light-emitting element can be enhanced.

[0609] The light transmittance of the transparent electrode is 40% or more. For example, an electrode with a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more is preferably used as the transparent electrode of the light-emitting element. The reflectance of the semi-transmissive semi-reflective electrode for visible light is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectance of the reflective electrode for visible light is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is preferably 1×10 -2 Ω·cm or less.

[0610] EL layers 113R, 113G, and 113B are all arranged in an island shape. In Figure 34 , the end of the adjacent EL layer 113R overlaps with the end of the EL layer 113G, the end of the adjacent EL layer 113G overlaps with the end of the EL layer 113B, and the end of the adjacent EL layer 113R overlaps with the end of the EL layer 113B. As Figure 34 shown, in the case of depositing the island-shaped EL layer using a high-precision metal mask, sometimes the ends of the adjacent EL layers overlap, but the present invention is not limited thereto. That is, the adjacent EL layers may also be separated without overlapping. In addition, in the display device, there may be both a part where the adjacent EL layers overlap and a part where the adjacent EL layers are separated without overlapping.

[0611] EL layers 113R, 113G, and 113B all include at least a light-emitting layer. The light-emitting layer contains one or more light-emitting substances. As the light-emitting substance, a substance that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red is appropriately used. In addition, as the light-emitting substance, a substance that emits near-infrared light may also be used.

[0612] Examples of the light-emitting substance include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0613] In addition to the light-emitting substance (guest material), the light-emitting layer may contain one or more organic compounds (host materials, auxiliary materials, etc.). As the one or more organic compounds, one or both of a substance with high hole-transporting properties (hole-transporting material) and a substance with high electron-transporting properties (electron-transporting material) can be used. In addition, as the one or more organic compounds, a bipolar substance (a substance with high electron-transporting and hole-transporting properties) or a TADF material may also be used.

[0614] For example, the light-emitting layer preferably contains a combination of a phosphorescent material, a hole-transporting material that easily forms an exciplex, and an electron-transporting material. By adopting such a structure, light emission by ExTET (Exciplex-Triplet Energy Transfer) that utilizes energy transfer from the exciplex to the luminescent substance (phosphorescent material) can be obtained efficiently. In addition, by selecting, as the exciplex, a combination that emits light whose wavelength overlaps with the absorption band on the lowest energy side of the luminescent substance, the energy transfer can be made smooth, and thus light emission can be obtained efficiently. By adopting the above structure, high efficiency, low-voltage driving, and long life of the light-emitting element can be achieved simultaneously.

[0615] In addition to the light-emitting layer, the EL layer may further include one or more of a layer containing a substance with high hole-injecting property (hole injection layer), a layer containing a hole-transporting material (hole transport layer), a layer containing a substance with high electron-blocking property (electron blocking layer), a layer containing a substance with high electron-injecting property (electron injection layer), a layer containing an electron-transporting material (electron transport layer), and a layer containing a substance with high hole-blocking property (hole blocking layer). In addition, the EL layer may also contain one or both of a bipolar material and a TADF material.

[0616] The light-emitting element may use a low-molecular compound or a high-molecular compound, and may also contain an inorganic compound. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet, and coating.

[0617] The light-emitting element may adopt a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure including a plurality of light-emitting units). The light-emitting unit includes at least one light-emitting layer. The tandem structure has a structure in which a plurality of light-emitting units are connected in series through a charge generation layer. The charge generation layer has a function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes. By adopting the tandem structure, a light-emitting element capable of emitting light with high brightness can be realized. In addition, since the tandem structure can reduce the current required to obtain the same brightness compared to the single structure, the reliability can be improved. In addition, the tandem structure may also be referred to as a stacked structure.

[0618] When Figure 34 using a light-emitting element with a tandem structure, preferably, the EL layer 113R includes a plurality of light-emitting units that emit red light, the EL layer 113G includes a plurality of light-emitting units that emit green light, and the EL layer 113B includes a plurality of light-emitting units that emit blue light.

[0619] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded by an adhesive layer 142. The substrate 152 is provided with a light-shielding layer 117. As the sealing of the light-emitting element, for example, a solid sealing structure or a hollow sealing structure can be adopted. In Figure 34 , the space between the substrate 152 and the substrate 151 is filled with the adhesive layer 142, that is, a solid sealing structure is adopted. Alternatively, a hollow sealing structure using an inert gas (such as nitrogen or argon) to fill the space can also be adopted. At this time, the adhesive layer 142 can also be provided in a manner that does not overlap with the light-emitting element. In addition, the space can also be filled with a resin different from the adhesive layer 142 provided in a frame shape.

[0620] The protective layer 131 is provided at least in the display portion 162, and is preferably provided so as to cover the entire display portion 162. The protective layer 131 is preferably provided so as to cover the connection portion 140 and the peripheral circuit portion 164 in addition to the display portion 162. In addition, the protective layer 131 is preferably provided so as to extend to the end of the display device 50A. On the other hand, in order to electrically connect the FPC 172 to the conductive layer 166, there is a portion in the connection portion 168 where the protective layer 131 is not provided.

[0621] By providing the protective layer 131 on the light-emitting elements 130R, the light-emitting element 130G, and the light-emitting element 130B, the reliability of the light-emitting element can be improved.

[0622] The protective layer 131 can be either a single-layer structure or a laminated structure of two or more layers. In addition, there is no limitation on the conductivity of the protective layer 131. As the protective layer 131, at least one of an insulating film, a semiconductor film, and a conductive film can be used.

[0623] When the protective layer 131 includes an inorganic film, deterioration of the light-emitting element can be suppressed, such as preventing oxidation of the common electrode 115 and suppressing the entry of impurities (such as moisture and oxygen) into the light-emitting element, etc., thereby improving the reliability of the display device.

[0624] The protective layer 131 can use inorganic insulating films such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitrogen oxide insulating film, for example. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably includes a nitride insulating film or a nitrogen oxide insulating film, and more preferably includes a nitride insulating film.

[0625] As the protective layer 131, an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO, etc. can also be used. This inorganic film preferably has a high resistance. Specifically, this inorganic film preferably has a higher resistance than the common electrode 115. This inorganic film can also contain nitrogen.

[0626] When extracting light emission from the light-emitting element through the protective layer 131, the visible light transmittance of the protective layer 131 is preferably high. For example, ITO, IGZO, and alumina are all inorganic materials with high visible light transmittance, so they are preferred.

[0627] As the protective layer 131, for example, a stacked structure of an alumina film and a silicon nitride film on the alumina film or a stacked structure of an alumina film and an IGZO film on the alumina film can be adopted. By using this stacked structure, entry of impurities (such as water and oxygen) into the EL layer side can be suppressed.

[0628] Moreover, the protective layer 131 may also include an organic film. For example, the protective layer 131 may include both an organic film and an inorganic film. As the organic film that can be used for the protective layer 131, for example, an organic insulating film that can be used for the insulating layer 235 can be cited.

[0629] A connection portion 168 is provided in a region of the substrate 151 that does not overlap with the substrate 152. In the connection portion 168, the wiring 165 is electrically connected to the FPC 172 through the conductive layer 166 and the connection layer 242. The conductive layer 166 shows an example of a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The conductive layer 166 is exposed on the top surface of the connection portion 168. Therefore, the connection portion 168 can be electrically connected to the FPC 172 through the connection layer 242.

[0630] The wiring 165 is electrically connected to a transistor included in the peripheral circuit portion 164. Figure 34 A structure in which the conductive layer 109 included in the transistor 205D extends and is used as the wiring 165 is shown. Note that the structure of the wiring 165 is not limited to this.

[0631] The display device 50A adopts a top emission type. The light emitted from the light-emitting element is emitted to the substrate 152 side. The substrate 152 is preferably made of a material with high visible light transmittance. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0632] Preferably, a light-shielding layer 117 is provided on the surface of the substrate 152 on the substrate 151 side. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection portion 140, the peripheral circuit portion 164, etc.

[0633] In addition, a color filter or other coloring layer may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When the color filter is provided overlapping the light-emitting element, the color purity of the light emitted from the pixel can be improved.

[0634] In addition, various optical members can be disposed on the outer side of the substrate 152 (the surface on the side opposite to the side of the substrate 151). Examples of the optical members include a polarizing plate, a retardation plate, a light diffusion layer (diffusion film, etc.), an antireflection layer, and a condensing film. In addition, an antistatic film that suppresses the attachment of dust, a water-repellent film that is not easily soiled, a hard coat film that suppresses damage during use, a shock absorption layer, and other surface protective layers can also be disposed on the outer side of the substrate 152. For example, by providing a glass layer or a silicon dioxide layer (SiO x layer) as the surface protective layer, it is possible to suppress the surface from being soiled or damaged, so it is preferable. In addition, DLC (diamond-like carbon), aluminum oxide (AlO x ), a polyester material, a polycarbonate material, or the like can also be used as the surface protective layer. In addition, a material having a high transmittance of visible light is preferably used as the surface protective layer. In addition, a material having a high hardness is preferably used as the surface protective layer.

[0635] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, or the like. The substrate on the side where light is extracted from the light-emitting element uses a material that transmits the light. By using a flexible material for the substrate 151 and the substrate 152, the flexibility of the display device can be improved, and thus a flexible display can be realized. As at least one of the substrate 151 and the substrate 152, a polarizing plate can also be used.

[0636] As the substrate 151 and the substrate 152, the following materials can be used respectively: polyester resins such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, and cellulose nanofibers. In addition, glass having a flexible thickness can also be used as at least one of the substrate 151 and the substrate 152.

[0637] When a circular polarizing plate is overlapped on the display device, it is preferable to use a substrate having high optical isotropy as the substrate included in the display device. The birefringence of the substrate having high optical isotropy is low (it can also be said that the amount of birefringence is small). Examples of the thin film having high optical isotropy include a cellulose triacetate (TAC, also called cellulose acetate) thin film, a cycloolefin polymer (COP) thin film, a cycloolefin copolymer (COC) thin film, and an acrylic resin thin film.

[0638] As the adhesive layer 142, various curable adhesives such as photocurable adhesives like ultraviolet curable adhesives, reaction curable adhesives, thermosetting adhesives, anaerobic adhesives, etc. can be used. As these adhesives, epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, EVA (ethylene-vinyl acetate) resins, etc. can be cited. In particular, materials with low moisture permeability such as epoxy resins are preferably used. In addition, two-component mixed resins can also be used. Further, adhesive sheets, etc. can also be used.

[0639] As the connection layer 242, an anisotropic conductive film (ACF: Anisotropic Conductive Film), an anisotropic conductive paste (ACP: Anisotropic Conductive Paste), etc. can be used.

[0640] <Example structure of display device 2>

[0641] Figure 35 The main difference between the shown display device 50B and the display device 50A is that light-emitting elements including an EL layer 113 shared by the light-emitting elements and a coloring layer (such as a color filter) are used in the sub-pixels of each color of the display device 50B. Note that in the description of the display device to be described later, parts that are the same as those of the previously described display device may sometimes be omitted from the description.

[0642] Figure 35 The shown display device 50B includes transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, 130B, a coloring layer 132R that transmits red light, a coloring layer 132G that transmits green light, and a coloring layer 132B that transmits blue light, etc. between a substrate 151 and a substrate 152.

[0643] The light-emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emission of the light-emitting element 130R is extracted as red light to the outside of the display device 50B through the coloring layer 132R.

[0644] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. The light emission of the light-emitting element 130G is extracted as green light to the outside of the display device 50B through the coloring layer 132G.

[0645] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. The light emitted by the light-emitting element 130B is extracted to the outside of the display device 50B as blue light through the color filter layer 132B.

[0646] The light-emitting elements 130R, 130G, and 130B share the EL layer 113 and the common electrode 115. Compared with a structure in which different EL layers are provided for each color sub-pixel, the structure in which each color sub-pixel shares the EL layer 113 can reduce the number of manufacturing processes.

[0647] For example, Figure 35 The light-emitting elements 130R, 130G, and 130B shown emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the color filter layers 132R, 132G, and 132B, whereby light of a desired color can be obtained.

[0648] The white light-emitting element preferably includes two or more light-emitting layers. In the case of obtaining white light emission using two light-emitting layers, the light-emitting layers may be selected such that the emission colors of the two light-emitting layers are complementary colors. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary colors, a structure in which the entire light-emitting element emits white light can be obtained. In addition, in the case of obtaining white light emission using three or more light-emitting layers, the emission colors of the three or more light-emitting layers may be combined to obtain a structure in which the entire light-emitting element emits white light.

[0649] The EL layer 113 preferably includes, for example, a light-emitting layer containing a light-emitting substance that emits blue light and a light-emitting layer containing a light-emitting substance that emits visible light having a wavelength longer than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0650] The light-emitting elements that emit white light preferably adopt a series structure. Specifically, the following structures can be adopted: a two-stage series structure including a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light; a two-stage series structure including a light-emitting unit that emits red light and green light and a light-emitting unit that emits blue light; a three-stage series structure including a light-emitting unit that emits blue light, a light-emitting unit that emits yellow light, yellow-green light or green light, and a light-emitting unit that emits blue light in sequence; or a three-stage...

Claims

1. A semiconductor device comprising a first transistor and a second transistor on a substrate, Among them, The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer and a first semiconductor layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer, The first insulating layer and the second conductive layer have openings reaching the first conductive layer, The first semiconductor layer is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the top surface of the second conductive layer in the opening. The second insulating layer is located on the first semiconductor layer, The third conductive layer is located on the first semiconductor layer via the second insulating layer. The second transistor includes a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, the first insulating layer, the second insulating layer and a second semiconductor layer, The fourth conductive layer and the fifth conductive layer are located on the first insulating layer. The second semiconductor layer is in contact with the top surface of the fourth conductive layer, the side surface of the fourth conductive layer, the top surface of the first insulating layer, the side surface of the fifth conductive layer, and the top surface of the fifth conductive layer. The second insulating layer is located on the second semiconductor layer, Furthermore, the sixth conductive layer is located on the second semiconductor layer via the second insulating layer.

2. The semiconductor device according to claim 1, The second conductive layer, the fourth conductive layer and the fifth conductive layer include the same material.

3. The semiconductor device according to claim 1, The third conductive layer and the sixth conductive layer include the same material.

4. The semiconductor device according to claim 1, wherein the second transistor comprises a third insulating layer, The second semiconductor layer is located on the third insulating layer via the second insulating layer. And the second insulating layer includes oxygen at a concentration higher than that of the third insulating layer.

5. A semiconductor device comprising a first transistor and a second transistor on a substrate, Among them, The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, a third insulating layer and a first semiconductor layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer, The second insulating layer covers the top surface and side surfaces of the second conductive layer. The third conductive layer is located on the second insulating layer, The first insulating layer, the second insulating layer and the third conductive layer have openings reaching the first conductive layer, The first semiconductor layer is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second insulating layer, the side surface of the third conductive layer, and the top surface of the third conductive layer in the opening. The third insulating layer is located on the first semiconductor layer. The fourth conductive layer is located on the first semiconductor layer via the third insulating layer. The second transistor includes a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, the first insulating layer, the second insulating layer, the third insulating layer, and a second semiconductor layer. The first insulating layer is located on the fifth conductive layer. The second insulating layer is located on the first insulating layer. The sixth conductive layer and the seventh conductive layer are located on the second insulating layer. The second semiconductor layer is in contact with the top surface of the sixth conductive layer, the side surface of the sixth conductive layer, the top surface of the second insulating layer, the side surface of the seventh conductive layer, and the top surface of the seventh conductive layer. The third insulating layer is located on the second semiconductor layer. Moreover, the eighth conductive layer is located on the second semiconductor layer with the third insulating layer therebetween.

6. The semiconductor device according to claim 5, wherein the third conductive layer, the sixth conductive layer, and the seventh conductive layer comprise the same material.

7. The semiconductor device according to claim 5, wherein the first conductive layer and the fifth conductive layer comprise the same material.

8. The semiconductor device according to claim 5, wherein the second transistor includes a fourth insulating layer. The second semiconductor layer is located on the fourth insulating layer with the third insulating layer therebetween. And the concentration of oxygen contained in the third insulating layer is higher than the concentration of oxygen contained in the fourth insulating layer.

9. The semiconductor device according to any one of claims 1 to 8, wherein both the first semiconductor layer and the second semiconductor layer comprise metal oxides.

10. The semiconductor device according to any one of claims 1 to 8, wherein the first semiconductor layer and the second semiconductor layer comprise the same material.

11. The semiconductor device according to any one of claims 1 to 8, wherein the first semiconductor layer and the second semiconductor layer comprise different materials.

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