AI ASIC chip test circuit, device and system

Abstract

The embodiment of the invention relates to the technical field of chip testing, and discloses an AI ASIC chip testing circuit, device and system.The AI ASIC chip testing circuit comprises an AI ASIC chip testing socket, a plurality of power interfaces and a control circuit, the power interfaces are connected with power signals of different voltages, and the control circuit is connected with the AI ASIC chip testing socket. The AI ASIC chip testing socket is used for testing the AI ASIC chip to be tested and supplying a working power supply to a plurality of core working modules of the AI ASIC chip to be tested on the AI ASIC chip testing socket so as to test whether the core working modules of the AI ASIC chip to be tested can be normally powered on or not, and the control circuit obtains a plurality of operator testing models. And providing the operator test models for the plurality of operators of the AI ASIC chip to be tested on the AI ASIC chip test socket in a one-to-one manner so as to test whether the plurality of operators of the AI ASIC chip to be tested work normally or not. According to the scheme, the special function of the AI ASIC chip is tested, namely the performance of multiple operators of the AI ASIC chip is tested in a one-to-one mode through the operator test model, and therefore the technical problem that the special function of the AI ASIC chip cannot be tested independently in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly relates to an AI ASIC chip testing circuit, device and system. Background Art

[0002] Currently, most chip tests rely on some large-scale automatic test machines. By applying some specific excitations to the input / output pins of the chip, observing its return value, and comparing it with the expected function, it is judged whether the chip can work stably. However, some large-scale automatic test equipment is expensive, and it is difficult to have the conditions to build a test environment. At the same time, it is difficult to debug using conventional software, greatly reducing the flexibility of the automatic test machine.

[0003] For AI (Artificial Intelligence) ASIC (Application-Specific Integrated Circuit) chips, conventional test equipment can only conduct conduction of some conventional pins and detection of conventional functions, and cannot detect the special functions of AI ASIC chips. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention provide an AI ASIC chip testing circuit, device and system for solving the technical problem that the special functions of AI ASIC chips cannot be tested separately.

[0005] According to one aspect of the embodiments of the present invention, an AI ASIC chip testing circuit is provided. The AI ASIC chip testing circuit includes:

[0006] An AI ASIC chip testing socket for fixing the AI ASIC chip to be tested, and when the AI ASIC chip to be tested is fixed, the pins of the AI ASIC chip testing socket are electrically connected to the pins of the AI ASIC chip one by one;

[0007] A plurality of power interfaces electrically connected to the AI ASIC chip testing socket for accessing power supply signals of multiple different voltages and supplying working power to multiple core working modules of the AI ASIC chip to be tested on the AI ASIC chip testing socket, so as to test whether the multiple core working modules of the AI ASIC chip to be tested can be powered on normally;

[0008] A control circuit, electrically connected to the AI ASIC chip test socket, is configured to obtain multiple operator test models and provide the operator test models to multiple operators of the AI ASIC chip to be tested on the AI ASIC chip test socket one by one, so as to test whether the multiple operators of the AI ASIC chip to be tested are working properly.

[0009] In an alternative embodiment, the control circuit is further configured to:

[0010] Obtain a test model, which integrates the operations of multiple operators, and sequentially input the calculations to be performed into the corresponding operators of the AI ASIC chip to be tested on the AI ASIC chip test socket according to the calculation order of the operators in the test model, so as to test whether the multiple operators of the AI ASIC chip to be tested are working properly.

[0011] In an alternative embodiment, the control circuit is further configured to:

[0012] Obtain the configuration information of the AI ASIC chip to be tested, configure the corresponding registers of the AI ASIC chip to be tested on the AI ASIC chip test socket according to the configuration information, and determine whether the configuration of the corresponding registers of the AI ASIC chip to be tested is successful based on the results fed back by the registers of the AI ASIC chip to be tested.

[0013] In an alternative embodiment, the model of the register is DDR3.

[0014] In an alternative embodiment, the AI ASIC chip test circuit further includes a camera signal input interface and an image format conversion circuit, and the camera signal input interface is connected to the control circuit through the image format conversion circuit;

[0015] The camera signal input interface is configured to obtain image data;

[0016] The image format conversion circuit is configured to perform format conversion on the image data and output it as an image signal to the control circuit;

[0017] The control circuit is configured to output the image signal to the AI ASIC chip to be tested for model operation and obtain the state result after the model operation output by the AI ASIC chip to be tested.

[0018] In an alternative embodiment, the image format conversion circuit is an image serial-to-parallel chip.

[0019] In an alternative manner, the AI ASIC chip test circuit further includes:

[0020] A plurality of indicator lights, with one indicator light provided between each power interface and the AI ASIC chip test socket;

[0021] The indicator light lights up to confirm that the core working module of the to-be-tested AI ASIC chip connected to the power interface is normally powered on when there is current transfer between the connected power interface and the AI ASIC chip test socket.

[0022] According to a second aspect provided by the present invention, the present invention further proposes an AI ASIC chip test device, and the AI ASIC chip test device includes the AI ASIC chip test circuit as described above.

[0023] According to a third aspect provided by the present invention, the present invention further proposes an AI ASIC chip test system, and the AI ASIC chip test system includes a host computer and the AI ASIC chip test circuit as described above, and a control circuit of the AI ASIC chip test circuit is connected to the host computer;

[0024] The host computer is configured to display the test results of the AI ASIC chip test circuit.

[0025] In an alternative manner of the third aspect, the AI ASIC chip test system further includes a camera and a power input circuit, the camera is connected to a camera signal input interface of the AI ASIC chip test circuit, and the power input circuit is connected to a power circuit of the AI ASIC chip test circuit;

[0026] The camera is configured to collect the image data;

[0027] The camera signal input interface is configured to input the image data into the AI ASIC chip test circuit.

[0028] In an embodiment of the present invention, new requirements are put forward for the test equipment of the AI ASIC chip, that is, to test the special functions of the AI ASIC chip, set up the test circuit, simulate the working environment of the AI ASIC chip by setting up the AI ASIC chip test socket, multiple power interfaces, and control circuits, etc., connect multiple power interfaces to power supply signals of various different voltages, and supply working power to multiple core working modules of the AI ASIC chip to be tested on the AI ASIC chip test socket, so as to test whether the multiple core working modules of the AI ASIC chip to be tested can be powered on normally. The control circuit obtains multiple operator test models and provides the operator test models to multiple operators of the AI ASIC chip to be tested on the AI ASIC chip test socket one by one, so as to test whether the multiple operators of the AI ASIC chip to be tested are working normally. Through the above solution, the special functions of the AI ASIC chip, that is, the performance of multiple operators of the AI ASIC chip is tested one by one through the operator test model, so as to verify the power-on situation of multiple core working modules of the AI ASIC chip and whether the calculation functions of the operators of multiple core working modules are normal, thus solving the technical problem in the prior art that the special functions of the AI ASIC chip cannot be tested separately.

[0029] The above description is only an overview of the technical solution of the embodiment of the present invention. In order to be able to understand the technical means of the embodiment of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the embodiment of the present invention more obvious and understandable, the following specifically illustrates the embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings are only used to illustrate the embodiments and are not considered as a limitation of the present invention. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0031] Figure 1 The module schematic diagram of the first embodiment of the AI ASIC chip test circuit provided by the present invention is shown;

[0032] Figure 2 The module schematic diagram of the second embodiment of the AI ASIC chip test circuit provided by the present invention is shown;

[0033] Figure 3 The module schematic diagram of the AI ASIC chip test system provided by the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein.

[0035] Combined with the related technology, the chip testing device solutions in the prior art are analyzed below.

[0036] According to the chip design process, simulation is carried out during design. Digital circuits usually use FPGAs for functional verification. However, due to the uncertainties in the production process, the instability of chip performance parameters may occur. After the chip is taped out, even if the tape-out manufacturer conducts relevant tests, as the end-user, functional verification still needs to be carried out.

[0037] The test modes of chips generally include test modes such as scan, BIST, and input / output, and each mode has different test purposes. Currently, most chip tests rely on some large-scale automatic test machines. By applying some specific excitations to the input / output pins of the chip and observing the returned values, and comparing them with the expected functions, it is determined whether the chip can work stably. However, some large-scale automatic test equipment is expensive, and it is difficult to have the conditions to build a test environment; at the same time, it is difficult to debug using conventional software.

[0038] The above analysis proves that at the manufacturer's end, there is a unified chip testing device for functional verification of chips. However, when used by customers, there is a technical problem that there is a lack of a separate testing device to test the special functions of each chip individually.

[0039] What this application provides is an AI ASIC chip testing circuit, device, and system, which can solve the technical problem in the prior art that the special functions of AI ASIC chips cannot be tested individually by setting up a dedicated testing circuit and assisting with a method for testing the operating functions of AI ASIC chips.

[0040] In one embodiment, referring to Figure 1 and Figure 3 As shown, the AI ASIC chip testing circuit includes an AI ASIC chip testing socket 10, a plurality of power interfaces 30, and a control circuit 20. The plurality of power interfaces 30 are electrically connected to the AI ASIC chip testing socket 10, and the control circuit 20 is electrically connected to the AI ASIC chip testing socket 10.

[0041] Among them, the AI ASIC chip test socket 10 is used to fix the AI ASIC chip to be tested. When the AI ASIC chip to be tested is fixed, the pins of the AI ASIC chip test socket 10 are electrically connected to the pins of the AI ASIC chip one by one. Multiple power interfaces 30 access power supply signals of multiple different voltages and supply working power to multiple core working modules of the AI ASIC chip to be tested on the AI ASIC chip test socket 10, so as to test whether the multiple core working modules of the AI ASIC chip to be tested can be powered on normally. The control circuit 20 obtains multiple operator test models and provides the operator test models to multiple operators of the AI ASIC chip to be tested on the AI ASIC chip test socket 10 one by one, so as to test whether the multiple operators of the AI ASIC chip to be tested are working properly.

[0042] In the above implementation, the operator test model can be a piece of operator test program written according to requirements, which is used to implement the function of operator function test. In an optional implementation, the data of the operator test model is downloaded to the control circuit 20 of the AI ASIC function test device through the host computer for operator test model verification. Different operator calculation programs are used to verify the calculation results of a single operator, and each operator module is verified. When the verification is successful, the "success" status can be fed back on the host computer, otherwise the "error" status is fed back. Through the above status, by downloading the verification programs of different operators, it is verified whether the functions of each arithmetic operator are normal.

[0043] In an embodiment of the present invention, new requirements are put forward for the test equipment of the AI ASIC chip, that is, to test the special functions of the AI ASIC chip, set up the test circuit, simulate the working environment of the AI ASIC chip by setting up the AI ASIC chip test socket 10, multiple power interfaces 30, and the control circuit 20, etc., connect multiple power interfaces 30 to power supply signals of various different voltages, and supply working power to multiple core working modules of the AI ASIC chip to be tested on the AI ASIC chip test socket 10, so as to test whether multiple core working modules of the AI ASIC chip to be tested can be powered on normally. The control circuit 20 obtains multiple operator test models and provides the operator test models to multiple operators of the AI ASIC chip to be tested on the AI ASIC chip test socket 10 one by one, so as to test whether multiple operators of the AI ASIC chip to be tested work normally. Through the above solution, the special functions of the AI ASIC chip, that is, the performance of multiple operators of the AI ASIC chip is tested one by one through the operator test model, so that the power-on situation of multiple core working modules of the AI ASIC chip and the calculation functions of the operators of multiple core working modules can be verified, and the computing power of each operator can be detected, thus solving the technical problem in the prior art that the special functions of the AI ASIC chip cannot be tested separately.

[0044] Moreover, the above AI ASIC chip test circuit is simple and the cost of the entire AI ASIC chip test circuit is low, which can conveniently verify whether each functional module of the AI ASIC chip works normally, and can also be used as a software development design and teaching platform.

[0045] It should be noted that the core working module refers to a hardware module with different functions, and the operator mentioned in this application refers to the computing unit in the operator test model running on the AI ASIC chip.

[0046] Among them, the power supply signals of different voltages can be voltage values such as 3.3V, 2.5V, 1.25V, 1.8V, 1.1V, etc., which are the voltages of the working power supply for the core working module.

[0047] In an embodiment, the AI ASIC chip test circuit further includes a power supply module 70. The power supply module 70 is respectively connected to multiple power interfaces 30, and supplies working power to multiple core working modules of the AI ASIC chip to be tested on the AI ASIC chip test socket 10 through the power interfaces 30.

[0048] Optionally, the control circuit 20 can be an FPGA controller. The control circuit 20 exchanges information with the AI ASIC chip test socket 10 through a 32-bit parallel interface, an 8-bit parallel interface, and a control and status interface. For example, it can output data to the AI ASIC chip to be tested through the 32-bit parallel interface, and can also obtain the processed data from the AI ASIC chip to be tested through the 8-bit parallel interface. It can also configure the basic environment of the relevant AI ASIC chip through the control and status interface.

[0049] In an alternative embodiment, the control circuit 20 is further configured to obtain a test model. The test model integrates the operations of multiple operators, and in accordance with the calculation order of the operators in the test model, sequentially inputs the calculations to be performed into the corresponding operators of the AI ASIC chip to be tested on the AI ASIC chip test socket 10 for calculation, so as to test whether the multiple operators of the AI ASIC chip to be tested are working properly.

[0050] Among them, based on the successful verification of each operator, that is, when the verification feedback of the operator test model to the host computer is in the "success" state, in this solution, the control circuit 20 downloads the test model integrating each operator from the host computer and outputs it to the AI ASIC chip to be tested for operation verification. When the verification is successful, the "success" state is feedback on the host computer, otherwise the "error" state is feedback. At this time, the number of operators that the test model can integrate can be designed as needed and the order of each operator position can be changed. Through the above solution, the cooperation degree between each operator can be tested to test the operation performance of the overall AI ASIC chip to be tested. That is, it can conveniently verify whether each functional module of the AI ASIC chip is working properly.

[0051] Optionally, referring to Figure 2 As shown, the control circuit 20 is further configured to obtain the configuration information of the AI ASIC chip to be tested, configure the corresponding register 80 of the AI ASIC chip to be tested on the AI ASIC chip test socket 10 according to the configuration information, and determine whether the configuration of the corresponding register 80 of the AI ASIC chip to be tested is successful based on the result feedback by the register 80 of the AI ASIC chip to be tested.

[0052] At this time, the configuration information can be reflected by a configuration program written by the user for containing the configuration information. By executing the configuration program, the configuration update of the configuration information is realized. The specific process is as follows:

[0053] The control circuit 20 downloads the configuration program of the AI ASIC chip from the host computer, and configures the relevant registers 80 in the AI ASIC chip to be tested through the SPI bus in the control and status interface. After the download is completed, the feedback information of the SPI bus can be used to test whether the configuration of the AI ASIC chip to be tested is successful. If the configuration is successful, the status result of "configuration successful" is fed back. At the same time, the corresponding indicator light is on, indicating that the configuration is successful. Through the above solution, the download of the configuration data of the AI ASIC chip to be tested is realized, and the various registers 80 of the AI ASIC chip to be tested are configured; it is verified whether each module unit in the AI ASIC chip to be tested can be correctly configured, and whether each functional module can work normally is verified by feeding back the status information.

[0054] Optionally, the model of the register 80 is DDR3.

[0055] Therefore, based on the above embodiments, during the configuration process of the register 80, the configuration information of the DDR3 driver can be verified, and the configuration of the DDR3 controller and the 4GB particles with a 32-bit width of DDR3 can be verified.

[0056] In an alternative embodiment, referring to Figure 2 As shown, the AI ASIC chip test circuit further includes a camera signal input interface 40 and an image format conversion circuit 50. The camera signal input interface 40 is connected to the control circuit 20 through the image format conversion circuit 50.

[0057] Among them, the camera signal input interface 40 acquires image data. The image format conversion circuit 50 converts the image data and outputs it as an image signal to the control circuit 20. The control circuit 20 outputs the image signal to the AI ASIC chip to be tested for model operation, and acquires the status result after the model operation output by the AI ASIC chip to be tested. The above process simulates the actual situation of image data of the AI ASIC chip to be tested, so that the processing effect of the AI ASIC chip to be tested can be tested through the above process.

[0058] Optionally, the image format conversion circuit 50 is an image serial-to-parallel chip.

[0059] In an alternative embodiment, referring to Figure 3 As shown, the AI ASIC chip test circuit further includes a plurality of indicator lights 60. An indicator light 60 is provided between each power supply interface 30 and the AI ASIC chip test socket 10. When there is current transfer between the connected power supply interface 30 and the AI ASIC chip test socket 10, the indicator light 60 lights up to confirm that the core working module of the AI ASIC chip connected to the power supply interface 30 is powered on normally.

[0060] Among them, when the AI ASIC chip to be tested is fixed in the AI ASIC chip test socket 10 for testing, the indicator lights 60 can be set one-to-one between each power supply interface 30 and the AI ASIC chip test socket 10. When there is current transmission in the corresponding path, that is, when there is a conductive path between the line where any power supply interface 30 is located and the tested AI ASIC chip, the indicator lights 60 on the same line are lit to confirm that the corresponding core working module of the AI ASIC chip to be tested can be powered on normally, so as to prompt the tester that the core working module of the AI ASIC chip to be tested corresponding to the current power supply interface 30 is powered on normally and subsequent test operations can be performed. When there is no current transmission between any power supply interface 30 and the AI ASIC chip test socket 10, the indicator lights 60 on the same line are extinguished to confirm that the corresponding core working module of the AI ASIC chip to be tested is not powered on normally, so as to prompt the tester that the corresponding core working module of the current AI ASIC chip to be tested cannot be powered on normally and needs to be repaired or returned to the factory for after-sales service. It should be noted that the indicator lights 60 can also be set in the power supply circuit of the power supply interface 30 and the corresponding core working module of the AI ASIC chip to be tested, and the indication function of normal or abnormal power supply access of the core working module of the AI ASIC chip to be tested can also be realized.

[0061] In the above embodiment, the indicator lights 60 can be realized by selecting various colors and various types of lights. Generally, LED lights are preferably used to facilitate small-volume fixed installation and save power.

[0062] The present application also proposes an AI ASIC chip test device, and the AI ASIC chip test device includes the above AI ASIC chip test circuit.

[0063] It should be noted that since the AI ASIC chip test device of the present application includes all the solutions of the above AI ASIC chip test circuit, therefore, the AI ASIC chip test device can also implement all the solutions of the AI ASIC chip test circuit and has the same beneficial effects, which will not be elaborated here.

[0064] The present application also proposes an AI ASIC chip test system. The AI ASIC chip test system includes a host computer and the above AI ASIC chip test circuit, and the control circuit 20 of the AI ASIC chip test circuit is connected to the host computer.

[0065] Among them, the host computer displays the test results of the AI ASIC chip test circuit.

[0066] It should be noted that since the AI ASIC chip test system of the present application includes all the solutions of the above-mentioned AI ASIC chip test circuit, the AI ASIC chip test system can also implement all the solutions of the AI ASIC chip test circuit and has the same beneficial effects, which will not be elaborated here.

[0067] Optionally, the AI ASIC chip test system further includes a camera and a power input circuit. The camera is connected to the camera signal input interface 40 of the AI ASIC chip test circuit, and the power input circuit is connected to the power circuit of the AI ASIC chip test circuit.

[0068] Among them, the camera collects image data, and the camera signal input interface 40 inputs the image data into the AI ASIC chip test circuit.

[0069] Based on the above embodiments, an SDI camera can be selected as the camera. After connecting the SDI camera, the FPGA controller receives 1080P image data, performs cropping and preprocessing, and then outputs it to the AI ASIC chip through a 32-bit parallel input interface for model operation. After the operation is completed, the result is transmitted to the FPGA controller through an 8-bit parallel interface. At the same time, the FPGA controller receives control commands and transmits status results, etc. to the FPGA controller. The FPGA controller transmits the data to the host computer through a USB3.0 interface. At this time, the test screen can be seen on the host computer, and the area of interest in the test screen can be marked and displayed. The host computer can download different test function codes (BIT streams) through the JTAG interface to configure the FPGA controller differently.

[0070] It should be noted that the power input circuit can be selected from various power circuits in the prior art. The power circuit can have function modules such as a clock, a reset, an LED, and a key.

[0071] The algorithms or displays provided herein are not inherently related to any specific computer, virtual system, or other device. In addition, the embodiments of the present invention are not directed to any specific programming language.

[0072] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that the embodiments of the present invention can be practiced without these specific details. Similarly, in order to streamline the present invention and assist in understanding one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present invention, the various features of the embodiments of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. Among them, the claims following the specific implementation manner are hereby expressly incorporated into the specific implementation manner, where each claim itself serves as a separate embodiment of the present invention.

[0073] Those skilled in the art can understand that the modules in the devices in the embodiments can be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive.

[0074] It should be noted that the above embodiments illustrate the present invention rather than limit the present invention, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim listing several devices, several of these devices can be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. An AI ASIC chip test circuit, characterized in that, The described AI ASIC chip test circuit includes: An AI ASIC chip test socket for fixing the AI ASIC chip to be tested. When the AI ASIC chip to be tested is fixed, the pins of the AI ASIC chip test socket are electrically connected to the pins of the AI ASIC chip one by one. Multiple power interfaces, electrically connected to the AI ASIC chip test socket, for accessing power supply signals of multiple different voltages and supplying working power to multiple core working modules of the AI ASIC chip to be tested on the AI ASIC chip test socket, so as to test whether the multiple core working modules of the AI ASIC chip to be tested can be powered on normally. A control circuit, electrically connected to the AI ASIC chip test socket, for obtaining multiple operator test models and providing the operator test models to multiple operators of the AI ASIC chip to be tested on the AI ASIC chip test socket one by one, so as to test whether the multiple operators of the AI ASIC chip to be tested are working normally.

2. The AI ASIC chip test circuit according to claim 1, wherein The control circuit is further used for: Obtaining a test model, which integrates the operations of multiple operators, and sequentially inputting the calculations to be performed into the corresponding operators of the AI ASIC chip to be tested on the AI ASIC chip test socket according to the calculation order of the operators in the test model for calculation, so as to test whether the multiple operators of the AI ASIC chip to be tested are working normally.

3. The AI ASIC chip test circuit according to claim 1, characterized in that The control circuit is further used for: Obtaining the configuration information of the AI ASIC chip to be tested, configuring the corresponding registers of the AI ASIC chip to be tested on the AI ASIC chip test socket according to the configuration information, and judging whether the configuration of the corresponding registers of the AI ASIC chip to be tested is successful through the results fed back by the registers of the AI ASIC chip to be tested.

4. The AI ASIC chip test circuit according to claim 3, characterized in that, The model of the register is DDR3.

5. The AI ASIC chip test circuit according to claim 1, characterized in that, The AI ASIC chip test circuit further includes a camera signal input interface and an image format conversion circuit. The camera signal input interface is connected to the control circuit through the image format conversion circuit. The camera signal input interface is used for obtaining image data. The image format conversion circuit is used for converting the format of the image data and outputting it as an image signal to the control circuit. The control circuit is used for outputting the image signal to the AI ASIC chip to be tested for model operation and obtaining the state result after the model operation output by the AI ASIC chip to be tested.

6. The AI ASIC chip test circuit according to claim 1, wherein, The AI ASIC chip test circuit further includes a power supply module, which is respectively connected to multiple power interfaces and supplies working power to multiple core working modules of the AI ASIC chip to be tested on the AI ASIC chip test socket through the power interfaces.

7. The AI ASIC chip test circuit according to claim 1, characterized in that, The AI ASIC chip test circuit further includes: Multiple indicator lights, each of which is provided between the power interface and the AI ASIC chip test socket; The indicator light lights up to confirm that the core working module of the AI ASIC chip to be tested connected to the power interface is normally powered on when there is current transfer between the connected power interface and the AI ASIC chip test socket.

8. An AI ASIC chip testing device, characterized in that, The AI ASIC chip test device includes the AI ASIC chip test circuit according to any one of claims 1-8.

9. An AI ASIC chip testing system, characterized in that, The AI ASIC chip test system includes a host computer and the AI ASIC chip test circuit according to any one of claims 1-8, and the control circuit of the AI ASIC chip test circuit is connected to the host computer; The host computer is used to display the test results of the AI ASIC chip test circuit.

10. The AI ASIC chip testing system according to claim 1, wherein The AI ASIC chip test system further includes a camera and a power input circuit, the camera is connected to the camera signal input interface of the AI ASIC chip test circuit, and the power input circuit is connected to the power circuit of the AI ASIC chip test circuit; The camera is used to collect the image data; The camera signal input interface is used to input the image data into the AI ASIC chip test circuit.

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