Myoelectricity control chip test circuit, device and system

Abstract

The embodiment of the invention relates to the technical field of chip testing, and discloses a myoelectricity control chip testing circuit, device and system.The myoelectricity control chip testing circuit comprises a myoelectricity control chip testing socket, a power interface, a first testing information end, a first control instruction access end and a multiplex testing signal output end; the first test information end accesses first test information to verify whether the register function of a core register of the myoelectric control chip to be tested is normal or not, the multiplex test signal output end outputs a first type of test signals to first type of peripheral verification equipment and outputs a second type of test signals to second peripheral verification equipment, and the multiplex test signal output end outputs the second type of test signals to the first type of peripheral verification equipment. And verifying whether the multiplexing function of the test signal output end is normal or not. According to the scheme, the special function of the myoelectricity control chip, namely the performance of outputting two signals through the multiplexing test signal output end, is tested, so that the technical problem that the special function of the myoelectricity control chip cannot be independently tested in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly to an electromyogram control chip testing circuit, device and system. Background Art

[0002] At present, most chip tests rely on some large-scale automatic test machines. By applying some specific excitations to the input / output pins of the chip, observing the returned values, and comparing them with the expected functions, it is determined whether the chip can work stably. However, some large-scale automatic test equipment is expensive, and it is difficult to have the conditions to build a test environment. At the same time, it is difficult to debug using conventional software, which greatly reduces the flexibility of the automatic test machine.

[0003] For electromyogram control chips, conventional test equipment can only perform conduction of some conventional pins and detection of conventional functions, and cannot detect the special functions of electromyogram control chips. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention provide an electromyogram control chip testing circuit, device and system, which are used to solve the technical problem that the special functions of electromyogram control chips cannot be tested separately.

[0005] According to one aspect of the embodiments of the present invention, an electromyogram control chip testing circuit is provided. The electromyogram control chip testing circuit includes:

[0006] An electromyogram control chip test socket for fixing the electromyogram control chip to be tested;

[0007] A power interface electrically connected to the electromyogram control chip test socket for accessing a power supply and supplying a working power supply to the electromyogram control chip test socket to test whether the electromyogram control chip to be tested can be normally powered on;

[0008] A first test information terminal electrically connected to the electromyogram control chip test socket for accessing first test information from a host computer and inputting the first test information into the electromyogram control chip to be tested for storage or reading to verify whether the storage function of the core register of the electromyogram control chip to be tested is normal;

[0009] A first control instruction access terminal electrically connected to the electromyogram control chip test socket for accessing a port multiplexing test instruction from a host computer;

[0010] The electromyogram control chip to be tested is used to output a first type of test signal and a second type of test signal according to the port multiplexing test instruction;

[0011] The multiplexed test signal output terminal is electrically connected to the myoelectric control chip test socket, and is used to output the first type of test signal to the first type of peripheral verification device and output the second type of test signal to the second peripheral verification device, so as to verify whether the multiplexing function of the test signal output terminal is normal.

[0012] In an optional manner, the myoelectric control chip test circuit further includes an indicator light, and the indicator light is arranged between the power interface and the myoelectric control chip test socket;

[0013] When there is current transmission between the power interface and the myoelectric control chip test socket, the indicator light lights up to confirm that the to-be-tested myoelectric control chip is normally powered on.

[0014] In an optional manner, the first control instruction access terminal is further used to access a first communication test instruction;

[0015] When the to-be-tested myoelectric control chip responds to the first communication test instruction through the myoelectric control chip test socket, it is confirmed that the communication function of the second test signal access terminal is normal;

[0016] When the to-be-tested myoelectric control chip does not respond or responds abnormally to the first communication test instruction through the myoelectric control chip test socket, it is confirmed that the communication function of the second test signal access terminal is abnormal.

[0017] In an optional manner, the myoelectric control chip test circuit further includes a myoelectric input port, and the myoelectric input port is electrically connected to the myoelectric control chip test socket;

[0018] The myoelectric input port is used to access myoelectric signals;

[0019] The first control instruction access terminal is further used to access a myoelectric amplification function test instruction;

[0020] The myoelectric amplification module of the to-be-tested myoelectric control chip is used to process the myoelectric signal according to the myoelectric amplification function test instruction to obtain a real-time myoelectric signal, and output it to the host computer;

[0021] The host computer is used to compare the real-time myoelectric signal with the expected signal to judge whether the function of the myoelectric amplification module of the to-be-tested myoelectric control chip is normal.

[0022] In an optional manner, the to-be-tested myoelectric control chip has a sampling module, and the sampling module is electrically connected to the myoelectric control chip test socket;

[0023] The myoelectric input port is used to access a sampling test signal;

[0024] The sampling module is configured to collect the sampling test signal to obtain a sampling signal and output it to the host computer;

[0025] The host computer is configured to compare the waveform of the sampling signal with the waveform of the sampling test signal to obtain the function and performance indexes of the sampling module.

[0026] In an alternative embodiment, the first type of test signal is a PWM signal, and the first type of peripheral verification device is an oscilloscope;

[0027] The multiplexed test signal output terminal is configured to convert the PWM signal into a PWM control signal and output it;

[0028] The oscilloscope is configured to compare the waveforms of the PWM signal and the PWM control signal to verify whether the PWM signal output function of the multiplexed test signal output terminal is normal.

[0029] In an alternative embodiment, the second type of test signal is an RS485 control signal, and the second type of peripheral verification device is an RS485 slave;

[0030] The multiplexed test signal output terminal is configured to convert the RS485 control signal into an RS485 working control signal and output it;

[0031] The RS485 slave is configured to receive the RS485 working control signal to verify whether the RS485 control signal output function of the multiplexed test signal output terminal is normal.

[0032] In an alternative embodiment, the first control instruction access terminal is further configured to access a third communication test instruction;

[0033] The myoelectric control chip to be tested is configured to output a corresponding third communication test signal to the first test information terminal according to the third communication test instruction;

[0034] The first test information terminal is configured to convert the third communication test signal into a third communication signal and output it to the host computer;

[0035] The host computer is configured to compare the level of the third communication signal with the level of the third communication test instruction to confirm whether the first test information terminal is working properly.

[0036] According to the second aspect of the present invention, the present invention further provides a myoelectric control chip testing device, and the myoelectric control chip testing device includes the myoelectric control chip testing circuit as described above.

[0037] According to a third aspect provided by the present invention, the present invention further provides an electromyogram (EMG) control chip test system, characterized in that the EMG control chip test system includes a host computer, a first type of peripheral verification device, a second peripheral verification device, and the EMG control chip test circuit as described above. A first test information terminal of the EMG control chip test circuit and a first control instruction access terminal of the EMG control chip test circuit are respectively connected to the host computer; a multiplexed test signal output terminal of the EMG control chip test circuit is respectively connected to the first type of peripheral verification device and the second peripheral verification device.

[0038] In an embodiment of the present invention, new requirements are proposed for the test equipment of the EMG control chip, that is, to test the working stability of the EMG control chip. The test circuit is set up. By setting interfaces such as an EMG control chip test socket, a power supply interface, a first test information terminal, a first control instruction access terminal, and a multiplexed test signal output terminal, the working environment of the EMG control chip is simulated. The first test information is accessed from the host computer through the first test information terminal, and the first test information is input into the EMG control chip to be tested for storage or reading, so as to verify whether the register function of the core register of the EMG control chip to be tested is normal. The multiplexed test signal output terminal outputs the first type of test signal to the first type of peripheral verification device and outputs the second type of test signal to the second peripheral verification device, so as to verify whether the multiplexing function of the test signal output terminal is normal. Thus, it can verify whether the conventional storage function of the EMG control chip and the multiplexing function of the test signal output terminal to be extended are normal, thereby solving the technical problem in the prior art that the special functions of the EMG control chip cannot be tested separately.

[0039] The above description is only an overview of the technical solution of the embodiment of the present invention. In order to be able to understand the technical means of the embodiment of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features, and advantages of the embodiment of the present invention more obvious and understandable, the following specifically illustrates the embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings are only used to illustrate the embodiments and are not considered as a limitation to the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0041] Figure 1 It shows a schematic block diagram of a first embodiment of the EMG control chip test circuit provided by the present invention;

[0042] Figure 2 It shows a schematic block diagram of a second embodiment of the EMG control chip test circuit provided by the present invention;

[0043] Figure 3The schematic diagram of the modules of the myoelectric control chip test system provided by the present invention is shown. Specific embodiments

[0044] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein.

[0045] The following analyzes the chip test device solutions in the prior art in combination with related technologies.

[0046] According to the chip design process, simulation is performed during design. Digital circuits usually use FPGAs for functional verification. However, due to the uncertainties in the production process, the instability of chip performance parameters may occur. After the chip is taped out, even if the tape-out manufacturer has conducted relevant tests, as the end-user, functional verification still needs to be carried out.

[0047] The test modes of chips generally include test modes such as scan, BIST, and input / output, and each mode has different test purposes. Currently, most chip tests rely on some large-scale automatic test machines. By applying some specific excitations to the input / output pins of the chip and observing the returned values, and comparing them with the expected functions, it is determined whether the chip can work stably. However, some large-scale automatic test equipment is expensive, and it is difficult to have the conditions to build a test environment; at the same time, it is difficult to debug using conventional software.

[0048] The above analysis proves that at the manufacturer's end, there is a unified chip test device for functional verification of chips, but when used by customers, there is a technical problem that there is a lack of a separate test device to test the special functions of each chip individually.

[0049] The present application provides a myoelectric control chip test circuit, device, and system, which can solve the technical problem in the prior art that the special functions of myoelectric control chips cannot be tested individually by setting up a dedicated test circuit and assisting with a method for testing the operating functions of myoelectric control chips.

[0050] In one embodiment, referring to Figure 1 and Figure 3As shown in the figure, the electromyogram (EMG) control chip test circuit includes an EMG control chip test socket 10, a power interface 50, a first test information terminal 20, a first control instruction access terminal 30, and a multiplexed test signal output terminal 40. The power interface 50 is electrically connected to the EMG control chip test socket 10, the first test information terminal 20 is electrically connected to the EMG control chip test socket 10, the first control instruction access terminal 30 is electrically connected to the EMG control chip test socket 10, and the multiplexed test signal output terminal 40 is electrically connected to the EMG control chip test socket 10.

[0051] Among them, the EMG control chip test socket 10 fixes the EMG control chip to be tested. The power interface 50 accesses the power supply and supplies the working power to the EMG control chip test socket 10 to test whether the EMG control chip to be tested can be powered on normally. The first test information terminal 20 accesses the first test information from the host computer 80 and inputs the first test information into the EMG control chip to be tested for storage or reading to verify whether the storage function of the core register of the EMG control chip to be tested is normal. The first control instruction access terminal 30 accesses the port multiplexing test instruction from the host computer 80, and the EMG control chip to be tested outputs a first type of test signal and a second type of test signal according to the port multiplexing test instruction. The multiplexed test signal output terminal 40 outputs the first type of test signal to the first type of peripheral verification device and outputs the second type of test signal to the second peripheral verification device to verify whether the multiplexing function of the test signal output terminal is normal.

[0052] In the embodiment of the present invention, new requirements are put forward for the test equipment of the EMG control chip, that is, to test the working stability of the EMG control chip. The test circuit is set up. By setting interfaces such as the EMG control chip test socket 10, the power interface 50, the first test information terminal 20, the first control instruction access terminal 30, and the multiplexed test signal output terminal 40, the working environment of the EMG control chip is simulated. The first test information terminal 20 accesses the first test information from the host computer 80 and inputs the first test information into the EMG control chip to be tested for storage or reading to verify whether the storage function of the core register of the EMG control chip to be tested is normal. The multiplexed test signal output terminal 40 outputs the first type of test signal to the first type of peripheral verification device and outputs the second type of test signal to the second peripheral verification device to verify whether the multiplexing function of the test signal output terminal is normal. Thus, the normal conventional storage function of the EMG control chip and the multiplexing function of the test signal output terminal to be expanded can be verified, and the technical problem in the prior art that the special functions of the EMG control chip cannot be tested separately is solved.

[0053] Optionally, based on the above embodiments, when the myoelectric control chip to be tested is fixed in the myoelectric control chip test socket 10 for testing, the power interface 50 is electrically connected to multiple power pins of the myoelectric control chip to be tested through the myoelectric control chip test socket 10, the first test information terminal 20 is electrically connected to the first test information pin of the myoelectric control chip to be tested through the myoelectric control chip test socket 10, the first control instruction access terminal 30 is electrically connected to the first control instruction access pin of the myoelectric control chip to be tested through the myoelectric control chip test socket 10, and the multiplexed test signal output terminal 40 is electrically connected to multiple multiplexed test signal output pins of the myoelectric control chip to be tested through the myoelectric control chip test socket 10.

[0054] Among them, taking EPC001 as an example, the multiple power pins of the myoelectric control chip may include at least one chip power pin MCU-VCC, the myoelectric amplification module power pin ADC-VCC, the sampling module power pin AFE-VCC, etc. The first test information pin of the myoelectric control chip to be tested may include pins of various interfaces such as the GOIO port that can access the first test information from the host computer 80, and the number thereof may be set to 1 or more. The first test information pin of the myoelectric control chip to be tested may include pins of serial ports such as the JTAG port and / or the RS232 interface that can perform serial signal transmission from the host computer 80. The multiple multiplexed test signal output pins of the myoelectric control chip to be tested may include multiplexed signal output pins such as MCU-PWM1, MCU-PWM2, MCU-PWM3, MCU-PWM4, MCU-PWM5, etc.

[0055] In an optional embodiment, the myoelectric control chip test circuit further includes an indicator light 60, and the indicator light 60 is disposed between the power interface 50 and the myoelectric control chip test socket 10.

[0056] Among them, when the myoelectric control chip to be tested is fixed in the myoelectric control chip test socket 10 for testing, when there is current transfer between the power interface 50 and the myoelectric control chip test socket 10, that is, when there is a conductive path between the power interface 50 and the tested myoelectric control chip, the indicator light 60 lights up to confirm that the myoelectric control chip to be tested is normally powered on, thereby prompting the tester that the myoelectric control chip to be tested is normally powered on and subsequent test operations can be performed. When there is no current transfer between the power interface 50 and the myoelectric control chip test socket 10, the indicator light 60 goes out to confirm that the myoelectric control chip to be tested is not normally powered on, thereby prompting the tester that the myoelectric control chip to be tested cannot be normally powered on and needs to be repaired or returned to the factory for after-sales service. It should be noted that the indicator light 60 can also be disposed in the power supply circuit of the power interface 50 and the myoelectric control chip to be tested, and the indication function of normal power access or abnormal power access can also be realized.

[0057] Optionally, the first control instruction access terminal 30 is also used to access a first communication test instruction. In this case, there are two test results:

[0058] In the first case, when the myoelectric control chip under test responds to the first communication test instruction through the myoelectric control chip test socket 10, it is confirmed that the communication function of the second test signal access terminal is normal. That is, when the data of the myoelectric control chip under test returned to the host computer 80 at this time is the information for replying the first communication test instruction, it proves that the current first control instruction access terminal 30 can receive and output instructions normally.

[0059] In the second case, when the myoelectric control chip under test does not respond or responds abnormally to the first communication test instruction through the myoelectric control chip test socket 10, it is confirmed that the communication function of the second test signal access terminal is abnormal. That is, when no information is returned to the host computer 80 at this time, it proves that the current first control instruction access terminal 30 cannot receive and output instructions normally.

[0060] Further, based on the above solution, the first communication test instruction can be a serial port test instruction. The host computer 80 inputs the first communication test instruction through the serial port. If the myoelectric control chip under test can reply to the first communication test instruction through the first control instruction access terminal 30, it can be verified that the communication function of the first control instruction access terminal 30 is normal, otherwise it is abnormal. Through the above solution, it can be verified whether multiple different serial ports of the myoelectric control chip under test can receive control instructions normally, and the response control instructions of the myoelectric control chip under test that execute the control instructions are transmitted back to the host computer 80. Thus, it is possible to quickly test each serial port of the chip only through the host computer 80, the test socket for fixing the myoelectric control chip under test, and the first control instruction access terminal 30 (serial port) to be tested, so as to ensure that each serial port can transmit data normally after testing.

[0061] In an optional embodiment, referring to Figure 2 as shown, the myoelectric control chip test circuit further includes a myoelectric input port 70, and the myoelectric input port 70 is electrically connected to the myoelectric control chip test socket 10.

[0062] Among them, the myoelectric input port 70 accesses a myoelectric signal; the first control instruction access terminal 30 is also used to access a myoelectric amplification function test instruction; the myoelectric amplification module of the myoelectric control chip under test processes the myoelectric signal according to the myoelectric amplification function test instruction to obtain a real-time myoelectric signal, and outputs it to the host computer 80. The host computer 80 compares the real-time myoelectric signal with the expected signal to determine whether the function of the myoelectric amplification module of the myoelectric control chip under test is normal.

[0063] In the above embodiments, the above test process is based on the electromyogram (EMG) control chip to be tested being fixed in the EMG control chip test socket 10 before the test. The function of the EMG amplification module of the EMG control chip to be tested can be detected in detail. Also, through different EMG amplification function test instructions, the amplification factor, working mode, output function, etc. of the EMG amplification module can be set, and other functions of the EMG amplification module can be tested, so as to realize the detection of the complete function and operating performance.

[0064] During the test process, the EMG amplification function test instruction can also be regarded as the MCU control EMG amplification module test function program. By means of the serial port control command, the MCU control EMG amplification module test function program can be entered, so that it is convenient to understand and repeatedly implement functions such as setting the amplification factor, working mode, output function, etc. of the EMG amplification module. At this time, the number of EMG input ports 70 can be set according to the need.

[0065] In an alternative embodiment, the EMG control chip to be tested has a sampling module, and the sampling module is electrically connected to the EMG control chip test socket 10.

[0066] Among them, the EMG input port 70 accesses the sampling test signal; the sampling module collects the sampling test signal to obtain a sampling signal and outputs it to the host computer 80. The host computer 80 compares the waveform of the sampling signal with the waveform of the sampling test signal to obtain the function and performance indicators of the sampling module.

[0067] When verifying this application, 8 EMG input ports 70 can be selected for testing. A sine wave signal with a frequency of 100 Hz and a Vpp amplitude of 1 mV is input in parallel to the 8 EMG input ports 70. The serial port output data is tested, and the digital signal is converted into the corresponding waveform to verify the ADC acquisition module of the MCU part and the function of the EMG amplification module; if the output signal is the expected signal, the ADC acquisition and the EMG amplification module function are normal, otherwise they are abnormal. Through different control commands, the amplification factor, working mode, output function, etc. of the EMG amplification module can be set, and other functions of the EMG amplification module can be tested.

[0068] In an alternative embodiment, the first type of test signal is a PWM signal, and the first type of peripheral verification device is an oscilloscope. The multiplexed test signal output terminal 40 is used to convert the PWM signal into a PWM control signal and then output it; the oscilloscope compares the waveforms of the PWM signal and the PWM control signal to verify whether the PWM signal output function of the multiplexed test signal output terminal 40 is normal. The first type of test signal can be regarded as entering the test PWM motor control function program. The test PWM motor control function program outputs the required PWM signal through the serial PWM control command, inputs this signal into the oscilloscope, and compares it with the theoretical waveform output by the corresponding control command. If they are the same, the PWM output function is normal. Optionally, for the 8-channel PWM motor control signal test: 1. Channel test, that is, the 8-channel PWM ports can normally output high level, low level, and PWM frequency output. 2. PWM performance test, PWM frequency output test from 1 to 20KHz, and duty cycle output test from 0 to 100% for each frequency. It should be noted that the function of the first type of peripheral verification device at this time can also be implemented by the host computer 80.

[0069] It should be noted that the multiplexed test signal output terminal 40 can be an 8-channel PWM motor control port or an I / O port with multiplexing function. At this time, the specific number of pins used can be set according to needs. When the multiplexed test signal output terminal 40 is not used as a PWM motor control, it can be used as a general I / O port. One of the major application directions of the electromyogram control chip is for prosthetic products. High-end prosthetic products can restore partial limb movement function, and in this case, the motor control function is required, and the commonly used motor control port is a PWM function control port. The multiplexed PWM motor control port function of this chip does not require an additional PWM control chip when controlling the motor output.

[0070] In an alternative embodiment, the second type of test signal is an RS485 control signal, and the second type of peripheral verification device is an RS485 slave.

[0071] Among them, the multiplexed test signal output terminal 40 converts the RS485 control signal into an RS485 working control signal and then outputs it; the RS485 slave receives the RS485 working control signal to verify whether the RS485 control signal output function of the multiplexed test signal output terminal 40 is normal. Among them, through the serial control command, enter the test RS485 communication function program, output the corresponding RS485 control signal through the serial RS485 control command, and connect it to an RS485 slave that is determined to be working properly. If the RS485 slave can normally receive the corresponding command signal, the RS485 communication function is normal, otherwise it is abnormal. It should be noted that the function of the second type of peripheral verification device at this time can also be implemented by the host computer 80.

[0072] Optionally, enter the test GPIO function program through the serial control command. Through the serial GPIO control command, test the signal level output by the corresponding GPIO interface. If it is consistent with the set level, the function of the GPIO interface is normal; if not, the function of the GPIO interface is abnormal.

[0073] In an optional embodiment, the first control instruction access terminal 30 is further configured to access a third communication test instruction. The myoelectric control chip to be tested outputs a corresponding third communication test signal to the first test information terminal 20 according to the third communication test instruction. The first test information terminal 20 converts the third communication test signal into a third communication signal and outputs it to the host computer 80. The host computer 80 compares the level of the third communication signal with the level of the third communication test instruction to confirm whether the first test information terminal 20 is working properly.

[0074] Optionally, enter the test GPIO function program through the serial control command. Through the serial GPIO control command, test the signal level output by the corresponding GPIO interface. If it is consistent with the set level, the function of the GPIO interface is normal; if not, the function of the GPIO interface is abnormal.

[0075] The present application also provides a myoelectric control chip testing device, which includes the above-mentioned myoelectric control chip testing circuit.

[0076] It should be noted that since the myoelectric control chip testing device of the present application includes all the solutions of the above-mentioned myoelectric control chip testing circuit, the myoelectric control chip testing device can also implement all the solutions of the myoelectric control chip testing circuit and has the same beneficial effects, which will not be elaborated here.

[0077] The present application also provides a myoelectric control chip testing system, which includes a host computer 80, a first type of peripheral verification device, a second peripheral verification device, and the above-mentioned myoelectric control chip testing circuit. The first test information terminal 20 of the myoelectric control chip testing circuit and the first control instruction access terminal 30 of the myoelectric control chip testing circuit are respectively connected to the host computer 80; the multiplexed test signal output terminal 40 of the myoelectric control chip testing circuit is respectively connected to the first type of peripheral verification device and the second peripheral verification device.

[0078] It should be noted that since the myoelectric control chip testing system of the present application includes all the solutions of the above-mentioned myoelectric control chip testing circuit, the myoelectric control chip testing system can also implement all the solutions of the myoelectric control chip testing circuit and has the same beneficial effects, which will not be elaborated here.

[0079] The algorithms or displays provided herein are not inherently related to any particular computer, virtual system, or other device. Additionally, embodiments of the present invention are not directed to any particular programming language.

[0080] In the specification provided herein, numerous specific details are set forth. However, it will be understood that embodiments of the present invention may be practiced without these specific details. Similarly, in order to streamline the present invention and assist in understanding one or more of the various inventive aspects, in the foregoing description of exemplary embodiments of the present invention, the various features of the embodiments of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. Among them, the claims following the specific implementation manner are hereby expressly incorporated into the specific implementation manner, where each claim itself serves as a separate embodiment of the present invention.

[0081] Those skilled in the art will appreciate that the modules in the devices in the embodiments can be adaptively changed and disposed in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into a single module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive.

[0082] It should be noted that the above embodiments illustrate the present invention rather than limit the present invention, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim listing several devices, several of these devices may be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. An electromyogram control chip test circuit, characterized in that The myoelectric control chip test circuit includes: A myoelectric control chip test socket for fixing the myoelectric control chip to be tested; A power interface electrically connected to the myoelectric control chip test socket, used to access a power supply and supply a working power supply to the myoelectric control chip test socket to test whether the myoelectric control chip to be tested can be powered on normally; A first test information terminal electrically connected to the myoelectric control chip test socket, used to access first test information from a host computer and input the first test information into the myoelectric control chip to be tested for storage or reading, so as to verify whether the register function of the core register of the myoelectric control chip to be tested is normal; A first control instruction access terminal electrically connected to the myoelectric control chip test socket, used to access a port multiplexing test instruction from a host computer; The myoelectric control chip to be tested is used to output a first type of test signal and a second type of test signal according to the port multiplexing test instruction; A multiplexing test signal output terminal electrically connected to the myoelectric control chip test socket, used to output the first type of test signal to a first type of peripheral verification device and output the second type of test signal to a second peripheral verification device, so as to verify whether the multiplexing function of the test signal output terminal is normal.

2. The electromyogram control chip test circuit according to claim 1, wherein The myoelectric control chip test circuit further includes an indicator light, and the indicator light is arranged between the power interface and the myoelectric control chip test socket; The indicator light lights up to confirm that the myoelectric control chip to be tested is powered on normally when there is current transmission between the power interface and the myoelectric control chip test socket.

3. The myoelectric control chip test circuit according to claim 1, wherein The first control instruction access terminal is further used to access a first communication test instruction; When the myoelectric control chip to be tested responds to the first communication test instruction through the myoelectric control chip test socket, it is confirmed that the communication function of the second test signal access terminal is normal; When the myoelectric control chip to be tested does not respond or fails to respond to the first communication test instruction normally through the myoelectric control chip test socket, it is confirmed that the communication function of the second test signal access terminal is abnormal.

4. The myoelectric control chip test circuit according to claim 1, wherein The myoelectric control chip test circuit further includes a myoelectric input port, and the myoelectric input port is electrically connected to the myoelectric control chip test socket; The myoelectric input port is used to access myoelectric signals; The first control instruction access terminal is further used to access a myoelectric amplification function test instruction; The myoelectric amplification module of the myoelectric control chip to be tested is used to process the myoelectric signal according to the myoelectric amplification function test instruction to obtain a real-time myoelectric signal and output it to the host computer; The host computer is used to compare the real-time myoelectric signal with an expected signal to judge whether the function of the myoelectric amplification module of the myoelectric control chip to be tested is normal.

5. The myoelectric control chip test circuit according to claim 4, characterized in that, The myoelectric control chip to be tested has a sampling module, and the sampling module is electrically connected to the myoelectric control chip test socket; The myoelectric input port is used to access a sampling test signal; The sampling module is used to collect the sampling test signal to obtain a sampling signal and output it to the host computer; The host computer is used to compare the waveform of the sampling signal with the waveform of the sampling test signal to obtain the function and performance indicators of the sampling module.

6. The electromyogram control chip test circuit according to claim 1, wherein The first type of test signal is a PWM signal, and the first type of peripheral verification device is an oscilloscope; The multiplexed test signal output terminal is used to convert the PWM signal into a PWM control signal and then output it; The oscilloscope is used to compare the waveforms of the PWM signal and the PWM control signal to verify whether the PWM signal output function of the multiplexed test signal output terminal is normal.

7. The electromyogram control chip test circuit according to claim 1, characterized in that The second type of test signal is an RS485 control signal, and the second type of peripheral verification device is an RS485 slave; The multiplexed test signal output terminal is used to convert the RS485 control signal into an RS485 working control signal and then output it; The RS485 slave is used to receive the RS485 working control signal to verify whether the RS485 control signal output function of the multiplexed test signal output terminal is normal.

8. The myoelectric control chip test circuit according to claim 1, wherein The first control instruction access terminal is further used to access a third communication test instruction; The myoelectric control chip to be tested is used to output a corresponding third communication test signal to the first test information terminal according to the third communication test instruction; The first test information terminal is used to convert the third communication test signal into a third communication signal and output it to the host computer; The host computer is used to compare the level of the third communication signal with the level of the third communication test instruction to confirm whether the first test information terminal works normally.

9. An electromyogram control chip testing device, characterized in that, The myoelectric control chip test device includes the myoelectric control chip test circuit according to any one of claims 1-8.

10. An electromyogram control chip testing system, characterized in that, The myoelectric control chip test system includes a host computer, a first type of peripheral verification device, a second peripheral verification device, and the myoelectric control chip test circuit according to any one of claims 1-8. The first test information terminal of the myoelectric control chip test circuit and the first control instruction access terminal of the myoelectric control chip test circuit are respectively connected to the host computer; the multiplexed test signal output terminal of the myoelectric control chip test circuit is respectively connected to the first type of peripheral verification device and the second type of peripheral verification device.

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