Manufacturing method of photonic integrated circuit chip and photonic integrated circuit chip

Abstract

The embodiment of the invention discloses a manufacturing method of a photon integrated circuit chip and the photon integrated circuit chip, and the manufacturing method of the photon integrated circuit chip comprises the steps: providing a substrate which comprises a buried oxide layer and a first silicon layer, and forming a first device structure and a second device structure through the first silicon layer; forming a polycrystalline silicon layer on the first silicon layer, wherein the polycrystalline silicon layer covers the surfaces of the first device structure and the second device structure; the polycrystalline silicon layer is etched to form a third device structure corresponding to the first device structure and a fourth device structure corresponding to the second device structure, and the third device structure and the fourth device structure are the same in thickness; a portion of the third device structure is removed such that a thickness of the third device structure is less than a thickness of the fourth device structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a manufacturing method of a photonic integrated circuit chip and a photonic integrated circuit chip. Background Art

[0002] For a photonic integrated circuit chip with a grating coupler, the grating thickness on the grating coupler directly affects the coupling efficiency and insertion loss of the grating coupler. The grating teeth of the grating can be used as the key structure for light coupling in the grating coupler. In some grating couplers, it may include an upper grating tooth and a lower grating tooth, and the thickness of the grating teeth affects the performance of the grating coupler.

[0003] On the other hand, devices such as an electro-optic modulator and a photodetector are usually further included in the photonic integrated circuit chip. The electro-optic modulator can be, for example, a silicon-insulator-silicon capacitive electro-optic modulator SISCAP. Summary of the Invention

[0004] The present invention provides a manufacturing method of a photonic integrated circuit chip and a photonic integrated circuit chip, aiming to effectively solve the problem that the coupling efficiency of the grating coupler on the photonic integrated circuit chip in the prior art is low, the insertion loss is large, and it affects the overall loss of the optical path.

[0005] According to a first aspect of the present invention, there is provided a manufacturing method of a photonic integrated circuit chip, including: the photonic integrated circuit chip includes a grating coupler and an electro-optic modulator, the grating coupler includes a first device structure and a third device structure, the electro-optic modulator includes a second device structure and a fourth device structure, and the method includes: providing a substrate, the substrate includes a buried oxide layer and a first silicon layer, and forming the first device structure and the second device structure by using the first silicon layer; forming a polysilicon layer on the first silicon layer, the polysilicon layer covering the surfaces of the first device structure and the second device structure; etching the polysilicon layer to respectively form a third device structure corresponding to the first device structure and a fourth device structure corresponding to the second device structure, wherein the third device structure and the fourth device structure have the same thickness; removing a part of the third device structure so that the thickness of the third device structure is less than the thickness of the fourth device structure.

[0006] Further, before removing a part of the third device structure, the method further includes: forming a planarization layer, the planarization layer covering the third device structure and the fourth device structure; etching the planarization layer to obtain a trench that partially penetrates the planarization layer in the thickness direction, wherein the end of the third device structure is exposed from the trench.

[0007] Further, the substrate is a silicon-on-insulator (SOI) substrate, and the substrate further includes a bottom silicon layer. The buried oxide layer and the first silicon layer are sequentially disposed on the bottom silicon layer.

[0008] Further, before forming the polysilicon layer, the method further includes: forming an insulating layer on the first silicon layer.

[0009] Further, the insulating layer between the second device structure and the fourth device structure is configured to be a part of the electro-optic modulator.

[0010] According to a second aspect of the present invention, there is provided a photonic integrated circuit chip, including: a grating coupler, the grating coupler including a first device structure and a third device structure sequentially disposed; and an electro-optic modulator, the electro-optic modulator including a second device structure and a fourth device structure sequentially disposed; wherein, the first device structure and the second device structure are fabricated based on a first silicon layer; the third device structure and the fourth device structure are fabricated based on a polysilicon layer; and the thickness of the third device structure is less than the thickness of the fourth device structure.

[0011] Further, the substrate of the photonic integrated circuit chip is a silicon-on-insulator (SOI) substrate, and the substrate includes a bottom silicon layer, a buried oxide layer, and the first silicon layer sequentially disposed.

[0012] Further, the grating coupler and the electro-optic modulator are spaced apart.

[0013] Further, the first device structure is configured as a planar waveguide and a plurality of first grating teeth spaced apart from each other formed on the planar waveguide, and the third device structure is configured as a plurality of second grating teeth corresponding to the first grating teeth; the second device structure is configured as a first capacitor portion, and the fourth device structure is configured as a second capacitor portion at least partially overlapping the first capacitor portion in the thickness direction. A part of the first capacitor portion, the second capacitor portion, and the second insulating layer sandwiched between the overlapping regions of the first capacitor portion and the second capacitor portion constitutes a capacitor structure, and the capacitor structure is used for modulating an optical signal.

[0014] Further, the first capacitor portion and the second capacitor portion have opposite conductivity types.

[0015] Further, the first capacitor portion includes a first region, a second region, and a third region doped with a first dopant, and the doping concentrations of the first region, the second region, and the third region increase in sequence; the second capacitor portion includes a fourth region, a fifth region, and a sixth region doped with a second dopant, and the doping concentrations of the fourth region, the fifth region, and the sixth region increase in sequence.

[0016] Furthermore, the projection of the first region in the thickness direction and the projection of the fourth region in the thickness direction at least partially overlap.

[0017] Furthermore, the first capacitive portion is of P-type conductivity type, and the second capacitive portion is of N-type conductivity type.

[0018] By one embodiment or multiple embodiments of the above embodiments in the present invention, at least the following technical effects can be achieved:

[0019] When the third device structure is the upper grating teeth of a grating coupler and the fourth device structure is a part of an electro-optic modulator, the third device structure and the fourth device structure are fabricated using the same polysilicon layer. Additionally, by removing a part of the third device structure to reduce its height, the thickness of the third device structure fabricated by the above manufacturing method is less than that of the fourth device structure, meeting the specific thickness requirements of the grating (grating teeth), enabling the thickness of the grating teeth to be adjusted to the thickness that maximizes the coupling efficiency of the grating coupler, thereby improving the performance of the grating coupler, and avoiding the complex processes required for separately depositing the third device structure and the fourth device structure with different thicknesses. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The technical solutions and other beneficial effects of the present invention will become apparent by describing the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0021] Figure 1 Schematic diagram of the structure of a photonic integrated circuit chip provided by an embodiment of the present invention;

[0022] Figure 2 Flowchart of the steps of a manufacturing method of a photonic integrated circuit chip provided by an embodiment of the present invention;

[0023] Figure 3 Schematic diagram of forming a first device structure and a second device structure provided by an embodiment of the present invention;

[0024] Figure 4 Schematic diagram of forming a planarization layer provided by an embodiment of the present invention;

[0025] Figure 5 Schematic diagram of forming a photoresist layer and exposing a target region provided by an embodiment of the present invention;

[0026] Figure 6 Schematic diagram of etching trenches partially penetrating the planarization layer in a target region provided by an embodiment of the present invention;

[0027] Figure 7 Schematic diagram of removing a part of the third device structure provided by an embodiment of the present invention;

[0028] The meanings of the reference numerals are as follows: 10 - substrate; 11 - bottom silicon; 12 - buried oxide layer; 13 - first silicon layer; 20 - insulating layer; 30 - planarization layer; 40 - photoresist; 100 - grating coupler; 110 - first device structure; 120 - third device structure; 200 - electro - optical modulator; 210 - second device structure; 220 - fourth device structure; 211 - first region; 212 - second region; 213 - third region; 221 - fourth region; 222 - fifth region; 223 - sixth region. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

[0030] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically and clearly defined.

[0031] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, an electrical connection, or a connection that can communicate with each other; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations. In this embodiment, the analog display screen touch unit is connected to the head tracking unit for obtaining the movement path of the induction cursor in the display device.

[0032] In this application, unless otherwise clearly specified or limited, the first feature being "on" or "under" the second feature may include direct contact between the first and second features, or may include contact between the first and second features not being direct but through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.

[0033] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0034] The inventor of the present invention has found that some semiconductor process methods can be adopted to manufacture a grating coupler and certain structures in an electro-optic modulator using the same material layer, so as to simplify the process flow. For example, by using the same material layer (such as a polysilicon layer), a partial grating tooth (upper grating tooth) of the grating coupler and a capacitor plate of a capacitive electro-optic modulator can be formed, which can simplify the process flow. At the same time, the inventor also found that using a deposition method to manufacture the above-mentioned partial grating teeth (upper grating teeth) and capacitor plates with the same thickness may not meet their respective optimal size requirements.

[0035] The present invention provides a photonic integrated circuit chip 1000, Figure 1 which shows a schematic structural diagram of the photonic integrated circuit chip 1000 in an embodiment of the present invention.

[0036] As Figure 1As shown, the above-mentioned photonic integrated circuit chip 1000 includes a grating coupler 100, and the grating coupler 100 includes a first device structure 110 and a third device structure 120 arranged in sequence; and an electro-optic modulator 200, and the electro-optic modulator 200 includes a second device structure 210 and a fourth device structure 220 arranged in sequence. Among them, the first device structure 110 and the second device structure 210 are fabricated based on a first silicon layer 13. Among them, the third device structure 120 and the fourth device structure 220 are fabricated based on a polysilicon layer. Exemplarily, the thickness of the third device structure 120 is less than the thickness of the fourth device structure 220.

[0037] In some embodiments, the photonic integrated circuit chip 1000 may be based on a semiconductor substrate 10, and the semiconductor substrate 10 may be a silicon-on-insulator (SOI) substrate. The semiconductor substrate 10 includes a bottom silicon layer 11, a buried oxide layer 12, and a first silicon layer 13 arranged in sequence.

[0038] In some embodiments, the first device structure 110 is configured as a planar waveguide and a plurality of first grating teeth (lower grating teeth) spaced apart from each other formed on the planar waveguide, and the third device structure 120 is configured as a plurality of second grating teeth (upper grating teeth) corresponding to the first grating teeth. Figure 1 The situation where the upper grating teeth and the lower grating teeth correspond one by one is shown. The first grating teeth and the second grating teeth constitute the grating tooth part of the grating coupler 100. Light can be coupled with the photonic integrated circuit chip through the grating tooth part, and the coupling efficiency is related to the thickness ha of the first grating teeth and the thickness hb of the second grating teeth.

[0039] The preset width of each first grating tooth and / or second grating tooth, and the preset interval distance between each first grating tooth and / or second grating tooth and the adjacent first grating tooth and / or second grating tooth are equal. The preset width and the preset interval distance have a preset duty cycle.

[0040] In some embodiments, the second device structure 210 is configured as a first capacitor part (also known as a first electrode plate), and the fourth device structure 220 is configured as a second capacitor part (also known as a second electrode plate) that at least partially overlaps the first capacitor part in the thickness direction. The first capacitor part, the second capacitor part, and a part 201 of the second insulating layer 20 sandwiched between the overlapping regions of the first capacitor part and the second capacitor part constitute the capacitor structure of the electro-optic modulator 200, and the capacitor structure is used to modulate the optical signal.

[0041] The first capacitor portion and the second capacitor portion have opposite conduction types. The opposite conduction types between the first capacitor portion and the second capacitor portion can be achieved through a doping process. That is, the first capacitor portion and the second capacitor portion are doped to exhibit opposite conduction types. The conduction types include P-type conduction type and N-type conduction type. In some embodiments, in order to make a certain capacitor portion exhibit an N-type conduction type, it can be doped with N-type impurities and P-type impurities simultaneously. Exemplarily, the concentration of the N-type impurities can be selected to be much greater than the concentration of the P-type impurities. In some other embodiments, in order to make a certain capacitor portion exhibit a P-type conduction type, it can be doped with N-type impurities and P-type impurities simultaneously. Exemplarily, the concentration of the N-type impurities can be selected to be much less than the concentration of the P-type impurities.

[0042] In some embodiments, the first capacitor portion can be doped to exhibit a P-type conduction type, and the second capacitor portion can be doped to exhibit an N-type conduction type.

[0043] In some embodiments, the first capacitor portion includes a first region 211, a second region 212, and a third region 213 doped with a first dopant, and the doping concentrations of the first region, the second region, and the third region increase in sequence. The second capacitor portion includes a fourth region 221, a fifth region 222, and a sixth region 223 doped with a second dopant, and the doping concentrations of the fourth region, the fifth region, and the sixth region increase in sequence.

[0044] In the first capacitor portion or the second capacitor portion, the first region and the second region with the lowest doping concentrations have semiconductor characteristics and are used to form the capacitor plates of the capacitor structure. The third region and the sixth region with the highest doping concentrations are used for metal connection with other devices to achieve ohmic contact. The second region with a doping concentration between the first region and the third region and the fifth region with a doping concentration between the fourth region and the sixth region play a transitional role.

[0045] In some embodiments, the projection of the first region 211 in the thickness direction and the projection of the fourth region 221 in the thickness direction overlap at least partially. As Figure 1 shown, the projection of the first region 211 in the thickness direction and the projection of the fourth region 221 in the thickness direction can completely overlap.

[0046] In some embodiments, the grating coupler 100 and the electro-optic modulator 200 are arranged at intervals.

[0047] The present invention also provides a manufacturing method for a photonic integrated circuit chip for preparing the photonic integrated circuit chip 1000 provided in each of the above embodiments. The photonic integrated circuit chip 1000 includes a grating coupler 100 and an electro-optic modulator 200. The grating coupler 100 includes a first device structure 110 and a third device structure 120, and the electro-optic modulator 200 includes a second device structure 210 and a fourth device structure 220. As Figure 2 shown, the above manufacturing method includes steps 101 to 104:

[0048] Step 101: Provide a semiconductor substrate 10, where the semiconductor substrate 10 includes a buried oxide layer 12 and a first silicon layer 13, and form the first device structure 110 and the second device structure 210 using the first silicon layer 13.

[0049] As Figure 3 shown, the semiconductor substrate 10 is a silicon-on-insulator (SOI) substrate 10, and the semiconductor substrate 10 further includes a bottom silicon layer 11. The buried oxide layer 12 and the first silicon layer 13 are sequentially disposed on the bottom silicon layer 11. The first device structure 110 and the second device structure 210 are formed on the first silicon layer 13 through processes such as etching, doping, and deposition.

[0050] Step 102: Form a polysilicon layer on the first silicon layer 13, and the polysilicon layer covers the surfaces of the first device structure 110 and the second device structure 210.

[0051] In some embodiments, before forming the polysilicon layer, the above method further includes: forming an insulating layer 20 on the first silicon layer 13. Specifically, the insulating layer 20 can be formed on the first silicon layer 13 by a deposition process, and the material of the insulating layer 20 can be a silicon dioxide material. The polysilicon layer is formed on the insulating silicon layer, and the polysilicon layer can be formed on the insulating layer 20 by a deposition process.

[0052] Step 103: Etch the polysilicon layer to respectively form a third device structure 120 corresponding to the first device structure 110 and a fourth device structure 220 corresponding to the second device structure 210, where the third device structure 120 and the fourth device structure 220 have the same thickness.

[0053] The insulating layer 20 between the second device structure 210 and the fourth device structure 220 is configured as a part of the electro-optic modulator 200.

[0054] Step 104: Remove a part of the third device structure 120 so that the thickness of the third device structure 120 is less than the thickness of the fourth device structure 220.

[0055] As Figure 4As shown, before removing a part of the third device structure 120, the above method further includes: forming a planarization layer 30 that covers the third device structure 120 and the fourth device structure 220. In some embodiments, the thickness of the planarization layer 30 is greater than the thickness of the polysilicon layer. Exemplarily, the material of the planarization layer 30 is an organic substance, and in the photon integrated circuit chip 1000, an anti-reflection coating can be used as the planarization layer 30.

[0056] After forming the planarization layer 30, etch the planarization layer 30 to obtain a trench that partially penetrates the planarization layer 30 in the thickness direction.

[0057] In some embodiments, as Figure 5 shown, the step of etching the planarization layer 30 to obtain a trench that partially penetrates the planarization layer 30 in the thickness direction may include: forming a photoresist layer 40, and patterning the photoresist layer 40 to expose a target area on the planarization layer 30, and the projection of the target area in the thickness direction overlaps with the opening projection of the trench. Etch the planarization layer 30 exposed through the target area to form a trench that partially penetrates the planarization layer 30 in the thickness direction.

[0058] As Figure 6 shown, the end of the third device structure 120 is exposed from the trench. As Figure 7 shown, thin the third device structure to remove a part of the third device structure 120 exposed on the bottom surface of the trench. Exemplarily, it further includes subsequently removing the planarization layer 30 to obtain the photon integrated circuit chip 1000 as shown in Figure 1 . By removing a part of the third device structure 120, the requirement of the grating for the third device structure 120 with a specific thickness is realized. Thus, the third device structure 120 of the grating coupler and the fourth device structure 220 of the electro-optic modulator are fabricated using the same polysilicon layer, and then by removing a part of the third device structure 120 to reduce its height, it adapts to the specific thickness requirement of the grating (grating teeth), and avoids the complex processes required for separately depositing the third device structure 120 and the fourth device structure 220 with different thicknesses.

[0059] In the above steps, the specific steps for depositing each layer can be designed according to actual needs, and the embodiments of the present application do not make specific limitations thereto. The specific steps for etching each layer can be designed according to actual needs, and the embodiments of the present application do not make specific limitations thereto. The specific steps for doping each layer can also be designed according to actual needs. Among them, the number of doping regions and the doping concentration and doping ions of each doping region can be determined according to actual needs.

[0060] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0061] In this text, specific examples are used to elaborate on the principles and implementation manners of the present application. The descriptions of the above embodiments are only used to help understand the technical solutions and their core ideas of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A manufacturing method of a photonic integrated circuit chip, characterized in that, The photon integrated circuit chip includes a grating coupler and an electro-optic modulator. The grating coupler includes a first device structure and a third device structure. The electro-optic modulator includes a second device structure and a fourth device structure. The method includes: Providing a substrate, the substrate includes a buried oxide layer and a first silicon layer, and forming the first device structure and the second device structure using the first silicon layer; Forming a polysilicon layer on the first silicon layer, the polysilicon layer covering the surfaces of the first device structure and the second device structure; Etching the polysilicon layer to respectively form a third device structure corresponding to the first device structure and a fourth device structure corresponding to the second device structure, wherein the third device structure and the fourth device structure have the same thickness; Removing a part of the third device structure such that the thickness of the third device structure is less than the thickness of the fourth device structure.

2. The manufacturing method according to claim 1, wherein Before removing a part of the third device structure, the method further includes: Forming a planarization layer, the planarization layer covering the third device structure and the fourth device structure; Etching the planarization layer to obtain a trench that partially penetrates the planarization layer in the thickness direction, wherein an end of the third device structure is exposed from the trench.

3. The manufacturing method according to claim 1, characterized in that, The substrate is a silicon-on-insulator (SOI) substrate, and the substrate further includes a bottom silicon layer, and the buried oxide layer and the first silicon layer are sequentially disposed on the bottom silicon layer.

4. The manufacturing method according to claim 1, characterized in that, Before forming the polysilicon layer, the method further includes: Forming an insulating layer on the first silicon layer.

5. The manufacturing method according to claim 4, characterized in that, The insulating layer between the second device structure and the fourth device structure is configured as a part of the electro-optic modulator.

6. A photonic integrated circuit chip, characterized in that, Including: A grating coupler, the grating coupler includes a first device structure and a third device structure sequentially disposed; And An electro-optic modulator, the electro-optic modulator includes a second device structure and a fourth device structure sequentially disposed; Wherein, the first device structure and the second device structure are manufactured based on a first silicon layer; The third device structure and the fourth device structure are manufactured based on a polysilicon layer; The thickness of the third device structure is less than the thickness of the fourth device structure.

7. The photonic integrated circuit chip according to claim 6, wherein The substrate of the photon integrated circuit chip is a silicon-on-insulator (SOI) substrate, and the substrate includes a bottom silicon layer, a buried oxide layer, and the first silicon layer sequentially disposed.

8. The photonic integrated circuit chip according to claim 6, wherein The grating coupler and the electro-optic modulator are spaced apart.

9. The photonic integrated circuit chip according to claim 6, wherein, The first device structure is configured as a planar waveguide and a plurality of spaced-apart first grating teeth formed on the planar waveguide, and the third device structure is configured as a plurality of second grating teeth corresponding to the first grating teeth; The second device structure is configured as a first capacitor portion, the fourth device structure is configured as a second capacitor portion that at least partially overlaps the first capacitor portion in the thickness direction, and a part of the first capacitor portion, the second capacitor portion, and a second insulating layer sandwiched between the overlapping regions of the first capacitor portion and the second capacitor portion constitute a capacitor structure, and the capacitor structure is used to modulate an optical signal.

10. The photonic integrated circuit chip according to claim 9, wherein, The first capacitor portion and the second capacitor portion have opposite conductivity types.

11. The photonic integrated circuit chip according to claim 9, characterized in that, The first capacitor portion includes a first region, a second region, and a third region doped with a first dopant, and the doping concentrations of the first region, the second region, and the third region increase in sequence. The second capacitor portion includes a fourth region, a fifth region, and a sixth region doped with a second dopant, and the doping concentrations of the fourth region, the fifth region, and the sixth region increase in sequence.

12. The photonic integrated circuit chip according to claim 11, wherein, The projection of the first region in the thickness direction and the projection of the fourth region in the thickness direction at least partially overlap.

13. The photonic integrated circuit chip according to claim 10, characterized in that, The first capacitor portion is of P-type conductivity, and the second capacitor portion is of N-type conductivity.

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