Mechanical alignment feature for glass waveguide to photonic integrated circuit mating

Abstract

An apparatus includes an optical interposer including a first surface, a first mating protrusion extending outwardly from the first surface, and two or more alignment protrusions extending outwardly from the first surface. The first mating protrusion is partially disposed within a first recess formed in a second surface of a photonic integrated circuit (PIC) die when the first surface of the optical interposer opposes the second surface of the PIC die and respective distal surfaces of the two or more alignment protrusions contact the second surface of the PIC die. A first portion of an outer surface of the first mating protrusion contacts a first sidewall of the first groove and a second portion of the outer surface of the first mating protrusion is opposite a second sidewall of the first groove such that a second space is defined between the second portion of the outer surface of the first mating protrusion and the second sidewall of the first groove.

Description

Background Art

[0001] Optical fiber cables (or fiber optic cables) can transmit information over long distances at high speeds via optical signals. For information carried by optical signals to be processed by electronic integrated circuit components, it is necessary to transmit the information from the photonic domain to the electrical domain. In some existing methods, this transmission can include transferring an optical signal from an optical fiber in a waveguide of a substrate to a waveguide in a photonic integrated circuit. The optical signal is converted into an electrical signal and transmitted to a processing unit or other components.

[0002] The passive mechanical mating between a glass substrate containing optical waveguides and a silicon-based photonic integrated circuit requires mechanical features with strict tolerances to achieve low-loss coupling. Typical alignment features on a silicon photonic integrated circuit can include V-grooves etched in the silicon to allow mechanical registration with corresponding waveguides in the substrate in both the vertical and lateral axes. However, the alignment features may suffer from dimensional variations, which can lead to undesirable levels of coupling loss. Therefore, alignment improvements are desired. Brief Description of the Drawings

[0003] Figure 1 is a top perspective view of a system having a photonic integrated circuit (PIC) and an optical interposer, where the optical interposer has exemplary alignment features.

[0004] Figure 2 is of Figure 1 the system without the optical interposer.

[0005] Figure 3 is Figure 1 the bottom perspective view of the optical interposer.

[0006] Figure 4 is Figure 1 the top plan view of the system.

[0007] Figure 5 is of Figure 2 the system without the optical interposer.

[0008] Figure 6 is Figure 2 the front view of the system.

[0009] Figure 7 is a cross-sectional view of Figure 5 the system taken along 7-7.

[0010] Figure 8 is a cross-sectional view of Figure 3 the optical interposer taken along 8-8.

[0011] Figure 9 is a cross-sectional view of Figure 4Cross-sectional view of the system.

[0012] Figure 10 Is a simplified flowchart of an example method for manufacturing a system including a PIC die and an optical interposer with example alignment and mating features.

[0013] Figure 11A and Figure 11B is part of a system at Figure 10 different stages of the method.

[0014] Figure 12A Is the first scatter-plot graph of a Monte Carlo analysis of mechanical misalignment between an optical interposer and a PIC die using a dual alignment scheme without lateral sliding of the optical interposer.

[0015] Figure 12B Is the second scatter-plot graph of a Monte Carlo analysis of mechanical misalignment between an optical interposer and a PIC die using a dual alignment scheme and performing lateral sliding of the optical interposer.

[0016] Figure 13 Is a line graph showing the excess optical coupling loss of waveguide-to-PIC die coupling for both a single alignment scheme and a dual alignment scheme.

[0017] Figure 14 Is a simplified diagram of an example system having multiple PIC dies and an optical interposer with alignment and mating features.

[0018] Figure 15 Is a simplified diagram of an example system having a PIC die, an optical interposer with alignment and mating features, and an optical plug.

[0019] Figure 16 Is a top view of a wafer and die that may be included in any microelectronic component or integrated circuit part disclosed herein.

[0020] Figure 17 Is a cross-section of an integrated circuit device that may be included in a microelectronic component or integrated circuit part according to any embodiment disclosed herein.

[0021] Figure 18 Is a cross-sectional side view of an integrated circuit device assembly that may be included in any microelectronic component or integrated circuit part disclosed herein.

[0022] Figure 19 Is a block diagram of an example electrical device that may include one or more of the microelectronic components or integrated circuit parts disclosed herein. Detailed Description

[0023] This disclosure relates to integrated circuit component packaging techniques that provide mechanical alignment features for waveguide-to-waveguide registration to achieve vertical and horizontal axis alignment. In various examples using the alignment features, an optical mediator is mated with a photonic integrated circuit (PIC) die. One or more waveguides are defined in the optical mediator and one or more waveguides are defined in the PIC die, and the optical mediator and the PIC die are mated such that the waveguides in the optical mediator are aligned with the waveguides in the PIC die, thereby allowing optical coupling between the optical mediator and the PIC die.

[0024] Typical systems that include components such as glass substrates with optical waveguides and silicon-based photonic integrated circuits typically use passive mechanical mating features to optically couple the components and align corresponding waveguides in the components. Passive mating features include anisotropically etched silicon features commonly used for mechanical registration between dies as they typically allow for the formation of angled planar structures such as V-grooves or inverted pyramids. Etching agents such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) are typically used to fabricate the etched structures, which preferentially etch along specific crystal planes such as the 111 crystal plane at a 54.74-degree angle in silicon. These structures can provide both lateral and vertical alignment; however, due to undercutting of the mask layer during the wet etching process, these structures suffer from undesired width variations. Size variations in these features can lead to undesired levels of coupling loss. These size variations typically result in a net vertical misalignment between the optical mediator and the PIC die, which coincides with the axis of maximum sensitivity in optical coupling efficiency due to asymmetries in the mode field of the PIC die spot size converter.

[0025] In some examples, glass mating features such as optical fibers or cylindrical protrusions on a glass waveguide mediator can be arranged such that the longitudinal axis of the mating feature (e.g., the cylinder axis) extends substantially parallel to the surface of the mediator, where the mating feature protrudes from the surface of the mediator. The glass mating feature (e.g., an optical fiber or cylindrical protrusion) can be received within a V-groove such that the mating feature abuts two angled sidewalls of the V-groove. Width variations in the V-groove of the PIC result in vertical alignment variations caused by the intersection of the chord of the cylinder that forms the contact points with the V-groove. The chord of the cylinder is defined by the Si crystal plane angle and the radius of curvature of the cylinder.

[0026] On the PIC side, mating structures such as silicon nitride (SiN)-based tapers typically have an asymmetric mode field shape due to manufacturing challenges in arbitrarily increasing the thickness of the SiN layer. Among them, the mode field of a typical edge-emitting taper structure can have an asymmetry ratio of 1.5:1 or greater. This asymmetric mode field results in increased sensitivity to misalignment in the Y-axis and X-axis, where Y is the major axis of misalignment due to changes in the V-groove width.

[0027] As disclosed herein, integrated circuit component packaging techniques with mechanical mating and alignment features can solve many of the above problems (and more). In one or more examples, separate sets of mechanical alignment features are used to facilitate waveguide-to-waveguide registration between optical components (e.g., PIC die and glass interposer). For lateral (also referred to herein as "horizontal") alignment, conventional etched features such as V-grooves or chamfered pyramids on the PIC die can be used, and their dimensions are designed to accommodate at least a portion of the mating protrusions provided on the lower surface of the optical interposer. However, for vertical alignment, standoff features such as alignment protrusions (also referred to herein as "bumps") are provided on the lower surface of the optical interposer to contact the top surface of the PIC die. This scheme effectively converts the major axis of misalignment from vertical to horizontal. This provides a significant optical coupling loss advantage, because a) typical edge couplers are less sensitive to misalignment on the horizontal axis, and b) the overall magnitude of misalignment is reduced.

[0028] Example mechanical alignment features can be provided to communicatively couple waveguides between various types of photonic integrated circuit (PIC) components associated with a computer system. PIC components that can utilize the mechanical alignment features disclosed herein include, but are not necessarily limited to, photonic integrated circuit (PIC) dies and optical interposers. The PIC die enables optical interconnection of processing units, memories, networking elements, storage elements, and other computer system components associated with computer processing functions and implemented in one or more integrated circuit dies. The optical interposer can include a solid structure (e.g., glass, ceramic, etc.) with waveguides. For example, the optical interposer includes, but is not necessarily limited to, edge couplers, optical couplers, etc. The optical interposer can be designed to transmit light between the PIC die and one or more optical plugs, optical fibers, lasers, photodiodes, micro light-emitting diodes (microLEDs), other transmitters, other receivers, other modulators, other switching elements, and / or other waveguides.

[0029] As disclosed herein, the use of alignment and mating features can provide several advantages. For example, existing manufacturing techniques can be utilized to achieve higher performance in optical components with lower optical losses. Due to the typically achieved more stringent manufacturing tolerances from the top surface of the PIC die to the optical waveguide, alignment protrusions can provide substantially better alignment accuracy. Since these features allow for a greater tolerance to component misalignment, the yield can be improved. The yield can be further improved since the total die area that needs to be defect-free is reduced. The reduced contact area between the mediator and the top surface of the PIC die allows for a reduction in the total die area that needs to be defect-free. This datum feature may reduce the channel-to-channel variation effect (multiple channel V-groove settings) since as few as two contact points define the relationship, where the channel-to-channel variation effect may cause a global tilt of the optical array. However, it should be noted that more than two contact points can be used to define the relationship. The use of a combination of alignment and mating features to provide better alignment accuracy, improved performance, and improved yield will become further apparent in the following description.

[0030] In the following description, specific details are set forth, but embodiments of the techniques described herein may be practiced without these specific details. Well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this specification. Phrases such as "an embodiment", "various embodiments", "some embodiments", "at least one embodiment", "one or more embodiments", etc. may include features, structures, or characteristics, but not every embodiment necessarily includes the specific features, structures, or characteristics.

[0031] Some embodiments may have some, all, or none of the features described for other embodiments. "First", "second", "third", etc. describe common objects and indicate different instances of the same object being referenced. Unless otherwise specifically stated, such adjectives do not imply that the objects so described must be in a given order in terms of time or space, in ranking, or in any other way. "Connected" may indicate that elements are in direct physical or electrical contact with each other, and "coupled" may indicate that elements cooperate, communicate, or interact with each other, but they may or may not be in direct physical or electrical contact. Additionally, as used with respect to embodiments of the present disclosure, the terms "comprising", "including", "having", etc. are synonymous.

[0032] As used herein, the phrase "optically coupled" refers to the interconnection of two or more components to facilitate the transmission of photon signals (e.g., optical signals) using light waves. For example, a PIC die can be optically coupled to an optical mediator. The PIC die can also be optically coupled via the optical mediator to another PIC die, a substrate, or other integrated circuit components in the same or different systems. The PIC die can also be optically coupled and / or electrically coupled to an integrated circuit die (e.g., a processing unit) via an electrical integrated circuit (EIC). As used herein, the phrase "communicatively coupled" refers to the direct or indirect interconnection of two or more components (e.g., having one or more intermediate components, mediators, traces, wirings, etc. between two components) to facilitate the transmission of photon signals (e.g., optical signals) using light waves, electrical signals using analog or digital signals, or any other type of signal that enables information to be transferred from one component to another.

[0033] Terms modified by the word "substantially" include arrangements, orientations, spacings, or positions that vary slightly from the meaning of the unmodified term. For example, an edge or surface of a PIC die or an optical mediator being substantially flush or coplanar with another surface or wall of a substrate or another component includes the edge of the PIC die being within the placement tolerance (e.g., 5 - 10 microns) for attaching an integrated circuit component to the substrate or another component. A substantially planar surface can include some surface roughness. A surface or sidewall that is substantially perpendicular to a wafer, substrate surface, die surface (e.g., the die surface of an IC, PIC, EIC, etc.) or another component surface (e.g., the component surface of an optical mediator) includes a surface or sidewall that deviates within 15 degrees from being perpendicular to the wafer, substrate surface, die surface, or other component surface. A surface or sidewall that is substantially parallel to a wafer, substrate surface, die surface (e.g., the die surface of an IC, PIC, EIC, etc.) or another component surface (e.g., the component surface of an optical mediator) includes a surface or sidewall that deviates within + / - 10 degrees from being parallel to the wafer, substrate surface, die surface, or other component surface. Additionally, the stated value of a dimension, feature, or property quantified by the term "about" includes values that deviate within + / - 10% of the stated value. Similarly, the stated range of values for a dimension, feature, or property includes values that deviate within 10% of the upper and lower limit values of the listed range. Further, it should be understood that in the examples further shown and described below, the drawings may not be drawn to scale and may not include all possible layers and / or circuit components.

[0034] Certain terms may also be used in this document for reference purposes only and are not intended to be limiting. For example, terms such as "upper", "lower", "above", "below", "bottom", and "top" refer to the directions in the referenced figures. Terms such as "front", "rear", "back", and "side" describe the orientation and / or position of parts of an integrated circuit component within a consistent but arbitrary reference system, which becomes clear by reference to the text describing the component in question and the associated figures. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0035] As used herein, the term "integrated circuit component" refers to a packaged or unpackaged integrated circuit product that includes at least one integrated circuit die and is mounted on a component substrate. A packaged integrated circuit component may or may not be encapsulated in a housing material, such as metal, plastic, glass, or ceramic. An integrated circuit component that includes multiple integrated circuit dies may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM). In one example, a packaged integrated circuit component includes two or more processor units (XPU), where corresponding electrical integrated circuits (EIC) and photonic integrated circuits (PIC) are arranged in a multi-die hierarchical structure mounted on a component substrate, and the outer surface of the component substrate includes a ball grid array (BGA) for connection to a socket. In one example of an unpackaged integrated circuit component, a single monolithic integrated circuit die includes solder bumps attached to conductive contacts on the die. The solder bumps allow the die to be directly attached to a printed circuit board. An integrated circuit component may include one or more of any of the computing system components described or referenced herein or any other computing system components, such as (but not necessarily limited to) processor units (e.g., system-on-a-chip (SoC), processor cores, graphics processing units (GPU), accelerators, chipset processors), I / O controllers, memories, memory controllers, or network interface controllers.

[0036] Reference is now made to the figures, which are not necessarily drawn to scale, where like or identical numbers may be used to represent like or similar parts in different figures. The use of like or identical numbers in different figures does not mean that all figures including those like or identical numbers constitute a single or identical embodiment. Like numbers with different letter suffixes may represent different instances of like components. The figures generally illustrate, by way of example and not limitation, the various embodiments discussed in the present disclosure.

[0037] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding thereof. It will be evident, however, that novel embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate description thereof. It is intended that all modifications, equivalents, and alternatives be included within the scope of the claims.

[0038] Referring Figure 1 , in one example, system 100 includes a substrate 108, a photonic integrated circuit (PIC) die 102 mounted on the substrate 108, and an optical mediator 104 that interfaces with the PIC die 102. Ends of one or more waveguides 106 (e.g., a waveguide array in this example) are exposed in an outward-facing surface 107 at one end of the optical mediator 104. The waveguides 106 extend through the body of the optical mediator 104 to the other end of the optical mediator (see Figure 3 ). The waveguides 106 are aligned with waveguides defined in an upper surface 114 of the PIC die 102 (see Figure 2 ), thereby allowing optical coupling between the optical mediator 104 and the PIC die 102. Waveguides 206 in the PIC die 102 may extend from a front portion of the PIC die 102 that couples to the optical mediator 104 to a rear end 113 of the PIC die 102 and may be disposed between outer sidewalls 112A and 112B. An optical plug may interface with the optical mediator 104, as described in more detail below with reference to Figure 14 and Figure 15 .

[0039] The illustrative optical mediator 104 can include glass, ceramic, or other suitable materials. In other embodiments, the optical mediator 104 can be made of any suitable material, which can be crystalline, non-crystalline, amorphous, etc., such as fused silica, borosilicate, sapphire, yttrium aluminum garnet, etc. Non-limiting examples of glass that the optical mediator 104 can comprise include any one or more of aluminosilicate, borosilicate, aluminoborosilicate, silica, and fused silica. The glass used in the optical mediator 104 can include any one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. The glass used in the optical mediator 104 can include silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. The optical mediator 104 can include at least 23% silicon by weight and at least 26% oxygen by weight. The optical mediator 104 can also include at least 5% aluminum by weight. The optical mediator 104 can have any suitable length or width, such as 1 - 500 millimeters. The optical mediator 104 can have any suitable thickness, such as 0.2 - 5 millimeters. The optical mediator 104 can also be referred to as an optical coupler, glass mediator, glass coupler, etc. In at least some examples, the substrate 108 can also include glass, ceramic, or other suitable materials as described above.

[0040] The optical mediator 104 can use the waveguide 106 defined in the optical mediator 104 to transmit light between the optical plug and the PIC die 102. The waveguide 106 can be routed in any suitable manner, including three-dimensional routing, thus allowing for a flexible layout. The optical mediator 104 can include optical elements, such as fan-outs, splitters, couplers, combiners, filters, etc.

[0041] The PIC die 102 can be made of any suitable material, such as silicon. In the illustrative embodiment, a waveguide 206 (see Figure 2 ) is defined in the PIC die 102, and the waveguide 206 docks with the waveguide 106 defined in the optical mediator 104 to transmit light to and from the PIC die 102. In the illustrative embodiment, the waveguide in the PIC die 102 can be a silicon waveguide embedded in a silica cladding. The PIC die 102 can include any suitable number of waveguides, including 1, 2, 3, ……, 1024 or more waveguides.

[0042] The PIC die 102 is configured to generate, detect, and / or manipulate light. The PIC die 102 may include active or passive optical components such as splitters, couplers, filters, optical amplifiers, lasers, photodetectors, modulators, etc. The PIC die 102 may have electrical connections to a substrate and / or an electrical integrated circuit (EIC) die, such as for power delivery, sending and receiving data, interconnecting and enabling communication between the PIC die and an integrated circuit (e.g., a central processing unit (CPU), a graphics processing unit (GPU), etc.).

[0043] The illustrative substrate 108 may be any suitable substrate, such as silicon, glass, ceramic, a circuit board, etc. In some embodiments, the substrate 108 is a circuit board made of any suitable material, such as ceramic, glass, and / or an organic-based material having glass fibers and resin, such as FR-4. The substrate 108 may have any suitable length or width, such as 10 - 500 millimeters. The substrate 108 may have any suitable thickness, such as 0.2 - 5 millimeters. In some examples, the substrate 108 may be a glass core substrate that includes a glass core having a thickness in the range of about 50 micrometers (also referred to herein as "microns" or "μm") to 1.4 millimeters (also referred to herein as "mm"). In other examples, the substrate 108 may include a multi-layer glass substrate (e.g., a coreless substrate) having a glass layer with a thickness in the range of about 25 micrometers to 50 micrometers. The glass core, the glass layer, or the entire substrate may have a thickness of about 10 mm to 250 mm (e.g., 10 mm × 10 mm to 250 mm × 250 mm). The glass core or glass layer of the substrate 108 may include a rectangular prism in which portions (e.g., vias) are removed and filled with other materials (e.g., metal or wiring).

[0044] In an illustrative embodiment, the system 100 is in a stage of manufacturing an integrated circuit package that will include the PIC die 102 and the optical mediator 104. As part of the packaged integrated circuit package, the PIC die 102 may be separated from the substrate 108. Reference is made below to Figure 11A and Figure 11B to describe an embodiment of an integrated circuit package including the PIC die 102 and the optical mediator 104 at different manufacturing stages. The system 100 may include additional components (not shown) at any suitable stage of the manufacturing process. Figure 1 not shown in

[0045] In Figure 2 is shown the system 100 without the optical mediator 104. Figure 2Shown are some structures of the PIC die 102 facilitating the mating of the optical interposer 104 with the PIC die 102. The PIC die 102 includes one or more grooves in the upper surface 114 that mate with structures in the optical interposer. In some examples, the PIC die 102 includes at least two grooves. In Figure 2 the example shown, the PIC die 102 includes grooves in the form of V-grooves in an array 202 of V-grooves formed in the upper surface 114. The array 202 of V-grooves in the PIC die 102 includes a series of alternating peaks 203 and valleys 204 defined by angled sidewalls 205A and 205B forming the V-grooves.

[0046] However, in other examples, one or more grooves in the PIC die 102 can have any suitable shape, including but not limited to rectangular grooves (e.g., horizontal cuboids), where the sidewalls of the groove are substantially perpendicular to the upper surface 114 of the PIC die 102, and the longer edges of the groove are substantially parallel to the upper surface 114 of the PIC die 102. In another example, one or more grooves in the PIC die 102 can have a three-dimensional square shape (e.g., cube) or a three-dimensional rectangular shape (e.g., vertical cuboid), where the sidewalls of each groove are substantially perpendicular to the upper surface 114 of the PIC die 102. For cuboid grooves, the longer edges can be substantially perpendicular to the upper surface 114 of the PIC die 102. If multiple cubes or cuboids are used, these grooves can be provided in an array form with some spacing or no spacing therebetween (e.g., a side-by-side form similar to the V-grooves in the V-groove array 202), or can be separately located in the upper surface 114 of the PIC die 102, or provided in a suitable combination thereof. The first ends of the sidewalls of the rectangular grooves, vertical cuboids, or cubes are connected to the upper surface 114, and the opposite ends of the sidewalls can be provided with square corners or rounded corners, and a generally planar surface therebetween. Alternatively, the opposite ends of the sidewalls can be provided with hemispherical, semi-conical, semi-cylindrical, or other curved surfaces therebetween.

[0047] In another example, one or more grooves in the PIC die 102 can be shaped as a frustum of a pyramid. One end of the sidewall intersects the upper surface 114, and the opposite end of the sidewall (e.g., the apex of the frustum of the pyramid) can have any suitable shape, including but not necessarily limited to a sharp, curved, or blunt (e.g., planar) shape, and if the apex is not sharp, the opposite end of the sidewall can be provided with an angled corner or a rounded corner. The base of the frustum of the pyramid can have any suitable shape, including but not limited to square, rectangular, triangular, hexagonal, etc. If multiple frustums of the pyramid are used, the frustums of the pyramid can be in the form of an array with some spacing or no spacing therebetween (e.g., a side-by-side form similar to the V-grooves in the V-groove array 202), or can be separately positioned in the upper surface 114 of the PIC die 102. For illustrative purposes, examples are shown and described herein with reference to the V-grooves in the V-groove array. However, it should be understood that any one of the V-grooves and V-groove arrays described herein can have alternative shapes (e.g., rectangular grooves, vertical cuboids, cylindrical grooves, frustums of a pyramid, cubes, etc.).

[0048] In an illustrative embodiment, a trench 210 is defined between the proximal end of the V-groove array 202 and the first end wall 216 of the PIC die 102, as Figure 2 shown. In at least one example, the trench 210 can optionally facilitate the placement of mechanical adhesives and / or refractive index matching materials. In an illustrative embodiment, the PIC die 102 includes only one trench 210. In other examples, the PIC die 102 can include one or more additional V-groove arrays, each additional V-groove array having peaks and valleys aligned with the peaks 203 and valleys 204 of the V-groove array 202, and wherein the trench separates each pair of adjacent V-groove arrays.

[0049] In an example, the V-groove array 202 has a pitch of about 160 microns and a depth of about 110 microns (i.e., the vertical distance between the peaks 203 and valleys 204). In other embodiments, for example, the V-groove array 202 can have any suitable pitch or depth, such as 30 microns to 500 microns.

[0050] In an example, the V-groove array 202, the trench 210, the first end wall 216, etc. are etched from the substrate of the PIC die 102, such as by using 2D and 3D lithography. In other embodiments, some or all of the V-groove array 202, the trench 210, the first end wall 216, etc. can be formed of another material, which is, for example, a material grown on or adhered to the PIC die 102.

[0051] Now refer to Figure 3, the optical interposer 104 includes a combination of registration features that minimize misalignment relative to the Y-axis and X-axis. The first registration feature includes a V-groove array 302 disposed on a substantially planar recessed surface 310 of the optical interposer 104, the surface 310 being recessed from the bottom surface 318 of the optical interposer 104. The V-groove array 302 includes alternating peaks 303 and valleys 304. The peaks 303 and valleys 304 define mating protrusions 305 that extend outward from the recessed surface 310 and enable the optical interposer 104 to mate with the PIC die 102 by at least partially receiving each mating protrusion 305 within a corresponding groove in the V-groove array 202 of the PIC die 102.

[0052] In this example, the waveguide 106 exposed at the end wall 316 of the optical interposer 104 extends through the optical interposer 104 to the outward-facing surface 107 of the optical interposer 104. When the optical interposer 104 mates with the PIC die 102, the waveguide 106 exposed at the end wall 316 of the optical interposer 104 aligns and engages with the waveguide 206 exposed at the end of the V-groove array 202 in the PIC die 102.

[0053] In the example, the distal ends of the mating protrusions 305 are generally cylindrical and each has a longitudinal axis substantially parallel to the recessed surface 310 of the optical interposer 104. Angled sides extend from opposite sides of the distal end to the recessed surface 310. In the example, the V-groove array 302 has a pitch of about 127 microns, 160 microns, or 250 microns. The depth of the V-groove array (i.e., the vertical distance between the peaks 303 and valleys 304) can be about 90 microns. In other embodiments, the V-groove array 302 can have any suitable pitch or depth, such as 30 - 500 microns. The vertical dimension (or height) of the mating protrusions 305 corresponds to the depth of the V-groove array 302.

[0054] It should be understood that many other shapes and various sizes can be utilized to form the mating protrusions 305. In one example, the distal end of the mating protrusion 305 can be generally trapezoidal in shape. In another example, the shape of the mating protrusion can be modified to dock with a specific shape of the groove in the PIC die 102 that houses the mating protrusion (e.g., rectangular groove, vertical cuboid, cube, chamfered pyramid, semi-cylindrical groove, etc.). However, the dimensions of the mating protrusions 305 can be designed to allow the mating protrusions 305 to be inserted into the grooves respectively without contacting the sidewalls of the grooves. After insertion, the mating protrusions 305 can be laterally moved until at least one mating protrusion 305 contacts one sidewall of the groove in which the mating protrusion is disposed. In some examples, the lateral movement causes some or all of the mating protrusions to each contact the sidewall of the corresponding groove in which the mating protrusion is disposed.

[0055] In an example, the optical mediator 104 includes inner sidewalls 312A and 312B of wings 308A and 308B, respectively. When the optical mediator 104 mates with the PIC die 102, at least a portion of the inner sidewalls 312A and 312B engages upper portions of outer sidewalls 112A and 112B of the PIC die 102, respectively. The inner sidewalls 112A and 112B can be bonded to the PIC die 102 using, for example, a mechanical adhesive. The optical mediator 104 further includes another inner wall 314 configured to engage an outer surface 214 of a first end wall 216 of the PIC die 102 and possibly an upper surface 215 of the first end wall 216. In at least some examples, a mechanical adhesive can be applied to some or all of the interfaces between respective surfaces and walls 312A, 312B, 314, and 316 of the optical mediator 104 and corresponding surfaces and walls of the PIC die 102. The mechanical adhesive can improve the mechanical attachment of the optical mediator 104 to the PIC die 102.

[0056] As Figure 3 shown, the second registration feature disposed on the optical mediator 104 includes two or more alignment protrusions extending outward from a recessed surface 310 of the optical mediator 104. In this example, four alignment protrusions 320A, 320B, 320C, and 320D are provided, with a pair of alignment protrusions disposed on each side of the V-groove array 302. In this example, the alignment protrusions each include a generally hemispherical distal surface and are disposed on the recessed surface 310 such that when the optical mediator 104 mates with the PIC die 102, at least a portion of the distal surface of the alignment protrusion contacts (e.g., abuts, touches, engages, etc.) an upper surface 114 of the PIC die 102. In some cases, the distal surface of the alignment protrusion can have other designs, including but not limited to a semi-conical shape, any other suitable curved shape, or a planar shape (e.g., circular, oval, square, rectangular, trapezoidal, etc.).

[0057] In an example, the vertical dimension (or height) of an alignment protrusion or a mating protrusion is measured along a line that is substantially perpendicular to the recessed surface 310. The vertical dimension of alignment protrusions 320A - 320D can be measured from the base of the alignment protrusion at the recessed surface 310 to the distal end of the alignment protrusion. The vertical dimension of a mating protrusion can be measured from the base of the mating protrusion at the recessed surface 310 to the peak of the mating protrusion. The vertical dimension of the mating protrusions in the V - groove array also corresponds to the depth of the V - groove array 302. In an example, when the distal - end surface (or its corresponding portion) of alignment protrusions 320A - 320D contacts the upper surface 114 of the PIC die 102, the vertical dimension of alignment protrusions 320A - 320D allows a space to be maintained between the recessed surface 310 of the optical interposer 104 and the upper surface 114 of the PIC die 102. Additionally, the vertical dimension of alignment protrusions 320A - 320D is less than the vertical dimension of mating protrusions 305. Thus, when the distal - end surface (or its corresponding portion) of alignment protrusions 320A - 320D contacts the upper surface 114 of the PIC die 102, the mating protrusions 305 are partially received in the corresponding grooves in the V - groove array 202 of the PIC die 102.

[0058] In other examples, the optical interposer can be provided with a smaller number (e.g., 2 or 3) or a larger number (e.g., 5, 6, or more) of alignment protrusions. In some cases, a single alignment protrusion can be provided on the optical interposer. For example, a single alignment protrusion having more than one contact point on the distal - end surface can be used. Examples include a distal - end surface having a substantially flat surface (e.g., square, rectangular, circular, etc.) or arrangement. For example, a plurality of cylinders having a central axis that is substantially parallel to the surface of the optical interposer can form a triangular protrusion, a rectangular protrusion, or other protrusions, where the cylinders project from the surface of the optical interposer.

[0059] Alignment protrusions 320A - 320D can be any suitable height that is less than the depth of the V - groove array 302 (and thus less than the height of mating protrusions 305) and allows at least a portion of the mating protrusions 305 to be partially received in the corresponding V - grooves in the V - groove array 202 of the PIC die 102. In an example, the alignment protrusions have a height such as 20 - 100 microns and a width such as 10 - 500 microns. In one particular example, the alignment protrusions are approximately 50 microns high and approximately 50 microns wide.

[0060] The upper surface 114 of the PIC die 102 is substantially planar and can provide tight geometric tolerances relative to the optical interposer 104. Alignment protrusions 320A - 320D are disposed on the optical interposer 104 to contact the upper surface 114 of the PIC die 102 (e.g., via the distal surfaces of the alignment protrusions 320A - 320D), which constrains the optical interposer 104 relative to the Y-axis. Additionally, mating protrusions 305 are partially received in and mate with anisotropic etch features (e.g., grooves such as the V-groove array 202, or other recesses or openings) in the upper surface 114 of the PIC die 102, which constrains the optical interposer 104 relative to the X-axis. Refer to Figure 9 , Figure 11A and Figure 11B for further description of the mating of the mating protrusions 305 with the corresponding grooves (or other recesses) formed in the PIC die 102.

[0061] The V-groove array 302 disposed in the optical interposer 104 provides one possible example of the mating protrusions 305, which can be used in combination with alignment protrusions such as alignment protrusions 320A - 320D to enable the optical interposer 104 to mate with the PIC die 102 and facilitate alignment of the waveguides 106 of the optical interposer 104 with the waveguides 206 of the PIC die 102. According to the present disclosure, many other possible designs and variations of the mating features can be used. For example, the mating protrusions can have alternative arrangements that are not arrays. In an example, the mating protrusions can have any suitable shape, such as a generally vertical cylinder, a generally horizontal cylinder, a bump, a rectangular prism, a cube, or any other suitable shape. Additionally, the waveguide 106 can not be routed through the mating protrusions 305, but can instead extend from another surface of the optical interposer 104 and pass through the optical interposer to another surface of the optical interposer 104 that mates with the PIC die 102.

[0062] In an illustrative embodiment, structures formed in the optical mediator 104, such as the V-groove array 302, the recessed surface 310, the sidewalls 312A - 312B, the inner wall 314, the alignment protrusions 320A - 320D, etc., are etched out from the substrate of the optical mediator 104. Any suitable etching process can be used, including anisotropic wet etching, dry etching, ion etching, etc. In some processes, one or more suitable chemicals can be used, including but not limited to hydrofluoric acid, nitric acid, sulfuric acid, phosphoric acid, acetic acid, water, or some suitable combination of two or more of the above. In one example, ultrashort pulse laser patterning can be used and then chemical etching can be used to pattern the structures of the optical mediator 104. However, other manufacturing techniques, such as laser ablation, hot embossing / molding, and / or three-dimensional (3D) printing, can be used. In other embodiments, some or all of the V-groove array 302, the recessed surface 310, the sidewalls 312A - 312B, the inner wall 314, the alignment protrusions 320A - 320D, etc., can be formed of another material, such as a material grown on or adhered to the optical mediator 104. The core of each waveguide is typically made of a material with a high refractive index, while the cladding surrounding the core has a low refractive index to confine light within the waveguide.

[0063] In one possible alternative embodiment, alignment protrusions can be formed on the first surface 114 of the PIC die 102. In this example, the alignment protrusions will extend outward from the first surface 114 of the PIC die 102. The alignment protrusions can be configured in the same or a similar manner as the alignment protrusions 320A - 320D provided on the optical mediator 104 and described herein, and can have the same or similar characteristics as the alignment protrusions 320A - 320D. In this example, when the optical mediator 104 is mounted on the PIC die 102, the distal surface (or its corresponding portion) of the alignment protrusions can contact the first surface 310 of the optical mediator 104.

[0064] Now referring to Figures 4 - 7 , various views of the system 100 are presented. Figure 4 A top plan view of the system 100 is shown, which includes a substrate 108, a PIC die 102 attached to the substrate 108, and an optical mediator 104 attached to the PIC die 102. Figure 5 A top plan view of the system 100 with the PIC die 102 and without the optical mediator 104 is shown. Figure 5 The V-groove array 202, the trench 210, and the first end wall 216 are shown. Figure 6 A front view of the system 100 with the PIC die 102 and without the optical mediator 104 is shown. Figure 6 The V-groove array 202 after the first end wall 216 and the trench 210 is shown.Figure 7 shows a cross-sectional view of system 100 with PIC die 102 and without optical interposer 104 taken along line 7-7 through trench 210 from the same perspective as shown in Figure 6 . Figure 5

[0065] Now referring to an example shown in Figure 8 and Figure 9 , a cross-sectional view of various parts of system 100 is presented. Figure 8 shows a cross-sectional view of the V-groove array 302 of optical interposer 104 and two alignment protrusions 320B and 320D taken along line 8-8 shown in Figure 3 . Since the other alignment protrusions 320A and 320C are respectively behind alignment protrusions 320B and 320D in the view shown in Figure 8 , the other alignment protrusions 320A and 320C are not visible in Figure 8 . In the example, the V-grooves in the V-groove array 302 on optical interposer 104 are rounder than the V-grooves in the V-groove array 202 of PIC die 102 shown in Figure 6 and Figure 7 . Figure 8 Also shown are the wings 308A and 308B of optical interposer 104, which can be bonded to the sidewalls 112A and 112B of PIC die 102 respectively using, for example, mechanical adhesives.

[0066] Figure 9 shows a cross-sectional view of system 100 including PIC die 102 and optical interposer 104. Figure 9 The cross-sectional view of system 100 in Figure 4 is taken along line 9-9 perpendicular to the V-grooves of the V-groove array 202 across trench 210. For clarity, Figure 9 the optional mechanical adhesives and refractive index matching materials are omitted in Figure 9 . The waveguides 106 in optical interposer 104 and the waveguides 206 in PIC die 102 are aligned and are labeled as waveguides 106 / 206 in

[0067] In Figure 9 ​In the view of the system 100 shown, alignment protrusions 320B and 320D are visible, while the other alignment protrusions 320A and 320C are respectively hidden behind alignment protrusions 320B and 320D. However, the alignment protrusions can be arranged on the optical mediator 104 in any number of other arrangements. In an example, at least one alignment protrusion is on one side of the V-groove array 302, and at least one alignment protrusion is on the opposite side of the V-groove array 302. In other examples, the alignment protrusions can be designed to have alignment protrusions only on one side of the V-groove array 302. In still other examples, the optical mediator 104 can have an alternative design, where the surface from which the alignment protrusions extend is opposite to other regions of the upper surface of the PIC die 102. The alignment protrusions can be arranged on such an optical mediator at any one or more positions spaced apart from the V-groove array 302 such that the alignment protrusions contact regions of the upper surface 114 of the PIC die 102 that are spaced apart from the V-groove array 202 in the PIC die 102.

[0068] In an example, the optical mediator is configured with a sufficient number of alignment protrusions to produce a plane that is substantially parallel to the recessed surface 310 of the optical mediator and such that a small gap 904 (e.g., space, region, etc.) can be produced and maintained when the distal surface (or its corresponding portion) of the alignment protrusion contacts the upper surface 114 of the PIC die 102. The alignment protrusions can have various designs, and these designs can affect the minimum number of alignment protrusions used on the optical mediator to produce the small gap 904. If the alignment protrusions 320A - 320D are shaped to have a distal surface that provides a point load (e.g., small surface area) for the optical mediator 104 on the PIC die 102, then three or more alignment protrusions can be provided on the optical mediator 104 to define a plane. If the alignment protrusions are shaped to provide a line load (e.g., larger surface area), then two or more alignment protrusions can be used. For example, the alignment protrusion (or the distal end of the alignment protrusion) can be shaped to have a cylindrical shape with a longitudinal axis that is substantially parallel to the upper surface 114. In this case, the alignment protrusion provides a line load, and thus two alignment protrusions may be sufficient to produce and maintain the gap 904 between the upper surface 114 of the PIC die 102 and the recessed surface 310 of the optical mediator 104. For any number of alignment protrusions, the distal surfaces of the alignment protrusions adopt a non-linear arrangement and define a plane that is substantially parallel to the optical mediator surface, where the alignment protrusions extend from the optical mediator surface. Additionally, for any alignment protrusion design, more than two alignment protrusions (in the case of a line load) or more than three alignment protrusions (in the case of a point load) can be provided.

[0069] As Figure 9As shown, at least a portion of the distal surface of alignment protrusions 320A - 320D contacts the upper surface 114 of the PIC die 102 such that a small gap 904 is maintained between the upper surface 114 of the PIC die 102 and the recessed surface 310 of the optical interposer 104. The height of alignment protrusions 320A - 320D corresponds to the size of the gap 904. Alignment protrusions 320A - 320D and thus the gap 904 can be less than the depth of the V - groove array 302 (and thus less than the height of the mating protrusions 305) and can be any suitable size that allows at least a portion of the mating protrusions 305 to be partially received in the corresponding V - grooves in the V - groove array 202 in the PIC die 102. The gap 904 (and thus the height of each alignment protrusion 320A - 320D) can be any suitable amount, such as 2 - 100 microns.

[0070] Generally, the mating protrusions 305 of the optical interposer 104 are smaller in diameter than the corresponding V - grooves in the (e.g., anisotropically etched) V - groove array 202 on the PIC die 102. This avoids the combined X - axis and Y - axis constraints from only the mating protrusions 305. As Figure 9 shown, the width of the valley 304 of each V - groove in the V - groove array 302 of the optical interposer 104 is wider than the peak 203 of the corresponding V - groove in the V - groove array 202 of the PIC die 102, allowing the peak 203 to be received in the corresponding V - groove in the V - groove array 302 of the optical interposer 104. Additionally, the width of the valley 204 of each V - groove in the V - groove array 202 of the PIC die 102 is wider than the peak 303 of the corresponding V - groove in the V - groove array 302 of the optical interposer 104, allowing the peak 303 to be received in the corresponding V - groove in the V - groove array 202 of the PIC die 102.

[0071] In an example, the mating protrusions 305 are smaller in diameter than the corresponding V - grooves in the V - groove array 202 to effect horizontal (or X - axis) alignment of the optical interposer 104 relative to the PIC die 102. Once the alignment protrusions contact the upper surface 114 of the PIC die 102 and the mating protrusions 305 are partially received in the corresponding V - grooves in the V - groove array 202 of the PIC die 102, the optical interposer 104 is laterally moved, such as by shifting or sliding, to mate the mating protrusions 305 with the anisotropically etched features (in this example, the V - grooves). This is shown at the contact point 906 in Figure 9 where a first portion of the outer surface of the mating protrusion 305 contacts (e.g., engages, abuts, touches, etc.) the angled sidewall 205A of the V - groove in the V - groove array 202. This results in a gap 908 (e.g., space, region, etc.) between another angled wall 205B and a second portion of the outer surface of the mating protrusion 305 that is opposite the another angled wall 205B (also in Figures 11A - 11Bas shown). It should be noted that the waveguide 206 of the PIC die 102 is adjusted to accommodate the left or right movement of the optical mediator 104 such that when the optical mediator 104 has moved and the mating protrusion 305 engages the corresponding V-groove in the V-groove array 202 of the PIC die 102, the waveguide 206 is aligned with the waveguide 106.

[0072] In an example, the height of the alignment protrusions 320A - 320D and the height of the mating protrusion 305 are such that another small gap 902 is maintained between the peak 303 of the mating protrusion 305 and the valley 204 of the V-groove in the V-groove array 202 of the PIC die 102. Such a gap 902 can reduce the sensitivity to foreign objects (such as dust) that may be trapped between the V-groove array 302 and the V-groove array 202. The gap 902 can be any suitable amount, such as 2 - 50 microns.

[0073] Reference Figure 10 and Figures 11A - 11B shows and describes an example method 1000 for manufacturing an integrated circuit package having an optical socket and having example alignment and mating features as disclosed herein. Figure 10 shows a flowchart of an example method 1000 for manufacturing an integrated circuit package having an optical socket and having example alignment and mating features as disclosed herein. Figures 11A - 11B is Figure 9 a cross-sectional view of a portion of the system 100 shown in

[0074] Method 1000 can be performed by a technician and / or by one or more automated machines. In some embodiments, one or more machines can be programmed to perform some or all of the activities in method 1000. Such machines can include, for example, a memory, a processor, a data storage device, etc. The memory and / or the data storage device can store instructions that, when executed by the machine, cause the machine to perform some or all of the activities of method 1000. Method 1000 can use any suitable set of techniques used in semiconductor processing, such as chemical vapor deposition, atomic layer deposition, physical layer deposition, molecular beam epitaxy, layer transfer, lithography, ion implantation, dry etching, wet etching, selective laser etching, heat treatment, flip chip, magnetron sputtering deposition, pulsed laser deposition, laser machining, 2D and / or 3D lithography, etc. It should be understood that method 1000 is merely an example of a method of an embodiment of a manufacturing system, and other methods can be used to manufacture any suitable embodiment of the system. In some examples, the activities of method 1000 can be performed in an order different from the order shown in the flowchart, or any one or more of the activities can be omitted or changed in any suitable manner to achieve the desired system. For clarity of description, method 1000 will be described with reference to system 100; however, as described herein, many variations and modifications of the specific features of system 100 are possible.

[0075] Method 1000 begins at 1002, where a PIC die 102 is formed. The PIC die 102 can include active or passive optical elements, such as splitters, couplers, filters, optical amplifiers, lasers, photodetectors, modulators, etc. The PIC die 102 can include electrical connections for connecting to a substrate and / or an EIC die, such as for power delivery, sending and receiving data, etc. In at least some examples, the EIC can be integrated with or communicatively coupled to an integrated circuit (e.g., a central processing unit (CPU), a graphics processing unit (GPU), an accelerator processing unit (APU), and any other processing unit (XPU)) to perform data processing functions. The PIC die 102 includes one or more waveguides defined in the PIC die 102. The PIC die 102 also includes one or more V-grooves (e.g., the V-grooves in the V-groove array 202) to facilitate the mating of the optical mediator 104 with the PIC die 102.

[0076] At 1004, an optical interposer 104 is formed. The optical interposer 104 can include one or more waveguides defined within the optical interposer 104. In an illustrative embodiment, the optical interposer 104 can be implemented as silica. In other embodiments, other glasses or other materials can be used, as described in more detail above. The waveguide 106 defined within the optical interposer 104 can be implemented as a direct-write waveguide, formed by applying a laser to the optical interposer 104 to modify the refractive index of a portion of the optical interposer 104. Structures such as alignment protrusions 320A - 320D and V-groove arrays 302 are formed in the optical interposer 104 using any suitable type of etching, laser, and / or lithography processes. In one non-limiting example, selective laser etching can be used to form the optical interposer 104. In another example, ultrashort pulse laser patterning can be used and then chemical etching can be used to pattern out the structure of the optical interposer. However, other manufacturing techniques such as laser ablation, hot embossing / molding, and / or 3D printing, such as a process based on multiphoton polymerization, can be used.

[0077] At 1006, the PIC die 102 is mounted on a substrate such as substrate 108.

[0078] At 1008, a suitable adhesive and / or refractive index matching material is deposited on the PIC die 102, the optical interposer 104, the substrate 108, or some suitable combination thereof. In one example, a mechanical adhesive can be applied over the entire V-groove array 302. Additionally or alternatively, a mechanical adhesive can be applied to the sidewalls 312A - 312B of the optical interposer 104.

[0079] At 1010, the optical interposer 104 is mounted on the PIC die 102. As Figure 11A shown, the optical interposer 104 can be positioned such that the alignment protrusions 320A - 320B contact a first region of the upper surface 114 of the PIC die 102 that is on one side of the V-groove array 202, and the alignment protrusions 320C - 320D contact a second region of the upper surface 114 of the PIC die 102 that is on the opposite side of the V-groove array 202. Additionally, as Figure 11AAs shown, the optical mediator 104 can be positioned such that the mating protrusions 305 are aligned with corresponding grooves in the PIC die 102, such as the V-grooves in the V-groove array 202. The positioning of the optical mediator 104 is such that when the alignment protrusions 320A - 320D contact the upper surface 114 of the PIC die 102, a gap 904 is created between the recessed surface 310 of the optical mediator 104 and the upper surface 114 of the PIC die 102, and each mating protrusion is partially disposed in a corresponding V-groove in the V-groove array 202 of the PIC die 102.

[0080] At 1012, the optical mediator 104 is laterally moved (e.g., slid, shifted, etc.) relative to the upper surface 114 of the PIC die 102 until at least one mating protrusion 305 contacts (e.g., abuts, touches, engages, etc.) the sidewall of the corresponding V-groove in the V-groove array 202. The Figure 11B movement or sliding / shifting action is shown therein. Based on the contact between the first portion of the outer surface of the mating protrusion 305 and the angled sidewall of the V-groove, this lateral movement effectively mates the optical mediator 104 with the PIC die 102 at the contact point 906. The lateral movement also aligns the waveguide 106 of the optical mediator 104 with the waveguide 206 of the PIC die 102. The placement of the waveguides in the PIC die 102 can be adjusted during manufacturing to account for the lateral movement of the optical mediator 104. For example, if the waveguides in the optical mediator 104 are disposed in the mating protrusions 305, during the formation of the PIC die 102, the corresponding waveguides at the ends of each V-groove in the PIC die 102 are shifted left or right (depending on the direction of movement of the optical mediator). This ensures that after the lateral movement of the optical mediator 104, the waveguides in the PIC die 102 are aligned with the waveguides in the optical mediator 104. In one example, the waveguides 206 and 106 are aligned to within one micron or less.

[0081] At 1014, the packaging of the integrated circuit components (e.g., PIC die 102, optical mediator 104, EIC die, XPU, etc.) is completed. The mechanical adhesive is cured. For example, the mechanical adhesive can be thermally cured while the optical mediator 104 is held in place relative to the PIC die 102. If there is a refractive index matching material, the refractive index matching material is also cured. For example, the refractive index matching material can be cured with ultraviolet light. The PIC die 102 and the optical mediator 104 can be removed from the substrate 108 and then integrated with another substrate, with an electronic integrated circuit die (EIC), with an XPU, etc.

[0082] By implementing the dual-feature alignment scheme as described herein, and in particular with reference to Figure 10 、 Figure 11A and Figure 11B, a typical main Y-axis misalignment is converted into an X-axis misalignment controlled by the width variation of the V-grooves in the V-groove array 202 of the PIC die 102. By using the dual alignment scheme during the assembly process together with the Figures 11A - 11B lateral sliding shown in, the resulting X-axis misalignment can be reduced by approximately a factor of two, where the mating protrusions contact only on one side of the V-groove structure.

[0083] Figure 12A and Figure 12B show scatter plot graphs 1200A and 1200B of Monte Carlo analyses of the mechanical misalignment between the optical mediator and the PIC die with and without lateral sliding using the dual feature alignment scheme disclosed herein, respectively. In Figure 12A , scatter plot 1210 shows an example scenario of misalignment variations on the X-axis and Y-axis when using the dual alignment scheme. Thus, scatter plot 1210 shows the misalignment of the waveguide when using alignment protrusions 320A - 320D to create a gap 904 between the upper surface 114 of the PIC die 102 and the recessed surface 310 of the optical mediator 104 and the mating protrusions 305 are partially disposed (but not laterally moved) in the corresponding V-grooves of the PIC die 102. The values 1212 along the Y-axis represent the possible Y-axis misalignment variations (in microns) of the waveguide. The values 1214 along the X-axis represent the possible X-axis misalignment variations (in microns) of the waveguide. As shown by scatter plot 1210 in scatter plot graph 1200A, the misalignment is mainly transferred to the X-axis, while a typical system without alignment protrusions mainly has misalignment on the Y-axis.

[0084] In Figure 12B , scatter plot 1220 shows an example scenario of misalignment variations on the X-axis and Y-axis when the dual alignment scheme is combined with the lateral sliding of the optical mediator 104 during assembly. Thus, scatter plot 1220 shows the misalignment of the waveguide when using alignment protrusions 320A - 320D to create a gap 904 between the upper surface 114 of the PIC die 102 and the recessed surface 310 of the optical mediator 104 and the mating protrusions 305 have been laterally moved to engage the sidewalls of the corresponding V-grooves of the PIC die 102. The values 1222 along the Y-axis represent the possible Y-axis misalignment variations (in microns) of the waveguide. The values 1224 along the X-axis represent the possible sliding X-axis misalignment variations (in microns) of the waveguide. As shown by scatter plot 1220 in scatter plot graph 1200B, the magnitude of the misalignment is significantly reduced, since the misalignment is mainly converted to the X-axis, which has a greater optical tolerance. Thus, the overall optical coupling loss between the PIC die 102 and the optical mediator 104 is significantly reduced.

[0085] Figure 13FIG. 1300 is a graph showing excess optical coupling loss varying due to misalignment-induced width variations of V-grooves or other anisotropic etch features on a silicon PIC die. The values 1314 along the X-axis represent possible X-axis V-groove width variations (in microns) of the waveguide, while the values 1312 along the Y-axis represent the excess optical coupling loss of the waveguide in decibels (dB). Graph 1300 shows the optical coupling loss for both a single alignment scheme and a dual alignment scheme. The single alignment scheme includes using mating protrusions that mate with corresponding V-grooves in the PIC die. The single alignment scheme does not include alignment protrusions. As shown by line 1306 for the single alignment scheme, when the single alignment scheme is used, the optical coupling loss increases significantly as the V-groove width variation increases.

[0086] During assembly, the dual alignment scheme uses mating protrusions (e.g., 305) and alignment protrusions (e.g., 320A - 320D) and lateral sliding. As shown by line 1308 for the dual alignment scheme, as the V-groove width variation increases, there is some optical coupling loss. However, this loss is less than the loss that occurs in the single alignment scheme as shown by line 1306.

[0087] An additional benefit of using the dual alignment scheme is that when performing co-optimization of the mode field diameters of the PIC die and the optical interposer waveguides, further loss advantages are possible. This is possible because it is much easier to increase the mode field diameter of the optical interposer along the X-axis than along the Y-axis. Additionally, a wider mode field diameter along the X-axis can achieve a significant increase in the tolerance to misalignment due to V-groove width variations.

[0088] Now referring Figure 14 , in one example, integrated circuit package 1400 includes one or more PIC dies 102, one or more optical interposers 104, substrate 1402, one or more optical sockets 1404, and an electrical integrated circuit (EIC) die 1406. In an illustrative embodiment, optical socket 1404 is formed by substrate 1402 and optical interposer 104. Optical interposer 104 has an outward-facing surface 107, and the ends of one or more waveguides 106 (shown in Figure 1 , Figure 3 ) are located in this outward-facing surface 107. When optical plug 1500 (see Figure 15 ) mates with optical socket 1404, the optical fibers of optical plug 1500 are aligned with waveguides 106 in optical interposer 104 to within a range of, for example, less than one micron.

[0089] In an illustrative embodiment, the optical receptacle 1404 is at least partially defined by a cavity 1418 defined in a substrate 1402. The illustrative cavity 1418 is cut all the way through the substrate 1402. The sidewalls of the cavity 1418 define rough lateral alignment features for an optical plug 1500. The optical plug 1500 can be roughly vertically aligned by a lid 1534 and another substrate 1532, as described in more detail below with reference to Figure 15 More specifically described.

[0090] The cavity 1418 can include a notch 1420 that serves as a latching feature. The notch 1420 extends further inward from the sidewall of the cavity 1418 into the substrate 1402. A protrusion 1530 of the optical plug 1500 can be locked into place in the notch 1420 to prevent the optical plug 1500 from being removed.

[0091] In an illustrative embodiment, the optical mediator 104 is positioned on a shelf 1416 that is slightly recessed from the top surface 1422 of the substrate 1402. The shelf 1416 can position the optical mediator 104 at a desired height relative to other components such as the substrate 1402, the lid 1534, the plug 1500, etc. The shelf 1416 can have any suitable depth, such as 0 - 250 microns.

[0092] In an illustrative embodiment, a photonic integrated circuit (PIC) die 102 mates with the optical mediator 104. In an illustrative embodiment, waveguides 106 in the optical mediator 104 can transmit light between the optical fibers of the optical plug 1500 and waveguides 206 ( Figure 2 shown therein) in the PIC die 102.

[0093] The substrate 1402 can support a number of additional integrated circuit dies 1410, which can be PIC dies, EIC dies, processing units, or a suitable combination thereof. The additional integrated circuit dies 1410 can facilitate communication, power delivery, and other suitable connections between the PIC die 102, the EIC die 1406, and a processing unit (which can be integrated with or separate from the EIC die 1406).

[0094] The illustrative substrate 1402 can be any suitable substrate, such as glass, silicon, ceramic, circuit board, etc. In some embodiments, the substrate 1402 is a circuit board made of any suitable material, such as ceramic, glass, and / or an organic-based material having glass fibers and resin, such as FR-4. In some embodiments, the substrate 1402 is formed of or otherwise includes a bismaleimide-triazine (BT) resin. The substrate 1402 can have any suitable length or width, such as 10 - 500 millimeters. The substrate 1402 can have any suitable thickness, such as 0.2 - 5 millimeters. The substrate 1402 can support additional components other than those shown in Figure 1 such as resistors, capacitors, other integrated circuit dies, power electronics devices, traces, etc.

[0095] The EIC die 1406 can include any suitable electronic integrated circuit package, such as resistors, capacitors, inductors, transistors, etc. The EIC die 1406 can include any suitable analog and / or digital circuits, such as processors, memories, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), etc. The EIC 1406 can be implemented as a central processing unit (CPU), a graphics processing unit (GPU), or any other processing unit (XPU), form part of a central processing unit (CPU), a graphics processing unit (GPU), or any other processing unit (XPU), be separate from and communicatively coupled to a central processing unit (CPU), a graphics processing unit (GPU), or any other processing unit (XPU), or include a central processing unit (CPU), a graphics processing unit (GPU), or any other processing unit (XPU). In some embodiments, the integrated circuit package 1400 can be implemented as a router, a switch, a network interface controller, etc. In such embodiments, the EIC die 1406 can include network interface controller circuitry to process, parse, route, etc., network packets transmitted and received by the integrated circuit package 1400 via the optical plug 1500.

[0096] Now referring to Figure 15, in one embodiment, the optical cable 1500 can be connected to the optical socket 1404 of the integrated circuit package 1400. The optical cable 1500 includes one or more optical fibers in a sheath 1506 that are connected to an optical plug 1502. A housing 1514 holds a ferrule holder and a ferrule that mate with the optical mediator 104. When the plug 1502 is inserted into the socket, a protrusion 1530 of a spring clip engages a notch 1420 of the socket 1404 to fix the optical plug 1502 in place. Pulling a tab 1520 of the retaining mechanism will pull the protrusion 1530 of the spring clip inward, thereby releasing the plug 1502 from the socket 1404.

[0097] The housing 1514 includes a notch 1524 that can be used not only for roughly aligning the plug 1502 but also serves as an orientation key to prevent the optical plug 1502 from being inserted upside down. The notch 1524 can mate with Figure 15 the rib 1540 shown in

[0098] The optical cable 1500 can include any suitable number of optical fibers, such as 1 - 32 optical fibers. The optical fibers can be arranged in a one - dimensional or two - dimensional array at the ferrule. Exemplary optical fibers are made of glass and can transmit light at any suitable wavelength, such as 400 - 2000 nanometers. In an illustrative embodiment, the optical fibers can support light in the C - band, O - band, L - band, S - band, etc. In other embodiments, the optical fibers can be made of different materials.

[0099] The optical plug 1502 can have any suitable size. In an illustrative embodiment, the optical plug 1502 has a width of approximately 5 millimeters and a height of approximately 1.5 millimeters. In other embodiments, the optical plug 1502 can have a height and / or width of, for example, 1 - 10 millimeters. The optical cable 1500 can have optical plugs at opposite ends, which can be similar to, the same as, or different from the optical plug 1502.

[0100] In one example, the integrated circuit component 1400 can be mounted on another component, such as a substrate 1532. The substrate 1532 can be, for example, a motherboard, another circuit board that connects the integrated circuit package 1400 to other components, a housing, etc. The substrate 1532 can be a material similar to or the same as the substrate 1402.

[0101] As Figure 15As shown, in use, the integrated circuit package 1400 can include a lid 1534. The lid 1534 can provide a rough alignment for the plug 1502. The lid 1534 can have ribs 1540 that form part of the socket 1404. The ribs 1540 can be aligned with notches 1524 defined in the optical plug 1502. The ribs 1540 and the notches 1524 can establish keying that prevents the optical plug 1502 from being inserted upside down.

[0102] Figure 16 is a top view of a wafer 1600 and dies 1602 that can be included in any of the microelectronic components or integrated circuit parts disclosed herein (e.g., any suitable die such as dies 102, 1406). The wafer 1600 can be composed of semiconductor material and can include one or more dies 1602 having integrated circuit structures formed on the surface of the wafer 1600. Each die 1602 can be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After the manufacture of the semiconductor product is complete, the wafer 1600 can undergo a singulation process in which the dies 1602 are separated from each other to provide discrete "chips" of the integrated circuit product. The die 1602 can be any processing unit disclosed herein. The die 1602 can be any one of dies 102, 1406 disclosed herein. The die 1602 can include one or more transistors (e.g., some of the transistors 1740 discussed below), support circuits for transmitting electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit parts. In some examples, the wafer 1600 or the die 1602 can include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive-bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices can be combined on a single die 1602. For example, a memory array formed by multiple memory devices can be formed on the same die 1602 as a processor unit or other logic configured to store information in the memory devices or execute instructions stored in the memory array. Die-to-wafer assembly techniques can be used to fabricate various microelectronic components among the microelectronic components disclosed herein, in which some dies 1602 are attached to a wafer 1600 that includes other dies among the dies 1602, and then the wafer 1600 is singulated. Figure 17 Some of the transistors in the transistor 1740), support circuits for transmitting electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit parts. In some examples, the wafer 1600 or the die 1602 can include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive-bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices can be combined on a single die 1602. For example, a memory array formed by multiple memory devices can be formed on the same die 1602 as a processor unit or other logic configured to store information in the memory devices or execute instructions stored in the memory array. Die-to-wafer assembly techniques can be used to fabricate various microelectronic components among the microelectronic components disclosed herein, in which some dies 1602 are attached to a wafer 1600 that includes other dies among the dies 1602, and then the wafer 1600 is singulated.

[0103] Figure 17is a cross-sectional view of an integrated circuit device 1700 that may be included in any microelectronic component or integrated circuit package 1400 disclosed herein (e.g., any die among die 102, 1406). One or more integrated circuit devices 1700 may be included in one or more dies 1602( Figure 16 ). The integrated circuit device 1700 may be formed on a die substrate 1702 (e.g., Figure 16 of the wafer 1600), and may be included in a die (e.g., Figure 16 of the die 1602). The die substrate 1702 may be a semiconductor substrate composed of a semiconductor material system, the semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). The die substrate 1702 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1702 may be formed using an alternative material that may or may not be combined with silicon, the alternative material including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as group II-VI, III-V, or IV may also be used to form the die substrate 1702. Although several examples of materials that may form the die substrate 1702 are described herein, any material that can serve as a basis for the integrated circuit device 1700 may be used. The die substrate 1702 may be a part of a single-cut die (e.g., Figure 16 of the die 1602) or a wafer (e.g., Figure 16 of the wafer 1600).

[0104] The integrated circuit device 1700 may include one or more device layers 1704 disposed on the die substrate 1702. The device layer 1704 may include features of one or more transistors 1740 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1702. The transistor 1740 may include, for example, one or more source and / or drain (S / D) regions 1720, a gate 1722 for controlling the current flow between the S / D regions 1720, and one or more S / D contacts 1724 for transmitting electrical signals to / from the S / D regions 1720. The transistor 1740 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. The transistor 1740 is not limited to Figure 17of the type and configuration shown, and can include a wide variety of other types and configurations, for example, by way of example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors, such as double-gate or triple-gate transistors, and surround or all-around gate transistors, such as nanoribbon, nanosheet, or nanowire transistors. Transistor 1740 can include a gate 1722 formed of at least two layers (gate dielectric and gate electrode). The gate dielectric can include a stack of one or more layers. The one or more layers can include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials.

[0105] High-k dielectric materials can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process can be performed on the gate dielectric to improve its quality.

[0106] The gate electrode can be formed on the gate dielectric and can include at least one p-type work function metal or n-type work function metal, depending on whether transistor 1740 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode can include a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, can be included for other purposes.

[0107] For PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment)

[0108] In some embodiments, when considered as a cross-section of the transistor 1740 along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1702 and two sidewall portions substantially perpendicular to the upper surface of the die substrate 1702. In other embodiments, at least one of the metal layers forming the gate electrode may be merely a planar layer substantially parallel to the upper surface of the die substrate 1702 and does not include sidewall portions substantially perpendicular to the upper surface of the die substrate 1702. In other embodiments, the gate electrode may include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0109] In some embodiments, a pair of sidewall spacers for surrounding the gate stack may be formed on opposite sides of the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. The processes for forming the sidewall spacers are well known in the art and typically include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used. For example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0110] The S / D regions 1720 may be formed within the die substrate 1702, adjacent to the gates 1722 of the individual transistors 1740. The S / D regions 1720 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1702 to form the S / D regions 1720. An annealing process may follow the ion implantation process to activate the dopants and cause them to further diffuse into the die substrate 1702. In the latter process, the die substrate 1702 may first be etched to form grooves at the locations of the S / D regions 1720. Then, an epitaxial deposition process may be performed to fill the grooves with the material for manufacturing the S / D regions 1720. In some embodiments, a silicon alloy such as silicon germanium or silicon carbide may be used to manufacture the S / D regions 1720. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials may be used to form the S / D regions 1720, such as germanium or III-V group materials or alloys. In further embodiments, one or more layers of metal and / or metal alloy may be used to form the S / D regions 1720.

[0111] One or more interconnect layers may be disposed on the device layer 1704 (at Figure 17shown as interconnect layers 1706-1710) transmit electrical signals such as power and / or input / output (I / O) signals to and / or from devices (e.g., transistor 1740) in device layer 1704. For example, conductive features (e.g., gate 1722 and S / D contacts 1724) in device layer 1704 can be electrically coupled to interconnect structures 1728 in interconnect layers 1706-1710. One or more of interconnect layers 1706-1710 can form metallization stack (also referred to as "ILD stack") 1719 of integrated circuit device 1700.

[0112] Interconnect structures 1728 can be arranged within interconnect layers 1706-1710 to transmit electrical signals according to various designs; in particular, the arrangement is not limited to Figure 17 the specific configuration of interconnect structures 1728 shown in. Although Figure 17 a specific number of interconnect layers 1706-1710 are shown in, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than those shown.

[0113] In some embodiments, interconnect structures 1728 can include lines 1728a and / or vias 1728b filled with a conductive material such as metal. Lines 1728a can be arranged to transmit electrical signals in a direction substantially parallel to the plane of the surface of die substrate 1702 on which device layer 1704 is formed. For example, from Figure 17 the perspective of, lines 1728a can transmit electrical signals in the direction into and out of the page and / or in the direction across the page. Vias 1728b can be arranged to transmit electrical signals in a direction substantially perpendicular to the plane of the surface of die substrate 1702 on which device layer 1704 is formed. In some embodiments, vias 1728b can electrically couple lines 1728a in different interconnect layers 1706-1710 together.

[0114] Interconnect layers 1706-1710 can include dielectric material 1726 disposed between interconnect structures 1728, as Figure 17As shown. In some embodiments, the dielectric material 1726 between the interconnect structures 1728 in different interconnect layers disposed in the interconnect layers 1706 - 1710 may have different compositions; in other embodiments, the composition of the dielectric material 1726 between different interconnect layers 1706 - 1710 may be the same. The device layer 1704 may also include a dielectric material 1726 disposed between the transistor 1740 and the bottom layer of the metallization stack. The dielectric material 1726 included in the device layer 1704 may have a different composition from the dielectric material 1726 included in the interconnect layers 1706 - 1710; in other embodiments, the composition of the dielectric material 1726 in the device layer 1704 may be the same as the dielectric material 1726 in any one of the interconnect layers included in the interconnect layers 1706 - 1710.

[0115] The first interconnect layer 1706 (referred to as Metal 1 or "M1") may be directly formed on the device layer 1704. In some embodiments, the first interconnect layer 1706 may include lines 1728a and / or vias 1728b, as shown. The lines 1728a of the first interconnect layer 1706 may be coupled to the contacts (e.g., S / D contacts 1724) of the device layer 1704. The vias 1728b of the first interconnect layer 1706 may be coupled to the lines 1728a of the second interconnect layer 1708.

[0116] The second interconnect layer 1708 (referred to as Metal 2 or "M2") may be directly formed on the first interconnect layer 1706. In some embodiments, the second interconnect layer 1708 may include vias 1728b to couple the lines 1728a of the second interconnect layer 1708 to the lines 1728a of the third interconnect layer 1710. Although, for clarity, the lines 1728a and vias 1728b are structurally defined by the lines within each interconnect layer, in some embodiments, the lines 1728a and vias 1728b may be structurally and / or materially continuous (e.g., simultaneously filled during a dual - damascene process).

[0117] According to similar techniques and configurations described in connection with the second interconnect layer 1708 or the first interconnect layer 1706, a third interconnect layer 1710 (referred to as Metal 3 or "M3") (and additional interconnect layers as needed) may be successively formed on the second interconnect layer 1708. In some embodiments, the "higher" (i.e., further from the device layer 1704) interconnect layers in the metallization stack 1719 of the integrated circuit device 1700 may be thicker than the lower interconnect layers in the metallization stack 1719, where the lines 1728a and vias 1728b in the higher interconnect layers are thicker than the lines and vias in the lower interconnect layers.

[0118] The integrated circuit device 1700 may include a solder mask material 1734 (e.g., polyimide or a similar material) and one or more conductive contacts 1736 formed on the interconnect layers 1706 - 1710. In Figure 17 , the conductive contacts 1736 are shown in the form of bond pads. The conductive contacts 1736 may be electrically coupled to the interconnect structure 1728 and configured to transmit electrical signals of one or more transistors 1740 to an external device. For example, solder joints may be formed on one or more conductive contacts 1736 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 1700 to another component (e.g., a printed circuit board). The integrated circuit device 1700 may include additional or alternative structures to transmit electrical signals from the interconnect layers 1706 - 1710; for example, the conductive contacts 1736 may include other similar features (e.g., pillars) for transmitting electrical signals to an external component.

[0119] In some embodiments where the integrated circuit device 1700 is a double - sided die, the integrated circuit device 1700 may include another metallization stack (not shown) on the opposite side of one or more device layers 1704. The metallization stack may include a plurality of interconnect layers as discussed above with reference to the interconnect layers 1706 - 1710 to provide a conductive path (e.g., including conductive lines and vias) between one or more device layers 1704 and additional conductive contacts (not shown) on the side of the integrated circuit device 1700 opposite the conductive contacts 1736.

[0120] In other embodiments where the integrated circuit device 1700 is a double - sided die, the integrated circuit device 1700 may include one or more through - silicon vias (TSVs) passing through the die substrate 1702; these TSVs may contact one or more device layers 1704 and may provide a conductive path between one or more device layers 1704 and additional conductive contacts (not shown) on the side of the integrated circuit device 1700 opposite the conductive contacts 1736. In some embodiments, the TSVs extending through the substrate may be used to transmit power and ground signals from the conductive contacts on the side of the integrated circuit device 1700 opposite the conductive contacts 1736 to the transistors 1740 and any other components integrated into the die 1700, and the metallization stack 1719 may be used to transmit I / O signals from the conductive contacts 1736 to the transistors 1740 and any other components integrated into the die 1700.

[0121] Multiple integrated circuit devices 1700 may be stacked with one or more TSVs in respective stacked devices to provide connections between one of the devices in the stack and any other device. For example, one or more high bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and the TSVs in the HBM die may provide connections between individual HBMs and the base integrated circuit die. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine pitch solder bumps (microbumps).

[0122] Figure 18 is a cross-sectional side of an integrated circuit device assembly 1800, which may include any of the microelectronic components or integrated circuit parts disclosed herein (e.g., any one of dies 102, 1406, optical intermediary 104). The integrated circuit device assembly 1800 includes a plurality of components disposed on a circuit board 1802, which may be a motherboard, a system board, a main board, etc. The integrated circuit device assembly 1800 includes components disposed on a first side 1840 of the circuit board 1802 and on an opposite second side 1842 of the circuit board 1802; generally, components may be disposed on one or both of sides 1840 and 1842. Any integrated circuit part discussed below with reference to the integrated circuit device assembly 1800 may take the form of any suitable embodiment of the microelectronic components disclosed herein.

[0123] In some embodiments, the circuit board 1802 may be a printed circuit board (PCB) including a plurality of metal (or interconnect) layers separated from each other by dielectric material layers and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to convey electrical signals (optionally in combination with other metal layers) between components coupled to the circuit board 1802. In other embodiments, the circuit board 1802 may be a non-PCB substrate. In some embodiments, the circuit board 1802 may be, for example, an integrated circuit component substrate (e.g., 1702) or a circuit board 1802 attached to a socket. Figure 18 The integrated circuit device assembly 1800 shown in includes a package-on-interposer structure 1836 coupled to the first side 1840 of the circuit board 1802 by a coupling component 1816. The coupling component 1816 may electrically and mechanically couple the package-on-interposer structure 1836 to the circuit board 1802 and may include solder balls, such as Figure 18as shown), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), protruding and recessed portions of a socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. When appropriate, coupling component 1816 can be used as the coupling component shown or described for any of the substrate assemblies or substrate assembly components described herein.

[0124] The encapsulation structure 1836 on the interposer can include an integrated circuit component 1820 coupled to the interposer 1804 through a coupling component 1818. The coupling component 1818 can take any form suitable for the application, such as the form discussed above with reference to the coupling component 1816. Although Figure 18 a single integrated circuit component 1820 is shown, multiple integrated circuit components can be coupled to the interposer 1804; in fact, additional interposers can be coupled to the interposer 1804. The interposer 1804 can provide an intermediate substrate for bridging the circuit board 1802 and the integrated circuit component 1820.

[0125] The integrated circuit component 1820 can be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (e.g., Figure 16 die 1602, Figure 17 integrated circuit device 1700) and / or one or more other suitable components. A packaged integrated circuit component includes one or more integrated circuit dies mounted on a component substrate, where the integrated circuit die and the component substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component 1820, a single monolithic integrated circuit die includes solder bumps attached to the contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1804. The integrated circuit component 1820 can include one or more computing system components, such as one or more processor units (e.g., system on a chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller. In some embodiments, the integrated circuit component 1820 can include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0126] In embodiments where the integrated circuit component 1820 includes multiple integrated circuit dies, the dies can be of the same type (homogeneous multi-die integrated circuit component) or two or more different types (heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0127] In addition to including one or more processor units, the integrated circuit component 1820 may include additional components, such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die including the processor unit. These separate integrated circuit dies may be referred to as "dielets". In embodiments where the integrated circuit component includes multiple integrated circuit dies, the integrated circuit dies may be conductively coupled by one or more conductive traces of a component substrate (and vias between the conductive traces, if the conductive traces are on multiple layers and / or if the conductive traces are embedded in the substrate, bridge, or interposer), one or more silicon interposers, one or more silicon bridges embedded in the component substrate, or a combination thereof.

[0128] Typically, the interposer 1804 may extend connections to a wider pitch or re-route connections to different connections. For example, the interposer 1804 may couple the integrated circuit component 1820 to a set of ball grid array (BGA) conductive contacts of the coupling component 1816 for coupling to the circuit board 1802. In Figure 18 the illustrated embodiment, the integrated circuit component 1820 and the circuit board 1802 are attached to opposite sides of the interposer 1804; in other embodiments, the integrated circuit component 1820 and the circuit board 1802 may be attached to the same side of the interposer 1804. In some embodiments, three or more components may be interconnected by the interposer 1804.

[0129] In some embodiments, the interposer 1804 may be formed as a PCB, including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1804 may be formed of epoxy resin, fiberglass-reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymer materials such as polyimide. In some embodiments, the interposer 1804 may be formed of alternative rigid or flexible materials, which may include the same materials as those used for semiconductor substrates described above, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 1804 may include metal interconnects 1808 and vias 1810, including but not limited to through vias 1810-1 (which extend from a first side 1850 of the interposer 1804 to a second side 1854 of the interposer 1804), blind vias 1810-2 (which extend from the first side 1850 or the second side 1854 of the interposer 1804 to an internal metal layer), and buried vias 1810-3 (which connect internal metal layers).

[0130] In some embodiments, the interposer 1804 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first face of the silicon interposer to an opposite second face of the silicon interposer. In some embodiments, the interposer 1804 including the silicon interposer may further include one or more wiring layers to route connections on a first face of the interposer 1804 to an opposite second face of the interposer 1804.

[0131] The interposer 1804 may further include embedded devices 1814, including both passive and active devices. These devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1804. The package-on-interposer structure 1836 may take the form of any package-on-interposer structure known in the art. In an embodiment, the interposer is a non-printable circuit board.

[0132] The integrated circuit device assembly 1800 may include an integrated circuit component 1824 coupled to a first face 1840 of the circuit board 1802 through a coupling component 1822. The coupling component 1822 may take the form of any of the embodiments discussed above with reference to the coupling component 1816, and the integrated circuit component 1824 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1820.

[0133] Figure 18 The integrated circuit device assembly 1800 shown in FIG. includes a package-on-package structure 1834 coupled to a second face 1842 of the circuit board 1802 through a coupling component 1828. The package-on-package structure 1834 may include an integrated circuit component 1826 and an integrated circuit component 1832 coupled together through a coupling component 1830 such that the integrated circuit component 1826 is disposed between the circuit board 1802 and the integrated circuit component 1832. The coupling components 1828 and 1830 may take the form of any of the embodiments of the coupling component 1816 discussed above, and the integrated circuit components 1826 and 1832 may take the form of any of the embodiments of the integrated circuit component 1820 discussed above. The package-on-package structure 1834 may be configured according to any package-on-package structure known in the art.

[0134] Figure 19is a block diagram of an example electrical device 1900 that can include one or more of the microelectronic components or integrated circuit components disclosed herein (e.g., any of die 102, 1406). For example, any suitable component of the electrical device 1900 can include one or more of the integrated circuit device components, integrated circuit components, integrated circuit devices, or integrated circuit dies disclosed herein and can be arranged in any of the microelectronic components disclosed herein. A plurality of components are shown as being included in the electrical device 1900 in Figure 19 but any one or more of these components can be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electrical device 1900 can be attached to one or more of a motherboard, mainboard, or system board. In some embodiments, one or more of these components are fabricated on a single system-on-chip (SoC) die.

[0135] Additionally, in various embodiments, the electrical device 1900 can exclude Figure 19 one or more of the components shown in but the electrical device 1900 can include interface circuitry for coupling to one or more components. For example, the electrical device 1900 can exclude the display device 1906 but can include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 1906 can be coupled. In another set of examples, the electrical device 1900 can exclude the audio input device 1924 or the audio output device 1908 but can include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1924 or the audio output device 1908 can be coupled.

[0136] The electrical device 1900 can include one or more processor units 1902 (e.g., one or more processing units). As used herein, the terms “processor unit,” “processing unit,” or “processor” can refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1902 can include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller crypto-processors (specialized processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Thus, the processor unit can be referred to as an XPU (or xPU).

[0137] The electrical device 1900 may include a memory 1904, which itself may include one or more memory devices, such as volatile memories (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memories (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-volatile memory), solid-state memories, and / or hard disk drives. In some embodiments, the memory 1904 may include a memory located on the same integrated circuit die as the processor unit 1902. This memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last-level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0138] In some embodiments, the electrical device 1900 may include one or more processor units 1902 that are heterogeneous or asymmetric with another processor unit 1902 in the electrical device 1900. There may be various differences among the processor units 1902 in the system in terms of a series of merit metrics, including architecture, microarchitecture, thermal, power consumption characteristics, etc. These differences may effectively indicate that they are asymmetric and heterogeneous among the processor units 1902 in the electrical device 1900.

[0139] In some embodiments, the electrical device 1900 may include a communication component 1912 (e.g., one or more communication components). For example, the communication component 1912 may manage wireless communication to facilitate the transmission of data to and from the electrical device 1900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can transfer data via a modulated electromagnetic radiation through a non-solid medium. The term "wireless" does not imply that the associated device does not include any wiring, although in some embodiments they may not include wiring.

[0140] The communication component 1912 may implement any one of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) project and any revisions, updates, and / or amendments thereof (e.g., LTE-Advanced project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX networks. WiMAX is an acronym representing Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass the compliance and interoperability tests of the IEEE 802.16 standard. The communication component 1912 may operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication component 1912 may operate according to Enhanced Data Rate for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1912 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and its derivatives, and any other wireless protocols named 3G, 4G, 5G, and higher generations. In other embodiments, the communication component 1912 may operate according to other wireless protocols. The electrical device 1900 may include an antenna 1922 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0141] In some embodiments, the communication component 1912 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 1912 may include multiple communication components. For example, a first communication component 1912 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 1912 may be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication component 1912 may be dedicated to wireless communications, and a second communication component (not shown) may be dedicated to wired communications.

[0142] The electrical device 1900 may include a battery / power circuit 1914. The battery / power circuit 1914 may include one or more energy storage devices (e.g., a battery or a capacitor) and / or circuitry for coupling components of the electrical device 1900 to an energy source (e.g., an AC line power source) that is separate from the electrical device 1900.

[0143] The electrical device 1900 may include a display device 1906 (or corresponding interface circuitry as discussed above). The display device 1906 may include one or more embedded or externally visible indicators that are wired or wirelessly connected, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0144] The electrical device 1900 may include an audio output device 1908 (or corresponding interface circuitry as discussed above). The audio output device 1908 may include any embedded or externally visible device that is wired or wirelessly connected and generates an audible indicator, such as a speaker, headphones, or earbuds.

[0145] The electrical device 1900 may include an audio input device 1924 (or corresponding interface circuitry as discussed above). The audio input device 1924 may include any embedded or externally visible device that is wired or wirelessly connected and generates a signal representative of sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output). The electrical device 1900 may include a Global Navigation Satellite System (GNSS) device 1918 (or corresponding interface circuitry as discussed above), such as a Global Positioning System (GPS) device. As is known in the art, the GNSS device 1918 may communicate with a satellite-based system and may determine the geographical location of the electrical device 1900 based on information received from one or more GNSS satellites.

[0146] The electrical device 1900 may include other output devices 1910 (or corresponding interface circuitry as discussed above). Examples of the other output devices 1910 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0147] The electrical device 1900 may include other input devices 1920 (or corresponding interface circuits as discussed above). Examples of other input devices 1920 may include accelerometers, gyroscopes, compasses, image capture devices (e.g., single field-of-view or stereo cameras), trackballs, trackpads, touchpads, keyboards, cursor control devices such as mice, styli, touchscreens, proximity sensors, microphones, barcode readers, quick response (QR) code readers, electrocardiogram (ECG) sensors, PPG (photoplethysmogram) sensors, skin conductance response sensors, any other sensors, or radio frequency identification (RFID) readers. One or more of the foregoing input devices may be a user interface through which a human user may provide input to the electrical device 1900. In at least some examples, such input may be presented on the display device 1906.

[0148] The electrical device 1900 may have any desired form factor, such as a handheld or mobile electrical device (e.g., cellular phone, smartphone, mobile Internet device, music player, tablet computer, laptop computer, 2-in-1 convertible computer, portable all-in-one computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, portable game console, etc.), desktop electrical device, server, rack-level computing solution (e.g., blade, tray, or slide computing system), workstation or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, fixed game console, smart TV, vehicle control unit, digital camera, digital video recorder, wearable electrical device, or embedded computing system (e.g., a computing system that is part of a vehicle, smart home appliance, consumer electronics product or device, manufacturing device). In some embodiments, the electrical device 1900 may be any other electronic device that processes data. In some embodiments, the electrical device 1900 may include multiple discrete physical components. Given the range of devices that the electrical device 1900 can assume in various embodiments, in some embodiments, the electrical device 1900 may be referred to as a computing device or computing system.

[0149] As used in this application and the claims, a list of items joined by the term "and / or" can represent any combination of the listed items. For example, the phrase "A, B, and / or C" can represent A; B; C; A and B; A and C; B and C; or A, B, and C. As used in this application and the claims, a list of items joined by the term "at least one of..." can represent any combination of the listed items. For example, the phrase "at least one of A, B, or C" can represent A; B; C; A and B; A and C; B and C; or A, B, and C. Additionally, as used in this application and the claims, a list of items joined by the term "one or more of..." can represent any combination of the listed items. For example, the phrase "one or more of A, B, and C" can represent A; B; C; A and B; A and C; B and C; or A, B, and C.

[0150] As used in this application and the claims, the phrase "each" or "respective" after a list of items recited or stated as having a property, characteristic, etc. means that all items in the list have the stated or recited property, characteristic, etc. For example, the phrase "each of A, B, or C includes a side wall" or "respective of A, B, or C includes a side wall" means that A includes a side wall, B includes a side wall, and C includes a side wall.

[0151] The disclosed methods, apparatuses, and systems should not be construed as being limited in any way. On the contrary, this disclosure relates to all novel and non-obvious features and aspects of the various disclosed embodiments (in isolation and in various combinations and sub-combinations with each other). The disclosed methods, apparatuses, and systems are not limited to any particular aspect or feature or combination thereof, and the disclosed embodiments do not require the presence of any one or more particular advantages or that problems be solved.

[0152] The description of the operating theory, scientific principles, or other theories presented herein with reference to the apparatuses or methods in this disclosure is provided for purposes of better understanding and is not intended to limit the scope. The apparatuses and methods in the appended claims are not limited to those that operate in the manner described by such operating theory.

[0153] Although, for convenience of presentation, the operations of some of the methods disclosed herein are described in a particular order of sequence, it should be understood that such description encompasses rearrangements, unless the particular language set forth herein requires a particular ordering. For example, in some cases, the operations described in sequence can be rearranged or performed simultaneously. Additionally, for simplicity, the drawings may not show the various ways in which the disclosed methods can be used in combination with other methods.

[0154] The following examples relate to additional embodiments of the technology disclosed herein.

[0155] The following examples relate to embodiments in accordance with this specification. Example A1 provides an apparatus that includes: an optical mediator that includes a first surface, a first mating protrusion that extends outward from the first surface of the optical mediator, and two or more alignment protrusions that extend outward from the first surface of the optical mediator, wherein when the first surface of the optical mediator faces a second surface of a photonic integrated circuit (PIC) die and distal surfaces of respective ones of the two or more alignment protrusions contact the second surface of the PIC die, the first mating protrusion is partially disposed within a first groove formed in the second surface of the PIC die.

[0156] Example A2 includes the subject matter of Example A1 and, when distal surfaces of respective ones of the two or more alignment protrusions contact the second surface of the PIC die, defines a first space between the first surface of the optical mediator and the second surface of the PIC die.

[0157] Example A3 includes the subject matter of any one of Examples A1 - A2 and the optical mediator further includes a first waveguide that is aligned with another waveguide in the PIC die.

[0158] Example A4 includes the subject matter of Example A3 and the first waveguide of the optical mediator is disposed within the first mating protrusion of the optical mediator.

[0159] Example A5 includes the subject matter of any one of Examples A1 - A4 and, when the first mating protrusion is partially disposed within the first groove of the PIC die, a first portion of an outer surface of the first mating protrusion contacts a first sidewall of the first groove and a second portion of the outer surface of the first mating protrusion is opposite a second sidewall of the first groove such that a second space is defined between the second portion of the outer surface of the first mating protrusion and the second sidewall of the first groove.

[0160] Example A6 includes the subject matter of Example A5 and the first portion and the second portion are on opposite sides of the first mating protrusion.

[0161] Example A7 includes the subject matter of any one of Examples A1 - A6 and a first height of the two or more alignment protrusions is less than a second height of the first mating protrusion.

[0162] Example A8 includes the subject matter of any one of Examples A1 - A7 and a first alignment protrusion of the two or more alignment protrusions includes a first distal surface having a substantially hemispherical shape, a substantially semi - conical shape, or a substantially planar shape.

[0163] Example A9 includes the subject matter of any one of Examples A1 - A8, and the two or more alignment protrusions include at least three alignment protrusions arranged in a non - linear arrangement.

[0164] Example A10 includes the subject matter of Example A9, and the three distal surfaces of the at least three alignment protrusions respectively define planes substantially parallel to the first surface of the optical mediator.

[0165] Example A11 includes the subject matter of any one of Examples A1 - A10, and the first alignment protrusion among the two or more alignment protrusions is substantially cylindrical and is arranged such that the longitudinal axis of the first alignment protrusion is substantially parallel to the first surface of the optical mediator.

[0166] Example A12 includes the subject matter of any one of Examples A1 - A11, and the first mating protrusion includes a distal portion that is substantially cylindrical and is arranged such that the longitudinal axis of the distal portion is substantially parallel to the first surface of the optical mediator.

[0167] Example A13 is an integrated circuit package and includes the subject matter of any one of Examples A1 - A12, and further includes the PIC die, one or more electronic integrated circuit (EIC) dies, and the one or more EIC dies are electrically coupled to the PIC die, wherein the one or more EIC dies are electrically coupled to a processor or integrated with a processor.

[0168] Example B1 provides a device that includes a photonic integrated circuit (PIC) die. The PIC die includes a first waveguide and one or more grooves formed in a first surface of the PIC die. The device further includes an optical mediator that includes a second waveguide aligned with the first waveguide of the PIC die, one or more mating protrusions respectively partially disposed in the one or more grooves, and one or more alignment protrusions that extend between a second surface of the optical mediator and the first surface of the PIC die such that the second surface of the optical mediator faces and is spaced apart from the first surface of the PIC die.

[0169] Example B2 includes the subject matter of Example B1, and the second waveguide of the optical mediator is disposed in one of the one or more mating protrusions of the optical mediator.

[0170] Example B3 includes the subject matter of any one of Examples B1 - B2, and the first groove among the one or more grooves is defined by at least a first wall and a second wall formed in the PIC die.

[0171] Example B4 includes the subject matter of Example B3, and a first portion of the outer surface of the first mating protrusion contacts the first wall formed in the PIC die, wherein a second portion of the outer surface of the first mating protrusion faces and is spaced apart from the second wall formed in the PIC die.

[0172] Example B5 includes the subject matter of any one of Examples B1 - B4, and the one or more alignment protrusions extend outwardly from the second surface of the optical mediator and include respective distal surfaces.

[0173] Example B6 includes the subject matter of Example B5, and a first height of the one or more alignment protrusions is less than a second height of the one or more mating protrusions.

[0174] Example B7 includes the subject matter of any one of Examples B5 - B6, and at least respective portions of the distal surfaces contact the first surface of the PIC die.

[0175] Example B8 includes the subject matter of any one of Examples B1 - B7, and at least one of the one or more alignment protrusions includes a first distal surface having a substantially hemispherical shape, a substantially semi - conical shape, or a substantially planar shape.

[0176] Example B9 includes the subject matter of any one of Examples B1 - B8, and the one or more alignment protrusions include at least three alignment protrusions arranged in a non - linear arrangement.

[0177] Example B10 includes the subject matter of Example B9, and three distal surfaces of the at least three alignment protrusions respectively define planes substantially parallel to the second surface of the optical mediator.

[0178] Example B11 includes the subject matter of any one of Examples B1 - B10, and a first alignment protrusion of the one or more alignment protrusions is substantially cylindrical and is arranged such that a longitudinal axis of the first alignment protrusion is substantially parallel to the second surface of the optical mediator.

[0179] Example B12 includes the subject matter of any one of Examples B1 - B11, and the one or more grooves are shaped as one or more V - shaped grooves or one or more chamfered pyramids.

[0180] Example B13 includes the subject matter of any one of Examples B1 - B4 or any one of Examples B8 - B12, and the one or more alignment protrusions extend outwardly from the first surface of the PIC die and include respective distal surfaces.

[0181] Example B14 includes the subject matter of Example B13, and at least a portion of the corresponding distal surface contacts the second surface of the optical mediator.

[0182] Example B15 includes the subject matter of any one of Examples B1 - B14, and the PIC die further includes a first plurality of waveguides, the optical mediator further includes a second plurality of waveguides, and the first plurality of waveguides are respectively aligned with the second plurality of waveguides.

[0183] Example B16 includes the subject matter of any one of Examples B1 - B15, and further includes: a processor communicatively coupled to the PIC die via an electrical integrated circuit (EIC), a display communicatively coupled to the processor, and a user interface configured to receive input from a user, the input to be presented on the display.

[0184] Example B17 is an integrated circuit package and includes the subject matter of any one of Examples B1 - B15, and further includes one or more electronic integrated circuit (EIC) dies, wherein the one or more EIC dies are electrically coupled to the PIC die, and wherein the one or more EIC dies are electrically coupled to or integrated with a processor.

[0185] Example C1 provides an apparatus that includes: a photonic integrated circuit (PIC) die including a first surface; an optical mediator including a second surface and a first mating protrusion that extends outwardly from the second surface and is partially disposed within a first groove formed in the first surface of the PIC die; and two or more alignment protrusions that extend between the first surface of the PIC die and the second surface of the optical mediator such that a first space is defined between the first surface of the PIC die and the second surface of the optical mediator.

[0186] Example D1 provides a method that includes: forming an optical mediator including a first mating protrusion and two or more alignment protrusions, wherein the first mating protrusion and the two or more alignment protrusions are formed on a first surface of the optical mediator; mounting the optical mediator on a photonic integrated circuit (PIC) die that includes a groove partially defined by a first sidewall formed in a second surface of the PIC die, wherein the mounting includes positioning the optical mediator such that the two or more alignment protrusions extend between the first surface of the optical mediator and the second surface of the PIC die and such that the first mating protrusion is partially received in the groove; and laterally moving the optical mediator relative to the second surface of the PIC die such that a portion of an outer surface of the first mating protrusion contacts the first sidewall of the groove.

[0187] Example D2 includes the subject matter of Example D1 and further includes aligning one or more first waveguides of the optical mediator with one or more second waveguides of the PIC die.

[0188] Example D3 includes the subject matter of Example D2 and further includes forming the one or more first waveguides in one or more mating protrusions of the optical mediator, respectively.

[0189] Example D4 includes the subject matter of any one of Examples D1 - D3 and further includes forming the groove in the PIC die, the groove being sized to allow the first mating protrusion to be partially inserted into the groove and defining a first space between a first portion of the outer surface of the first mating protrusion and the first sidewall of the groove and a second space between a second portion of the outer surface of the first mating protrusion and a second sidewall of the groove before laterally moving the optical mediator.

[0190] Example D5 includes the subject matter of any one of Examples D1 - D4 and the groove is defined by at least the first sidewall and the second sidewall formed in the PIC die.

[0191] Example D6 includes the subject matter of any one of Examples D1 - D5 and the two or more alignment protrusions extend outward from the first surface of the optical mediator and include respective distal surfaces.

[0192] Example D7 includes the subject matter of Example D6 and a first height of the two or more alignment protrusions is less than a second height of the first mating protrusion.

[0193] Example D8 includes the subject matter of any one of Examples D6 - D7, and mounting the optical mediator on the PIC die further includes: bringing at least a portion of each of the respective distal surfaces into contact with the second surface of the PIC die.

[0194] Example D9 includes the subject matter of any one of Examples D1 - D8, and at least one of the two or more alignment protrusions includes a first distal surface having a substantially hemispherical shape, a substantially semi - conical shape, or a substantially planar shape.

[0195] Example D10 includes the subject matter of any one of Examples D1 - D9, and the two or more alignment protrusions include at least three alignment protrusions arranged in a non - linear arrangement.

[0196] Example D11 includes the subject matter of Example D10, and the three distal surfaces of the at least three alignment protrusions respectively define planes substantially parallel to the first surface of the optical mediator.

[0197] Example D12 includes the subject matter of any one of Examples D1 - D11, and the first alignment protrusion of the two or more alignment protrusions is substantially cylindrical and is arranged such that the longitudinal axis of the first alignment protrusion is substantially parallel to the first surface of the optical mediator.

[0198] Example D13 includes the subject matter of any one of Examples D1 - D12, and the groove of the PIC die and the second groove of the PIC die are shaped as V - shaped grooves or chamfered pyramids.

[0199] Example D14 includes the subject matter of any one of Examples D1 - D13, and further includes mounting the PIC die to a substrate, mounting a processor to the substrate such that the processor is communicatively coupled to the PIC die via an electrical integrated circuit (EIC), and completing the packaging of an integrated circuit package including the substrate, the PIC die, the EIC, the processor, and the optical mediator.

[0200] Example D15 includes the subject matter of Example D14, and the EIC is integrated with or separately connected to the processor.

[0201] Example D16 includes the subject matter of any one of Examples D1 - D5 or any one of Examples D9 - D15, and the two or more alignment protrusions extend outward from the second surface of the PIC die and include respective distal surfaces.

[0202] Example D17 includes the subject matter of Example D16, and at least a portion of the respective distal surfaces contacts the first surface of the optical mediator.

Claims

1. A device comprising: An optical mediator, the optical mediator comprising a first surface; a first mating protrusion extending outwardly from the first surface of the optical mediator; as well as Two or more alignment protrusions extending outwardly from the first surface of the optical interposer, wherein when the first surface of the optical interposer is opposite to the second surface of a photonic integrated circuit (PIC) die and corresponding distal surfaces of the two or more alignment protrusions contact the second surface of the PIC die, the first mating protrusion is partially disposed within a first recess formed in the second surface of the PIC die.

2. The device according to claim 1, wherein: When the respective distal surfaces of the two or more alignment protrusions contact the second surface of the PIC die, a first space is defined between the first surface of the optical interposer and the second surface of the PIC die.

3. The device according to claim 1, wherein: When the first mating protrusion is partially disposed in the first recess of the PIC die, a first portion of an outer surface of the first mating protrusion contacts a first side wall of the first recess, and a second portion of the outer surface of the first mating protrusion is opposite to a second side wall of the first recess, so that a second space is defined between the second portion of the outer surface of the first mating protrusion and the second side wall of the first recess.

4. The device according to claim 3, wherein: The first portion and the second portion are on opposite sides of the first mating protrusion.

5. The device according to claim 1, wherein: The optical interposer also includes a first waveguide aligned with another waveguide in the PIC die.

6. The device according to any one of claims 1 to 5, wherein: A first height of the two or more alignment protrusions is smaller than a second height of the first mating protrusion.

7. The device according to any one of claims 1 to 6, wherein: A first alignment protrusion of the two or more alignment protrusions includes a first distal end surface having a substantially hemispherical shape, a substantially semi-conical shape, or a substantially planar shape.

8. The device according to any one of claims 1 to 6, wherein: The two or more alignment protrusions include at least three alignment protrusions in a non-linear arrangement.

9. The device according to claim 8, wherein: The three distal end surfaces of the at least three alignment protrusions respectively define planes that are substantially parallel to the first surface of the optical mediator.

10. The device according to any one of claims 1 to 6, wherein: A first alignment protrusion of the two or more alignment protrusions is substantially cylindrical and is arranged such that a longitudinal axis of the first alignment protrusion is substantially parallel to the first surface of the optical mediator.

11. An apparatus comprising: Photonic integrated circuit (PIC) die, including: a first waveguide; and one or more grooves in the first surface of the PIC die; and Optical mediator, including: a second waveguide aligned with the first waveguide of the PIC die; one or more mating protrusions, the one or more mating protrusions being partially disposed in the one or more grooves, respectively; and One or more alignment protrusions extending between a second surface of the optical interposer and the first surface of the PIC die such that the second surface of the optical interposer is opposite to and spaced apart from the first surface of the PIC die.

12. The device according to claim 11, wherein The second waveguide of the optical interposer is disposed in one of the one or more mating protrusions of the optical interposer.

13. The device according to claim 11, wherein: A first recess of the one or more recesses is defined by at least a first wall and a second wall formed in the PIC die.

14. The device according to claim 13, wherein: A first portion of an outer surface of a first mating protrusion contacts the first wall formed in the PIC die, wherein a second portion of the outer surface of the first mating protrusion is spaced apart from the second wall formed in the PIC die.

15. The device according to any one of claims 11 to 14, wherein: The one or more grooves are shaped as one or more V-shaped grooves or one or more inverted pyramids.

16. The apparatus according to any one of claims 11 to 15, further comprising: a processor communicatively coupled to the PIC die via an electronic integrated circuit (EIC); a display communicatively coupled to the processor; as well as A user interface is configured to receive input from a user, the input to be presented on the display.

17. The device according to any one of claims 11 to 15, wherein: The one or more alignment protrusions extend outwardly from the second surface of the optical interposer and include respective distal surfaces, wherein at least a portion of the respective distal surfaces contacts the first surface of the PIC die.

18. A method comprising: forming an optical interposer including a first mating protrusion and two or more alignment protrusions, wherein the first mating protrusion and the two or more alignment protrusions are formed on a first surface of the optical interposer; and The optical interposer is mounted on a photonic integrated circuit (PIC) die, the PIC die comprising a recess defined in part by a first sidewall formed in a second surface of the PIC die, wherein the mounting comprises positioning the optical interposer such that the two or more alignment protrusions extend between the first surface of the optical interposer and the second surface of the PIC die, and such that the first mating protrusion is partially received in the recess.

19. The method according to claim 18, further comprising: The optical interposer is laterally moved relative to the second surface of the PIC die such that a first portion of an outer surface of the first mating protrusion contacts the first sidewall of the recess.

20. The method according to any one of claims 18-19, further comprising: One or more first waveguides of the optical interposer are aligned with one or more second waveguides of the PIC die.

Images