Control system, control method for control system, and control program for control system

Abstract

The present disclosure uses a multiplexed controller provided with a plurality of CPU cores, and appropriately performs control of logical operations based on height. The present application relates to a control system provided with a plurality of controllers that are multiplexed with each other, the controllers having a plurality of CPU cores capable of executing logical operations including a plurality of operation tasks for controlling a control object. Each of the plurality of controllers stores operation results of the plurality of operation tasks as a first local data arrangement, and stores operation results received from the other controllers as a second local data arrangement. Data elements selected from the first local data arrangement and the second local data arrangement are stored as a global data arrangement referenced among the plurality of computing tasks. In addition, the first local data arrangement is sent as tracking data to other controllers.

Description

Technical Field

[0001] The present disclosure relates to a control system, a control method for the control system, and a control program for the control system. Background Art

[0002] For example, a control system for controlling factory equipment such as power generation equipment is configured to include a controller having an arithmetic device such as a CPU. In such a controller, a field signal from a field device such as a sensor provided in the factory equipment to be controlled is input, and the arithmetic result is output to an operation terminal such as an actuator or a switch by executing a control logic including a plurality of logic pieces described in a graphical language such as a graphical processing language (POL: Problem Oriented Language) (or the FBD (Function Block Diagram) language of IEC61131-3 in the international standard language of a PLC (Programmable Logic Controller)), thereby implementing the control of the factory equipment. A series of arithmetic processes performed by such a controller are periodically executed according to a predetermined arithmetic cycle.

[0003] Furthermore, such a control system is sometimes configured to include controllers that are reused with each other to improve reliability. In a system in which controllers are reused, even when an abnormal condition such as a failure occurs in the controller in the control state, the control function can be maintained by switching to another controller in the standby state. Sometimes in such a system in which controllers are reused, there is a unit for synchronizing the arithmetic results of the control logic between the controllers so that the output to the operation terminal does not change abruptly when switching the controller (for example, Patent Document 1).

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Patent Laid-Open No. 2003-65004 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] In a control system composed of arithmetic processing devices, in order to improve its arithmetic performance, a controller with multiple CPU cores (multi-core CPU) is sometimes used. In such a controller, the arithmetic operations of each logic slice of the control logic are executed in parallel by multiple CPU cores. However, depending on the arithmetic execution states of the respective CPU cores, differences may occur in the logic operation results between the multiplexed controllers. When differences occur in the logic operation results between the multiplexed controllers, the output value to the operation terminal may suddenly change when switching to the standby-side controller. Therefore, in a control system with multiplexed controllers, even assuming that the controller has multiple CPU cores, the control logic operation is executed by a single CPU core so that differences do not occur in the operation results between the controllers. Currently, the advantages of the multi-core CPU cannot be fully utilized.

[0009] In addition, in recent years, the sophistication of logic operations implemented as arithmetic processing in control systems has been continuously evolving. For example, advanced control such as model predictive control (MPC: Model Predictive Control) and advanced arithmetic processing such as artificial intelligence (AI) are described in general-purpose programming languages such as C and Python, and there is already a mechanism to call functions within the object code thereof from the control logic and execute them. However, in the case where such logic operations are implemented by a single CPU core, the processing time for convergence calculations to obtain the optimal solution and learning operations becomes longer through repeated calculations, and thus it may not be possible to output the logic operation result to the operation terminal within a preset control cycle.

[0010] At least one embodiment of the present disclosure has been completed in view of the above circumstances, and an object thereof is to provide a control system, a control method for a control system, and a control program for a control system that can use a multiplexed controller having multiple CPU cores and appropriately implement control based on advanced logic operations.

[0011] Technical solution

[0012] To solve the above problems, a control system according to at least one embodiment of the present disclosure includes a plurality of controllers multiplexed with each other, the controller having a plurality of CPU cores capable of executing a logic operation including a plurality of arithmetic tasks for controlling a control object. In the control system,

[0013] Each of the plurality of controllers includes:

[0014] A first local data arrangement storage unit that stores the arithmetic operation results of the plurality of arithmetic tasks as a first local data arrangement;

[0015] A second local data arrangement storage unit that stores the arithmetic operation results received from other controllers as a second local data arrangement;

[0016] A global data arrangement storage unit that stores data elements selected from the first local data arrangement and the second local data arrangement as a global data arrangement that can be referenced among the multiple arithmetic tasks; and

[0017] A trace data transmission unit that transmits the first local data arrangement as trace data to the other controller.

[0018] To solve the above problems, a control method of a control system according to at least one embodiment of the present disclosure is a control method of a control system having a plurality of controllers that are reused with each other. The controller has a plurality of CPU cores that can perform logical operations including a plurality of arithmetic tasks for controlling a controlled object. In the control method of the control system, the following processes are included in each of the plurality of controllers:

[0019] Store the operation results of the multiple arithmetic tasks as a first local data arrangement;

[0020] Store the operation results received from other controllers as a second local data arrangement;

[0021] Store data elements selected from the first local data arrangement and the second local data arrangement as a global data arrangement that can be referenced among the multiple arithmetic tasks; and

[0022] Transmit the first local data arrangement as trace data to the other controller.

[0023] To solve the above problems, a control program of a control system according to at least one embodiment of the present disclosure is a control program of a control system having a plurality of controllers that are reused with each other. The controller has a plurality of CPU cores that can perform logical operations including a plurality of arithmetic tasks for controlling a controlled object. In the control program of the control system,

[0024] Can cause a computer device to execute the following processes in each of the plurality of controllers:

[0025] Store the operation results of the multiple arithmetic tasks as a first local data arrangement;

[0026] Store the operation results received from other controllers as a second local data arrangement;

[0027] Store data elements selected from the first local data arrangement and the second local data arrangement as a global data arrangement that can be referenced among the multiple arithmetic tasks; and

[0028] Transmit the first local data arrangement as trace data to the other controller.

[0029] Advantageous Effects

[0030] According to at least one embodiment of the present disclosure, a control system, a control method of the control system, and a control program of the control system can be provided that can appropriately perform altitude-based logical operation control using a multiplexed controller having multiple CPU cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram showing the overall configuration of a control system according to one embodiment.

[0032] Figure 2 It shows Figure 1 a schematic diagram of the configuration of the controller unit.

[0033] Figure 3 It is Figure 2 an internal configuration diagram of the controller.

[0034] Figure 4 It shows Figure 1 a flowchart of the control method of the control system.

[0035] REFERENCE MARK DESCRIPTION

[0036] 1: Control system;

[0037] 2: Controlled object;

[0038] 2a: Oscillator;

[0039] 2b: Switching device;

[0040] 2c: Control valve;

[0041] 2d: Check valve;

[0042] 4: Controller unit;

[0043] 6(6A, 6B,...): Controller;

[0044] 8: CPU core;

[0045] 10: I / O unit;

[0046] 12: I / O communication network;

[0047] 20: Memory unit;

[0048] 22: First local data arrangement storage unit;

[0049] 24: Second local data arrangement storage unit;

[0050] 26: Global data arrangement storage unit;

[0051] LS: Logic slice

[0052] CL: Control Logic;

[0053] D1: First local data arrangement;

[0054] D2: Second local data arrangement;

[0055] Dg: Global data arrangement. Detailed implementation

[0056] Hereinafter, some embodiments of the present invention will be described with reference to the accompanying drawings. However, the configurations described as embodiments or shown in the drawings are not intended to limit the scope of the present invention thereto, but are merely illustrative examples.

[0057] First, refer to Figure 1 and Figure 2 to describe the schematic configuration of the control system 1 of one embodiment. Figure 1 is a schematic diagram showing the overall configuration of the control system 1 of one embodiment, Figure 2 is showing Figure 1 the schematic configuration of the controller unit 4.

[0058] The control system 1 takes the factory equipment composed of many devices as the control object 2. The specific configuration of the control object 2 is not limited, but the control object 2 is, for example, the factory equipment constituting the infrastructure of oil, gas, electricity, manufacturing, etc. In Figure 1 as some examples of the control object 2, the oscillator 2a, the switching device 2b, the control valve 2c, and the stop valve 2d, which are the constituent devices of the factory equipment, are shown.

[0059] The control system 1 includes a controller unit 4 that can implement various functions for controlling the control object 2. The controller unit 4 includes a plurality of controllers 6 as described later (in the following description, when distinguishing the plurality of controllers 6 included in the controller unit 4, they are respectively appropriately referred to as controllers 6A, 6B,...). Each controller 6 is composed of, for example, a CPU (Central Processing Unit), a RAM (Random Access Memory), a ROM (ReadOnly Memory), and a computer-readable storage medium, etc. And a series of processes for implementing various functions are stored in a storage medium or the like as a control program, and the CPU reads the control program into the RAM or the like and executes information processing and arithmetic processing to thereby implement various functions. In the present embodiment, in particular, the control program is prepared as a plurality of logic slices LS including the control logic CL described in a graphical language.

[0060] It should be noted that in the control program, it can also be provided in a manner of being pre-installed in a ROM or other storage medium, in a state of being stored in a computer-readable storage medium, or transmitted via a wired or wireless communication unit. The computer-readable storage medium is a magnetic disk, an optical disk, a CD-ROM (Compact Disc-Read Only Memory), a DVD-ROM (Digital Video Disc-Read Only Memory), a semiconductor memory, etc.

[0061] A plurality of controllers 6 included in the controller unit 4 are multiplexed with each other. The multiplexing degree of the plurality of controllers 6 only needs to be 2 or more. The multiplexed plurality of controllers 6 respectively have substantially the same configuration, and as an operation mode, either a control mode capable of controlling the control object 2 or a standby mode can be selected. In the controller unit 4, any one of the controllers 6A selected from the plurality of controllers 6 is set to the control mode, thereby implementing the control of the control object 2, and the other controllers 6B, 6C,... are set to the standby mode. When a phenomenon occurs in which the control of the control object 2 cannot be continued for some reason in the controller 6A in the control mode, the operation mode of the controller 6A is removed from the control mode or switched to a critical failure mode, and the operation mode of any one of the other controllers 6B, 6C,... is switched from the standby mode to the control mode, thereby enabling the control of the control object 2 to be continued.

[0062] In addition, as a CPU for implementing a logical operation including a plurality of arithmetic tasks by executing a control program, each of the plurality of controllers 6 included in the controller unit 4 is a so-called multi-core CPU type having a plurality of CPU cores 8. Each controller 6 has two or more CPU cores 8, but in Figure 2 the example, a case where each controller 6 has two CPU cores 8 is shown (for example, the controller 6A has CPU cores 8A-1 and 8A-2, and the controller 6B has CPU cores 8B-1 and 8B-2).

[0063] Each controller 6 can transmit and receive various information required for arithmetic processing with the controlled object 2 via the I / O unit 10. The I / O unit 10 is an input / output interface for inputting / outputting various information between the controller 6 and the controlled object 2, and is connected to the controller 6 via the I / O communication network 12. The input information from the controlled object 2 is taken into the controller 6 via the I / O unit 10 and input to a plurality of logic slices LS pre-installed in each controller 6. The input information (analog data or digital data) input to each logic slice LS is used for the operation of the control logic CL described in POL, and the operation result (analog data or digital data) is output. The operation result output from each logic slice LS is output to the controlled object 2 as a control signal via the I / O unit 10.

[0064] Next, the functional configuration of each controller 6 in the control system 1 having the above configuration will be described. Figure 3 is Figure 2 The internal configuration diagram of the controller 6. It should be noted that in the following description, the controller 6A among the plurality of controllers 6 included in the controller unit 4 is used as a representative for description, but unless otherwise specified, the same applies to other controllers 6B, 6C,....

[0065] The controller 6A has a first CPU core 8A-1, a second CPU core 8A-2, and a memory unit 20. The first CPU core 8A-1 and the second CPU core 8A-2 execute a plurality of arithmetic tasks corresponding to a plurality of logic slices LS pre-installed as described above. The memory unit 20 includes a first local data arrangement storage unit 22, a second local data arrangement storage unit 24, and a global data arrangement storage unit 26.

[0066] In the controller 6A, based on the plurality of logic slices LS pre-installed, arithmetic tasks to be executed by each CPU core 8 (the first CPU core 8A-1, the second CPU core 8A-2) included in the controller 6A are created. The plurality of logic slices LS define control cycles corresponding to the control logic CL included in each of them. The controller 6A divides the plurality of logic slices LS into logic slice groups LSG for each control cycle, creates an arithmetic task (hereinafter referred to as "arithmetic task 1") for operating the logic slice group LSG with the shortest control cycle among them, and assigns it to the first CPU core 8A-1.

[0067] In addition, the controller 6A creates arithmetic tasks for executing other logic slice groups except for the logic slice group included in the arithmetic task 1 as arithmetic tasks N (N = 2, 3,...) in the order from the shortest to the longest control cycle. Here, the control cycle of the arithmetic task N is n (n = 1, 2,...) times that of the arithmetic task 1.

[0068] Here, among the multiple logical slices LS executed by the controller 6A, for example, there is a control logic CL that includes a lot of general programs with a large amount of computation, such as convergence calculations for finding the optimal solution through repeated calculations and artificial intelligence (AI). The control cycle of such a logical slice LS with a large amount of computation is long, and there is a possibility that the operation may not be completed within a pre-specified control cycle. Therefore, it is not included in the operation task 1, but is allocated to the logical slice group LSG in a manner that it is executed in an operation task N (for example, operation task 2) different from the operation task 1.

[0069] Each of the controllers 6A, 6B,... included in the controller unit 4 synchronizes the execution timing of a specific operation task. In the present embodiment, as will be described later, the execution timing of the operation task 1 with the shortest control cycle among the multiple operation tasks is synchronized among one of the CPU cores 8A-1, 8B-1,... of each of the controllers 6A, 6B,.... After the operation task 1 is executed, the operation task N (N = 2, 3,...) is awakened at a specified timing from the operation task 1 and is executed by the other CPU cores 8A-2, 8B-2,... of each of the controllers 6A, 6B,....

[0070] The first local data arrangement storage unit 22 is configured to store the operation results of multiple operation tasks implemented by the controller 6A as the first local data arrangement D1. That is, in each operation task implemented by the controller 6A, the intermediate operation value or the final operation value delivered to other operation tasks is stored as a specified data element of the first local data arrangement storage unit 22. In Figure 3 it, the following situation is exemplified: the operation result of the logical slice LS1-1 executed by the first CPU core 8A-1 is stored in the data element 1 of the first local data arrangement D1, and the operation results of the logical slices LS2-1 executed by the second CPU core 8A-2 are stored in the data elements 101 and 102. In this way, each data element stored in the first local data arrangement D1 is sent as trace data to other controllers 6B, 6C,....

[0071] The second local data arrangement storage unit 24 is configured to store the operation results referred to among multiple operation tasks received from other controllers 6B, 6C,... as trace data as the second local data arrangement D2. That is, in each data element of the second local data arrangement D2, the operation results corresponding to the data elements of the first local data arrangement D1 are received and stored from other controllers 6B, 6C,.... In Figure 3Among them, the second local data arrangement storage unit 24 has a plurality of second local data arrangements D2 corresponding to each of the other controllers 6B, 6C,.... Specifically, in each data element of the second local data arrangement D2 corresponding to the other controller 6B, the operation result received from the controller 6B as trace data is stored. In addition, in each data element of the second local data arrangement D2 corresponding to the other controller 6C, the operation result received from the controller 6C as trace data is stored.

[0072] The global data arrangement storage unit 26 has a global data arrangement Dg capable of storing data elements selected from the first local data arrangement D1 and the second local data arrangement D2. In the data elements of the global data arrangement Dg, the result of comparing the data elements of the first local data arrangement D1 and the data elements of the second local data arrangement D2 is stored. Here, as the data elements of the global data arrangement Dg, which data elements are stored is input and selected according to a specified rule such that the respective controllers 6A, 6B,... that reuse each other have the same operation result. For example, in each data element of the global data arrangement Dg, the intermediate value of the data elements of the first local data arrangement D1 and the data elements of the second local data arrangement D2 may be stored. In addition, in each data element of the global data arrangement Dg, the value selected as the value with the highest frequency (i.e., majority decision) among the data elements of the first local data arrangement D1 and the data elements of the second local data arrangement D2 may also be stored. In this way, each data element stored in the global data arrangement Dg is sent as an operation result referred to among a plurality of operation tasks to each operation task implemented by the controller 6A.

[0073] Next, a control method of the control system 1 having the above configuration will be described. Figure 4 It is a Figure 1 flowchart showing the control method of the control system 1. In Figure 4 it, the processes of performing processing related to the operation tasks 1 and N in the two CPU cores 8A-1 and 8A-2 provided in the controller 6A are sequentially shown. It should be noted that regarding the processing performed by the other controllers 6B, 6C,..., unless otherwise specified, it is the same as that of the controller 6A.

[0074] In each of the reused controllers 6A, 6B, …, the arithmetic task 1 is executed synchronously. In controller 6A, when the arithmetic task 1 is executed synchronously with other controllers 6B, 6C, …, in the first CPU core 8A-1 that executes the arithmetic task 1, each data element of the first local data arrangement D1 stored in other controllers 6B, 6C, … is received as trace data (step S1-1). These respective data elements received as trace data are stored in the second local data arrangement D2 of controller 6A. As described above, the result of comparing the data elements selected from the first local data arrangement D1 and the second local data arrangement D2 is stored in the global data arrangement Dg (step S1-2). Each data element stored in the global data arrangement Dg can be referred to in multiple arithmetic tasks in controller 6A as the arithmetic result referred to between multiple arithmetic tasks (step S1-3).

[0075] Next, in the first CPU core 8A-1, it is determined whether it is the wake-up timing of arithmetic task N in the second CPU core 8A-2 on the other side of controller 6A (step S1_4). When it is the wake-up timing of arithmetic task N in the second CPU core 8A-2 (step S1_4: Yes), in the second CPU core 8A-2 independent of the first CPU core 8A-1, arithmetic task N (N = 2, 3, …) is woken up (step S1-5). Thereby, the operation of the control logic corresponding to arithmetic task 1 starts in the first CPU core 8A-1 (step S1-6), and the operation of the control logic corresponding to arithmetic task N starts in the second CPU core 8A-2 (step S2-1).

[0076] It should be noted that when it is not the wake-up timing of arithmetic task N in the second CPU core 8A-2 (step S1_4: No), that is, when the operation of the logical slice of arithmetic task N in the second CPU core 8A-2 is not completed, the wake-up of arithmetic task N is not performed.

[0077] Next, the operations of the respective logical slices corresponding to arithmetic task 1 are implemented in the first CPU core 8A-1 (step S1-7). In step S1-7, in the first CPU core 8A-1, interfaces are made between arithmetic tasks through the input element (IFAI: InterFace Analog Input) and the analog output element (IFAO: InterFace Analog Output) that are POL elements described in each logical slice. By referring to the global data arrangement Dg stored in the global data arrangement storage unit 26, the data elements required for the operation can be input to the input element among these dedicated POL elements. In addition, for the output element, its operation result is stored in the first local data arrangement storage unit 22 serving as a local buffer as the first local data arrangement D1.

[0078] In the first CPU core 8A-1, when the operations of all logical slices are completed (step S1-8), the first CPU core 8A-1 determines whether the logical operation of the operation task N in the other second CPU core 8A-2 is completed (step S1-9). Then, when the first CPU core 8A-1 confirms the completion of the operation task N (step S1-9: Yes), each data element stored in the first local data arrangement D1 is sent as trace data to other controllers 6B, 6C,... (step S1-10).

[0079] It should be noted that in the determination of step S1-8, the process returns to step S1-6 until the operations of all logical slices are completed, thereby performing the operation of the next logical slice. Such processing is repeatedly implemented until the operations of all logical slices are completed.

[0080] In the second CPU core 8A-2 of one party, the operations of the logical slices corresponding to the operation task N are implemented (step S2-2). In step S2-2, in the second CPU core 8A-2, through the input element (IFAI: InterFace Analog Input) and the analog output element (IFAO: InterFace Analog Output) that are POL elements described in each logical slice, the interface is performed between operation tasks. By referring to the global data arrangement Dg stored in the global data arrangement storage unit 26, the data elements required for the operation can be input to the input elements in these dedicated POL elements. In addition, for the output elements, their operation results are stored in the first local data arrangement storage unit 22 as the first local data arrangement D1, which is used as a local buffer.

[0081] In the second CPU core 8A-2, when the operations of all logical slices are completed (step S2-3), the second CPU core 8A-2 determines whether the logical operation in the operation task 1 in the other first CPU core 8A-1 is completed (step S2-4). Then, when the second CPU core 8A-2 confirms the completion of the operation task 1 (step S2-4: Yes), each data element stored in the first local data arrangement D1 is sent as trace data to other controllers 6B, 6C,... (step S2-5). The transmission timing of this trace data is set to when the operations of both operation tasks 1 and N are completed so as not to send the state during the operation in each operation task.

[0082] It should be noted that in the determination of step S2-3, the process returns to step S2-1 until the operations of all logical slices are completed, thereby performing the operation of the next logical slice. Such processing is repeatedly implemented until the operations of all logical slices are completed.

[0083] As described above, according to the above-described embodiment, in each of the multiplexed controllers 6 having a plurality of CPU cores, the operation results of a plurality of arithmetic tasks are stored as a first local data arrangement D1. Each data element stored in the first local data arrangement D1 is stored as trace data in a second local data arrangement D2 of another controller 6. In the second local data arrangement D2, each data element received as trace data from the first local data arrangement D1 of another controller 6 is stored. In the global data arrangement Dg, the data elements selected from the first local data arrangement D1 and the second local data arrangement D2 stored in this way are stored and can be referred to in the operations of a plurality of arithmetic tasks in the controller 6. Thus, there are no differences in the operation results of each controller 6 having a plurality of CPU cores. Therefore, even when a control switch to another controller 6 is performed when a malfunction or the like occurs in a specific controller 6, the output signal to the control object does not suddenly change. As a result, it is possible to appropriately implement control based on high-level logical operations using the multiplexed controller 6 having a plurality of CPU cores.

[0084] In addition, within the scope not exceeding the gist of the present disclosure, the constituent elements in the above-described embodiment can be appropriately replaced with well-known constituent elements, and in addition, the above-described embodiments can be appropriately combined.

[0085] For example, the content described in each of the above embodiments is grasped as follows.

[0086] (1) A control system according to one aspect includes a plurality of controllers multiplexed with each other, the controllers having a plurality of CPU cores capable of performing a logical operation including a plurality of arithmetic tasks for controlling a control object. In the control system,

[0087] Each of the plurality of controllers includes:

[0088] A first local data arrangement storage unit that stores the operation results of the plurality of arithmetic tasks as a first local data arrangement;

[0089] A second local data arrangement storage unit that stores the operation results received from other controllers as a second local data arrangement;

[0090] A global data arrangement storage unit that stores data elements selected from the first local data arrangement and the second local data arrangement as a global data arrangement that can be referred to among the plurality of arithmetic tasks; and

[0091] A trace data transmission unit that transmits the first local data arrangement as trace data to the other controllers.

[0092] According to the solution in (1) above, in each of the multiplexed controllers with multiple CPU cores, the operation results of multiple operation tasks are stored as a first local data arrangement. Each data element stored in the first local data arrangement is sent as tracking data to other controllers, and thus, a second local data arrangement is stored in other controllers. Each data element received from the first local data arrangement of other controllers as tracking data is stored in the second local data arrangement. Data elements selected from the first local data arrangement and the second local data arrangement stored in this way are stored in the global data arrangement and can be referred to in the operations of multiple operation tasks in this controller. Therefore, there will be no difference in the operation results of each controller with multiple CPU cores. As a result, even when a control switch to other controllers is performed in the case of a malfunction or the like in a specific controller, the output signal to the controlled object will not mutate. As a result, it is possible to appropriately implement control based on high-level logical operations using the multiplexed controllers with multiple CPU cores.

[0093] (2) In other solutions, in the solution in (1) above,

[0094] The global data arrangement is selected in such a way as to have an intermediate value between the first local data arrangement and the second local data arrangement.

[0095] According to the solution in (2) above, by adopting the intermediate value between the first local data arrangement and the second local data arrangement as the global data arrangement, it is possible to effectively prevent differences in the operation results of each controller.

[0096] (3) In other solutions, in the solution in (1) or (2) above,

[0097] The multiple operation tasks include:

[0098] A first operation task that executes the logic slice group with the shortest control cycle among the multiple logic slice groups obtained by dividing the multiple logic slices included in the controller capable of performing the logic operation for each control cycle; and

[0099] The Nth operation task (where N = 2, 3,...), which has a control cycle n times (n = 1, 2,...) that of the first operation task, and executes the multiple logic slice groups in ascending order of the control cycle.

[0100] According to the solution in (3) above, when multiple operation tasks including the first operation task and the Nth operation task are executed in multiple CPU cores, it is possible to effectively prevent differences in the operation results between the multiplexed controllers.

[0101] (4) In other solutions, in the solution in (3) above,

[0102] The plurality of CPU cores includes:

[0103] A first CPU core that executes the first arithmetic task; and

[0104] A second CPU core that executes the Nth arithmetic task.

[0105] According to the solution in (4) above, the first arithmetic task including the logic slice group with the shortest control period is assigned to the first CPU core, and the other Nth arithmetic tasks are assigned to the second CPU core. Thus, in a control system where a controller with multiple CPU cores is reused, efficient arithmetic operations can be performed.

[0106] (5) In other solutions, in the solution in (4) above,

[0107] The plurality of controllers synchronize the execution timing of the first arithmetic task in the first CPU core.

[0108] According to the solution in (5) above, in each of the reused controllers, it is controlled to synchronize the execution timing of the first arithmetic task in the first CPU core.

[0109] (6) In other solutions, in the solution in (4) above,

[0110] The Nth arithmetic task in the second CPU core is awakened by the first arithmetic task executed by the first CPU core.

[0111] According to the solution in (6) above, in each of the reused controllers, it is controlled to awaken the Nth arithmetic task executed by the second CPU core through the first arithmetic task executed by the first CPU core.

[0112] (7) In other solutions, in any one of the solutions in (1) to (6) above,

[0113] The plurality of arithmetic tasks include arithmetic operations with a processing time equal to or greater than a specified value.

[0114] According to the solution in (7) above, by making the processing time equal to or greater than a specified value such as convergence calculation and learning calculation, it is possible to appropriately perform arithmetic operations including arithmetic operation logics of operation objects that may exceed a pre-assumed control period through a control system having a reused controller with multiple CPU cores.

[0115] (8) A control method of a control system in one solution is a control method of a control system having a plurality of controllers reused with each other. The controller has a plurality of CPU cores capable of performing logical operations including a plurality of arithmetic tasks for controlling a control object. In the control method of the control system, the following processes performed in each of the plurality of controllers are included:

[0116] Store the operation results of the multiple operation tasks as a first local data arrangement;

[0117] Store the operation results received from other controllers as a second local data arrangement;

[0118] Store the data elements selected from the first local data arrangement and the second local data arrangement as a global data arrangement that can be referenced among the multiple operation tasks; and

[0119] Send the first local data arrangement as trace data to the other controllers.

[0120] According to the solution in (8) above, in each of the multiplexed controllers with multiple CPU cores, the operation results of multiple operation tasks are stored as a first local data arrangement. Each data element stored in the first local data arrangement is sent as trace data to other controllers, and thus is stored in the second local data arrangement of the other controllers. Each data element received from the first local data arrangement of other controllers as trace data is stored in the second local data arrangement. The data elements selected from the first local data arrangement and the second local data arrangement stored in this way are stored in the global data arrangement and can be referenced in the operations of multiple operation tasks in the controller. Therefore, there will be no difference in the operation results of each controller with multiple CPU cores. As a result, even when a control switch is made to other controllers in the case of a malfunction or the like in a specific controller, the output signal to the controlled object will not suddenly change. As a result, a multiplexed controller with multiple CPU cores can be used to appropriately implement control based on high-level logical operations.

[0121] (9) The control program of a control system in one solution is the control program of a control system with multiple controllers multiplexed with each other. The controller has multiple CPU cores capable of performing logical operations including multiple operation tasks for controlling a controlled object. In the control program of the control system,

[0122] It can cause a computer device to execute the following processes in each of the multiple controllers:

[0123] Store the operation results of the multiple operation tasks as a first local data arrangement;

[0124] Store the operation results received from other controllers as a second local data arrangement;

[0125] Store the data elements selected from the first local data arrangement and the second local data arrangement as a global data arrangement that can be referenced among the multiple operation tasks; and

[0126] Arrange the first local data as trace data and send it to the other controller.

[0127] According to the solution in (9) above, in each of the multiplexed controllers with multiple CPU cores, the operation results of multiple operation tasks are stored as the first local data arrangement. Each data element stored in the first local data arrangement is sent to other controllers as trace data, whereby the second local data arrangement is stored in other controllers. Each data element received from the first local data arrangement of other controllers as trace data is stored in the second local data arrangement. The data elements selected from the first local data arrangement and the second local data arrangement stored in this way are stored in the global data arrangement and can be referred to in the operations of multiple operation tasks in this controller. Therefore, there will be no difference in the operation results of each controller with multiple CPU cores. As a result, even when a control switch is made to other controllers in the case of a malfunction or the like occurring in a specific controller, the output signal to the control object will not suddenly change. As a result, it is possible to appropriately implement control based on high-level logical operations using the multiplexed controller with multiple CPU cores.

Claims

1. A control system comprising a plurality of controllers that are multiplexed with each other, wherein the controllers have a plurality of CPU cores that can execute logical operations including a plurality of operation tasks for controlling a control object, wherein: Each of the plurality of controllers comprises: A first local data arrangement storage unit stores the calculation results of the plurality of calculation tasks as a first local data arrangement; A second local data arrangement storage unit stores the calculation results received from other controllers as a second local data arrangement; a global data array storage unit that stores data elements selected from the first local data array and the second local data array as a global data array that can be referenced between the plurality of computing tasks; and The tracking data sending unit sends the first local data array as tracking data to the other controller.

2. The control system according to claim 1, wherein: The global data arrangement is selected in such a manner as to have an intermediate value between the first local data arrangement and the second local data arrangement.

3. The control system according to claim 1 or 2, wherein: The multiple computing tasks include: A first operation task is to execute a logic slice group having the shortest control cycle among a plurality of logic slice groups formed by dividing a plurality of logic slices included in a controller capable of executing the logic operation according to each control cycle; and The Nth operation task has a control period that is n times that of the first operation task, and executes the multiple logic slice groups in order from short to long control period, where N=2, 3, ..., n=1, 2, ...

4. The control system according to claim 3, wherein: The multiple CPU cores include: A first CPU core is used to execute the first computing task; and The second CPU core executes the Nth computing task.

5. The control system according to claim 4, wherein: The plurality of controllers synchronize execution timings of the first computing tasks in the first CPU core.

6. The control system according to claim 4, wherein: The Nth computing task in the second CPU core is awakened by the first computing task executed by the first CPU core.

7. The control system according to claim 1 or 2, wherein: The plurality of computation tasks include computations whose processing time is equal to or longer than a predetermined value.

8. A control method of a control system, comprising a plurality of controllers that are multiplexed with each other, wherein the controllers have a plurality of CPU cores that can execute logical operations including a plurality of operation tasks for controlling a control object, wherein the control method of the control system comprises the following steps performed in each of the plurality of controllers: storing the computing results of the plurality of computing tasks as a first local data arrangement; storing the operation results received from other controllers as a second local data arrangement; storing data elements selected from the first local data array and the second local data array as a global data array that can be referenced among the plurality of computing tasks; and The first local data arrangement is sent to the other controller as tracking data.

9. A control program of a control system, comprising a plurality of controllers that are reused, the controllers having a plurality of CPU cores capable of executing logical operations including a plurality of operation tasks for controlling a control object, wherein: The computer device can be caused to execute the following steps in each of the plurality of controllers: storing the computing results of the plurality of computing tasks as a first local data arrangement; storing the operation results received from other controllers as a second local data arrangement; storing data elements selected from the first local data array and the second local data array as a global data array that can be referenced among the plurality of computing tasks; and The first local data arrangement is sent to the other controller as tracking data.

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