Device power-on control method and device, storage medium, and electronic device

Abstract

The present application discloses a device power-on control method and apparatus, a storage medium, and an electronic device, and relates to the field of computer hardware technology. The method comprises: when a clock buffer group is powered on, receiving a reference clock signal transmitted from a host end through the clock buffer group, and converting the received reference clock signal into an output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to a control component; detecting a signal state of the output clock signal of the clock buffer group through the control component, and performing power-on control on a hardware device through the control component based on the detected signal state, and performing power-on control on a hardware device through the control component after converting the reference clock signal and distributing it to the control component, and performing power-on control on the device based on the signal state, thereby solving the technical problem of low stability of the device power-on control method in the related art due to limited power-on timing control.

Description

Technical Field

[0001] The present application relates to the field of computer hardware technology, and in particular to a method and apparatus for controlling power-on of a device, a storage medium, and an electronic device. Background Art

[0002] To meet the high demands of server performance, a multi-module architecture combined with a universal baseboard can be adopted, with the host side providing the baseboard with a reference clock signal for initialization and data transmission. However, in this case, the hardware devices on the universal baseboard need to rely on the reference clock signal for power-on timing control. The host side needs to adapt the firmware according to the power-on and power-off timing of the UBB board (Universal Baseboard), or readjust and retest the firmware on the UBB board when the host side's power-on strategy changes. This adjustment not only increases the workload of firmware development and verification, but also may cause compatibility issues when facing diverse server hardware configurations, increasing the risk of device initialization errors and system instability.

[0003] It can be seen that the device power-on control method in the related art has a technical problem of low stability due to limited power-on timing control. Summary of the Invention

[0004] The present application provides a device power-on control method and apparatus, a storage medium, and an electronic device to at least solve the technical problem of low stability caused by limited power-on timing control in the device power-on control method in the related art.

[0005] The present application provides a device power-on control method applied to an electronic device, wherein the electronic device includes a clock buffer group, a control component and a hardware device, wherein the clock buffer group is connected to the control component; the method includes: when the clock buffer group is powered on, receiving a reference clock signal transmitted from a host end through the clock buffer group, and converting the received reference clock signal into an output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component; detecting a signal state of the output clock signal of the clock buffer group through the control component, and based on the detected signal state, performing power-on control on the hardware device through the control component.

[0006] The present application also provides a device power-on control apparatus, which is applied to an electronic device, wherein the electronic device includes a clock buffer group, a control component and a hardware device, wherein the clock buffer group is connected to the control component; the apparatus includes: a first execution unit, which is used to receive a reference clock signal transmitted from a host end through the clock buffer group when the clock buffer group is powered on, and convert the received reference clock signal into an output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component; a second execution unit, which is used to detect a signal state of the output clock signal of the clock buffer group through the control component, and based on the detected signal state, perform power-on control on the hardware device through the control component.

[0007] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned device power-on control methods when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned device power-on control methods are implemented.

[0009] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned device power-on control methods when executed by a processor.

[0010] Through the present application, when the clock buffer group is powered on, the reference clock signal transmitted from the host side is received by the clock buffer group, and the received reference clock signal is converted into the output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component; the signal state of the output clock signal of the clock buffer group is detected by the control component, and based on the detected signal state, the hardware device is powered on by the control component, and the reference clock signal transmitted from the host side received by the clock buffer is directly distributed to the control component, and the reference clock signal is monitored and detected in real time by the control component, and the power-on control of the hardware device is dynamically adjusted based on the signal state of the detected reference clock signal. Therefore, the technical problem of low stability caused by limited power-on timing control in the device power-on control method in the related technology can be solved, thereby achieving the technical effect of improving the accuracy and reliability of device power-on control. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A schematic diagram of an application scenario of a device power-on control method provided in an embodiment of the present application.

[0013] Figure 2 The figure is a flowchart of an optional device power-on control method according to an embodiment of the present application.

[0014] Figure 3 Schematic diagram of an optional device power-on control method according to an embodiment of the present application.

[0015] Figure 4 Schematic diagram of another optional device power-on control method according to an embodiment of the present application.

[0016] Figure 5 4 is a flow chart of another optional device power-on control method according to an embodiment of the present application.

[0017] Figure 6 Schematic diagram of another optional device power-on control method according to an embodiment of the present application.

[0018] Figure 7 Schematic diagram of a circuit for an optional device power-on control method according to an embodiment of the present application.

[0019] Figure 8 This is a structural block diagram of an optional device power-on control apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0022] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0023] According to one aspect of the embodiment of the present application, a device power-on control method is provided. Optionally, in this embodiment, the device power-on control method can be applied to Figure 1 In the hardware environment constituted by the electronic device 101 shown in FIG. Figure 1 As shown, the electronic device 101 may include a clock buffer group 1011, a control component 1012 and a hardware device 1013, wherein the clock buffer group 1011 is connected to the control component 1012. Figure 2 FIG. 1 is a flow chart of an optional device power-on control method according to an embodiment of the present application, such as Figure 2 As shown, the process of this method includes the following steps:

[0024] Step S202: When the clock buffer group is powered on, a reference clock signal transmitted from the host is received through the clock buffer group, and the received reference clock signal is converted into an output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component;

[0025] Step S204 : detecting the signal state of the output clock signal of the clock buffer group through the control component, and performing power-on control on the hardware device based on the detected signal state through the control component.

[0026] The device power-on control method in this embodiment can be applied to the field of computer hardware technology, and can be applied to the scenario of powering on hardware devices on a universal substrate.

[0027] With the advancement of informatization, servers, as the infrastructure of data centers and cloud computing platforms, play a vital role. Breakthroughs in artificial intelligence (AI) in recent years have further increased demand for high-performance AI servers, particularly those designed to handle large-scale machine learning (ML) and deep learning (DL) models and high-performance computing (HPC) tasks. AI applications often require rapid processing of massive amounts of data, real-time feedback from model training, and complex parallel computing capabilities. However, these requirements are difficult to meet with traditional PCIe CEM (PCI Express Card Electromechanical Specification) form factors. Although CEM cards dominated early server designs, their physical size limitations and signal integrity considerations have limited support for high-bandwidth AI workloads. In particular, CEM card designs lack targeted optimization for scenarios requiring fast, reliable data transmission and flexible interconnection.

[0028] To this end, new UBB architectures and hardware designs have emerged, such as the Open Accelerator Module (OAM) module. Designed specifically for accelerating AI and HPC computing, OAM modules offer higher bandwidth and interconnect flexibility than traditional PCIe CEM cards. Typically, an AI server integrates multiple OAM modules, with unified management and signal distribution via the UBB board. This creates an efficient and scalable computing platform that enhances multi-module parallel processing capabilities without sacrificing signal integrity or system stability.

[0029] To meet the high-performance requirements of this architecture, a new interface specification has been proposed to optimize signal transmission efficiency and timing control between the UBB and the host. Within this specification, the host is required to provide the UBB with a set of reference clock signals for initialization and data transmission. This can affect the startup, configuration, and data transmission rates of hardware devices on the universal baseboard. It is not only crucial for proper device startup but also a crucial foundation for high-bandwidth data exchange and optimized system performance.

[0030] It's important to note that hardware devices on the baseboard are typically extremely sensitive to timing control during power-up and power-down. The orderly arrival of power and reset signals, as well as the stability and availability of reference clock signals, are essential factors in ensuring the proper startup and operation of hardware devices on the baseboard. Improper timing control can prevent devices from initializing properly, or lead to data transmission errors, system hangs, or even hardware damage during operation, seriously impacting the overall performance and stability of the server.

[0031] Optionally, taking a PCIe (Peripheral Component Interconnect Express) device as an example, the host side can provide three stable and reliable 100MHz (megahertz) clock signals to the universal baseboard to support the normal operation of each PCIe device on the UBB board. The transmission of this reference clock signal can be input into the clock buffer, which is then strengthened and distributed. That is, the clock buffer can be used to replicate and amplify the single 100MHz clock signal from the host side to generate multiple identical clock signals, which are then evenly distributed to all PCIe devices on the UBB board.

[0032] For example, Figure 3 As shown in the figure, the three PCIe 100MHz reference clock signals input from the host end (which can be transmitted through the connector) can be connected to three clock buffers respectively, and the generated clock signals (including the main reference clock signal and the auxiliary reference clock signal) can be provided to 8 PCIe retimers and 8 OAMs respectively.

[0033] Optionally, only two of the three reference clock signals may be used, for example, Figure 4 As shown in the figure, two of the three PCIe 100MHz reference clocks input from the host, CLK_REFCLK_0_DP / DN (reference clock signal_0) and CLK_REFCLK_1_DP / DN (reference clock signal_1), can be connected to two clock buffers respectively. These signals are subdivided into modular outputs and provided to the retimer, OAM, and expansion slot respectively.

[0034] However, in this scenario, the power-on of hardware devices on the universal baseboard is controlled according to a preset timing strategy. The host must consider the UBB board's dependence on clock signals when designing the power-on timing firmware. Adjust the firmware according to the UBB board's power-on and power-off timing to ensure a stable clock signal supply and coordinate with the device power-on sequence. Consequently, once the host's power-on strategy changes, the firmware on the UBB board must be readjusted and tested to ensure that all PCIe devices initialize with the correct clock signal state to avoid power-on failures or device malfunctions. In other words, in some cases, when the host's timing is fixed and the UBB board needs to adapt to different server environments, the UBB board's firmware may need to be modified to adjust the device's power-on and power-off timing to synchronize it with the host's clock signal state. This adjustment not only increases the workload of firmware development and verification, but also can lead to compatibility issues with diverse server hardware configurations, increasing the risk of device initialization errors and system instability.

[0035] It can be seen that in the power-on and power-off logic control of the server system, the control components are in a passive state and rely on the preset firmware strategy to make power-on control decisions. This limitation not only affects the accuracy and reliability of device initialization and fails to adjust the device power-on in time when the clock signal changes, but also restricts the adaptability and compatibility of the server system in different hardware environments. That is, the device power-on control method in the relevant technology has a technical problem of low stability due to limited power-on timing control.

[0036] In order to at least partially solve the above technical problems, a device power-on control method is provided in the present embodiment. When the clock buffer group is powered on, the reference clock signal transmitted from the host end is received by the clock buffer group, and the received reference clock signal is converted into the output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component; the signal state of the output clock signal of the clock buffer group is detected by the control component, and based on the detected signal state, the hardware device is powered on by the control component. By directly distributing the reference clock signal transmitted from the host end received by the clock buffer to the control component, the control component monitors and detects the reference clock signal in real time, and dynamically adjusts the power-on control of the hardware device based on the signal state of the detected reference clock signal, the technical problem of low stability caused by limited power-on timing control in the device power-on control method in the related technology can be solved, thereby achieving the technical effect of improving the accuracy and reliability of device power-on control.

[0037] Optionally, the above-mentioned device power-on control method can be applied to an electronic device, which includes a clock buffer group, a control component and a hardware device, wherein the clock buffer group is connected to the control component, so that the clock buffer can directly send its output clock signal to the control component.

[0038] Optionally, when the clock buffer group is powered on, the reference clock signal transmitted by the host side according to a predefined signal standard and interface protocol can be received through the clock buffer group, and the received reference clock signal can be received.

[0039] Optionally, after receiving the reference clock signal, the clock buffer group can optimize and convert the reference clock signal level, impedance and frequency characteristics through its internal signal processing circuit, and convert it into the output clock signal of the clock buffer group. The processing method for the reference clock signal can be pre-set and can include but is not limited to: amplifying the reference clock signal and copying the reference clock signal.

[0040] Optionally, the output clock signal of the clock buffer group can be distributed to multiple targets, for example, can be distributed to the control component, so that the control component can perform real-time detection of the output clock signal distributed by the clock buffer group through its internal integrated signal detection hardware.

[0041] The above-mentioned control component can be a CPLD (Complex Programmable Logic Device), or it can be other control components such as an FPGA (Field Programmable Gate Array), an MCU (Microcontroller Unit) or a BMC (Baseboard Management Controller), which is not limited in this embodiment.

[0042] Optionally, the control component can control the power-on of the hardware device based on the detected signal status according to a preset algorithm. For example, if the signal frequency is lower than expected, the control component can delay or pause the power-on of the device until the signal becomes stable again; conversely, when the signal status is good, the device is allowed to continue to power on until the initialization process is completed.

[0043] Optionally, the control component may have built-in signal detection hardware, such as a phase-locked loop (PLL) module, to perform real-time evaluation of the frequency, phase, amplitude, and jitter of the signal. Here, the phase-locked loop is an electronic circuit based on the negative feedback control principle, which can be used to capture and lock the frequency and phase of the input signal using mechanisms such as phase detection, loop filtering, and frequency adjustment. In this embodiment, the phase-locked loop module can be used to quickly capture the clock signal and compare and adjust the phase and frequency to ensure the stability and quality of the signal. Once the signal reaches a stable locked state, a feedback signal can be sent to the control component.

[0044] The above-mentioned process of power-on control of the hardware device may include the process of controlling the hardware device to receive power and the process of controlling the hardware device to complete initialization. The control of the hardware device to complete initialization may be completed by sending a control signal to the hardware device, that is, the above-mentioned hardware device first receives current input from the power supply, and then initializes the device after the control component sends the control signal, thereby completing the complete power-on process of the hardware device.

[0045] Implementation of the aforementioned device power-on control method allows for greater flexibility in the design of server power-on sequences. Specifically, in server systems, the UBB board previously had a tight timing coupling relationship with other boards, such as the motherboard or switch board. This coupling relationship, to a certain extent, limited the flexibility of server power-on sequence design. By effectively monitoring the reference clock signal, the degree of timing coupling between the UBB and other boards can be reduced, providing greater flexibility in server power-on sequence design.

[0046] Furthermore, when UBB is applied to servers with different platforms and architectures, complex design adjustments are typically required for each platform and architecture, a cumbersome and inefficient process. However, based on the embodiments of the present application, UBB is much simpler and more convenient to operate when adapting to servers with different platforms and architectures, greatly enhancing its flexibility. This not only improves UBB's versatility, enabling it to operate efficiently in a variety of server environments, but also reduces development costs and time.

[0047] Through the embodiments provided by the present application, when the clock buffer group is powered on, the reference clock signal transmitted from the host side is received by the clock buffer group, and the received reference clock signal is converted into the output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component; the signal state of the output clock signal of the clock buffer group is detected by the control component, and based on the detected signal state, the power-on control of the hardware device is performed by the control component, which can solve the technical problem of low stability caused by limited power-on timing control in the device power-on control method in the related art, and achieve the technical effect of improving the accuracy and reliability of the device power-on control.

[0048] In an exemplary embodiment, the clock buffer group is also connected to a hardware device, and based on the detected signal status, the hardware device is powered on by a control component, including: when it is detected that the output clock signal of the clock buffer group is connected, the hardware device is controlled to be powered on by the control component, wherein after the hardware device is powered on, the output clock signal of the clock buffer group is also distributed to the hardware device; when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches a signal frequency threshold, a reset signal is released to the hardware device by the control component to reset the hardware device.

[0049] In this embodiment, the clock buffer group may also be connected to a hardware device, so that the clock buffer group may distribute its processed output clock signal to the hardware device.

[0050] Optionally, when the control component detects that the output clock signal of the clock buffer group has been connected, it can start the power-on process of the hardware device.

[0051] First, the control component can control the hardware device to power on, that is, control the hardware device to obtain current input from the power supply. After the hardware device is powered on, the hardware device can receive the output clock signal from the clock buffer group.

[0052] After that, the control component can continuously monitor the signal frequency of the output clock signal of the clock buffer group. Here, a signal frequency threshold can be set in advance. When the output clock signal of the clock buffer group reaches the signal frequency threshold, it can be considered that the clock signal has stabilized. For example, for PCIe devices, this clock signal threshold can be 100MHz.

[0053] Optionally, in order to adapt to the differences in different environments and devices, the control component may allow modification of the signal frequency threshold. The signal frequency threshold may be pre-set with a modification range. For example, the custom range of the signal frequency threshold may be set to cover from 99.9 MHz to 100.1 MHz.

[0054] Optionally, when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches the signal frequency threshold, the control component can release a reset signal to the hardware device, thereby completing the initialization process of the hardware device and ensuring that the device can enter a normal working state under the drive of a stable clock signal.

[0055] Optionally, a time window for judging the stability of the signal frequency threshold can be set. This time window is used to measure the minimum time requirement for the clock signal to remain continuously within the threshold range after reaching the preset frequency threshold. Only when the signal remains continuously and stably within the specified frequency range during this time window, the control component will determine that the clock signal has stabilized and execute subsequent hardware device control operations accordingly, such as releasing the reset signal.

[0056] For example, a signal frequency threshold stabilization time window can be defined and set to 500 milliseconds (ms). The control component can consider the signal stable after detecting that the clock signal frequency reaches a preset threshold and continuously monitoring the signal to remain within this frequency range for at least 500ms.

[0057] Optionally, the PLL module or other signal detection component within the control unit can be equipped with continuous monitoring capabilities. For example, upon detecting that the signal first reaches a threshold, the control unit can start an internal timer to begin recording the duration that the signal remains within the threshold. The control unit will only consider the signal stable when the timer reading reaches a preset time window.

[0058] Optionally, the length of the time window for signal stability judgment can be dynamically adjusted according to changes in environmental conditions (such as temperature fluctuations, power supply stability). It can be adjusted automatically or manually, which is not limited in this embodiment.

[0059] Through this embodiment, by controlling the hardware device to power on when the output clock signal of the clock buffer is detected, and then controlling the hardware device to reset when the output clock signal of the clock buffer is detected to be stable, the stability and reliability of the device power-on control can be improved.

[0060] In an exemplary embodiment, a clock buffer group, a control component and a hardware device are located on the same substrate and are connected through a peripheral device interconnect bus. The hardware device is a peripheral device interconnect device, and the number of hardware devices is at least two. When it is detected that the signal frequency of the output clock signal of the clock buffer group reaches a signal frequency threshold, a reset signal is released to the hardware device through the control component, including: when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches the signal frequency threshold, a reset signal is released on the peripheral device interconnect bus through the control component to reset at least two hardware devices.

[0061] In this embodiment, the clock buffer group, the control component and the hardware device are located on the same substrate and are connected through a peripheral device interconnect bus. The hardware device is a peripheral device interconnect device. When the control component detects that the output clock signal frequency of the clock buffer group reaches a preset signal frequency threshold, it can release a reset signal to at least two hardware devices through the peripheral device interconnect bus. This reset signal is designed to be recognized and responded to by all hardware devices connected to the bus, that is, the control component can broadcast the reset signal to all related hardware devices through the peripheral device interconnect bus, which is a shared communication path, to ensure that all devices can be reset and initialized synchronously, thereby achieving system-level coordination and stable operation.

[0062] Optionally, the number of hardware devices is at least two, that is, there may be multiple hardware devices on the same substrate, and the multiple hardware devices may be the same type of devices or different types of devices. For example, the hardware devices on the same substrate may include a PCIe retimer, OAM or expansion slot, which is not limited in this embodiment.

[0063] In this embodiment, the clock buffer group on the substrate can receive a reference clock signal (i.e., the master clock signal) from the host end, and can enhance the signal strength of the master clock signal to compensate for the attenuation and distortion of the signal during transmission on the substrate. At the same time, the clock buffer also has the function of signal bifurcation and replication, and can replicate and convert a single master clock signal into multiple identical clock signals. Each signal has the same frequency and phase as the master clock or has been appropriately adjusted. In this process, the clock buffer can use its internal clock replication and distribution network to ensure that the quality of the clock signal is not affected by the number of replications. Therefore, the multiple clock signals output by it can be distributed to the clock input ports of various hardware devices through the wiring on the substrate.

[0064] Through this embodiment, by generating and distributing multiple clock signals to multiple hardware devices on the same substrate through a clock buffer group, and uniformly resetting multiple hardware devices, the power-on process of the hardware devices can be optimized and the stability of the power-on control of the devices can be improved.

[0065] In an exemplary embodiment, the above method also includes: in response to a power-on indication signal from the host side, controlling the clock buffer group to power on through a control component, and opening the output channel of the clock buffer group, wherein the output clock signal of the clock buffer group is transmitted through the output channel of the clock buffer group.

[0066] In this embodiment, when the hardware device on the substrate needs to be powered on, the host side can send a power-on indication signal to the control component on the substrate to instruct the control component on the substrate to start the power-on process, which can be sent through the peripheral interconnect bus; in response to the power-on indication signal from the host side, the control component can control the clock buffer group to power on and open its output channel.

[0067] Optionally, after receiving the power-on command, the clock buffer is powered on to start working its internal circuit components and activate the output channel, which allows the main clock signal to be transmitted through the channel to downstream hardware devices, such as PCIe retimers, OAM modules, etc.

[0068] For example, Figure 5 As shown in the figure, the control components (such as the CPLD) on the UBB board receive a power-on signal from the host. This controls the clock buffer to power on and open its channels, preparing for subsequent reception of the host's reference clock. Once the clock signal is received, the CPLD then controls the power-on of devices such as the PCIe board and continuously monitors the clock status. When the CPLD detects that the PCIe 100MHz reference clock frequency reaches 100MHz and remains stable, it releases the PCIe reset signal, thereby enabling the normal power-on of all PCIe devices on the UBB board.

[0069] Through this embodiment, by controlling the clock buffer group to power on and open its output channels when the host sends a power-on instruction, the accuracy of controlling the power-on timing of multiple devices can be improved.

[0070] In an exemplary embodiment, a clock buffer group includes a first clock buffer and a second clock buffer; a reference clock signal transmitted from a host end is received through the clock buffer group, and the received reference clock signal is converted into an output clock signal of the clock buffer group, including: receiving a first reference clock signal transmitted from the host end through the first clock buffer, and converting the first reference clock signal into an output clock signal of the first clock buffer; receiving a second reference clock signal transmitted from the host end through the second clock buffer, and converting the second reference clock signal into an output clock signal of the second clock buffer; wherein the reference clock signals transmitted from the host end include the first reference clock signal and the second reference clock signal.

[0071] In this embodiment, the host side can be configured with two central processing units to improve its parallel processing capability and system redundancy. Correspondingly, each reference clock signal on the host side can be provided by an independent clock source (for example, a clock generator inside the processor). In order to support the input and processing of such multiple clock signals, the clock buffer group can include a first clock buffer and a second clock buffer, each buffer being specifically responsible for processing and forwarding the reference clock signal from a CPU.

[0072] Optionally, the first clock buffer can use the first reference clock signal corresponding to the first processor to perform amplification, shaping and frequency lock on the received clock signal. The processed signal can be used as the output clock signal of the first clock buffer and will be distributed to the hardware devices connected to the first processor. The control component can also decide when to release the power-on control of the hardware devices connected to the first processor based on the output clock signal status of the first clock buffer to ensure that the equipment can start under optimal conditions.

[0073] Similarly, the second clock buffer can also receive the second reference clock signal corresponding to the second processor, convert it into the output clock signal of the second clock buffer, and then transmit it in a direction to the hardware devices connected to the second processor. The control component controls the power-on process of these devices connected to the second processor based on the output clock signal status of the second clock buffer.

[0074] Optionally, when setting the hardware devices on the substrate, they can be set in different modules according to the corresponding situations with the processors, for example, Figure 6 As shown in the figure, two of the three PCIe 100MHz reference clocks (CLK_REFCLK_0_DP / DN and CLK_REFCLK_1_DP / DN) input from the host are connected to two clock buffers and provided to the corresponding retimer, open acceleration module, and expansion slot respectively. The output clocks of the clock buffers are synchronously connected to the differential signal input pins of the control component (such as CPLD) on the board that controls the power-on and power-off timing. The control component monitors the status of the PCIe 100MHz reference clock, ensuring that the CPLD on the UBB can achieve more precise power-on control of the PCIe device by monitoring the clock status.

[0075] Through this embodiment, the corresponding reference clock signal is converted into the corresponding output clock signal through multiple clock buffers. This modular signal processing and distribution can enhance the stability and performance of the server and improve the overall operating efficiency and reliability of the server.

[0076] In an exemplary embodiment, a level conversion circuit is connected between the output end of the clock buffer group and the input end of the control component; after receiving the reference clock signal transmitted from the host end through the clock buffer group and converting the received reference clock signal into the output clock signal of the clock buffer group, the above method also includes: adjusting the level state of the output clock signal of the clock buffer group to the target level state through the level conversion circuit, and inputting the adjusted output clock signal of the clock buffer group into the signal input end of the control component.

[0077] The clock buffer group's output clock signal typically uses a high-speed, low-power standard level, such as LP-HCSL (LowPower High Speed ​​Low Swing). However, the control component's input level may differ. For example, a CPLD may require LP-PECL (Low Voltage Positive Emitter Coupled Logic) levels. This means there may be a mismatch between the clock buffer group's output level and the control component's input level. Directly inputting the clock signal to the control component without level conversion can cause signal misinterpretation and even damage the control component, affecting overall system stability.

[0078] In this embodiment, a level conversion circuit can be connected between the output end of the clock buffer group and the input end of the control component to adjust the level state of the output clock signal of the clock buffer group to a level state that can be correctly identified by the control component, that is, the target level state.

[0079] For example, Figure 7 As shown, the PCIe 100 MHz reference clock signal output by the clock buffer can be sent to the control component CPLD on the substrate for controlling power on and off through a level conversion circuit between the clock buffer and the control component (eg, CPLD).

[0080] According to this embodiment, the output signal of the clock buffer is distributed to the control component after level conversion, thereby avoiding the risk of level mismatch and improving the stability of power-on control of the device.

[0081] In an exemplary embodiment, the frequency of the output clock signal of the clock buffer group is greater than the signal frequency of the clock signal of the control component itself; the above method further includes: inputting the output clock signal of the clock buffer group into a first phase-locked loop for clock frequency division to obtain the output clock signal of the clock buffer group after frequency division, wherein the signal frequency of the output clock signal of the clock buffer group after frequency division is less than the signal frequency of the clock signal of the control component itself; sampling the output clock signal of the clock buffer group after frequency division within the signal period of the clock signal of the control component itself to detect the signal state of the output clock signal of the clock buffer group; or,

[0082] Inputting the clock signal of the control component itself into the second phase-locked loop for clock multiplication to obtain the multiplied clock signal of the control component itself, wherein the signal frequency of the output clock signal of the clock buffer group is less than the signal frequency of the multiplied clock signal of the control component itself; sampling the output clock signal of the clock buffer group within the signal period of the multiplied clock signal of the control component itself by the control component to detect the signal state of the output clock signal of the clock buffer group; or

[0083] The output clock signal of the clock buffer group is input into the third phase-locked loop for clock division to obtain the output clock signal of the clock buffer group after division, and the clock signal of the control component itself is input into the fourth phase-locked loop for clock multiplication to obtain the clock signal of the control component itself after multiplication, wherein the signal frequency of the output clock signal of the clock buffer group after division is less than the signal frequency of the clock signal of the control component itself after multiplication; the output clock signal of the clock buffer group after division is sampled by the control component within the signal period of the clock signal of the control component itself after multiplication to detect the signal state of the output clock signal of the clock buffer group.

[0084] In this embodiment, the frequency of the output clock signal of the clock buffer group may be greater than the signal frequency of the clock signal of the control component itself. For example, taking the control component as a CPLD, the CPLD's own clock generally uses an external 25MHz crystal oscillator clock input, and the PCIE reference clock monitored by the CPLD is 100MHz. This frequency asymmetry means that directly using the CPLD's own clock for monitoring may not capture enough clock edges, resulting in inaccurate monitoring results. If the PCIE reference clock is to be monitored, the CPLD's own clock needs to be much higher than the monitored clock to ensure that the frequency of the PCIe reference clock can be accurately determined.

[0085] Optionally, the output clock signal of the clock buffer group can be input into the first phase-locked loop for clock division to obtain the output clock signal of the divided clock buffer group, wherein the signal frequency of the output clock signal of the divided clock buffer group is less than the signal frequency of the clock signal of the control component itself; the output clock signal of the divided clock buffer group is sampled by the control component within the signal period of the clock signal of the control component itself to detect the signal state of the output clock signal of the clock buffer group. For example, the 100MHz PCIe reference clock signal can be divided by the PLL phase-locked loop and converted into a 5MHz low-frequency signal, so that the CPLD can sample the 5MHz signal multiple times within its own 25MHz clock period, and 5 samples can be performed in each CPLD clock period, thereby realizing the frequency judgment of the monitored clock and improving the monitoring accuracy.

[0086] Optionally, the control component's own clock signal can be input into a second phase-locked loop (PLL) for clock multiplication to obtain a multiplied clock signal of the control component itself. The output clock signal of the clock buffer group has a frequency lower than the frequency of the multiplied clock signal of the control component itself. The control component samples the output clock signal of the clock buffer group within a signal cycle of the multiplied clock signal of the control component itself to detect the signal state of the output clock signal of the clock buffer group. For example, the CPLD's own clock (25 MHz) can be multiplied to 400 MHz through a PLL phase-locked loop, thereby increasing the CPLD's clock frequency. This allows the CPLD to sample the 100 MHz PCIe reference clock at least four times within each 400 MHz high-speed clock cycle, similarly achieving accurate determination of the monitored clock frequency.

[0087] Optionally, when the number of PLL phase-locked loops inside the CPLD is equal to or greater than two, two methods can be used simultaneously, namely, self-clock multiplication and monitored clock division, the output clock signal of the clock buffer group is input into the third phase-locked loop for clock division to obtain the output clock signal of the clock buffer group after division, and the clock signal of the control component itself is input into the fourth phase-locked loop for clock multiplication to obtain the clock signal of the control component itself after multiplication, wherein the signal frequency of the output clock signal of the clock buffer group after division is less than the signal frequency of the clock signal of the control component itself after multiplication; the control component samples the output clock signal of the clock buffer group after division within the signal period of the clock signal of the control component itself after multiplication to detect the signal state of the output clock signal of the clock buffer group, thereby combining the advantages of frequency increase and decrease, so that the CPLD can capture signal changes with higher resolution when monitoring the PCIe reference clock, and achieve more accurate frequency judgment.

[0088] Through this embodiment, by using a phase-locked loop to divide or multiply the clock signal, the control component can efficiently sample within its own clock cycle, which can improve the accuracy of clock status monitoring and further improve the accuracy of device power-on control.

[0089] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0090] According to another aspect of the embodiments of the present application, a device power-on control device is also provided, which can be used to implement the device power-on control method provided in the above embodiments, and will not be repeated here. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0091] Figure 8 This is a structural block diagram of an optional device power-on control device according to an embodiment of the present application, such as Figure 8 As shown in , the power-on control device of the device includes:

[0092] a first execution unit 802, configured to receive, through the clock buffer group, a reference clock signal transmitted from the host end, when the clock buffer group is powered on, and convert the received reference clock signal into an output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component;

[0093] The second execution unit 804 is configured to detect the signal state of the output clock signal of the clock buffer group through the control component, and perform power-on control on the hardware device through the control component based on the detected signal state.

[0094] It should be noted that the first execution unit 802 in this embodiment can be used to execute the above step S202, and the second execution unit 804 in this embodiment can be used to execute the above step S204.

[0095] Through the embodiments provided by the present application, when the clock buffer group is powered on, the reference clock signal transmitted from the host side is received by the clock buffer group, and the received reference clock signal is converted into the output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component; the signal state of the output clock signal of the clock buffer group is detected by the control component, and based on the detected signal state, the hardware device is powered on by the control component, which can solve the technical problem of low stability of the device power-on control device in the related technology due to limited power-on timing control, thereby achieving the technical effect of improving the accuracy and reliability of the device power-on control.

[0096] In an exemplary embodiment, the clock buffer group is also connected to the hardware device, and the second execution unit includes: a power-on module, which is used to control the power-on of the hardware device through the control component when it detects that the output clock signal of the clock buffer group is connected, wherein after the hardware device is powered on, the output clock signal of the clock buffer group is also distributed to the hardware device; a reset module, which is used to release a reset signal to the hardware device through the control component to reset the hardware device when it detects that the signal frequency of the output clock signal of the clock buffer group reaches a signal frequency threshold.

[0097] In an exemplary embodiment, a clock buffer group, a control component, and a hardware device are located on the same substrate and connected via a peripheral device interconnect bus. The hardware device is a peripheral device interconnect device, and the number of the hardware devices is at least two. The reset module includes: a reset submodule, which is used to release a reset signal on the peripheral device interconnect bus through the control component to reset the at least two hardware devices when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches a signal frequency threshold.

[0098] In an exemplary embodiment, the above-mentioned device also includes: a third execution unit, which is used to control the clock buffer group to power on through the control component in response to the power-on indication signal of the host side, and open the output channel of the clock buffer group, wherein the output clock signal of the clock buffer group is transmitted through the output channel of the clock buffer group.

[0099] In an exemplary embodiment, a clock buffer group includes a first clock buffer and a second clock buffer; a first execution unit includes: a first execution module, used to receive a first reference clock signal transmitted from a host end through the first clock buffer, and convert the first reference clock signal into an output clock signal of the first clock buffer; a second execution module, used to receive a second reference clock signal transmitted from a host end through a second clock buffer, and convert the second reference clock signal into an output clock signal of the second clock buffer; wherein the reference clock signals transmitted from the host end include the first reference clock signal and the second reference clock signal.

[0100] In an exemplary embodiment, a level conversion circuit is connected between the output end of the clock buffer group and the input end of the control component; the above-mentioned device also includes: a fourth execution unit, which is used to receive the reference clock signal transmitted from the host end through the clock buffer group and convert the received reference clock signal into the output clock signal of the clock buffer group, and then adjust the level state of the output clock signal of the clock buffer group to the target level state through the level conversion circuit, and input the adjusted output clock signal of the clock buffer group to the signal input end of the control component.

[0101] In an exemplary embodiment, the frequency of the output clock signal of the clock buffer group is greater than the signal frequency of the clock signal of the control component itself; the above-mentioned device also includes: a frequency dividing unit, which is used to input the output clock signal of the clock buffer group into the first phase-locked loop for clock division to obtain the output clock signal of the clock buffer group after frequency division, wherein the signal frequency of the output clock signal of the clock buffer group after frequency division is less than the signal frequency of the clock signal of the control component itself; the control component samples the output clock signal of the clock buffer group after frequency division within the signal period of the clock signal of the control component itself to detect the signal state of the output clock signal of the clock buffer group; or, a frequency multiplication unit, which is used to input the clock signal of the control component itself into the second phase-locked loop for clock multiplication to obtain the clock signal of the control component itself after frequency multiplication, wherein the signal frequency of the output clock signal of the clock buffer group is less than the signal frequency of the clock signal of the control component itself after frequency multiplication the signal frequency of its own clock signal; sampling the output clock signal of the clock buffer group within the signal period of the control component's own clock signal after frequency multiplication by the control component to detect the signal state of the output clock signal of the clock buffer group; or, a fifth execution unit, for inputting the output clock signal of the clock buffer group into the third phase-locked loop for clock division to obtain the output clock signal of the clock buffer group after frequency division, and inputting the clock signal of the control component itself into the fourth phase-locked loop for clock multiplication to obtain the clock signal of the control component itself after frequency multiplication, wherein the signal frequency of the output clock signal of the clock buffer group after frequency division is less than the signal frequency of the clock signal of the control component itself after frequency multiplication; sampling the output clock signal of the clock buffer group after frequency division within the signal period of the control component's own clock signal after frequency multiplication by the control component to detect the signal state of the output clock signal of the clock buffer group.

[0102] For the description of the features in the embodiments corresponding to the above-mentioned device power-on control apparatus, reference can be made to the relevant description of the embodiments corresponding to the device power-on control method, which will not be repeated here.

[0103] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps of any of the above-mentioned device power-on control method embodiments.

[0104] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned device power-on control method embodiments when run.

[0105] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0106] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned device power-on control method embodiments are implemented.

[0107] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of any of the above-mentioned device power-on control method embodiments.

[0108] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0109] The above is a detailed introduction to a device power-on control method and apparatus, storage medium, and electronic device provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A device power-on control method, characterized in that: Applied to an electronic device, the electronic device includes a clock buffer group, a control component, and a hardware device, wherein the clock buffer group is connected to the control component; the method includes: When the clock buffer group is powered on, the clock buffer group receives a reference clock signal transmitted from the host end, and converts the received reference clock signal into an output clock signal of the clock buffer group, wherein the output clock signal of the clock buffer group is distributed to the control component; detecting, by the control component, a signal state of an output clock signal of the clock buffer group, and performing power-on control on the hardware device by the control component based on the detected signal state; In which, the clock buffer group is also connected to the hardware device, and the power-on control of the hardware device is performed through the control component based on the detected signal status, including: when it is detected that the output clock signal of the clock buffer group is connected, the hardware device is controlled to be powered on through the control component, wherein after the hardware device is powered on, the output clock signal of the clock buffer group is also distributed to the hardware device; when it is detected that the signal frequency of the output clock signal of the clock buffer group reaches the signal frequency threshold, a reset signal is released to the hardware device through the control component to reset the hardware device; the control component has built-in signal detection hardware to perform real-time evaluation of the frequency, phase, amplitude and jitter of the signal.

2. The method according to claim 1, characterized in that The clock buffer group, the control component and the hardware device are located on the same substrate and are connected via a peripheral device interconnect bus, the hardware device is a peripheral device interconnect device, and the number of the hardware devices is at least two; When it is detected that the signal frequency of the output clock signal of the clock buffer group reaches a signal frequency threshold, releasing a reset signal to the hardware device through the control component includes: When it is detected that the signal frequency of the output clock signal of the clock buffer group reaches a signal frequency threshold, the control component releases a reset signal on the peripheral device interconnect bus to reset at least two of the hardware devices.

3. The method according to claim 1, characterized in that The method further comprises: In response to the power-on indication signal of the host end, the control component controls the clock buffer group to be powered on and opens the output channel of the clock buffer group, wherein the output clock signal of the clock buffer group is transmitted through the output channel of the clock buffer group.

4. The method according to claim 1, wherein The clock buffer group includes a first clock buffer and a second clock buffer; The step of receiving a reference clock signal transmitted from a host end through the clock buffer group and converting the received reference clock signal into an output clock signal of the clock buffer group includes: receiving a first reference clock signal transmitted by the host end through the first clock buffer, and converting the first reference clock signal into an output clock signal of the first clock buffer; receiving a second reference clock signal transmitted by the host end through the second clock buffer, and converting the second reference clock signal into an output clock signal of the second clock buffer; The reference clock signals transmitted by the host end include the first reference clock signal and the second reference clock signal.

5. The method according to claim 1, characterized in that A level conversion circuit is connected between the output terminal of the clock buffer group and the input terminal of the control component; After receiving the reference clock signal transmitted from the host end through the clock buffer group and converting the received reference clock signal into the output clock signal of the clock buffer group, the method further includes: The level state of the output clock signal of the clock buffer group is adjusted to a target level state through the level conversion circuit, and the adjusted output clock signal of the clock buffer group is input to the signal input terminal of the control component.

6. The method according to any one of claims 1 to 5, characterized in that The frequency of the output clock signal of the clock buffer group is greater than the signal frequency of the clock signal of the control component itself; The method further comprises: Inputting the output clock signal of the clock buffer group into a first phase-locked loop for clock frequency division to obtain the output clock signal of the clock buffer group after frequency division, wherein the signal frequency of the output clock signal of the clock buffer group after frequency division is less than the signal frequency of the clock signal of the control component itself; sampling the output clock signal of the clock buffer group after frequency division within the signal period of the clock signal of the control component itself by the control component to detect the signal state of the output clock signal of the clock buffer group; or Inputting the clock signal of the control component itself into a second phase-locked loop for clock multiplication to obtain the multiplied clock signal of the control component itself, wherein the signal frequency of the output clock signal of the clock buffer group is less than the signal frequency of the multiplied clock signal of the control component itself; sampling the output clock signal of the clock buffer group within the signal period of the multiplied clock signal of the control component itself by the control component to detect the signal state of the output clock signal of the clock buffer group; or The output clock signal of the clock buffer group is input into a third phase-locked loop for clock division to obtain the output clock signal of the clock buffer group after division, and the clock signal of the control component itself is input into a fourth phase-locked loop for clock multiplication to obtain the clock signal of the control component itself after multiplication, wherein the signal frequency of the output clock signal of the clock buffer group after division is less than the signal frequency of the clock signal of the control component itself after multiplication; the output clock signal of the clock buffer group after division is sampled by the control component within the signal period of the clock signal of the control component itself after multiplication to detect the signal state of the output clock signal of the clock buffer group.

7. A device power-on control device, characterized in that: Applied to electronic equipment, the electronic equipment includes a clock buffer group, a control component and a hardware device, wherein the clock buffer group is connected to the control component; the device includes: a first execution unit, configured to receive, through the clock buffer group, a reference clock signal transmitted from a host end, and convert the received reference clock signal into an output clock signal of the clock buffer group when the clock buffer group is powered on, wherein the output clock signal of the clock buffer group is distributed to the control component; a second execution unit, configured to detect a signal state of an output clock signal of the clock buffer group through the control component, and perform power-on control on the hardware device through the control component based on the detected signal state; In which, the clock buffer group is also connected to the hardware device, and the second execution unit includes: a power-on module, which is used to control the power-on of the hardware device through the control component when it detects that the output clock signal of the clock buffer group is connected, wherein after the hardware device is powered on, the output clock signal of the clock buffer group is also distributed to the hardware device; a reset module, which is used to release a reset signal to the hardware device through the control component to reset the hardware device when it detects that the signal frequency of the output clock signal of the clock buffer group reaches a signal frequency threshold; the control component has built-in signal detection hardware to perform real-time evaluation of the frequency, phase, amplitude and jitter of the signal.

8. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the device power-on control method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the device power-on control method according to any one of claims 1 to 6 are implemented.

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