Frequency control system, method, device, electronic device and storage medium

Abstract

The present application discloses a frequency control system, method, device, electronic device and storage medium, which relates to the field of computer technology. Through the present application, based on the statistics and analysis of the repetitive cycle law at the time point of the first system management interrupt, the triggering time of the second system management interrupt is set, thereby reducing unnecessary interrupts and reducing the negative impact of frequent interrupts on processor performance. After the second system management interrupt is triggered, the number of instructions executed by the processor between the two system management interrupts is obtained, the occupancy rate is calculated, and the processor frequency is adjusted in combination with the frequency control scheme corresponding to different occupancy rate intervals, so that the processor frequency adjustment is more in line with the actual load requirements. The problem of performance degradation caused by frequent interruptions is avoided, and the frequency is flexibly adjusted according to the actual workload, thereby solving the technical problem of frequent system management interrupts reducing processor performance in the prior art, and achieving the technical effect of achieving system energy saving while ensuring processor performance.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a frequency control system, method, device, electronic device and storage medium. Background Art

[0002] In order to achieve system energy saving, the operating frequency of the central processing unit (CPU) is adjusted to reduce power consumption, so that the energy saving effect of the computer system is optimized.

[0003] Currently, the CPU operating frequency is adjusted by calculating the CPU operating frequency occupancy after a System Management Interrupt (SMI interrupt) and adjusting the CPU operating frequency according to the CPU operating frequency occupancy. However, frequent SMI interrupts may reduce CPU performance. Summary of the Invention

[0004] The present application provides a frequency control system, method, device, electronic device and storage medium to at least solve the problem in the related art that frequent SMI interrupts may lead to reduced CPU performance.

[0005] The present application provides a frequency control system, comprising a basic input / output system, a baseboard management controller, and a shared memory; the shared memory is connected to the basic input / output system and the baseboard management controller respectively;

[0006] a baseboard management controller configured to determine, based on the time points of the first system management interrupts and the number of processor instructions between each first system management interrupt, a first repetition period and a time point at which the system management interrupt is generated in the first repetition period, and send the time point at which the system management interrupt is generated in the first repetition period to the shared memory;

[0007] The shared memory sends, in response to a first acquisition instruction of the basic input / output system, a time point at which the system management interrupt is generated in the first repetition cycle to the basic input / output system;

[0008] The basic input and output system is configured to perform frequency control on the processor according to a time point at which the system management interrupt is generated in the first repetition cycle.

[0009] This application provides a frequency control method, including:

[0010] determining a first repetition period and a time point at which the system management interrupt is generated in the first repetition period based on a time point of the first system management interrupt and a number of instructions of the processor between each first system management interrupt;

[0011] The time point of the first system management interrupt and the number of instructions of the processor between each first system management interrupt are obtained from the basic input and output system;

[0012] The frequency of the processor is controlled according to the time point when the system management interrupt is generated in the first repetition cycle.

[0013] The present application also provides a frequency control device, comprising:

[0014] a determining unit, configured to determine a first repetition period and a time point at which a system management interrupt is generated in the first repetition period based on a time point of the first system management interrupt and a number of instructions of the processor between each first system management interrupt;

[0015] The time point of the first system management interrupt and the number of instructions of the processor between each first system management interrupt are obtained from the basic input and output system;

[0016] The control unit is configured to control the frequency of the processor according to a time point at which the system management interrupt is generated in the first repetition period.

[0017] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned frequency control methods when executing the computer program.

[0018] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned frequency control methods are implemented.

[0019] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned frequency control methods when executed by a processor.

[0020] Through this application, since the repetitive cycle pattern is counted and analyzed based on the time point of the first system management interrupt, the triggering time of the second system management interrupt is set, thereby reducing the number of unnecessary interrupts and reducing the negative impact of frequent interrupts on processor performance. After the second system management interrupt is triggered, the number of instructions executed by the processor between the two system management interrupts is obtained, and the occupancy rate is calculated based on this. The processor frequency is adjusted in combination with the frequency control scheme corresponding to different occupancy rate intervals, so that the processor frequency adjustment is more in line with the actual load requirements. This method not only avoids the performance degradation problem caused by frequent interruptions, but also can flexibly adjust the frequency according to the actual workload. This can solve the technical problem of frequent system management interrupts reducing processor performance in the prior art, and achieve the technical effect of achieving system energy saving while ensuring processor performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A schematic diagram of a frequency control system provided by this application;

[0023] Figure 2 A schematic diagram of another frequency control system provided by this application;

[0024] Figure 3 A flow chart of a frequency control method provided by an embodiment of the present disclosure;

[0025] Figure 4 A time series diagram of instruction density provided in an embodiment of the present application;

[0026] Figure 5 A time series diagram of another instruction density provided in an embodiment of the present application;

[0027] Figure 6 A schematic diagram of a repetition cycle provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of confirming the time point of a system management interruption provided by an embodiment of the present application;

[0029] Figure 8 A schematic structural diagram of a frequency control device provided in an embodiment of the present disclosure;

[0030] Figure 9 A schematic structural diagram of another frequency control device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0033] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0034] The embodiment of the present application provides a frequency control system, please refer to Figure 1 , Figure 1 A schematic diagram of a frequency control system provided by an embodiment of the present application, the system includes a basic input and output system 101, a baseboard management controller 102 and a shared memory 103;

[0035] The shared memory is connected to the basic input and output system and the baseboard management controller respectively;

[0036] The baseboard management controller is configured to determine a first repetition period and a time point at which a system management interrupt is generated in the first repetition period based on a time point of the first system management interrupt and a number of processor instructions between each first system management interrupt, and send the time point at which the system management interrupt is generated in the first repetition period to the shared memory;

[0037] The shared memory sends the time point of generating the system management interrupt in the first repetition cycle to the basic input and output system in response to the first acquisition instruction of the basic input and output system;

[0038] The basic input and output system is configured to perform frequency control on the processor according to a time point when a system management interrupt is generated in the first repetitive cycle.

[0039] Frequency control systems are a key component of modern computer architecture, designed to optimize energy efficiency while maintaining system performance. By intelligently adjusting processor frequency, this frequency control system can significantly improve the system's energy efficiency, making it particularly suitable for power-sensitive scenarios such as high-performance computing, data centers, and embedded systems. This system utilizes a dynamic frequency adjustment mechanism based on system management interrupts. In some embodiments, the basic input / output system (BIOS) is the basic input / output system. Through the collaborative operation of the BIOS and the baseboard management controller (BMC), fine-grained control of processor frequency is achieved.

[0040] See also Figure 2 , Figure 2 This is a schematic diagram of another frequency control system provided by this application. In this frequency control system, the BIOS uses a high-precision timer to capture the triggering time of system management interrupts (SMIs) in real time and count the number of instructions executed by the processor between adjacent SMIs. This data is considered an important indicator of system load changes and can reflect the processor's workload over different time periods.

[0041] A BMC is a dedicated management unit independent of the main processor, typically based on the ARM or x86 architecture, with its own power supply and network connection. Its primary functions include monitoring system hardware status, managing system logs, and performing remote management. In a frequency control system, the BMC plays a key role in data analysis and decision-making. It retrieves SMI timing and instruction count data collected by the BIOS from shared memory, applies pattern recognition algorithms to analyze system operating patterns, and identifies recurring workload patterns (i.e., recurring cycles).

[0042] In some embodiments, the system further comprises:

[0043] The basic input / output system, after acquiring the time point of the first system management interrupt and the number of instructions of the processor between each of the first system management interrupts, sends the time point of the first system management interrupt and the number of instructions of the processor between each of the first system management interrupts to the shared memory;

[0044] The shared memory sends the time points of the first system management interrupts and the number of instructions of the processor between each of the first system management interrupts to the baseboard management controller in response to the second acquisition instruction of the baseboard management controller.

[0045] Shared memory (Shared Memory Region) is a key component for efficient data exchange between the BIOS and BMC, typically implemented through a dedicated area in system memory. In some embodiments, shared memory uses a dual-buffer design, consisting of an SMI monitoring data buffer and an optimized SMI time point buffer, respectively used to store raw data collected by the BIOS and optimized results generated by the BMC. To ensure data consistency, shared memory implements an atomic operation-based synchronization mechanism, allowing the BIOS and BMC to safely read and write data between different threads. This design avoids the overhead of traditional I / O communication and significantly improves system responsiveness.

[0046] During system operation, the BIOS first enters the data collection phase. Based on a high-precision timer, it records the precise timestamp of each SMI trigger and uses processor performance counters to obtain the number of instructions executed between consecutive SMIs. This data is organized into time series and written in real time to the SMI monitoring data buffer in shared memory. To ensure data integrity, the BIOS uses a ring buffer structure, automatically overwriting the oldest data when the buffer is full.

[0047] The BMC periodically reads SMI monitoring data from shared memory and enters the data analysis phase. It first preprocesses the raw data, including time series alignment, outlier filtering, and data smoothing. The BMC then applies a pattern recognition algorithm based on a hidden Markov model (HMM) to analyze the distribution of SMI intervals and instruction counts, identifying recurring cycles in system operation. These cycles may correspond to specific application behaviors, such as database queries, video encoding, or scientific computing.

[0048] After identifying recurring cycles, the BMC enters the optimization decision phase. It dynamically adjusts the SMI trigger frequency based on instruction execution density. In high-load areas with dense instructions, the algorithm increases the SMI frequency to more frequently check system status and adjust the frequency. In low-load areas with sparse instructions, the algorithm decreases the SMI frequency to reduce interrupt overhead. This adaptive adjustment strategy accurately matches actual system load variations, avoiding the unnecessary overhead associated with traditional evenly spaced SMIs.

[0049] The optimized SMI time is written to the optimized SMI time buffer in shared memory. After each data collection, the BIOS checks this buffer for new optimization results. If an update is found, the BIOS immediately enters the frequency control phase, adjusting the processor frequency based on the new SMI time. This process involves modifying the processor's clock control registers, adjusting the multiplier or bus frequency, and dynamically adjusting processor performance.

[0050] The core of the non-uniform system management interruption method lies in its adaptive adjustment strategy. The algorithm first calculates the instruction execution rate distribution from historical data and then uses K-means clustering to partition the system load into distinct regions. For each region, the algorithm applies a different SMI interval strategy. This hierarchical strategy ensures system responsiveness during peak loads while minimizing interrupt overhead during periods of low load.

[0051] Implementing a frequency control system involves multiple key technologies. For data acquisition, the BIOS requires precise synchronization of hardware timers and processor performance counters to ensure the accuracy of timestamps and instruction counts. Furthermore, the pattern recognition and optimization algorithms executed by the BMC require efficient computing resources, often employing multi-threaded parallel processing to accelerate analysis.

[0052] In some embodiments, to confirm whether there is valid SMI time point data in the first repetition period in the shared memory, the BIOS continuously polls a specific status flag in the shared memory. This flag is set by the baseboard management controller (BMC) after completing data calculation and writing. To ensure the accuracy and consistency of data reading, the BIOS uses atomic operations to access this flag to avoid contention issues in a multi-threaded environment.

[0053] When the flag is detected, the BIOS reads the data in the shared memory. The data in the shared memory is stored in a specific structure, which contains key information such as the time point array, data version number, and checksum.

[0054] In some embodiments, determining the first repetition period and the time point at which the system management interrupt is generated in the first repetition period based on the time point of the first system management interrupt and the number of processor instructions between each first system management interrupt includes:

[0055] plotting an autocorrelation function graph of instruction density and time based on the time points of the first system management interrupts and the number of instructions of the processor between each first system management interrupt;

[0056] In the BMC periodic load analysis process, the quantitative analysis of the business load periodicity is achieved by constructing the autocorrelation function (ACF) diagram of the time series. The specific implementation process is as follows: First, the BMC obtains the first system management interrupt (SMI) time point sequence and the corresponding instruction number sequence Convert to instruction density sequence ,in , represents the processor load intensity per unit time. Subsequently, the system normalizes the time series, calculates its mean μ and standard deviation σ, and obtains the normalized series

[0057] .

[0058] The plotting of the autocorrelation function is based on the calculation of the lagged correlation of the normalized series: for each lag value k (k=1,2,...,m, m is the maximum lag period), the autocorrelation coefficient is calculated , where Z is the normalized sequence mean and n is the total number of samples. This coefficient reflects the degree of linear correlation of the time series when it is lagged by k units, and its value range is [-1,1]. BMC calculates the corresponding value of each lag value k as Draw a two-dimensional coordinate graph with the horizontal axis being the lag time and the vertical axis being the correlation coefficient to form an autocorrelation function graph.

[0059] When analyzing the features in the graph, the system focuses on detecting the location of the significant positive correlation peak: if it appears at the lag a time If the local maximum value exceeds 0.7 (a configurable threshold), the traffic load is determined to have a recurring pattern with a period of a. For example, in an e-commerce promotion system, the ACF graph may peak at a lag of 24 hours, corresponding to the daily peak traffic period. To improve detection robustness, the system uses a sliding window smoothing algorithm to reduce noise on the ACF curve and verifies the significance of periodicity through statistical tests (such as the Ljung-Box test) to avoid misjudgments caused by random fluctuations. This mechanism uses mathematical modeling to transform implicit periodicity in the traffic load into visual features, providing a quantitative basis for dynamically adjusting the SMI interruption period.

[0060] A first repetition period is determined in the autocorrelation function graph, and a time point of generating a system management interrupt is determined in the first repetition period based on a non-uniform system management interrupt method; wherein the density of the system management interrupt is positively correlated with the variation amplitude of the instruction density.

[0061] After the BMC identifies the cyclical characteristics of the workload using the ACF plot (e.g., a significant positive correlation peak at lag time a), it first divides the complete cycle into several subintervals with varying rates of change in instruction density. In practice, the system performs a sliding window differential calculation on the historical instruction density curve, defining areas where the absolute value of the slope exceeds a threshold as "high-density change zones" and the remaining areas as "stable zones."

[0062] In terms of interruption scheduling, the BMC employs an adaptive density control algorithm. In high-density fluctuation zones (e.g., load fluctuations exceeding ±15% of the baseline value), the SMI trigger interval is shortened to a minimum T value (e.g., two seconds), creating a dense monitoring window. In stable zones (fluctuations less than ±5%), the interval is extended to a maximum T value (e.g., five seconds) to reduce system overhead and ensure a strict positive correlation between interruption density and the severity of load fluctuations. For example, upon identifying peak ticket purchase patterns, the system automatically initiates dense monitoring 30 minutes before 8:00 AM daily.

[0063] In some embodiments, controlling the frequency of the processor according to the time point at which the system management interrupt is generated in the first repetition period includes:

[0064] Setting a second system management interrupt based on a time point of the system management interrupt in the first repetition period;

[0065] The basic input and output system, after determining that the second system management interrupt is triggered, obtains the number of instructions executed by the processor between two second system management interrupts;

[0066] BIOS converts time points into actual hardware scheduling instructions. This process involves multiple levels of timing control and hardware interaction.

[0067] The BIOS first converts the relative time point provided by the BMC (the offset from the cycle start) into absolute system time. This requires accurately calculating the elapsed time since system boot. Because the Time Stamp Counter (TSC) may be paused during system hibernation or deep C-states, the BIOS maintains a cumulative hibernation time correction value, which is subtracted from the current TSC value to obtain the accurate run time. For periodic load patterns, the BIOS constructs a circular buffer in memory to precalculate SMI trigger points for multiple cycles in the future to reduce real-time computation overhead.

[0068] Calculating the processor occupancy rate based on the number of instructions executed by the processor between the two second system management interrupts;

[0069] The actual utilization rate is calculated using the formula "Utilization Rate = Actual Number of Instructions / (Theoretical Throughput × Time)." In some embodiments, utilization data is used not only for current decision-making but also for predicting load trends based on historical data to further optimize frequency adjustment strategies.

[0070] determining an occupancy interval into which the occupancy falls, where different occupancy intervals correspond to different frequency control schemes;

[0071] In some embodiments, a three-stage mapping system between occupancy ranges and frequency control schemes is constructed to achieve precise control of processor performance and power consumption. Occupancy is divided into three ranges with clear engineering significance: occupancy < 90% indicates suboptimal system resource utilization, and the processor frequency level is reduced; 90% ≤ occupancy ≤ 95% is the system's optimal energy efficiency zone, maintaining the current frequency level; occupancy > 95% is considered an overload state, and the processor frequency level is increased.

[0072] Unnecessary frequency adjustments are reduced through trend extrapolation in the low-load area, relaxation control is used in the stable area to reduce monitoring energy consumption, and emergency response mechanisms are enabled in the overload area to ensure system reliability.

[0073] A frequency control scheme for frequency control of the processor is determined according to the occupancy rate interval, and frequency control of the processor is performed.

[0074] After the occupancy interval is determined, the frequency of the processor is controlled according to a frequency control scheme corresponding to the occupancy interval.

[0075] Figure 3 A flow chart of a frequency control method provided by an embodiment of the present disclosure.

[0076] like Figure 3 Shown, including:

[0077] Step 201, determining a first repetition period and a time point at which a system management interrupt is generated in the first repetition period based on a time point of a first system management interrupt and a number of processor instructions between each first system management interrupt;

[0078] The time point of the first system management interrupt and the number of instructions of the processor between each first system management interrupt are obtained from the basic input and output system;

[0079] During the BIOS initialization phase, a hardware timer is configured to capture SMI events. In some embodiments, a timestamp counter or a high-precision event timer can be used to achieve nanosecond time accuracy. Specifically, the embodiments of the present application do not limit the type of timer.

[0080] When an SMI is triggered, the BIOS interrupt handler responds immediately, first saving the current processor context, including the state of general-purpose registers, segment registers, and flag registers. This process must be completed in an extremely short time to ensure the accuracy of the captured time point. The handler then reads the value of the high-precision timer, converts it into a system timestamp, and stores it in a temporary buffer along with the SMI event type and related parameters. To ensure accurate time measurement, the BIOS uses a time synchronization algorithm to periodically calibrate with the system real-time clock (RTC) to compensate for possible timer drift.

[0081] Instruction count statistics rely on the processor's performance monitoring unit (PMU). Modern processors such as the Intel Core series and AMD Ryzen series are equipped with a PMU that can accurately count various microarchitectural events, including the number of instructions executed. The BIOS configures the PMU by writing to certain model-specific registers, selecting the appropriate event counter and enabling instruction retirement event counting. During each SMI interval, the PMU continuously accumulates the number of instructions executed until the next SMI is triggered, at which point the BIOS reads the counter value and resets it.

[0082] To handle multi-core processor environments, the BIOS needs to traverse all logical processors in the system and configure independent performance counters for each core. With Hyper-Threading technology, each physical core contains multiple logical processors, and the BIOS needs to distinguish instruction counts for different threads. This is typically achieved by setting a thread affinity mask in conjunction with specific MSR registers.

[0083] The BIOS organizes the processed data into a specific data structure, including a timestamp array, an instruction count array, and metadata (such as sampling frequency and processor model). This data structure is written to a designated area of shared memory, typically using double buffering to separate reads and writes. To ensure data consistency, the BIOS sets an atomic flag to notify the BMC of the availability of new data.

[0084] Step 202: Control the frequency of the processor according to the time point at which the system management interrupt is generated in the first repetition period.

[0085] For the detailed implementation process of step 202, please refer to the description in the above-mentioned application embodiment, and the present application embodiment will not repeat them one by one again.

[0086] In some embodiments, determining the first repetition period and the time point at which the system management interrupt is generated in the first repetition period based on the time point of the first system management interrupt and the number of processor instructions between each first system management interrupt further includes:

[0087] plotting an autocorrelation function graph of instruction density and time according to the time points of the first system management interrupts and the number of instructions of the processor between the first system management interrupts;

[0088] A first repetition period is determined in the autocorrelation function graph, and a time point of generating a system management interrupt is determined in the first repetition period based on a non-uniform system management interrupt method; wherein the density of the system management interrupt is positively correlated with the variation amplitude of the instruction density.

[0089] For the detailed implementation process, please refer to the description in the above application embodiment, and the present application embodiment will not be described in detail again.

[0090] In some embodiments, setting a second system management interrupt based on a time point of the system management interrupt in the first repetition period to control the frequency of the processor includes:

[0091] Setting a second system management interrupt based on a time point of the system management interrupt in the first repetition period;

[0092] After determining that the second system management interrupt is triggered, obtaining the number of instructions executed by the processor between two second system management interrupts;

[0093] Calculating an occupancy rate of the processor based on the number of instructions executed by the processor;

[0094] determining an occupancy interval into which the occupancy falls, where different occupancy intervals correspond to different frequency control schemes;

[0095] A frequency control scheme for frequency control of the processor is determined according to the occupancy rate interval, and frequency control of the processor is performed.

[0096] For the detailed implementation process, please refer to the description in the above application embodiment, and the present application embodiment will not be described in detail again.

[0097] In some embodiments, determining a frequency control scheme for controlling the frequency of the processor according to the occupancy interval, and performing frequency control on the processor includes:

[0098] When the occupancy rate falls within the first occupancy rate interval, determining the frequency control scheme to reduce the operating frequency of the processor until the occupancy rate of the processor after adjusting the operating frequency falls within the second occupancy rate interval;

[0099] When the occupancy rate falls within the second occupancy rate interval, determining the frequency control scheme to maintain the operating frequency of the processor unchanged;

[0100] When the occupancy rate falls within the third occupancy rate range, the frequency control scheme is determined to be to increase the operating frequency of the processor until the occupancy rate of the processor after the operating frequency is adjusted falls within the second occupancy rate range.

[0101] When the real-time monitored processor occupancy falls into the first interval, which is below the target interval, the system triggers a progressive frequency reduction strategy. By gradually lowering the operating frequency and continuously collecting occupancy data, a "adjustment-feedback-readjustment" control loop is formed until the occupancy enters the target interval. If the occupancy is already in the target interval (the second interval), the frequency lock mechanism is activated to maintain the current operating frequency unchanged. At the same time, a dynamic sampling interval is used to optimize monitoring efficiency, reducing system interruption overhead while ensuring load sensing accuracy. When the occupancy exceeds the third interval, which is above the target interval, a step-by-step frequency increase operation is executed. By increasing the frequency in stages and verifying the occupancy changes in real time, a "rapid response-gradual convergence" adjustment path is established until the occupancy returns to the target interval.

[0102] This control strategy introduces a hysteresis comparator mechanism to avoid frequent oscillations at interval boundaries. It also uses a sliding window to smooth occupancy data across multiple consecutive sampling periods, ensuring the stability and accuracy of frequency adjustments. This three-stage adjustment logic, through the collaborative work of the hardware performance monitoring unit and the firmware control engine, forms a complete control chain from load sensing, policy decision-making, to execution feedback. This allows for both deep frequency reduction to reduce power consumption in low-load scenarios and rapid performance improvements in high-load scenarios to meet sudden demands, ultimately achieving efficient and stable processor operation within the target load range.

[0103] In some embodiments, the first repetition period includes a system management interrupt sparse area and a system management interrupt dense area; after determining the occupancy interval into which the occupancy falls, and different occupancy intervals correspond to different frequency control schemes, the method further includes:

[0104] When it is determined that the number of times that the occupancy rate of the processor corresponding to the system management interrupt sparse area falls into the first occupancy rate interval or the third occupancy rate interval exceeds a preset threshold, obtaining the second system management interrupt time point and the number of instructions of the processor between each of the second system management interrupt time points;

[0105] A second repetition period is determined according to the second system management interrupt time points and the number of instructions of the processor between the second system management interrupt time points, and a system management interrupt is set in the second repetition period based on the non-uniform system management interrupt method.

[0106] When the BMC receives the cycle count instruction (carrying abnormal interval statistics) from the shared memory, it uses the PIT to set the second system management interrupt to trigger at a fixed interval, continuously collecting instruction count and timestamp data for N complete cycles (for example, set to 10 or 20). In some embodiments, to ensure data quality, a Kalman filter algorithm can be used to fuse the HPET timestamp with the PMU instruction counter data to eliminate clock drift errors.

[0107] See also Figure 4 , Figure 4 A time series diagram of instruction density provided in an embodiment of the present application is shown as follows: Figure 4 As shown, it can be seen intuitively that after every a time period, there is a repetitive cycle of instruction density. When the two cycle curves are overlapped, it can be found that the curve overlap is very high; take the average value of each point on the curve, as shown Figure 5 As shown, Figure 5 A time series diagram of instruction density provided by an embodiment of the present application; Figure 5 As shown, at a certain time point c, curve 1 corresponds to instruction density 1, and curve 2 corresponds to instruction density 2. The instruction density corresponding to the merged curve at time c is (instruction density 1 + instruction density 2) ÷ 2 = instruction density 3.

[0108] Calculate the instruction density of each point and draw a new curve graph, which is the repeated cycle curve graph, such as Figure 6 As shown, Figure 6 A schematic diagram of a repetition cycle provided in an embodiment of the present application.

[0109] See also Figure 7 , Figure 7 A schematic diagram of confirming the time point of a system management interruption provided by an embodiment of the present application is shown as follows: Figure 7 As shown in the figure, when the BMC predicts that the instruction density is in a stable period, a sparse SMI setting is used. At this time, since there is no need to adjust the processor frequency on a large scale, when it is predicted that the instruction density needs to change, it enters the SMI intensive area, intensively generates SMI to calculate the processor occupancy, and accurately adjusts the frequency.

[0110] In the periodic analysis stage, BMC uses multi-resolution wavelet transform to decompose the time series into different frequency components and identifies the dominant periodic components through spectral analysis.

[0111] Based on the newly determined second repetition period, the BMC implements a non-uniform SMI scheduling strategy: By performing a sliding window regression analysis on the historical instruction density curve, it predicts the extreme points of load change rate and sets a dense SMI monitoring window around these extreme points, while using sparse monitoring in other areas. This dynamic adjustment reduces the number of SMI triggers while maintaining the same monitoring accuracy.

[0112] The BMC sends the optimized second repetition cycle parameters (including cycle length, SMI time point array, and confidence score) to the BIOS through the shared memory.

[0113] In some embodiments, before determining the first repetition period and the time point at which the system management interrupt is generated in the first repetition period based on the time point of the first system management interrupt and the number of processor instructions between each first system management interrupt, the method further includes:

[0114] Setting the first system management interrupt based on a fixed time interval;

[0115] After determining that the first system management interrupt is triggered, a time point of the first system management interrupt and a number of instructions executed by the processor between the two first system management interrupts are obtained.

[0116] Set a baseline interrupt period, such as 2 or 3 seconds, and generate an SMI signal at each time boundary. When the BIOS detects an SMI trigger, it reads the interrupt trigger time from the timestamp counter. This timestamp serves as the reference point for subsequent cycle calculations. It also reads the current value of the instruction counter. The difference between the two SMI interrupts is the total number of instructions executed by the processor during that cycle.

[0117] In some embodiments, determining the first repetition period in the autocorrelation function graph further comprises:

[0118] When it is determined that there is no repetitive cycle in the autocorrelation function graph, a time point for generating a system management interrupt at a fixed time interval is determined.

[0119] In fixed interval mode, BMC implements a dual redundancy protection mechanism: on the one hand, the deviation between the actual SMI trigger time and the theoretical time is monitored in real time through the timestamp comparator. If the deviation exceeds ±5μs for three consecutive times, the hardware clock calibration process is triggered; on the other hand, a sliding window counter is maintained to count the total number of instruction executions within every 100 intervals. If the fluctuation coefficient exceeds 15%, the periodic re-detection algorithm is automatically triggered. This design enables the system to maintain stable monitoring efficiency in scenarios without obvious periodic loads, while being adaptable to potential periodic characteristics. It should be noted that this narrative method is only an exemplary description and is not a specific limitation on specific numerical values. The embodiments of this application do not limit this.

[0120] In some embodiments, the density of generating the system management interrupt is determined based on the non-uniform system management interrupt method less than the density of generating the system management interrupt at fixed time intervals.

[0121] The embodiment of the present application also provides a frequency control device, Figure 8A schematic diagram of a frequency control device according to an embodiment of the present disclosure is shown in FIG. Figure 8 As shown, the device is applied to a basic input and output system, including:

[0122] A first determining unit 31 is configured to determine a first repetition period and a time point at which a system management interrupt is generated in the first repetition period based on a time point of the first system management interrupt and a number of processor instructions between each first system management interrupt;

[0123] The time point of the first system management interrupt and the number of instructions of the processor between each first system management interrupt are obtained from the basic input and output system;

[0124] The control unit 32 is configured to control the frequency of the processor according to the time point at which the system management interrupt is generated in the first repetition period.

[0125] Furthermore, in a possible implementation of the embodiment of the present disclosure, the first determining unit 31 is further configured to:

[0126] plotting an autocorrelation function graph of instruction density and time according to the time points of the first system management interrupts and the number of instructions of the processor between each first system management interrupt;

[0127] A first repetition period is determined in the autocorrelation function graph, and a time point of generating a system management interrupt is determined in the first repetition period based on a non-uniform system management interrupt method; wherein the density of the system management interrupt is positively correlated with the variation range of the instruction density.

[0128] Furthermore, in a possible implementation of the embodiment of the present disclosure, the control unit 32 is further configured to:

[0129] Setting a second system management interrupt based on a time point of the system management interrupt in the first repetition period;

[0130] After determining that the second system management interrupt is triggered, obtaining the number of instructions executed by the processor between two second system management interrupts;

[0131] Calculate the processor utilization based on the number of instructions executed by the processor;

[0132] Determine the occupancy rate interval into which the occupancy rate falls, where different occupancy rate intervals correspond to different frequency control schemes;

[0133] A frequency control scheme for controlling the frequency of the processor is determined according to the occupancy rate range, and the frequency control of the processor is executed.

[0134] Furthermore, in a possible implementation of the embodiment of the present disclosure, the control unit 32 is further configured to:

[0135] When the occupancy rate falls within the first occupancy rate range, determining a frequency control scheme to reduce the operating frequency of the processor until the occupancy rate of the processor after the operating frequency is adjusted falls within the second occupancy rate range;

[0136] When the occupancy rate falls within the second occupancy rate interval, determining a frequency control scheme to keep the operating frequency of the processor unchanged;

[0137] When the occupancy rate falls within the third occupancy rate range, the frequency control scheme is determined to be to increase the operating frequency of the processor until the occupancy rate of the processor after the operating frequency is adjusted falls within the second occupancy rate range.

[0138] Furthermore, in a possible implementation of the embodiment of the present disclosure, the first repetition period includes a system management interrupt sparse area and a system management interrupt dense area, such as Figure 9 As shown, the device also includes:

[0139] a generating unit 33 configured to, after the control unit 32 determines the occupancy interval into which the occupancy falls, and different occupancy intervals correspond to different frequency control schemes, obtain second system management interrupt time points and the number of instructions of the processor between each second system management interrupt time point when it is determined that the number of times the occupancy of the processor corresponding to the system management interrupt sparse area falls within the first occupancy interval or the third occupancy interval exceeds a preset threshold;

[0140] The second determining unit 34 is configured to determine a second repetition period according to the second system management interrupt time points and the number of processor instructions between the second system management interrupt time points, and set a system management interrupt based on the non-uniform system management interrupt method in the second repetition period.

[0141] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 9 As shown, the device also includes:

[0142] a setting unit 35 configured to set the first system management interrupt based on a fixed time interval before the first determining unit 31 determines the first repetition period and the time point at which the system management interrupt is generated in the first repetition period based on the time point of the first system management interrupt and the number of processor instructions between each first system management interrupt;

[0143] The acquiring unit 36 is configured to acquire the time point of the first system management interrupt and the number of instructions executed by the processor between two first system management interrupts after determining that the first system management interrupt is triggered.

[0144] Furthermore, in a possible implementation of the embodiment of the present disclosure, the first determining unit 31 is further configured to:

[0145] When it is determined that there is no repetitive cycle in the autocorrelation function graph, a time point for generating a system management interrupt at a fixed time interval is determined.

[0146] For the description of the features in the embodiment corresponding to the frequency control device, reference can be made to the relevant description of the embodiment corresponding to the frequency control method, and no further details will be given here.

[0147] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above frequency control method embodiments.

[0148] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above frequency control method embodiments when running.

[0149] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0150] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above frequency control method embodiments are implemented.

[0151] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned frequency control method embodiments are implemented.

[0152] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0153] The above describes in detail a frequency control system, method, device, electronic device, and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. It should be noted that, for those skilled in the art, various improvements and modifications may be made to the present application without departing from the principles of the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A frequency control system, characterized in that: It includes a basic input and output system, a baseboard management controller and a shared memory; the shared memory is connected to the basic input and output system and the baseboard management controller respectively; The baseboard management controller is configured to determine a first repetition period and a time point at which a system management interrupt is generated in the first repetition period based on a time point of the first system management interrupt and a number of processor instructions between each first system management interrupt, and send the time point at which the system management interrupt is generated in the first repetition period to the shared memory; The shared memory sends the time point of generating the system management interrupt in the first repetition cycle to the basic input and output system in response to the first acquisition instruction of the basic input and output system; The basic input and output system is configured to perform frequency control on the processor according to the time point when the system management interrupt is generated in the first repetitive cycle; The performing of frequency control on the processor according to the time point at which the system management interrupt is generated in the first repetition period includes: Setting a second system management interrupt based on a time point of the system management interrupt in the first repetition period; The basic input and output system, after determining that the second system management interrupt is triggered, obtains the number of instructions executed by the processor between two second system management interrupts; Calculating the processor occupancy rate based on the number of instructions executed by the processor between the two second system management interrupts; determining an occupancy interval into which the occupancy falls, where different occupancy intervals correspond to different frequency control schemes; A frequency control scheme for frequency control of the processor is determined according to the occupancy rate interval, and frequency control of the processor is performed.

2. The frequency control system according to claim 1, characterized in that: The system further comprises: The basic input / output system, after acquiring the time point of the first system management interrupt and the number of instructions of the processor between each of the first system management interrupts, sends the time point of the first system management interrupt and the number of instructions of the processor between each of the first system management interrupts to the shared memory; The shared memory sends the time points of the first system management interrupts and the number of instructions of the processor between each of the first system management interrupts to the baseboard management controller in response to the second acquisition instruction of the baseboard management controller.

3. The frequency control system according to claim 1, characterized in that: The determining, based on the time points of the first system management interrupts and the number of processor instructions between the first system management interrupts, of the first repetition period and the time points at which the system management interrupts are generated in the first repetition period includes: plotting an autocorrelation function graph of instruction density and time based on the time points of the first system management interrupts and the number of instructions of the processor between each first system management interrupt; A first repetition period is determined in the autocorrelation function graph, and a time point of generating a system management interrupt is determined in the first repetition period based on a non-uniform system management interrupt method; wherein the density of the system management interrupt is positively correlated with the variation amplitude of the instruction density.

4. A frequency control method, characterized in that: include: determining a first repetition period and a time point at which a system management interrupt is generated in the first repetition period based on a time point of the first system management interrupt and a number of instructions of the processor between each first system management interrupt; The time point of the first system management interrupt and the number of instructions of the processor between each first system management interrupt are obtained from the basic input and output system; executing frequency control of the processor according to the time point at which the system management interrupt is generated in the first repetitive cycle; The step of setting a second system management interrupt based on the time point of the system management interrupt in the first repetition period to control the frequency of the processor includes: Setting a second system management interrupt based on a time point of the system management interrupt in the first repetition period; After determining that the second system management interrupt is triggered, obtaining the number of instructions executed by the processor between two second system management interrupts; Calculating an occupancy rate of the processor based on the number of instructions executed by the processor; determining an occupancy interval into which the occupancy falls, where different occupancy intervals correspond to different frequency control schemes; A frequency control scheme for frequency control of the processor is determined according to the occupancy rate interval, and frequency control of the processor is performed.

5. The frequency control method according to claim 4, characterized in that: The determining of the first repetition period and the time point at which the system management interrupt is generated in the first repetition period based on the time point of the first system management interrupt and the number of instructions of the processor between the first system management interrupts further includes: plotting an autocorrelation function graph of instruction density and time according to the time points of the first system management interrupts and the number of instructions of the processor between the first system management interrupts; A first repetition period is determined in the autocorrelation function graph, and a time point of generating a system management interrupt is determined in the first repetition period based on a non-uniform system management interrupt method; wherein the density of the system management interrupt is positively correlated with the variation amplitude of the instruction density.

6. The method according to claim 4, characterized in that Determining a frequency control scheme for controlling the frequency of the processor according to the occupancy interval, and performing frequency control on the processor includes: When the occupancy rate falls within the first occupancy rate interval, determining the frequency control scheme to reduce the operating frequency of the processor until the occupancy rate of the processor after adjusting the operating frequency falls within the second occupancy rate interval; When the occupancy rate falls within the second occupancy rate interval, determining the frequency control scheme to maintain the operating frequency of the processor unchanged; When the occupancy rate falls within the third occupancy rate range, the frequency control scheme is determined to be to increase the operating frequency of the processor until the occupancy rate of the processor after the operating frequency is adjusted falls within the second occupancy rate range.

7. The method according to claim 4, characterized in that The first repetition period includes a system management interrupt sparse area and a system management interrupt dense area; after determining the occupancy interval into which the occupancy falls, and different occupancy intervals correspond to different frequency control schemes, the method further includes: When it is determined that the number of times that the occupancy rate of the processor corresponding to the system management interrupt sparse area falls into the first occupancy rate interval or the third occupancy rate interval exceeds a preset threshold, obtaining the second system management interrupt time point and the number of instructions of the processor between each of the second system management interrupt time points; A second repetition period is determined according to the second system management interrupt time points and the number of instructions of the processor between the second system management interrupt time points, and a system management interrupt is set in the second repetition period based on a non-uniform system management interrupt method.

8. The method according to claim 4, characterized in that Before determining the first repetition period and the time point at which the system management interrupt is generated in the first repetition period based on the time point of the first system management interrupt and the number of instructions of the processor between the first system management interrupts, the method further includes: Setting the first system management interrupt based on a fixed time interval; After determining that the first system management interrupt is triggered, a time point of the first system management interrupt and a number of instructions executed by the processor between two first system management interrupts are obtained.

9. The method according to claim 5, characterized in that Determining the first repetition period in the autocorrelation function graph further comprises: When it is determined that there is no repetitive cycle in the autocorrelation function graph, a time point for generating a system management interrupt at a fixed time interval is determined.

10. A frequency control device, characterized in that: include: a determining unit, configured to determine a first repetition period and a time point at which a system management interrupt is generated in the first repetition period based on a time point of the first system management interrupt and a number of instructions of the processor between each first system management interrupt; The time point of the first system management interrupt and the number of instructions of the processor between each first system management interrupt are obtained from the basic input and output system; a control unit, configured to perform frequency control on the processor according to a time point at which a system management interrupt is generated in the first repetition period; The control unit is also used for: Setting a second system management interrupt based on a time point of the system management interrupt in the first repetition period; After determining that the second system management interrupt is triggered, obtaining the number of instructions executed by the processor between two second system management interrupts; Calculate the processor utilization based on the number of instructions executed by the processor; Determine the occupancy rate interval into which the occupancy rate falls, where different occupancy rate intervals correspond to different frequency control schemes; A frequency control scheme for controlling the frequency of the processor is determined according to the occupancy rate range, and the frequency control of the processor is executed.

11. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the frequency control method according to any one of claims 4 to 9 when executing the computer program.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the frequency control method according to any one of claims 4 to 9.

13. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the frequency control method according to any one of claims 4 to 9 are implemented.

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