Data storage device selection

Abstract

A system can include multiple storage devices, such as pseudo-static random access memory and static random access memory. Techniques for data exchange can include receiving a write request to store data to a storage device, selecting a storage device from one or more storage devices. The data can be stored in the selected device. The method can include receiving a read request and returning data from the appropriate storage device. In some examples, the system can decide data storage location based on factors such as data size, data type, or address proximity, which can optimize memory usage, balance speed, capacity, or power efficiency. The systems and techniques described herein are particularly beneficial for resource-limited devices, such as system-on-chips.

Description

Technical Field

[0001] The systems and technologies described in this article relate to computing systems, and more specifically, to systems-on-a-chip (SoC). Background Technology

[0002] System-on-a-chip (SoC) can be used in Internet of Things (IoT) devices. SoC may include a processor, memory, and input / output components.

[0003] IoT devices can connect to each other or communicate with servers. Examples of IoT devices can be sensors that monitor environmental conditions, smart home controllers, or wearable devices. IoT devices can be implemented using a system-on-a-chip (SoC), which is configured to perform various tasks such as data acquisition, processing, or communication. SoCs typically maintain low power consumption and a small physical footprint. Summary of the Invention

[0004] The systems and techniques described herein relate to a computing system comprising: one or more processors; a controller; and one or more storage devices, including: a first storage device comprising static random access memory (SRAM); a second storage device comprising pseudo-static random access memory (PSRAM) coupled to the controller, wherein the SRAM has higher performance metrics than the PSRAM, but a smaller capacity; and a cache memory coupled to the controller. The one or more storage devices store instructions that, when executed by the one or more processors, configure the computing system to perform: receiving a write request to store data at a storage address by the one or more processors; selecting a storage device from the one or more storage devices based on the storage address to store the data; and storing the data in the selected storage device. Attached Figure Description

[0005] To facilitate identification of any discussion of a particular element or action, the highest digit in the figure reference numerals corresponds to the figure number in which the element is first introduced.

[0006] Based on some examples, Figure 1 This is a schematic diagram of a computing system in which instructions can be executed to cause the computing system to perform any one or more of the methods discussed herein.

[0007] Based on some examples, Figure 2 This is a flowchart illustrating the method of writing data.

[0008] Based on some examples, Figure 3 This is a flowchart illustrating the method for reading data.

[0009] Based on some examples, Figure 4 This is a schematic diagram of the additional components of the computing system. Detailed Implementation

[0010] The systems and techniques described in this article address several technical challenges related to data exchange in computing systems, particularly those with limited resources. One such challenge is the trade-off between performance and capacity between different types of memory. Static random access memory (SRAM) offers superior performance but has limited capacity, while pseudo-static random access memory (PSRAM) offers greater capacity but is slower. To address this challenge, computing systems can implement hybrid configurations that include both SRAM and PSRAM, thereby efficiently utilizing both memory types based on specific data characteristics or access patterns.

[0011] Another challenge may be optimizing data storage and retrieval in resource-constrained systems, such as IoT devices or systems-on-a-chip. The technical solutions described in this article may involve selecting storage devices based on factors such as data size, type, and storage address.

[0012] For example, smaller, frequently accessed data can be stored in faster SRAM or cache memory, while larger datasets can be directed to PSRAM.

[0013] In some cases, directly combining SRAM and PSRAM may not be the optimal solution due to the inherent differences in their performance characteristics. PSRAM can incur significant overhead during data exchange, which may degrade overall system performance. These overhead costs may include the additional time required for read / write operations.

[0014] To address this technical challenge, the system can implement a controller with cache memory or a buffer as an intermediary for the PSRAM, enabling the entire system to manage data storage or retrieval operations more efficiently. By utilizing the cache memory or buffer in the controller, the system can reduce the impact of higher overhead costs on overall performance. The system and techniques described in this paper enable computing systems to leverage the advantages of PSRAM while minimizing performance bottlenecks associated with direct access to PSRAM. The controller can optimize data exchange and reduce overhead costs, potentially improving the overall performance and energy efficiency of computing systems such as IoT devices or systems-on-a-chip.

[0015] Based on some examples, Figure 1 This is a block diagram illustrating the components that may be present in the computing system 100. These components enable the computing system 100 to operate according to the techniques discussed herein. As understood, Figure 1 The various functional blocks shown may include hardware elements (including dedicated or general-purpose circuitry), software elements (including computer code stored on a machine-readable medium), or a combination of hardware and software elements. It should also be noted that... Figure 1 This is merely an example of a specific implementation and is intended only to illustrate the types of components that may exist in computing system 100.

[0016] The computing system 100 may include a processor 102 and a memory 114, which may be configured to communicate via a main bus 112. In some examples, the processor 102 (e.g., a central processing unit (CPU), a reduced instruction set processor, a complex instruction set processor, a graphics processing unit (GPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a radio frequency integrated circuit (RFIC), other processors, or any suitable combination thereof) may include processors 104 and 106 that execute instructions 108 and 110, respectively. The term "processor" is intended to include multi-core processors that may contain two or more independent processors (sometimes referred to as "cores") capable of executing instructions simultaneously. Although Figure 1 Multiple processors 102 are shown, but computing system 100 may include a single processor with a single core, a single processor with multiple cores (e.g., a multi-core processor), multiple processors with a single core, multiple processors with multiple cores, or any combination thereof.

[0017] The main bus 112 may include a data bus (dbus) 132 or a control bus (cbus) 134. The data bus 132 may be configured to transmit data between components of the computing system 100. The control bus 134 may be configured to transmit control signals between different components of the computing system 100.

[0018] Memory 114 may include controller 116, a first storage device 128, and a second storage device 130. Processor 102 can access the first storage device 128 via main bus 112 or data bus 132. Controller 116 can be communicatively coupled to processor 102 via main bus 112. In some examples, controller 116 is coupled to main bus 112 via data bus 132 and / or control bus 134. In some examples, processor 102 can access second storage device 130 via controller 116. Memory 114 may include a non-transitory computer-readable storage medium storing instructions that enable a computing system to perform any one or more of the methods discussed herein.

[0019] The controller 116 may store instructions 118 embodying any one or more methods or functions described herein. During execution of the computing system 100, the instructions 118 may also reside wholly or partially in the first storage device 128, the second storage device 130, the processor 102, or any suitable combination thereof.

[0020] Controller 116 may include bus input / output component 120, register 122, cache memory 124, or buffer 126. In some examples, controller 116 determines the locations where data is stored, retrieved, or transferred between cache memory 124, buffer 126, and second storage device 130. In some examples, controller 116 manages the communication interface between processor 102 and second storage device 130. In some examples, controller 116 coordinates with bus input / output component 120 to regulate the timing or sequence of data exchanges.

[0021] In some examples, controller 116 may be coupled to main bus 112 via both data bus 132 and control bus 134. Control signal exchange may be performed via control bus 134, while other data exchange may be performed via data bus 132 or control bus 134.

[0022] Bus I / O component 120 provides a path for data transfer between components. In some examples, bus I / O component 120 handles data input or output. Data input may be referred to as writing (e.g., storing, saving) data into memory 114. Data output may be referred to as reading (e.g., acquiring, accessing, retrieving, obtaining, retrieving) data from memory 114. Data input or output may also be referred to as data exchange, data transfer. In some examples, bus I / O component 120 manages data exchange between main bus 112 and memory 114. Bus I / O component 120 may interpret or execute read or write requests from processor 102, and coordinate data transfer between cache memory 124, buffer 126, first storage device 128, or second storage device 130. Bus I / O component 120 may be configured to implement different protocols for different data exchange modes. For example, bus I / O component 120 implements burst mode for accessing or storing sequential data or batches of data containing multiple data items. Sequential data may be data associated with substantially adjacent memory addresses. For example, memory addresses 0x1000, 0x1001, and 0x1002 are substantially adjacent memory addresses because they are contiguously adjacent to each other. In some examples, substantially adjacent memory addresses do not need to be contiguous; instead, substantially adjacent memory addresses can be separated by a predetermined number of memory addresses. For example, memory addresses 0x1000 and 0x1004 are substantially adjacent, separated only by a predetermined number of memory addresses (e.g., 4). In some examples, substantially adjacent memory addresses may include multiple memory addresses falling within a predetermined range. In another example, bus input / output component 120 implements a single-transfer mode for accessing or storing data at random access memory locations.

[0023] In some examples, the memory address provided in the write request is converted, decoded, or converted by the bus input / output component 120 into the address format used by the selected memory device in order to correctly interpret the memory address or store the data in the correct memory location.

[0024] Register 122 can serve as a small, fast storage location for holding or managing data or control information related to operations performed by controller 116. Register 122 can store control signals or configuration settings that indicate how to control various storage devices, such as memory timing, refresh rate, and different data exchange modes. Register 122 can store memory addresses, enabling controller 116 to determine where to read or write data from memory 114. In some examples, register 122 in controller 116 temporarily holds data transferred between memory 114 and processor 102 or other system components, ensuring efficient data flow. In some examples, register 122 stores the status of data exchange, providing feedback on whether the data exchange was successfully completed or if an error occurred. In some examples, register 122 may contain commands for causing one or more storage devices to perform operations (such as read, write, or refresh).

[0025] In some examples, register 122 includes a configuration register containing pre-configured command codes that enable controller 116 to communicate with second storage device 130. The configuration register may store parameters of the second storage device 130, such as timing configuration, refresh rate, or access mode. The configuration register may include settings for caching policies, buffer management, or address mapping schemes. In some examples, controller 116 uses configuration registers containing different pre-configured command codes to communicate with second storage devices 130 manufactured by different companies.

[0026] Cache memory 124 can be configured to store data or instructions for fast retrieval. In some examples, cache memory 124 stores data or instructions smaller than or equal to a first predetermined size threshold. Cache memory 124 can implement various caching algorithms, such as write-through, write-back, or write-around strategies. In some examples, cache memory 124 supports prefetching to preload data that may be accessed soon. In some examples, cache memory 124 supports features such as cache coherency protocols to ensure data consistency among multiple processors (e.g., processor 104 and processor 106). Cache memory 124 can be implemented as a partition of the first storage device 128. Cache memory 124 can be a static random access memory (SRAM) different from the first storage device 128.

[0027] Buffer 126 can be configured to store data transferred between different components of computing system 100. In some examples, buffer 126 can temporarily hold data during data transfer. In some examples, buffer 126 can be used in burst mode. For example, burst mode is used when transferring batches of data (such as image data). For example, burst mode is used when data corresponds to multiple addresses, and these multiple addresses contain more than a predetermined number of storage addresses. Buffer 126 can implement a circular buffer algorithm, which allows continuous data flow without constant space reallocation. Buffer 126 can assist in data rate matching between components with different processing speeds. For example, buffer 126 temporarily stores data from processor 102 before it can be written to one or more storage devices. In some examples, buffer 126 can be used to assemble or decompose data packets for more efficient data exchange with a second storage device 130. In some examples, buffer 126 works with cache memory 124 or bus input / output component 120 to optimize data movement within memory 114. Buffer 126 can help reduce data transmission latency and may help to utilize the bandwidth of main bus 112 more effectively.

[0028] The first storage device 128 may be a storage area for frequently accessed data or instructions within the computing system 100. The first storage device 128 may include static random access memory (SRAM). The first storage device 128 may be coupled to the processor 102 via the main bus 112 or the data bus 132. In other words, the processor 102 may directly exchange data with the first storage device 128. In some examples, when the computing system 100 is implemented as a system-on-a-chip, the first storage device 128 is integrated into the computing system 100. For example, the first storage device 128 may be built directly on the same semiconductor die or chip as the processor 102. In some examples, the first storage device 128 provides fast access to stored information (e.g., data). In some examples, the first storage device 128 may support simultaneous read and write operations, potentially improving overall performance. In some examples, the first storage device 128 may be organized into multiple partitions, allowing parallel access to multiple partitions. For example, one or more of the multiple partitions may be used as cache memory 124 or buffer 126 of the controller 116. The first storage device 128 can implement Error Redundancy Check (ECC) functionality to maintain data integrity. In some examples, ECC functionality detects or corrects certain types of data errors, improving the reliability of stored information.

[0029] The second storage device 130 can provide storage space for the computing system 100. The second storage device 130 may include pseudo-static random access memory (PSRAM). In some examples, the second storage device 130 has a larger capacity (e.g., storage space, storage size) than the first storage device 128; however, the first storage device 128 has higher (e.g., better) performance metrics. For example, performance metrics include read or write speeds. For example, the first storage device 128 has a better read / write speed than the second storage device 130. Another example is that performance metrics include latency or bandwidth. In some examples, the second storage device 130 is coupled to the computing system 100 via an external connection. The second storage device 130, including pseudo-static random access memory, can be externally coupled to the computing system 100 via a four-wire serial peripheral interface. In some examples, the second storage device 130 is directly integrated into the computing system 100 by sharing the same circuitry or embedding it in the same semiconductor die or chip as the processor 102.

[0030] The second storage device 130 can support different modes to improve performance in various scenarios. In some examples, the second storage device 130 can also support burst mode for data transfer, allowing data batches to be transferred in a single operation. To reduce power consumption, especially during inactivity, the second storage device 130 can implement energy-saving features. In some examples, energy-saving features include partial array refresh, where only the portion of the second storage device 130 containing data is refreshed, thereby saving energy. In some examples, the second storage device 130 utilizes a temperature-compensated self-refresh mechanism, adjusting the refresh rate based on ambient temperature to optimize power usage while maintaining data integrity. The second storage device 130 can work in conjunction with one or more storage devices (such as the first storage device 128) to leverage the strengths of each storage device, potentially improving overall system performance or energy efficiency.

[0031] By using a hybrid configuration including a first storage device 128 and a second storage device 130, the computing system 100 can use the first storage device 128 to provide fast access to frequently used or critical data or instructions, and use the second storage device 130 to provide sufficient storage space for other types of data. In some examples, the cost per bit of storage space in static random access memory may be higher than that in pseudo static random access memory. Therefore, the hybrid configuration can reduce the overall manufacturing cost of the computing system 100. In summary, the hybrid configuration allows the computing system 100 to achieve a balance between speed, storage capacity (e.g., storage space), power efficiency, and cost-effectiveness.

[0032] Based on some examples, Figure 2 This is a flowchart illustrating a data exchange method in a computing system.

[0033] In block 202, processor 102 may receive (e.g., execute) a write request to store data in a storage address. The write request may include the storage address where data needs to be written.

[0034] In block 204, processor 102 may select one or more storage devices to store data. The one or more storage devices may include a first storage device 128 and a second storage device 130. In some examples, selection may be based on storage addresses provided in a write request. For example, data including storage addresses in the range from a first address to a second address is configured to be written to the first storage device 128; data including storage addresses in the range from a third address to a fourth address is configured to be written to the second storage device 130.

[0035] In some examples, the selection is based on a set of rules. These rules determine the selection of a storage device based on data size, data type, and other factors. The rules can optimize data storage based on the characteristics of one or more storage devices, such as access speed, latency, power consumption, and storage capacity. In some examples, processor 102 selects a first storage device 128 to store data based on data exceeding a second predetermined size threshold. In some examples, processor 102 selects a second storage device 130 based on data exceeding a second predetermined size threshold. In some examples, processor 102 selects a storage device based on access frequency. For example, configuring counter data for counting the number of times a specific event occurs may require frequent access. The storage address associated with the counter data falls within the address range associated with the first storage device 128. The storage address associated with the data can be predetermined. For example, the storage address associated with the data is predetermined to be associated with the second storage device 130.

[0036] In some examples, this set of rules can use machine learning algorithms to predict data exchange patterns and optimize data placement between the first storage device 128 and the second storage device 130. Data exchange patterns can be collected through logs generated by the computing system 100. The machine learning algorithms can analyze historical access patterns, including data access frequency, temporal and spatial locality, data type, and data dependencies. By learning data exchange patterns, this set of rules can adjust data placement strategies to optimize data placement. The machine learning model can be continuously updated based on newly generated logs indicating new exchange patterns, and the set of rules can adaptively optimize, potentially improving the overall performance and energy efficiency of the computing system 100.

[0037] In some examples, computing system 100 distributes large amounts of data across multiple storage devices. For instance, the data to be stored might include a graphical user interface (GUI) comprising one or more interactive buttons and a background graphic. Processor 102 can select a first storage device 128 to store one or more interactive buttons and a second storage device 130 to store the background graphic, which is not frequently accessed. In these examples, computing system 100 utilizes the faster access speed of the first storage device 128 to process interactive elements that may require frequent updates or interactions, while leveraging the larger capacity of the second storage device 130 to store the less frequently accessed background graphic. For example, when a user interacts with a button, processor 102 can quickly retrieve and update the button's state from the first storage device 128, ensuring the responsiveness of the GUI. Meanwhile, the background graphic, which remains static after initial loading, can be efficiently stored in the second storage device 130 without impacting responsiveness. This approach helps balance the performance and capacity requirements of the GUI and may optimize system responsiveness and storage utilization in resource-constrained devices such as IoT devices or systems-on-a-chip.

[0038] When the first storage device 128 is selected as the storage device, the first storage device 128 can store the data. In some examples, when the first storage device 128 is selected as the storage device, the processor 102 instructs the first storage device 128 to write data via the main bus 112 or the data bus 132. When the second storage device 130 is selected as the storage device, the controller 116 can receive a write request. In some examples, the controller 116 determines the storage location of the data. For example, the controller 116 can override a write request to store data in the second storage device 130 by temporarily storing the data in the cache memory 124 or the buffer 126.

[0039] In block 206, controller 116 stores data in a cache memory (e.g., cache memory 124). The second storage device 130 may require a prerequisite operation for each write operation. This prerequisite operation can be referred to as overhead. In some examples, prerequisite operations include powering on the storage cell, configuring the operating mode, or translating the storage address to the physical address of the corresponding storage cell. Writing larger datasets may be more efficient than writing smaller datasets. By merging multiple write operations, the number of individual write cycles and associated overhead can be reduced, thereby improving overall performance or efficiency. Writing data associated with substantially adjacent storage addresses may be more efficient because overhead can be shared when writing data to the storage location. In some examples, controller 116 accumulates multiple write operations by storing the data to be written in cache memory 124 or buffer 126. In some examples, controller 116 triggers a refresh of cache memory 124 by writing data stored in cache memory 124 to the second storage device 130. For example, controller 116 triggers a refresh of cache memory 124 at a predetermined frequency. Alternatively, controller 116 triggers a refresh of cache memory 124 based on a smart refresh strategy. The intelligent refresh strategy can be determined based on the fill level of the cache memory 124, the duration of data storage, or the access pattern.

[0040] In block 208, processor 102 may receive a second write request for storing second data at a second storage address. The write request, data, and storage address mentioned in block 202 may be referred to as a first write request, first data, and first storage address, respectively. The second write request may have the same format as the first write request. In response to receiving the second write request, processor 102 may perform the method in block 204 to select a storage device from one or more storage devices. In some examples, when the second storage device 130 is selected as the storage device, controller 116 receives the second write request for storing the second data at the second storage address.

[0041] In block 210, controller 116 may cause second storage device 130 to store first data and second data. In some examples, controller 116 causes second storage device 130 to store first data and second data based on the cumulative size exceeding a first predetermined size threshold. For example, second storage device 130 stores first data and second data when the cumulative size of first data and second data exceeds the first predetermined size threshold. In some examples, controller 116 causes second storage device 130 to store first data and second data based on the fact that cache lines in cache memory 124 are substantially full. In some examples, controller 116 causes second storage device 130 to store first data and second data in response to the number of available cache lines in cache memory 124 being less than a preset number (e.g., 1). In some examples, controller 116 causes second storage device 130 to store first data and second data based on the fact that the first storage address and the second storage address are substantially adjacent storage addresses. For example, when first data and second data correspond to substantially adjacent storage addresses, the overhead of storing in second storage device 130 is shared between writing first data and second data, thereby improving efficiency. In some examples, controller 116 employs a smart cache eviction strategy that considers access frequency when deciding which cache lines to evict. Instead of removing data only when cache lines are substantially full (e.g., when the number of available cache lines in cache memory 124 exceeds a preset number), controller 116 retains frequently accessed data in cache memory 124 even if some less frequently accessed data has been present in cache memory 124 for a longer period. This prioritizes retaining frequently accessed data in the faster cache memory 124 rather than moving it to the slower secondary storage device 130. By implementing this access frequency-based eviction strategy, computing system 100 can optimize storage, reduce unnecessary data transfers between cache memory 124 and the secondary storage device 130, and improve overall system performance.

[0042] In some examples, controller 116 implements a read-before-write mechanism for storing new data batches in one or more substantially adjacent memory addresses. The read-before-write mechanism includes: receiving a write request for a new data batch containing multiple data items associated with one or more substantially adjacent memory addresses; reading the current data batch from the one or more substantially adjacent memory addresses from second storage device 130; storing the current data batch to first storage device 128; updating the current data batch with the new data batch to obtain the updated data batch; and writing the updated data batch to the second storage device. The read-before-write mechanism allows controller 116 to efficiently write data batches in substantially adjacent memory addresses by utilizing the faster write speed of first storage device 128 (e.g., static random access memory) while optimizing write operations to the larger but slower second storage device 130 (e.g., pseudo-static random access memory).

[0043] In some examples, controller 116 implements a direct write mechanism for storing new data batches in one or more substantially adjacent storage addresses. The direct write mechanism involves directly writing the new data batches to the second storage device 130 based on the determination that the number of one or more substantially adjacent storage addresses exceeds a predetermined threshold.

[0044] In some examples, processor 102 implements a data lifecycle management mechanism that tracks the duration and access patterns of stored data. Processor 102 can monitor and analyze the access frequency, time since the last access, and other relevant metrics of data stored in the first storage device 128 and the second storage device 130. Based on this analysis, processor 102 can identify whether data stored in the first storage device 128 has become less frequently accessed or has not been accessed for a specified period. In response to this identification, processor 102 can initiate a data migration process to move the identified data from the first storage device 128 to the second storage device 130. Processor 102 can coordinate with controller 116 to efficiently execute this data migration process. For example, processor 102 reads the identified data from the first storage device 128 and instructs controller 116 to write the identified data to the second storage device 130. In response to receiving the instruction from processor 102 to write the identified data to the second storage device 130, controller 116 can temporarily store the identified data in cache memory 124 or buffer 126. Controller 116 can write identified data to second storage device 130 according to the techniques described herein. In some examples, the data migration process can be performed during periods of low system activity to minimize the impact on overall system performance. In some examples, processor 102 can update the addresses associated with the identified data to reflect the new location of the migrated data in second storage device 130, ensuring that subsequent read or write requests for the migrated data are directed to the correct storage device. Processor 102 can also perform a reverse migration process for data that becomes frequently accessed again. In response to determining that a subset of data stored in second storage device 130 begins to show increased access frequency, processor 102 can initiate the migration of the data subset to first storage device 128 to improve the access speed of the frequently accessed data subset. By implementing this data lifecycle management mechanism, processor 102 can help maintain optimal performance for frequently accessed data while efficiently utilizing the larger capacity of second storage device 130 to store less active data. This approach can contribute to overall system efficiency and may improve the performance and energy efficiency of resource-constrained devices such as IoT or systems-on-a-chip.

[0045] In some examples, controller 116 may implement a data compression mechanism that compresses data stored in cache memory 124. This approach allows for more efficient use of cache memory 124 or the secondary storage device 130. The compression algorithm can be selected based on the data type and characteristics of the data stored in cache memory 124. For example, controller 116 may employ lightweight compression techniques (such as LZ77 or LZ78 algorithms), which offer a balance between compression ratio and computational overhead. Lightweight compression techniques can provide a degree of compression while maintaining fast access times. Traditional systems may be reluctant to implement compression techniques because the computational overhead associated with compression and decompression operations can consume valuable processing resources and potentially impact the overall system responsiveness of resource-constrained devices. In some examples, controller 116 may perform data compression in cache memory 124 during periods of low system activity or when computing system 100 is relatively idle, thus not impacting system performance during periods of high demand. The controller 116 can adaptively compress data in the cache memory 124, dynamically adjusting the compression level based on factors such as current load, available space in the cache memory 124, or data-related access patterns. For example, during periods of high cache memory 124 utilization, the controller 116 can apply more aggressive compression to optimize cache memory 124 usage, while during periods of low utilization, the controller 116 can prioritize faster access by using lighter compression or no compression.

[0046] By compressing the data in cache memory 124, controller 116 may increase the amount of data that can be stored in the cache, thereby reducing the frequency of data transfer between cache memory 124 and slower storage devices (such as second storage device 130). This approach may help optimize cache utilization, particularly in resource-constrained devices such as IoT or system-on-a-chip, potentially improving overall system performance and responsiveness.

[0047] Based on some examples, Figure 3 This is a flowchart illustrating more details of the data exchange methods in a computing system.

[0048] In block 302, controller 116 may receive a read request for reading data associated with a storage address. In some examples, controller 116 receives a read request when processor 102 determines that data is associated with second storage device 130 based on a storage address or primary identifier.

[0049] In block 304, if the data is stored in cache memory, controller 116 may return the data from cache memory. Block 304 may be executed upon determining that the data is stored in cache memory 124. In response to receiving a read request, controller 116 may cause cache memory 124 to return the data. For example, when controller 116 determines that the data is stored in cache memory 124, it causes cache memory 124 to return the data stored in cache memory 124.

[0050] In block 306, controller 116 can cause second storage device 130 to return data. In some examples, controller 116 uses second storage device 130 when data is not found in cache memory 124. In some examples, controller 116 causes second storage device 130 to return data based on determining that data is stored in second storage device 130. In some examples, when a batch of data containing first data and second data is stored in second storage device 130, controller 116 causes second storage device 130 to return the first data. In some examples, controller 116 can select a command code from a plurality of pre-configured command codes and send it to second storage device 130 to cause second storage device 130 to return data. These command codes may include different command codes configured for establishing communication with pseudo-static random access memory manufactured by different manufacturers.

[0051] In block 308, controller 116 may implement a prefetch mechanism. This prefetch mechanism may include causing the second storage device 130 to return data batches associated with multiple addresses. In some examples, reading from the second storage device 130 includes a preparatory operation. In some examples, the preparatory operation includes decoding the storage address to locate the requested data within the second storage device 130. In some examples, the preparatory operation includes activating an appropriate memory array or precharge bit line to prepare for reading data. In some examples, the prefetch mechanism includes retrieving a data batch containing data associated with a fundamentally adjacent storage address. For example, the data batch size is 16 to 256 bytes. By prefetching additional data, subsequent read requests for adjacent addresses can be returned from a temporary location (e.g., cache memory 124), potentially reducing pseudo-static random access memory read operations or associated overhead. In some examples, controller 116 implements an adaptive prefetch mechanism that dynamically adjusts the prefetch size (e.g., the size of the data batch to be prefetched) based on access patterns. For example, the prefetch size may be increased in response to the detection of sequential data access. The prefetch size may be decreased in response to the detection of a random access pattern. Adaptive prefetching mechanisms can optimize memory usage and reduce unnecessary data transfers.

[0052] Controller 116 helps maintain data consistency among multiple processors, such as processor 104 and processor 106. For example, controller 116 can determine whether data is stored in cache memory 124 or in a second storage device 130. When a processor sends a read request associated with a memory address, controller 116 returns the data associated with that memory address without processor 102 directly accessing the memory location, thus preventing inconsistency. In some examples, controller 116 manages the translation between memory addresses used by the processor and physical addresses in different storage devices, maintaining a consistent view of memory space for processor 102.

[0053] Based on some examples, Figure 4 This is a schematic diagram showing more details of the computing system 100.

[0054] The computing system 100 may include input / output components (I / O components) 402. I / O components 402 may include various components for receiving input, providing output, generating output, transmitting information, exchanging information, or capturing measurements. The specific I / O component 402 included in a particular machine depends on the machine type. For example, portable machines such as mobile phones may include touch input devices or other such input mechanisms, while headless server machines may not include such touch input devices. I / O component 402 may include... Figure 4 Many other components are not shown. In various examples, I / O component 402 may include output component 426 and input component 428. Output component 426 may include visual components (e.g., displays such as plasma display panels (PDPs), light-emitting diode (LED) displays, liquid crystal displays (LCDs), projectors, or cathode ray tubes (CRTs)), acoustic components (e.g., speakers), haptic components (e.g., vibration motors, resistance mechanisms), or other signal generators. Input component 428 may include alphanumeric input components (e.g., keyboards, touchscreens configured to receive alphanumeric input, photoelectric keyboards, or other alphanumeric input components), point-based input components (e.g., mice, touchpads, trackballs, joysticks, motion sensors, or other pointing tools), haptic input components (e.g., physical buttons, touchscreens or other haptic input components that provide touch location and / or force or touch gestures), audio input components (e.g., microphones), etc.

[0055] In a further example, I / O component 402 may include biometric component 430, motion component 432, environmental component 434 or position component 436, and many other components. For example, biometric component 430 includes components for detecting facial expressions (e.g., hand expressions, facial expressions, voice expressions, body posture, or eye tracking), measuring biosignals (e.g., blood pressure, heart rate, body temperature, sweating, or brain waves), or identifying a person (e.g., voice recognition, retinal recognition, facial recognition, fingerprint recognition, or electroencephalogram recognition). Motion component 432 includes accelerometer components (e.g., accelerometers), gravity sensor components, and rotation sensor components (e.g., gyroscopes). Environmental component 434 includes, for example, one or more cameras, illuminance sensor components (e.g., photometers), temperature sensor components (e.g., one or more thermometers for detecting ambient temperature), humidity sensor components, pressure sensor components (e.g., barometers), acoustic sensor components (e.g., one or more microphones for detecting background noise), proximity sensor components (e.g., infrared sensors for detecting nearby objects), gas sensors (e.g., gas detection sensors for detecting hazardous gas concentrations or measuring atmospheric pollutants for safety purposes), or other components that provide indications, measurements, or signals corresponding to the surrounding physical environment. Position component 436 includes position sensor components (e.g., Global Positioning System (GPS) receiver components), altitude sensor components (e.g., barometers or altimeters from which altitude can be derived), orientation sensor components (e.g., magnetometers), etc.

[0056] Communication can be implemented using various technologies. I / O component 402 also includes communication component 438, which can couple computing system 100 to network 422 or device 424 via its respective coupling or connection. For example, communication component 438 may include a network interface component or other device suitable for interfacing with network 422. In further examples, communication component 438 may include wired communication component, wireless communication component, cellular communication component, near field communication (NFC) component, etc. Components (e.g.) (low power consumption) Components, as well as other communication components, to provide communication in other ways. Device 424 can be another machine or any various peripheral devices (e.g., peripheral devices coupled via USB).

[0057] Furthermore, communication component 438 can detect identifiers or includes components that can detect identifiers. For example, communication component 438 may include a radio frequency identification (RFID) tag reader component, an NFC smart tag detection component, an optical reader component (e.g., an optical sensor for detecting one-dimensional barcodes such as Universal Product Code (UPC) barcodes, multi-dimensional barcodes such as Quick Response (QR) codes, Aztec codes, data matrices, data graphs, Maxi codes, PDF417, Ultra codes, UCC RSS-2D barcodes, and other optical codes), or an acoustic detection component (e.g., a microphone for identifying tag audio signals). Additionally, various information, such as location geolocation via Internet Protocol (IP), can be obtained through communication component 438. The location is determined by signal triangulation, or by detecting the location of an NFC beacon signal that indicates a specific location.

[0058] Example

[0059] Example 1 is a method comprising: generating a write request for writing data to a second storage device of a memory, the memory including a first storage device and a second storage device, the first storage device including static random access memory (SRAM) and the second storage device including pseudo static random access memory (PSRAM), the first storage device having a higher performance metric than the second storage device and a smaller capacity than the second storage device; receiving the write request by a controller coupled to the second storage device, wherein the controller includes a cache memory having one or more cache lines, the cache memory having a higher performance metric than the second storage device; overriding the write request for writing data to the second storage device by alternatively writing data to one or more cache lines in the memory; and writing data to the second storage device in response to one or more cache lines being substantially full.

[0060] Example 2 further includes, based on Example 1, wherein the write request is a first write request and the data is first data, and the method further includes: receiving a second write request by the controller for storing the second data in the second storage device; and storing the first data and the second data in the second storage device based on the fact that the storage addresses of the first data and the second data are substantially adjacent.

[0061] Example 3 further includes, based on Examples 1-2, wherein the write request is a first write request and the data is first data, the method further includes: receiving a second write request by the controller for storing the second data in the second storage device; and storing the first data and the second data in the second storage device in response to the number of available cache lines in the cache memory being less than a preset number.

[0062] Example 4 further includes, based on Example 3, receiving a read request for reading first data from a second storage device; and after storing the first data and the second data in the second storage device, causing the second storage device to return the first data.

[0063] Example 5 further includes, based on Examples 1-4, receiving a read request for reading data from a second storage device; and returning the data from the cache memory based on one or more cache lines stored in the cache memory.

[0064] Example 6 further includes, based on Examples 1-5, reading a current data batch located in one or more basic adjacent storage addresses from a second storage device; storing the current data batch in a first storage device; updating the current data batch with data to obtain an updated data batch; and writing the updated data batch to the second storage device.

[0065] Example 7 further includes, based on Examples 1-6, receiving a read request for reading data from a second storage device; and causing the second storage device to return a batch of data containing multiple data items, the multiple data items including the data, and the multiple addresses associated with the multiple data items being substantially adjacent storage addresses.

[0066] Example 8 further includes, based on Examples 1-7, storing the second data in the first storage device.

[0067] Example 9 further includes, based on Examples 1-8, a buffer in which the controller also includes a buffer, and the method further includes covering write requests by storing data in the buffer based on the data size exceeding a predetermined size threshold.

[0068] Example 10 is at least one machine-readable medium that includes instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any one of Examples 1-9.

[0069] Example 11 is a device that includes implementations of any one of Examples 1-9.

[0070] Example 12 is a system for implementing any one of Examples 1-9.

[0071] Example 13 is a method for implementing any one of Examples 1-9.

Claims

1. A computing system, comprising: comprise: one or more processors; and one or more storage devices, including a first storage device and a second storage device, the first storage device comprising static random access memory (SRAM), the second storage device comprising pseudo static random access memory (PSRAM), the first storage device having a performance metric superior to the second storage device and a capacity smaller than the second storage device; and, the second storage device being connected to a controller, the controller comprising a memory having a performance metric superior to the second storage device, the one or more storage devices storing instructions that, when executed by the one or more processors, configure the computing system to perform the following operations: receive a write request to write data to the second storage device; store the data in the memory; receive a read request to read the data from the second storage device; and return the data from the memory based on the data being stored in the memory; and, the write request being a first write request, the data being first data, the memory comprising a cache memory, the cache memory comprising one or more cache lines, the instructions further configuring the computing system to perform the following operations: receive a second write request to store second data in the second storage device; and store the first data and the second data into the second storage device in response to a number of available cache lines in the memory being below a predetermined number. the first write request comprising a first storage address, the instructions further configuring the computing system to perform the following operations: receive a second write request to store second data in the second storage device based on a second storage address; and 2. The computing system of claim 1, wherein, store the first data and the second data into the second storage device based on the first storage address and the second storage address being substantially adjacent. the read request being a first read request, the instructions further configuring the computing system to perform the following operations: receive a second read request to read the data from the second storage device; and cause the second storage device to return the data in response to the first data and the second data being stored in the second storage device.

3. The computing system of claim 1, wherein, the instructions further configuring the computing system to perform the following operations: read a current batch of data stored in one or more substantially adjacent storage addresses from the second storage device; store the current batch of data to the first storage device; update the current batch of data using a plurality of data items to obtain an updated batch of data; and 4. The computing system of claim 1, wherein, write the updated batch of data to the second storage device. the instructions further configuring the computing system to perform the following operations: in response to receiving the read request, cause the second storage device to return a batch of data comprising a plurality of data items, wherein the plurality of data items comprises the data, a plurality of addresses associated with the plurality of data items being substantially adjacent storage addresses. the instructions further configuring the computing system to perform the following operations: ​ ​ 5. The computing system of claim 1, wherein, ​ ​ 6. The computing system of claim 1, wherein, ​ receiving a second write request to write second data to the first storage device; and storing the second data in the first storage device.

7. The computing system of claim 1, wherein, The controller includes a buffer, and the instructions further configure the computing system to perform the following operations: based on the size of the data exceeding a predetermined size threshold, store the data in the buffer.

8. The computing system of claim 1, wherein, The instructions further configure the computing system to perform the following operations: identify information of the second storage device; based on the identified information, select a command code corresponding to the second storage device from a plurality of preconfigured command codes; and establish communication between the controller and the second storage device using the selected command code corresponding to the second storage device.

9. A computer-implemented data storage management method, characterized by, comprise: generating a write request to write data to a second storage device of a memory, the memory comprising the first storage device and the second storage device, the first storage device comprising a static random access memory (SRAM), the second storage device comprising a pseudo static random access memory (PSRAM), a performance metric of the first storage device being superior to the second storage device, and a capacity of the first storage device being less than the second storage device; receiving, by a controller connected to the second storage device, the write request, wherein the controller comprises a cache memory, the cache memory comprising one or more cache lines, a performance metric of the cache memory being superior to the second storage device; overriding the write request to write data to the second storage device by alternatively writing the data to one of the one or more cache lines of the cache memory; and in response to the one or more cache lines having been substantially filled, writing the data to the second storage device; the method further comprising the steps of: receiving a read request to read the data from the second storage device; and based on the data being stored in one of the one or more cache lines of the cache memory, returning the data from the cache memory; wherein the write request is a first write request, the data is first data, and the method further comprises: receiving, by the controller, a second write request to store second data in the second storage device; and in response to a number of available cache lines in the cache memory being below a predetermined number, storing the first data and the second data into the second storage device.

10. The method of claim 9, wherein, the method further comprising: based on storage addresses of the first data and the second data being substantially adjacent, storing the first data and the second data in the second storage device.

11. The method of claim 9, wherein, further comprising: receiving a read request to read the first data from the second storage device; and in response to storing the first data and the second data in the second storage device, causing the second storage device to return the first data.

12. The method of claim 9, wherein, further comprising: reading a current batch of data located at one or more substantially adjacent storage addresses from the second storage device; storing the current batch of data to a first storage device; updating the current batch of data using the data to obtain an updated batch of data; and writing the updated data batch to the second storage device.

13. The method of claim 9, wherein, Further comprising: causing the second storage device to return a data batch comprising a plurality of data items, the plurality of data items comprising the data, a plurality of addresses associated with the plurality of data items being substantially contiguous storage addresses.

14. The method of claim 9, wherein, Further comprising storing second data in the first storage device.

15. The method of claim 9, wherein, The controller further comprises a buffer, the method further comprising overriding the write request by storing the data in the buffer instead of writing to the second storage device based on a size of the data exceeding a predetermined size threshold.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a computing system, cause the computing system to perform operations of: generating a write request to write data to a second storage device of a memory, the memory comprising the first storage device and the second storage device, the first storage device comprising a static random access memory (SRAM), the second storage device comprising a pseudo static random access memory (PSRAM), a performance metric of the first storage device being superior to the second storage device, and a capacity of the first storage device being less than the second storage device; receiving, by a controller connected to the second storage device, the write request, wherein the controller comprises a cache memory, the cache memory comprising one or more cache lines, a performance metric of the cache memory being superior to the second storage device; overriding the write request to write data to the second storage device by alternatively writing the data to one of the one or more cache lines of the memory and writing the data to the second storage device in response to the one or more cache lines being substantially filled; the operations further comprising: receiving a read request to read the data from the second storage device; and returning the data from the cache memory based on the data being stored in the one of the one or more cache lines of the cache memory; wherein the write request is a first write request, the data is first data, the operations further comprising: receiving, by the controller, a second write request to store second data in the second storage device; and storing the first data and the second data into the second storage device in response to a number of available cache lines in the cache memory being below a predetermined number.

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