Hardware acceleration module and data reading method and device

Abstract

The invention provides a hardware acceleration module and a data reading method and device.The hardware acceleration module is connected with a storage module and a processing module and comprises a read-write controller, a data register, an address register and a comparison register; the data register is used for storing valid data read from the plurality of structural bodies in the storage module; the address register is used for storing address offsets corresponding to respective valid data in the plurality of structural bodies in the slave storage module; the comparison register is used for performing equal comparison on the read effective data; and the read-write controller is used for starting reading from the first structural body in the storage module to the end of the last structural body, and sending the read valid data to the processing module when the valid data is determined to meet a preset condition according to the comparison register. According to the scheme, the data reading efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and particularly to a hardware acceleration module and a method and device for reading data. Background Art

[0002] At present, in the field of non-volatile data storage technology, during the process of firmware managing Nand Flash particles, it is necessary to perform pattern matching on data stored in consecutive address spaces in the internal cache of the chip (such as index, address, etc. data) to find data addresses or other information that meet the requirements. After frequent operations on the internal storage buff, there will be many address space fragments in the internal storage buff, such as unused spaces of one or more 32-bit addresses, thus forming discretized address space fragments. In the prior art, reading data stored in discretized address space fragments takes a lot of time, thereby resulting in low reading efficiency of data in discrete storage spaces. Therefore, how to improve the efficiency of reading data has become an urgent problem to be solved. Summary of the Invention

[0003] The main technical problem to be solved by the present invention is the low reading efficiency of data in discrete spaces in the prior art.

[0004] According to a first aspect, a hardware acceleration module is provided. The hardware acceleration module is respectively connected to a storage module and a processing module. The storage module stores a plurality of structures, and each structure includes a data segment of valid data and a data segment of address offset. The hardware acceleration module includes a read-write controller, a data register, an address register, and a comparison register. The data register is used to store the valid data read from the plurality of structures in the storage module. The address register is used to store the address offset corresponding to the valid data of each of the plurality of structures in the storage module. The comparison register is used to perform an equality comparison on the read valid data. The read-write controller is used to: start reading from the first structure in the storage module until the last structure ends. Wherein, when reading any one of the structures and the any one structure is not the last structure, the valid data and the address offset of the any one structure are respectively written into the data register and the address register, and the next structure corresponding to the any one structure is read from the storage module according to the address indicated by the address offset of the any one structure; if it is determined that the last structure is read, the data reading of the plurality of structures is ended, and after reading each structure, all the read valid data are compared according to the comparison register to determine whether the read valid data meet a preset condition; if it is determined according to the comparison register that the valid data meet the preset condition, the read valid data are sent to the processing module, wherein the valid data can be traced by the processing module based on the address offset stored in the address register for the valid data.

[0005] According to a second aspect, a method for reading data is provided. The method is applied to a hardware acceleration module, and the hardware acceleration module is respectively connected to a storage module and a processing module. The method includes: starting to read from the first structure in the storage module until the end structure ends. When any one of the structures is read and the any one structure is not the end structure, the valid data and the address offset of the any one structure are respectively written into the data register of the hardware acceleration module and the address register of the hardware acceleration module, and the next structure corresponding to the any one structure is read from the storage module according to the address indicated by the address offset of the any one structure; if it is determined that the end structure is read, the data reading of the multiple structures is ended, and after each structure is read, all the read valid data are compared according to the comparison register of the hardware acceleration module to determine whether the read valid data meet a preset condition; if it is determined according to the comparison register that the valid data meet the preset condition, the read valid data are sent to the processing module, where the valid data can be traced by the processing module based on the address offset stored in the address register for the valid data.

[0006] According to a third aspect of the embodiments of the present application, a data reading device is provided. The device is applied to a hardware acceleration module, and the hardware acceleration module is respectively connected to a storage module and a processing module. The device includes: a reading unit, configured to start reading from the first structure in the storage module until the end structure ends. When any one of the structures is read and the any one structure is not the end structure, the valid data and the address offset of the any one structure are respectively written into the data register of the hardware acceleration module and the address register of the hardware acceleration module, and the next structure corresponding to the any one structure is read from the storage module according to the address indicated by the address offset of the any one structure; a judging unit, configured to end the data reading of the multiple structures if it is determined that the end structure is read, and after each structure is read, all the read valid data are compared according to the comparison register of the hardware acceleration module to determine whether the read valid data meet a preset condition; a sending unit, configured to send the read valid data to the processing module if it is determined according to the comparison register that the valid data meet the preset condition, where the valid data can be traced by the processing module based on the address offset stored in the address register for the valid data.

[0007] According to the hardware acceleration module of the above embodiment, through the hardware acceleration module provided with a read-write controller, a data register, an address register, and a comparison register, based on the read-write controller, it reads from the first structure in the storage module connected to the hardware acceleration module until the end structure, and after reading to the end structure and finishing reading the data of multiple structures, it compares all the read valid data according to the comparison register. Furthermore, when it is determined that the valid data meets the preset conditions according to the comparison register, the read valid data is stored in the data register and sent to the processing module connected to the hardware acceleration module, and at the same time, the address offset corresponding to the read valid data is stored in the address register. The solution of this application enables the read-write controller of the hardware acceleration module to continuously read the data of multiple structures in the storage module based on the valid data and the address offset of the start address of the next structure included in the structure, avoiding the increase in the reading duration caused by operations such as addressing in the storage module and improving the data reading efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0009] Figure 1 It is a schematic diagram of a data reading system according to an embodiment of the present application.

[0010] Figure 2 It is a schematic diagram of a hardware acceleration module according to an embodiment of the present application.

[0011] Figure 3 It is a timing schematic diagram of data reading by a hardware acceleration module according to an embodiment of the present application.

[0012] Figure 4 It is a flowchart of a data reading method according to an embodiment of the present application.

[0013] Figure 5 It is a block diagram of a data reading device according to an embodiment of the present application.

[0014] Figure 6 It is a hardware structure diagram of an electronic device according to an embodiment of the present application.

[0015] Through the above-mentioned accompanying drawings, specific embodiments of the present invention have been shown, and will be described in more detail hereinafter. These drawings and written descriptions are not intended to limit the scope of the inventive concept in any way, but to illustrate the concept of the present invention to those skilled in the art through specific embodiments. Detailed Embodiments

[0016] The present invention will be further described in detail below in conjunction with the accompanying drawings through specific embodiments. Similar elements in different embodiments are labeled with related similar element numbers. In the following embodiments, many details are described to enable a better understanding of the present application. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification to avoid submerging the core part of the present application with excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0017] In addition, the features, operations, or characteristics described in the specification can be combined in any appropriate manner to form various embodiments. At the same time, the steps or actions in the method description can also be reordered or adjusted in an obvious manner by those skilled in the art. Therefore, the various sequences in the specification and drawings are only for clearly describing a certain embodiment and do not mean that they are necessary sequences, unless it is stated that a certain sequence must be followed.

[0018] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, both include direct and indirect connection (coupling).

[0019] Currently, for the management of address space fragmentation caused during the process of firmware managing Nand Flash particles in the field of non-volatile data storage technology, the traditional approach is to defragment the internal storage buff to improve the utilization rate of the internal storage buff. During this operation, the internal storage buff used for data transfer between the host and the NandFlash particles will be paused, which will affect the performance of the overall chip. Or these fragmented spaces are left ignored, and when a large amount of space for storing data becomes invalid next time, they are cleaned up collectively. However, the existing methods will lead to low data reading efficiency and low utilization rate of the storage space.

[0020] In an embodiment of the present invention, a hardware acceleration module provided with a read-write controller, a data register, an address register, and a comparison register reads from the first structure in a storage module connected to the hardware acceleration module until the end structure based on the read-write controller, and when reading to the end structure and ending the data reading of multiple structures, and after reading each structure, compares all the read valid data according to the comparison register. Furthermore, when it is determined that the valid data meets a preset condition according to the comparison register, the read valid data is stored in the data register and sent to a processing module connected to the hardware acceleration module, and at the same time, the address offset corresponding to the read valid data is stored in the address register. The solution of the present application enables the read-write controller of the hardware acceleration module to continuously read data from multiple structures in the storage module based on the address offset including valid data and the start address of the next structure in the structure, avoiding the increase in the reading duration caused by operations such as addressing in the storage module, and improving the data reading efficiency.

[0021] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices. The flowcharts shown in the drawings are only illustrative and do not necessarily include all the contents and operations / steps, nor do they necessarily need to be executed in the described order. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to the actual situation.

[0022] Please refer to Figure 1 , Figure 1 which shows a hardware acceleration module provided by an embodiment of the present application. In a specific embodiment, the hardware acceleration module 120 is respectively connected to a storage module 110 and a processing module 130, as Figure 1 shown. The storage module stores multiple structures, and each structure includes a data segment of valid data and a data segment of address offset. The hardware acceleration module 120 includes a read-write controller 121, a data register 124, an address register 122, and a comparison register 123, as Figure 2As shown in the figure, the data register is used to store the valid data read from multiple structures in the storage module; the address register is used to store the address offsets corresponding to the valid data of each of the multiple structures in the storage module; the comparison register is used to perform an equality comparison on the read valid data; the read / write controller is configured to: start reading from the first structure in the storage module until the last structure ends. When any one of the structures is read and the any one structure is not the last structure, the valid data and the address offset of the any one structure are respectively written into the data register and the address register, and the next structure corresponding to the any one structure is read from the storage module according to the address indicated by the address offset of the any one structure; if it is determined that the last structure is read, the data reading of the multiple structures is ended, and after each structure is read, all the read valid data are compared according to the comparison register to determine whether the read valid data meet a preset condition; if it is determined according to the comparison register that the valid data meet the preset condition, the read valid data are sent to the processing module, where the valid data can be traced by the processing module based on the address offset stored in the address register for the valid data.

[0023] Currently, in the field of non-volatile data storage technologies, such as storage hardware like EMMC, UFS, SSD, etc., during the firmware management of Nand Flash particles, it is necessary to perform pattern matching on the data (such as index, address, etc.) stored in the continuous address space of the internal cache of the chip to find the data addresses or other information that meet the requirements. After frequent operations on the internal storage buff, there will be more address space fragments in the internal storage buff. When such address space fragments gradually accumulate and increase, the storage space where the corresponding data is located is distributed in a non-continuous and scattered manner on the physical or logical storage medium. This storage mode may lead to a decrease in access efficiency, an increase in management complexity, or in order to adapt to scenarios (such as distributed systems), in order to improve scalability or fault tolerance, the storage space is actively set as a discrete storage space, which in turn makes the process of reading data complex and the reading efficiency low. Therefore, to solve this problem, the solution of this application sets up a hardware acceleration module, and in this hardware acceleration module, there are a read / write controller, a data register, an address register, and a comparison register. Thus, through the read / write controller, the data register, the address register, and the comparison register, the structures stored in the storage module connected to the hardware acceleration module are read for data, and the read valid data are sent to the processing module connected to the hardware acceleration module, so as to achieve fast reading of the data stored in the storage module and improve the data processing efficiency.

[0024] As a way to ensure that the hardware acceleration module can read data from multiple structures stored in the storage module, a read-write controller can be set in the hardware acceleration module, so as to read data from multiple structures stored in the storage module based on the connection relationship between the hardware acceleration module and the storage module through the read-write controller.

[0025] As a way to ensure that the storage space in the discrete space of the storage module can be fully utilized and to avoid the problem of low data access efficiency caused by the complexity of fragmentation storage allocation and addressing, multiple structures composed of valid data and address offsets can be set to fill the corresponding discrete space. Optionally, each structure includes a data segment of valid data and a data segment of the address offset corresponding to the valid data, so as to store the valid data dispersedly in discontinuous areas and track the position of the valid data through the address offset.

[0026] Optionally, the discrete space can be first divided into blocks according to a fixed size to obtain data blocks, and then the valid data and the address offset are respectively stored in each data block after division. For example, the discrete space can be divided into blocks according to a size of 64 bits, so that each structure is 64 bits in size, where the upper 32 bits are used to store valid data and the lower 32 bits are used to store the address offset. Optionally, the storage module can be a module using SRAM, with a certain number of address fragments inside and filled with structures including data segments of valid data and data segments of address offsets, thereby improving the storage space utilization rate of the storage module.

[0027] Optionally, in order to be able to perform continuous data reading operations on multiple structures in the discrete storage space of the storage module, the read-write controller of the hardware acceleration module can sequentially read data from multiple structures. In this way, the order in which the read-write controller reads multiple structures is to start reading from the first structure until the last structure is read, and then the data reading operation on multiple structures in the storage module is completed.

[0028] Optionally, in order to ensure that the data read by the hardware acceleration module is complete data, when the last structure is read, the read-write controller is controlled to stop the reading operation in the storage module, and it is determined whether the data read by the read-write controller meets the preset conditions according to the comparison register. In this way, only when it meets the conditions, the valid data read is stored in the data register in the hardware acceleration module, and the address offset of the valid address is stored in the address register in the hardware acceleration module, and at the same time, the valid data read is sent to the processing module, so that the processing module can process based on the received valid data.

[0029] Optionally, to ensure that the data received by the processing module is complete and valid data, when the read-write controller reads the last structure, all the data read from the first structure to the last structure is compared and matched to determine whether all the data read by the read-write controller meets the preset conditions. Furthermore, when it is determined that all the data meets the preset conditions, all the read data is sent to the processing module.

[0030] Optionally, to accurately determine whether the data read by the read-write controller meets the preset conditions, a comparison register can be set in the hardware acceleration module. After the read-write controller finishes the data reading operation on multiple structures in the storage module, the preset conditions and the corresponding comparison data stored in the comparison register are obtained, and then it is determined whether all the read data meets the preset conditions. Optionally, the patterns to be matched, such as strings, regular expressions, or binary feature templates, can be pre-stored in the comparison register for setting the preset conditions.

[0031] Optionally, when it is determined that all the valid data read by the read-write controller meets the preset conditions, it is determined that the read-write controller has completed the data reading operation on multiple structures in the storage module. To ensure that the subsequent processing module can process the valid data, a data register and an address register can be set in the hardware acceleration module. In this way, the valid data is stored in the data register respectively, and the address offset corresponding to the valid data is stored in the address register, so that the valid data stored in the data register can be sent to the processing module, enabling the processing module to process the valid data received from the data register.

[0032] Optionally, during the process of the processing module processing the valid data, to ensure the accuracy of the processing result, the processing module can trace the valid data according to the address offset stored in the address register, so as to know the source of the valid data and ensure that the valid data is valid. Optionally, it can be that the processing module receives a tracing instruction sent by other processors or verifies the source of the valid data during the process of processing the valid data, and the valid data can be traced based on the address register in the hardware acceleration module.

[0033] Optionally, to ensure that the processing module can trace the address offset stored in the address register based on the valid data, the corresponding relationship between the valid data and the address offset in the structure of the storage module can be stored, or the identifier of the corresponding address offset can be carried in the valid data, so that the corresponding address offset can be determined based on the identifier of the valid data, and it can be determined whether there is an address offset with the same identifier in the address register, so as to achieve tracing, or the address offset can also be sent to the processing module at the same time, so that the processing module can trace the valid data through the address offset.

[0034] In the embodiment of the present application, through a hardware acceleration module provided with a read-write controller, a data register, an address register, and a comparison register, the read-write controller reads from the first structure in the storage module connected to the hardware acceleration module until the end structure, and when reading to the end structure and finishing reading the data of multiple structures, all the read valid data are compared according to the comparison register. Then, when it is determined that the valid data meets the preset conditions according to the comparison register, the read valid data is stored in the data register and sent to the processing module connected to the hardware acceleration module, and at the same time, the address offset corresponding to the read valid data is stored in the address register. The solution of the present application enables the read-write controller of the hardware acceleration module to continuously read the data of multiple structures in the storage module based on the valid data and the address offset of the start address of the next structure included in the structure, avoiding the increase in the reading duration caused by operations such as addressing in the storage module and improving the data reading efficiency.

[0035] In some embodiments, the read-write controller compares the sizes of all the read valid data according to the comparison register to determine whether the read valid data meets the preset conditions, including: if the read-write controller determines that the end structure is read in the multiple structures, it obtains the comparison data size configured in the comparison register; the read-write controller makes an equality comparison between the actual data size of the read valid data and the comparison data size to obtain a comparison result; if the read-write controller determines that the comparison result indicates that the actual data size is equal to the comparison data size, it determines that the read valid data meets the preset conditions.

[0036] As a way, to ensure the accuracy of the valid data received by the processing module, when the read-write controller reads the end structure and determines to end the operation of reading the data of multiple structures in the storage module, all the read valid data from the first structure to the end structure are compared based on the comparison register. Thus, when it is determined that all the read valid data meet the preset conditions, the read-write controller sends the valid data to the processing module.

[0037] Optionally, since the pattern to be matched, such as a string, a regular expression, or a binary feature template, etc., is stored in advance in the comparison register, the comparison data size corresponding to the data required in the pattern to be matched in the comparison register can be directly obtained, so as to facilitate determining whether the valid data meets the preset conditions based on the comparison data size.

[0038] Optionally, to ensure the integrity of the valid data received by the processing module, the read-write controller may first determine the actual data size corresponding to all the read valid data, and then compare the actual data size with the comparison data size to determine whether the valid data actually read by the read-write controller is complete.

[0039] Optionally, when it is determined that the actual data size is equal to the comparison data size, it can be determined that all the valid data read by the read-write controller is complete, so as to determine that the read valid data meets the preset conditions. Then, all the valid data can be stored in the data register, the address offset that meets the preset conditions can be stored in the address register, and at the same time, all the valid data can be sent to the processing module, so that the processing module can process the valid data according to actual needs.

[0040] Optionally, if it is determined that the actual data size is not equal to the comparison data size, it is determined that there may be a read-write error in the read-write controller. Thus, the read-write controller can be controlled to re-perform the data reading operation from the first structure in the storage module until the last structure is read, thereby ending the data reading operation of the structure, and then determining again whether the read valid data meets the preset conditions according to the comparison register.

[0041] Optionally, when it is determined that the valid data corresponding to any one of the read structures does not meet the preset conditions, the structure can be re-read, and it is determined again whether the read valid data meets the preset conditions. Or, when it is determined that the valid data corresponding to any one of the read structures does not meet the preset conditions, an error message can be generated to prompt the user that the data reading fails.

[0042] In some embodiments, the read-write controller is further configured to obtain the reference data size corresponding to any one of the multiple structures in the storage module, and configure the comparison data size of the comparison register according to the reference data size.

[0043] As a way to further ensure the accuracy of valid data, when configuring the comparison register, the reference data size corresponding to any one structure in the storage module can be determined first, and then the reference data size corresponding to any one structure can be configured as the comparison data size in the comparison register. Or the total reference data size can be determined based on the reference data size corresponding to any one structure and the number of all structures, and then the total reference data size can be configured as the comparison data size in the comparison register, so as to ensure that the valid data read by the read / write controller in the hardware acceleration module can be determined to be complete based on the total parameter data size actually corresponding to all structures in the storage module, avoiding the subsequent work of the processing module being affected due to incomplete data read by the acceleration module being sent to the processing module.

[0044] In some embodiments, for the multiple structures stored in the storage module, the address offset of the previous structure is the start address of the next structure; the address offset of the last structure is an invalid address; the read / write controller is further configured to determine whether the structure read is the last structure; wherein, when the read / write controller determines whether the address offset of the structure read is an invalid address, if so, it is determined that the structure read is the last structure, otherwise, it is determined that the structure read is not the last structure.

[0045] As a way to improve the storage space utilization rate of the storage module and the reading efficiency of valid data, in any one of the multiple structures of the storage module, the data segment of the valid data and the data segment of the address offset can be combined, and the address indicated in the data segment of the address offset is the start address of the next structure, that is, a structure includes the valid data of the current structure and the address offset of the next structure, so that the next structure can be continuously read after the current structure is read, without re-addressing the structure.

[0046] Optionally, in order to prevent the read / write controller of the hardware acceleration module from continuously performing data read operations in the storage module, the address offset corresponding to the last structure in the multiple structures of the storage module is set to an invalid address, and the read / write controller is configured to end the data read operation on the storage module when an invalid address is read.

[0047] In some embodiments, the hardware acceleration module is connected to the storage module in a manner of direct port connection.

[0048] As a way to improve the data reading efficiency of the hardware acceleration module from the storage module, the hardware acceleration module and the storage module can be connected by direct port connection. Among them, there are end-to-end data transfer interfaces in both the hardware acceleration module and the storage module, and the REQ / ACK mode can be used to transfer data between the hardware acceleration module and the storage module with end-to-end connection, reducing the time overhead brought by the data transfer protocol.

[0049] In some embodiments, the read-write controller is further configured to read the valid data corresponding to the Nth structure and the address offset of the (N + 1)th structure in multiple structures within N clock signals.

[0050] As a way to ensure that the hardware acceleration module can continuously read data in the discrete space of the storage module, the valid data stored in the current structure is read within the corresponding current clock signal, so as to read the address offset of the next structure, and based on the address offset, determine the position of the valid data corresponding to the next structure, and realize the continuous reading of multiple structures. As Figure 3 shown, the starting address of the first structure is read within the first clock signal and the first valid period of the request signal. Since the end-to-end transmission interface is adopted, the hardware acceleration module can read the valid data of the first structure and the address offset as the starting address of the next structure during the first valid period of the acknowledgment signal (at this time, it is also during the second valid period of the request signal), and read the corresponding valid data and the address offset as the starting address of the next structure according to the starting address of the second structure read within the second clock signal and the first valid period of the acknowledgment signal, and so on, until the invalid address in the last structure is read.

[0051] In some embodiments, the hardware acceleration module further includes a target address register, and the target address register is used to store the address of the valid data of the first structure in the multiple structures; the read-write controller obtains the address of the valid data of the first structure from the target address register, and reads the first structure from the storage module according to the address of the valid data of the first structure.

[0052] As a way to avoid the need for the read-write controller to spend a large amount of time addressing the first structure among multiple structures in the storage module when reading data from them, the first structure among the multiple structures can be stored at a fixed address in the storage module first, and then written to the target address register in the hardware acceleration module in advance based on this fixed address, so that the hardware acceleration module can read the valid data corresponding to the first structure and the address offset serving as the starting address of the next structure from the storage module based on the address of the valid data of the first structure in the target address register, thereby achieving continuous data reading from multiple structures.

[0053] In some embodiments, the read data bit width of the read-write controller is greater than the processing data bit width of the processing module.

[0054] As a way to further improve the read efficiency of the hardware acceleration module for reading data from the storage module, the processing data bit width corresponding to the processing module can be determined first, and then the read data bit width of the read-write controller can be configured based on the processing data bit width, so that the read data bit width of the read-write controller is greater than the processing data bit width of the processing module, thereby achieving a higher data throughput.

[0055] As another way, it is also possible to determine the data bit width occupied by any structure in the storage module, and thereby set the read-write data bit width of the read-write controller to the data bit width occupied by any structure in the storage module, so as to ensure that the read-write controller can read the complete data segment corresponding to the structure within one clock signal.

[0056] Please refer to Figure 4 , Figure 4 which shows the data reading method provided by an embodiment of the present application. In a specific embodiment, this data reading method can be applied to a data reading device 300 as shown in Figure 5 and an electronic device 400 configured with the data reading device 300 ( Figure 6 ). The specific process of this embodiment will be described below. Of course, it can be understood that this method can be executed by a computer terminal with computing and processing capabilities, or by other processors, or by a storage chip. The following will elaborate in detail on the process shown in Figure 4 . The data reading method can specifically include the following steps: Step 210: Read from the first structure in the storage module until the end structure. When any structure is read and it is not the end structure, write the valid data and address offset of the any structure into the data register of the hardware acceleration module and the address register of the hardware acceleration module respectively, and read the next structure corresponding to the any structure from the storage module according to the address indicated by the address offset of the any structure.

[0057] Step 220: If it is determined that the end structure is read, end the data reading of the multiple structures, and compare all the read valid data according to the comparison register of the hardware acceleration module after each structure is read to determine whether the read valid data meets the preset conditions.

[0058] Step 230: If it is determined according to the comparison register that the valid data meets the preset conditions, send the read valid data to the processing module, where the valid data can be traced by the processing module based on the address offset stored in the address register for the valid data.

[0059] In some embodiments, the multiple structures are stored in the storage module. In the multiple structures, each structure includes valid data and an address offset. The address offset of the previous structure is the starting address of the next structure, and the address offset of the end structure is an invalid address. The method further includes: determining whether the read structure is the end structure; judging whether the address offset of the read structure is an invalid address. If so, it is determined that the read structure is the end structure; otherwise, it is determined that the read structure is not the end structure.

[0060] In the embodiments of the present application, the hardware acceleration module is used to read data of multiple structures, so that continuous reading of multiple structures can be realized based on the data segment including valid data in any structure and the address offset serving as the starting address of the next structure, thereby quickly and accurately reading the valid data, improving the utilization rate of the storage space and the reading efficiency of the valid data at the same time. And when it is determined that the end structure is read and the data reading of the multiple structures is ended, it is determined whether the read valid data meets the preset conditions according to the comparison register, and the valid data is sent to the processing module only when it is determined that the preset conditions are met, ensuring the accuracy of the valid data received by the processing module.

[0061] Figure 5 is a block diagram of a data reading device shown according to an embodiment of the present application, as Figure 5As shown, the data reading device 300 is applied to a hardware acceleration module. The hardware acceleration module is respectively connected to a storage module and a processing module. The data reading device 300 includes: a reading unit 310, a judging unit 320, and a sending unit 330.

[0062] The reading unit 310 is configured to read from the first structure body in the storage module until the end structure body ends. Among them, when any one of the structure bodies is read and the any one of the structure bodies is not the end structure body, the valid data and the address offset of the any one of the structure bodies are respectively written into the data register of the hardware acceleration module and the address register of the hardware acceleration module, and the next structure body corresponding to the any one of the structure bodies is read from the storage module according to the address indicated by the address offset of the any one of the structure bodies; the judging unit 320 is configured to, if it is determined that the end structure body is read, end the data reading of the multiple structure bodies, and compare all the read valid data according to the comparison register of the hardware acceleration module after each structure body is read, so as to judge whether the read valid data meets a preset condition; the sending unit 330 is configured to, if it is determined according to the comparison register that the valid data meets the preset condition, send the read valid data to the processing module, wherein the valid data can be traced by the processing module based on the address offset stored in the address register where the valid data is located.

[0063] In some embodiments, the multiple structure bodies are stored in the storage module. In the multiple structure bodies, each structure body includes valid data and an address offset. The address offset of the previous structure body is the start address of the next structure body, and the address offset of the end structure body is an invalid address. The data reading device 300 further includes: a first determining unit, configured to determine whether the read structure body is the end structure body; a second determining unit, configured to judge whether the address offset of the read structure body is an invalid address. If so, it is determined that the read structure body is the end structure body, otherwise, it is determined that the read structure body is not the end structure body.

[0064] According to one aspect of the embodiments of the present application, an electronic device is further provided, as Figure 6 shown. The electronic device 400 includes a processor 410 and one or more memories 420. The one or more memories 420 are used to store program instructions executed by the processor 410. When the processor 410 executes the program instructions, the above data reading method is implemented.

[0065] Further, the processor 410 may include one or more processing cores. The processor 410 runs or executes instructions, programs, code sets, or instruction sets stored in the memory 420, and calls data stored in the memory 420. Optionally, the processor 410 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 410 may integrate one or a combination of several of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, application programs, etc.; the GPU is responsible for rendering and drawing the display content; the modem is used to process wireless communication. It can be understood that the above modem may not be integrated into the processor and may be implemented separately through a communication chip.

[0066] According to one aspect of the present application, the present application also provides a computer-readable storage medium. The computer-readable medium may be included in the electronic device described in the above embodiments; or it may exist separately without being assembled into the electronic device. The above computer-readable storage medium carries computer-readable instructions, and when the computer-readable storage instructions are executed by a processor, the method in any of the above embodiments is implemented.

[0067] It should be noted that the computer-readable medium shown in the embodiments of the present application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device. In the present application, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, and this computer-readable medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0068] The units involved in the embodiments described in the present application can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not, in some cases, constitute a limitation on the unit itself.

[0069] The above uses specific examples to elaborate on the present invention, which is only for helping to understand the present invention and is not intended to limit the present invention. For those skilled in the technical field to which the present invention pertains, based on the idea of the present invention, several simple deductions, deformations, or substitutions can also be made.

Claims

1. A hardware acceleration module, characterized in that, The hardware acceleration module is respectively connected to the storage module and the processing module. The storage module stores a plurality of structures, and each structure includes a data segment of valid data and a data segment of address offset. The hardware acceleration module includes a read-write controller, a data register, an address register, and a comparison register; The data register is used to store the valid data read from the plurality of structures in the storage module; The address register is used to store the address offset corresponding to the valid data of each of the plurality of structures in the storage module; The comparison register is used to perform an equality comparison on the read valid data; The read-write controller is used for: Reading from the first structure in the storage module until the end structure is reached. Among them, when any one of the structures is read and the any one structure is not the end structure, the valid data and the address offset of the any one structure are respectively written into the data register and the address register, and the next structure corresponding to the any one structure is read from the storage module according to the address indicated by the address offset of the any one structure; If it is determined that the end structure is read, the data reading of the plurality of structures is ended, and after each structure is read, all the read valid data are compared according to the comparison register to determine whether the read valid data meet the preset conditions; If it is determined according to the comparison register that the valid data meet the preset conditions, the read valid data are sent to the processing module, where the valid data can be traced by the processing module based on the address offset stored in the address register.

2. The hardware acceleration module according to claim 1, wherein The comparing all the read valid data according to the comparison register to determine whether the read valid data meet the preset conditions includes: If the read-write controller determines that the end structure is read in the plurality of structures, it obtains the configured comparison data size in the comparison register; The read-write controller performs an equality comparison on the actual data size of the read valid data and the comparison data size to obtain a comparison result; If the read-write controller determines that the comparison result indicates that the actual data size is equal to the comparison data size, it determines that the read valid data meet the preset conditions.

3. The hardware acceleration module according to claim 2, characterized in that, The read-write controller is further used to obtain the reference data size corresponding to any one structure in the plurality of structures in the storage module, and configure the comparison data size of the comparison register according to the reference data size.

4. The hardware acceleration module according to claim 1, wherein For the plurality of structures stored in the storage module, the address offset of the previous structure is the start address of the next structure; the address offset of the end structure is an invalid address; The read-write controller is further configured to determine whether the read structure is the last structure; wherein, when the read-write controller determines whether the address offset of the read structure is an invalid address, if so, it is determined that the read structure is the last structure, otherwise, it is determined that the read structure is not the last structure.

5. The hardware acceleration module according to claim 1, characterized in that, The hardware acceleration module is connected to the storage module in a direct port connection manner.

6. The hardware acceleration module according to claim 1, wherein The hardware acceleration module further includes a target address register, and the target address register is used to store the address of the valid data of the first structure among the multiple structures; the read-write controller obtains the address of the valid data of the first structure from the target address register, and reads the first structure from the storage module according to the address of the valid data of the first structure.

7. The hardware acceleration module according to claim 1, characterized in that The read data bit width of the read-write controller is greater than the processing data bit width of the processing module.

8. A method for reading data, characterized in that, The method is applied to a hardware acceleration module, and the hardware acceleration module is respectively connected to a storage module and a processing module, and includes: Reading starts from the first structure in the storage module until the last structure ends. Among them, when any one of the structures is read and the any one structure is not the last structure, the valid data and the address offset of the any one structure are respectively written into the hardware acceleration module data register and the hardware acceleration module address register, and the next structure corresponding to the any one structure is read from the storage module according to the address indicated by the address offset of the any one structure; If it is determined that the last structure is read, the data reading of the multiple structures is ended, and after each structure is read, all the read valid data are compared according to the hardware acceleration module comparison register to determine whether the read valid data meet the preset conditions; When it is determined according to the comparison register that the valid data meet the preset conditions, the read valid data are sent to the processing module, wherein the valid data can be traced by the processing module based on the address offset stored in the address register.

9. The method according to claim 8, wherein The multiple structures are stored in the storage module. Among the multiple structures, each structure includes valid data and an address offset. The address offset of the previous structure is the starting address of the next structure, and the address offset of the last structure is an invalid address. The method further includes: Determining whether the read structure is the last structure; Judging whether the address offset of the read structure is an invalid address. If so, it is determined that the read structure is the last structure, otherwise, it is determined that the read structure is not the last structure.

10. A data reading device, characterized in that, The device is applied to a hardware acceleration module, and the hardware acceleration module is respectively connected to a storage module and a processing module, and includes: A reading unit for reading from the first structure in the storage module until the end structure, wherein when any one of the structures is read and the any one structure is not the end structure, the valid data and the address offset of the any one structure are respectively written into the data register of the hardware acceleration module and the address register of the hardware acceleration module, and the next structure corresponding to the any one structure is read from the storage module according to the address indicated by the address offset of the any one structure; A judging unit for ending the data reading of the multiple structures if it is determined that the end structure is read, and comparing all the read valid data according to the comparison register of the hardware acceleration module to judge whether the read valid data meets a preset condition; A sending unit for sending the read valid data to the processing module if it is determined according to the comparison register that the valid data meets the preset condition, wherein the valid data can be traced by the processing module based on the address offset stored in the address register where the valid data is located.

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