Chip test program processing method and test system

Abstract

The invention discloses a chip test program processing method and a test system. The method is applied to a test system and comprises the following steps: editing and transmitting a chip test program to a compiler through an editor; through a compiler, analyzing the chip test program based on a first configuration file including function information of each test device to obtain general test program data, the general test program data indicating that a plurality of target test devices in each test device are adapted to the chip test program in the function aspect; transmitting universal test program data to a converter through a compiler on the basis of the hardware abstraction layer of each piece of target test equipment under the condition of verifying that each piece of target test equipment adapts to a chip test program in the hardware aspect; and converting the general test program data into a target test program adapted to each target test device through the converter based on a second configuration file including the hardware information of each test device. According to the method, the universality and portability of the chip test program can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of chip testing, and in particular, to a method for processing a chip test program and a test system. Background Art

[0002] In the semiconductor industry, chip testing is crucial to ensure that the reliability and performance of products meet the design standards. With the continuous improvement of the integration and functional complexity of chips, the complexity of test programs for chip testing has also increased accordingly, and the development and maintenance of test programs have become the focus of attention.

[0003] In traditional chip testing, due to the specific interfaces and operation methods of different types of test equipment (Automatic Test Equipment, ATE), test programs are usually developed in a customized manner for each type of test equipment, making the test programs tightly coupled with specific test equipment. This tight coupling relationship limits the generality and portability of test programs. Summary of the Invention

[0004] The present invention provides a method for processing a chip test program and a test system, which can improve the generality and portability of chip test programs.

[0005] In a first aspect, an embodiment of the present invention provides a method for processing a chip test program, which is applied to a test system. The test system includes at least an editor, a compiler, a converter, and multiple test devices. Hardware abstraction layers are included on the multiple test devices. The method includes:

[0006] Editing and transmitting a chip test program to the compiler through the editor;

[0007] Parsing the chip test program by the compiler based on a first configuration file including function information of each of the test devices to obtain general test program data, where the general test program data indicates that multiple target test devices among the test devices are functionally adapted to the chip test program;

[0008] Transmitting the general test program data to the converter by the compiler based on the hardware abstraction layers of the target test devices on the premise of verifying that the target test devices are hardware-adapted to the chip test program;

[0009] Converting the general test program data into a target test program adapted to each of the target test devices by the converter based on a second configuration file including hardware information of each of the test devices.

[0010] Second aspect, an embodiment of the present invention provides a test system, which at least includes an editor, a compiler, a converter, and multiple test devices, and a hardware abstraction layer is included on each of the multiple test devices;

[0011] The editor is configured to edit and transmit a chip test program to the compiler;

[0012] The compiler is configured to parse the chip test program based on a first configuration file including function information of each of the test devices to obtain general test program data, and the general test program data indicates that multiple target test devices among the test devices are functionally adapted to the chip test program;

[0013] The compiler is configured to, based on the hardware abstraction layer of each of the target test devices, transmit the general test program data to the converter when verifying that each of the target test devices is hardware-adapted to the chip test program;

[0014] The converter is configured to convert the general test program data into a target test program adapted to each of the target test devices based on a second configuration file including hardware information of each of the test devices.

[0015] The technical solution of the embodiment of the present invention obtains a chip test program through editing by an editor; parses the chip test program into general test program data by a compiler, and the general test program data indicates that multiple target test devices are functionally adapted to the chip test program; then verifies through the compiler based on the hardware abstraction layer of each target test device to ensure that each target test device is hardware-adapted to the chip test program; finally, converts the general test program data into a target test program adapted to each target test device by a converter. This solution can abstract the chip test program into code that can be executed on different target test devices, reduces the tight coupling relationship between the chip test program and specific test devices, enables the chip test program to be independent of specific hardware implementation, and thus improves the generality and portability of the chip test program.

[0016] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 is a flowchart of a method for processing a chip test program provided in Embodiment 1 of the present invention;

[0019] Figure 2 is a schematic diagram of an abstraction framework provided in Embodiment 1 of the present invention;

[0020] Figure 3 is a schematic structural diagram of a test system provided in Embodiment 2 of the present invention;

[0021] Figure 4 is a schematic structural diagram of a test system provided in Embodiment 3 of the present invention. Detailed implementation manners

[0022] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0023] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily need to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0024] Embodiment 1

[0025] Figure 1 is a flowchart of a method for processing a chip test program provided in Embodiment 1 of the present invention. This embodiment is applicable to the situation of processing a chip test program to make it adaptable to multiple different test devices. The method is applied to a test system, and the test system at least includes an editor, a compiler, a converter, and multiple test devices, and a hardware abstraction layer is included on each of the multiple test devices.

[0026] As Figure 1 shown, the method includes:

[0027] S110. Edit and transmit the chip test program to the compiler through the editor.

[0028] Among them, the chip test program can be a test program for chip testing. The editor can be a part for editing the chip test program. The compiler can be a part for compiling the chip test program. In the test system, the editor and the compiler can be deployed on the same server or on different servers, which is not limited here.

[0029] In the test system, a user interface can be provided. Through the user interface, the user can remotely access the editor and write the chip test program in the editor using the Test Description Language (TDL). The editor responds to the operation of the user writing the program in the user interface to determine the chip test program. Among them, TDL can be a high-level programming language specially designed for chip testing, allowing users to write test logic in a hardware-independent manner. TDL provides a rich set of libraries and instruction sets for describing test operations and control logic.

[0030] When the chip test program is edited in the editor, the editor can transmit the chip test program to the compiler. The transmission method is not limited. For example, the editor realizes the transmission in response to the operation of the user transmitting the program in the user interface, or the editor automatically transmits when it detects that the chip test program is written.

[0031] S120. Parse the chip test program through the compiler based on the first configuration file including the function information of each test device to obtain general test program data, and the general test program data indicates that multiple target test devices among each test device are functionally adapted to the chip test program.

[0032] In the test system, multiple test devices can be included. The test device (Automatic Test Equipment, ATE) can be a device that can automatically execute a series of test operations based on the test program and can perform chip testing. The target test device can be a test device that is functionally adapted to the chip test program, that is, the function of the target test device supports the execution of the chip test program.

[0033] The first configuration file can be a configuration file indicating the functions of each test device in the test system. The first configuration file can include the function information of each test device, and the function information is the information indicating the function of the corresponding test device. Exemplarily, the function information can be the capability range of the test device, such as the voltage range supported by the test device, the frequency range supported by the test device, etc.

[0034] In this step, the chip test program can be compiled by a compiler to obtain the abstract syntax tree corresponding to the chip test program; based on the abstract syntax tree of the chip test program, it is possible to determine what specific test instructions are included in the chip test program, what functional support of the test equipment is required for each test instruction, what hardware support of the test equipment is required for each test instruction, and what test conditions correspond to each test instruction, etc.; based on the information determined above, functional matching can be performed in the first configuration file to determine the target test equipment among each test equipment that is functionally adapted to the chip test program; in the case of determining the target test equipment, the content determined based on the abstract syntax tree can be combined with the target test equipment to obtain general test program data. Among them, the general test program data can be data parsed from the chip test program and is used to abstract the chip test program into a test program adapted to different target test equipment.

[0035] The general test program data can indicate that multiple target test equipment among each test equipment are functionally adapted to the chip test program, that is, multiple target test equipment among each test equipment all meet the capability range required for executing the chip test program.

[0036] In one embodiment, the general test program data further indicates:

[0037] Test configuration information, indicating the test conditions corresponding to the chip test program, the corresponding test hardware, and the hardware connection relationship of the test hardware in each of the target test equipment;

[0038] Test method information, indicating the methods that each of the target test equipment needs to execute through the test hardware when executing the chip test program;

[0039] Test sequence information, indicating the execution sequence of the methods that each of the target test equipment needs to execute.

[0040] The test configuration information can be information related to the configuration of the test. The test configuration information can indicate the following content: the test conditions corresponding to the chip test program, and the test conditions can be the conditions that need to be met when executing the chip test program for testing, specifically, the conditions that the input or output of the chip should meet during testing, etc.; the test hardware corresponding to the chip test program, and the test hardware can be the test board required for executing the chip test program, and the test board can be inserted into the test equipment to realize the corresponding functions of the test board; the hardware connection relationship of the test hardware in each target test equipment, that is, the connection relationship between the pins of the test hardware and the target test equipment.

[0041] The test method information may be information related to the test method. The test method information may indicate what kind of test hardware in each target test device is required to execute what method when executing the chip test program.

[0042] The test sequence information may be information about the sequence corresponding to the test method information. The test sequence information may indicate the execution sequence of the methods to be executed by each target test device when executing the chip test program, and the execution sequence is the order of method execution.

[0043] Exemplarily, analyzing the abstract syntax tree of the chip test program, assume the following test instructions are obtained:

[0044] Test instruction 1: Send a call to the waveform generator to generate a sine wave with an amplitude of 2V.

[0045] Test instruction 2: Send a call to the analog-to-digital converter to collect an analog signal at a sampling rate of 1000 samples per second and convert it into a digital signal, and the reference voltage of the analog-to-digital converter is 2V.

[0046] Based on the above example, the target test device should support a voltage of 2V and a sampling rate of 1000 samples per second in terms of function; the target test device should support including a waveform generator and an analog-to-digital converter in terms of hardware.

[0047] Assume there are two target test devices, namely device one and device two. Then the test configuration information may indicate: the test conditions corresponding to the above two test instructions, that device one should include a waveform generator and an analog-to-digital converter, and the pin connection relationship between the waveform generator and the analog-to-digital converter and the hardware of device one. The test method information may indicate: device one should generate a sine wave with an amplitude of 2V through the waveform generator, and device one should collect an analog signal at a sampling rate of 1000 samples per second through the analog-to-digital converter and convert it into a digital signal, and the reference voltage of the analog-to-digital converter is 2V. The test sequence information may indicate: device one first executes the generation of a sine wave with an amplitude of 2V, and then executes the sampling and signal conversion of the analog-to-digital converter. Correspondingly, the same applies to device two, which will not be elaborated here.

[0048] S130, through the compiler, based on the hardware abstraction layer of each target test device, when verifying that each target test device is hardware-adapted to the chip test program, transmit the general test program data to the converter.

[0049] In the embodiments of the present invention, each test device in the test system may include a Hardware Abstraction Layer (HAL). The HAL can be an intermediate layer that provides a set of unified interfaces for accessing the hardware resources of different test devices. The HAL hides the specific details of the hardware, enabling the chip test program to interact with the hardware in different test devices through these unified interfaces.

[0050] As mentioned in S120, through the general test program data, it can be indicated what kind of hardware support the target test device is required to have for executing the chip test program. For example, in the above example, the target test device is required to support a waveform generator and an analog-to-digital converter in terms of hardware, and the waveform generator is used to generate sine waves.

[0051] In this step, the hardware abstraction layer of each target test device can be accessed through a compiler to verify whether the test hardware in the target test device meets the hardware support required for executing the chip test program. If it meets the requirements, the verification passes, that is, it is determined that the target test device is hardware-adapted to the chip test program, and the general test program data is transmitted to the converter. The specific manner of implementing the transmission of the general test program data is not limited here. Exemplarily, when the HAL is abstracted, the test hardware for generating sine waves and square waves can be abstracted as waveform generators. This step is to verify whether there is a waveform generator in the target test device that can generate sine waves.

[0052] S140: Through the converter, based on a second configuration file including the hardware information of each test device, convert the general test program data into a target test program adapted to each target test device.

[0053] The converter can be the part that converts the general test program data into a target test program adapted to different target test devices. In the test system, the converter can be deployed on the same server as the editor and the compiler, or on different servers, which is not limited here.

[0054] The target test program can be a test program adapted to the target test device obtained by converting the chip test program. The target test programs corresponding to different target test devices may be different, but they can all execute the test instructions corresponding to the chip test program.

[0055] The second configuration file can be a configuration file indicating the hardware of each test device in the test system. The second configuration file may include the hardware information of each test device, and the hardware information is the information indicating the hardware of the corresponding test device. Exemplarily, the hardware information can indicate what test hardware is included in the test device, the traces and electrical specifications of the included test hardware, etc. This part of the test hardware is the hardware in the test device before unified abstraction.

[0056] In this step, for any target test device, the hardware configuration part for the target test device can be determined in the second configuration file; then, through the converter, based on the determined hardware configuration part, the general test program data is converted into a target test program adapted to the target test device, specifically as follows: during the conversion, for the conversion of the test configuration information in the general test program data, the target test program can include the test conditions, test hardware, and hardware connection relationships corresponding to the target test device in the test configuration information; for the conversion of the test method information in the general test program data, the target test program can include the methods that the target test device should execute in the test method information; for the conversion of the test sequence information in the general test program data, the execution sequence of the methods that the target test device should execute in the target test program is consistent with the execution sequence of the methods that the target test device should execute in the test sequence information. Through the above method, the general test program data can be converted into target test programs adapted to different target test devices.

[0057] Figure 2 is a schematic diagram of an abstraction framework provided in the first embodiment of the present invention. The abstraction framework is reflected in the editor, compiler, HAL, and converter. With reference to this abstraction framework, Figure 1 the method shown is more intuitively illustrated. Specifically, the editor edits the chip test program and transmits it to the compiler; the compiler parses the chip test program based on the first configuration file to obtain the general test program data; the compiler verifies whether each target test device is hardware-adapted to the chip test program based on the hardware abstraction layer (HAL) of each target test device. If it is adapted, the general test program data is transmitted to the converter; the converter converts the general test program data into a target test program adapted to the target test device based on the second configuration file. The hardware interface of the target test device is the interface for accessing the test hardware of the target test device.

[0058] The core purpose of the above abstraction framework is to decouple the chip test program from specific test devices, enabling the chip test program to run across different test devices without the need for custom development for each type of hardware.

[0059] In the technical solution of the embodiment of the present invention, a chip test program is obtained by editing through an editor; the chip test program is parsed into general test program data by a compiler, and the general test program data indicates that multiple target test devices are functionally adapted to the chip test program; then the compiler verifies based on the hardware abstraction layer of each target test device to ensure that each target test device is hardware-adapted to the chip test program; finally, the general test program data is converted into a target test program adapted to each target test device by a converter. This solution can abstract the chip test program into code that can be executed on different target test devices, reducing the tight coupling relationship between the chip test program and specific test devices, enabling the chip test program to be independent of specific hardware implementation, and thus improving the generality and portability of the chip test program.

[0060] In one embodiment, the test system further includes a version control system and an automatic test deployment tool. Correspondingly, editing and transmitting the chip test program to the compiler through the editor includes:

[0061] Obtaining a chip test program by editing through the editor, and submitting the chip test program to a code repository in combination with the version control system;

[0062] When it is determined that there is a code change in the code repository through the automatic test deployment tool, transmitting the chip test program corresponding to the code change to the compiler.

[0063] Among them, the version control system can be a part for tracking the version of the test program in the test system, can be deployed on a server, is used to track the change history and version iteration of the test program, and supports multi-user collaborative development. The automatic test deployment tool can be a part for automating the construction, testing, and deployment processes of the test program in the test system, can be deployed on a server, and the automatic test deployment tool can be understood as continuous integration (CI) / continuous deployment (CD).

[0064] Obtaining a chip test program by editing through the editor, and submitting the chip test program to the code repository through the version control system. The submission operation can be implemented by the editor and the version control system in response to the user's operation of submitting code on the user interface; the automatic test deployment tool can monitor the changes in the code repository, and when it is determined that there is a code change in the code repository, automatically trigger compilation, testing, and deployment tasks, that is, automatically transmit the chip test program corresponding to the code change to the compiler, trigger the subsequent operations of S120 - S140, and trigger the operation of deploying the target test program obtained in S140 to the corresponding target test device for testing.

[0065] In one embodiment, the test system further includes a task scheduler and a central control node. Correspondingly, after converting the general test program data into target test programs adapted to each of the target test devices, the method further includes:

[0066] Transmitting, through the converter, the target test programs of each of the target test devices to the task scheduler;

[0067] Determining, through the task scheduler and in combination with the central control node, the test devices to be executed among each of the target test devices, and transmitting the target test programs of the test devices to be executed to the test devices to be executed, where the test devices to be executed are used to execute the test tasks corresponding to the chip test program;

[0068] Executing, through the test devices to be executed, the received target test programs, and transmitting the corresponding execution results to the central control node.

[0069] Among them, the task scheduler can be the part in the test system for scheduling test tasks and can be deployed on a server. The central control node can be the node responsible for coordinating work in the entire test system, including task allocation, result collection, and status monitoring.

[0070] After converting the general test program data into target test programs of each target test device through the converter, it is possible to determine which target test device the test task is specifically assigned to execute through the task scheduler in combination with the central control node. Specifically: Transmitting the target test programs of each target test device to the task scheduler through the converter; determining, through the task scheduler and in combination with the central control node, the test devices to be executed that execute the test tasks corresponding to the chip test program from multiple target test devices, and transmitting the target test programs of the test devices to be executed to the test devices to be executed; executing, through the test devices to be executed, the received target test programs, and transmitting the corresponding execution results to the central control node.

[0071] In one embodiment, determining, through the task scheduler and in combination with the central control node, the test devices to be executed among each of the target test devices includes: obtaining, through the task scheduler, the loads and capabilities of each of the target test devices from the central control node, and determining the test devices to be executed based on the obtained content.

[0072] That is, through the task scheduler, obtaining the loads and capabilities of each target test device from the central control node, and intelligently allocating test tasks according to the loads and capabilities of each target test device, with the aim of achieving load balancing, to determine the test devices to be executed. Optionally, the task scheduler can also perform intelligent scheduling according to the priorities and dependencies of the test tasks to optimize the test process.

[0073] Optionally, in practical applications, it can also be that when verifying in S130 that each target test device is hardware-compatible with the chip test program, the information of each target test device that is compatible with the chip test program is transmitted from the compiler to the task scheduler; the task scheduler determines the test devices to be executed among the target test devices in combination with the central control node, and returns the information of the test tasks corresponding to the execution of the chip test program by the test devices to be executed to the compiler; the compiler transmits the general test program data to the converter; the converter converts the general test program data into a target test program adapted to the test device to be executed based on the hardware configuration part of the test device to be executed in the second configuration file, and transmits the target test program adapted to the test device to be executed to the test device to be executed for execution.

[0074] In one embodiment, the test system further includes a remote debugging tool. Correspondingly, the method further includes: remotely debugging the test program on any one of the multiple test devices through the remote debugging tool.

[0075] Among them, the remote debugging tool can be a tool for remotely debugging the test program. Through the remote debugging tool, it is allowed for a user to remotely connect to any one of the multiple test devices through the user interface, and to monitor and debug the execution of the test program in this test device in real time. Optionally, the test system can also include a collaborative development environment. Integrating the remote debugging tool and the collaborative development environment can support multiple users to remotely edit and maintain the test program of any one of the test devices simultaneously, while ensuring data consistency and integrity.

[0076] In one embodiment, the test system further includes a permission management system. Correspondingly, the method further includes: controlling the access and modification permissions of different users of the test system to the test programs existing in the test system through the permission management system.

[0077] Among them, the permission management system can be the part in the test system for performing permission management. Through the permission management system, it is allowed to control the access and modification permissions of different users of the test system to the test programs existing in the test system through the user interface, ensuring data security.

[0078] Embodiment Two

[0079] Figure 3 is a schematic structural diagram of a test system provided according to Embodiment Two of the present invention. This embodiment is applicable to the situation of processing a chip test program to make it adapted to multiple different test devices. As Figure 3As shown in the figure, the specific structure of the system at least includes: an editor 31, a compiler 32, a converter 33, and multiple test devices 34. Each of the multiple test devices 34 includes a hardware abstraction layer;

[0080] The editor 31 is used to edit and transmit a chip test program to the compiler 32;

[0081] The compiler 32 is used to parse the chip test program based on a first configuration file including the function information of each of the test devices 34 to obtain general test program data, and the general test program data indicates that multiple target test devices among the test devices 34 are functionally adapted to the chip test program;

[0082] The compiler 32 is used to, based on the hardware abstraction layer of each of the target test devices, transfer the general test program data to the converter 33 when verifying that each of the target test devices is hardware-adapted to the chip test program;

[0083] The converter 33 is used to convert the general test program data into a target test program adapted to each of the target test devices based on a second configuration file including the hardware information of each of the test devices 34.

[0084] In the test system according to the embodiment of the present invention, a chip test program is obtained by editing through an editor; the chip test program is parsed into general test program data by a compiler, and the general test program data indicates that multiple target test devices are functionally adapted to the chip test program; then, through the compiler, verification is performed based on the hardware abstraction layer of each target test device to ensure that each target test device is hardware-adapted to the chip test program; finally, the general test program data is converted into a target test program adapted to each target test device by a converter. This solution can abstract the chip test program into code that can be executed on different target test devices, reducing the tight coupling relationship between the chip test program and a specific test device, enabling the chip test program to be independent of specific hardware implementation, and thus improving the generality and portability of the chip test program.

[0085] Further, the test system further includes a version control system and an automatic test deployment tool. Correspondingly, the editor is specifically used to edit and obtain a chip test program, and submit the chip test program to a code repository in combination with the version control system;

[0086] The automatic test deployment tool is used to transfer the chip test program corresponding to the code change to the compiler when it is determined that there is a code change in the code repository.

[0087] Further, the general test program data further indicates:

[0088] Test configuration information, indicating the test conditions corresponding to the chip test program, the corresponding test hardware, and the hardware connection relationship of the test hardware in each of the target test devices;

[0089] Test method information, indicating the methods that each of the target test devices needs to execute through the test hardware when executing the chip test program;

[0090] Test sequence information, indicating the execution sequence of the methods that each of the target test devices needs to execute.

[0091] Furthermore, the test system further includes a task scheduler and a central control node. Correspondingly, the converter is further configured to, after converting the general test program data into a target test program adapted to each of the target test devices, transmit the target test programs of each of the target test devices to the task scheduler;

[0092] The task scheduler is configured to determine the to-be-executed test devices in each of the target test devices in combination with the central control node, and transmit the target test programs of the to-be-executed test devices to the to-be-executed test devices, and the to-be-executed test devices are configured to execute the test tasks corresponding to the chip test program;

[0093] The to-be-executed test device is configured to execute the received target test program and transmit the corresponding execution result to the central control node.

[0094] Furthermore, the task scheduler is specifically configured to:

[0095] Obtain the loads and capabilities of each of the target test devices from the central control node, and determine the to-be-executed test devices based on the obtained content.

[0096] Furthermore, the test system further includes a remote debugging tool. Correspondingly, the remote debugging tool is configured to remotely debug the test program on any one of the multiple test devices.

[0097] Furthermore, the test system further includes a permission management system. Correspondingly, the permission management system is configured to control the access and modification permissions of different users of the test system to the test programs existing in the test system.

[0098] The test system provided by the embodiments of the present invention can execute the chip test program processing method provided by the embodiments of the present invention, and has the corresponding modules and beneficial effects of the execution method.

[0099] Embodiment III

[0100] Figure 4It is a schematic structural diagram of a test system provided by Embodiment 3 of the present invention. Figure 4 It can be an exemplary illustration of the test system in the above embodiment. As Figure 4 shown, the test system includes the following parts:

[0101] Abstraction framework part:

[0102] The abstraction framework is reflected in the TDL editor, compiler, and hardware abstraction layer HAL. The descriptions of each part in the abstraction framework are as follows:

[0103] The TDL editor, which is the editor involved in the present invention, is used to write chip test programs; the TDL editor is developed based on World Wide Web (Web) technology and integrated in the user interface; TDL provides a rich set of libraries and instruction sets for describing test operations and control logic;

[0104] The compiler is used to combine a converter ( Figure 4 not shown in the figure) to convert the chip test program into code that can be executed on different hardware (i.e., the target test device);

[0105] The hardware abstraction layer HAL is used to ensure that the chip test program can interact with the specific hardware without caring about the specific details of the hardware; HAL defines a set of unified interfaces for accessing the hardware resources of different test devices.

[0106] Distributed management part:

[0107] The distributed management part is reflected in the test nodes, task scheduler, version control system, permission management system, and central control node. The specific descriptions of the distributed management part are as follows:

[0108] The test node can be a node that executes specific test tasks, i.e., a test device. The test node can be a physical test machine or a simulation environment. Each test node is installed with HAL and the necessary test execution environment; the test node can be containerized to ensure environmental consistency;

[0109] The task scheduler is used to intelligently allocate test tasks according to the load and capabilities of the test nodes to achieve load balancing; it can also perform intelligent scheduling according to the priorities and dependencies of the test tasks to optimize the test process;

[0110] The version control system is used to track the change history and version iterations of the test program and support multi-user collaborative development;

[0111] The permission management system is used to control the access and modification permissions of different users to the test program to ensure data security, and it can be implemented through a role-based access control model;

[0112] A central control node for coordinating the entire test process, including task allocation, result collection, and status monitoring;

[0113] The distributed management part aims to improve the efficiency of test program writing and debugging by decentralizing the management and execution of the test program to multiple nodes to achieve parallel processing and load balancing.

[0114] Remote debugging and collaborative development support part:

[0115] Through remote debugging tools, it allows test engineers to remotely connect to test nodes to monitor and debug the execution of test programs in real time;

[0116] Through a collaborative development environment, it supports multiple users to edit and maintain test programs simultaneously while ensuring data consistency and integrity.

[0117] Continuous integration and continuous deployment (CI / CD) support part:

[0118] Integrate CI / CD tools to automate the build, test, and deployment processes of test programs.

[0119] User interface and interaction design part:

[0120] Design an intuitive user interface to enable test engineers to easily write, manage, and monitor test programs; provide graphical programming tools and debugging tools to improve the work efficiency of test engineers and the quality of test programs.

[0121] Security and reliability guarantee part:

[0122] Implement strict security measures in the test system, including data encryption, access control, and audit logs, to protect the security of test data and programs; design a fault recovery mechanism and redundant system to ensure the high availability and reliability of test programs.

[0123] Scalability and flexibility part:

[0124] The test system design takes into account future technological developments, allowing new test machine support and function expansion to be easily added; provides plugins and application programming interfaces to allow third - party developers and users to expand system functions as needed.

[0125] For the test system of the embodiments of the present invention, before actual deployment, the system will conduct comprehensive tests in a simulation environment to verify the functions of each component and the stability of the entire workflow; the tests can include unit tests, integration tests, and performance tests to ensure the reliability and efficiency of the system under different loads and conditions; after deployment, the system will be continuously monitored and maintained to ensure long - term stable operation and perform iterative optimization based on user feedback.

[0126] The test system according to the embodiments of the present invention can have the following advantages:

[0127] 1. Improve the portability of test programs:

[0128] By abstracting test programs, this system significantly reduces the dependence of test programs on the hardware of specific test machines, enabling test programs to be easily migrated and adapted between test machines of different brands and models, thus improving the generality and portability of test programs.

[0129] 2. Reduce the cost of hardware replacement and upgrade:

[0130] Due to the decoupling of test programs from hardware, when replacing or upgrading hardware, there is no need to re-develop or significantly modify test programs, thus saving development costs and time and accelerating the speed of product listing.

[0131] 3. Improve the development and maintenance efficiency of test programs:

[0132] Adopting distributed management enables the development and maintenance of test programs to be carried out in parallel on multiple nodes, significantly improving development efficiency and shortening the development cycle.

[0133] 4. Enhance teamwork and project management:

[0134] Distributed management supports remote debugging and collaborative development, enabling engineers in different locations to share the status and progress of test programs in real time, improving the teamwork efficiency and the convenience of project management.

[0135] 5. Reduce the learning cost of test engineers:

[0136] The abstract framework enables test engineers to not need to deeply understand the hardware details of each test machine, reducing the learning cost and enabling engineers to adapt to new test tasks and environments faster.

[0137] 6. Improve the stability and reliability of test programs:

[0138] Through abstraction and distributed management, the structure of test programs is clearer, making them easier to maintain and update, thus improving the stability and reliability of test programs.

[0139] 7. Support continuous integration and continuous deployment (CI / CD):

[0140] The system supports the automated building and deployment of test programs, further accelerating the iteration speed of test programs.

[0141] 8. Strong environmental adaptability:

[0142] The system design takes into account the requirements of different test environments, can quickly adapt to new test requirements and technological changes, and maintain long-term technological competitiveness.

[0143] 9. Improve resource utilization rate:

[0144] Distributed management allows for more efficient allocation and utilization of test resources, reduces resource idleness and waste, and improves the utilization rate of resources.

[0145] 10. Enhance the scalability of the system:

[0146] The system design has good scalability and can be expanded and upgraded as technology develops and test requirements change, ensuring long-term technological adaptability.

[0147] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. There is no limitation herein.

[0148] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A chip test program processing method, characterized in that: Applied to a test system, the test system includes at least an editor, a compiler, a converter and a plurality of test devices, and the plurality of test devices each include a hardware abstraction layer, the method includes: Edit and transmit the chip test program to the compiler through the editor; Parsing the chip test program by the compiler based on a first configuration file including functional information of each of the test devices to obtain universal test program data, wherein the universal test program data indicates that a plurality of target test devices in each of the test devices are functionally adapted to the chip test program; By means of the compiler, based on the hardware abstraction layer of each of the target test devices, the universal test program data is transmitted to the converter after verifying that each of the target test devices is adapted to the chip test program in terms of hardware; The converter converts the general test program data into a target test program adapted to each of the target test devices based on a second configuration file including hardware information of each of the test devices.

2. The method according to claim 1, characterized in that The test system also includes a version control system and an automatic test deployment tool. Accordingly, the chip test program is edited and transmitted to the compiler through the editor, including: The chip test program is edited by the editor, and the chip test program is submitted to the code repository in combination with the version control system; By using the automatic test deployment tool, when it is determined that there is a code change in the code repository, the chip test program corresponding to the code change is transmitted to the compiler.

3. The method according to claim 1, characterized in that The generic test program data also indicates: Test configuration information, indicating the test conditions corresponding to the chip test program, the corresponding test hardware, and the hardware connection relationship of the test hardware in each of the target test devices; Test method information, indicating the method to be performed by the test hardware when each of the target test devices executes the chip test program; The test sequence information indicates the execution sequence of the method to be executed by each target test device.

4. The method according to claim 1, characterized in that The test system further includes a task scheduler and a central control node. Accordingly, after converting the general test program data into a target test program adapted to each of the target test devices, the method further includes: Transmitting the target test program of each target test device to the task scheduler through the converter; Determine the test device to be executed in each of the target test devices by combining the task scheduler with the central control node, and transmit the target test program of the test device to be executed to the test device to be executed, and the test device to be executed is used to execute the test task corresponding to the chip test program; The received target test program is executed through the to-be-executed test device, and the corresponding execution result is transmitted to the central control node.

5. The method according to claim 4, characterized in that Determining the test device to be executed in each of the target test devices by the task scheduler in combination with the central control node includes: The task scheduler obtains the load and capacity of each target test device from the central control node, and determines the test device to be executed based on the obtained content.

6. The method according to claim 1, characterized in that The test system also includes a remote debugging tool, and accordingly, the method also includes: The test program on any test device among the multiple test devices is remotely debugged through the remote debugging tool.

7. The method according to claim 1, characterized in that The test system also includes a rights management system, and accordingly, the method also includes: The authority management system is used to control the access and modification authority of different users of the test system to the test programs existing in the test system.

8. A testing system, characterized in that: The test system at least includes an editor, a compiler, a converter and a plurality of test devices, and the plurality of test devices each include a hardware abstraction layer; The editor is used to edit and transmit the chip test program to the compiler; The compiler is used to parse the chip test program based on a first configuration file including functional information of each of the test devices to obtain universal test program data, wherein the universal test program data indicates that multiple target test devices in each of the test devices are adapted to the chip test program in terms of functions; The compiler is used to transmit the general test program data to the converter based on the hardware abstraction layer of each target test device and verify that each target test device is adapted to the chip test program in terms of hardware; The converter is used to convert the general test program data into a target test program adapted for each of the target test devices based on a second configuration file including hardware information of each of the test devices.

9. The test system according to claim 8, characterized in that: The test system also includes a version control system and an automatic test deployment tool. Accordingly, the editor is specifically used to edit and obtain a chip test program, and submit the chip test program to a code repository in combination with the version control system; The automatic test deployment tool is used to transmit the chip test program corresponding to the code change to the compiler when it is determined that there is a code change in the code repository.

10. The test system according to claim 8, characterized in that: The generic test program data also indicates: Test configuration information, indicating the test conditions corresponding to the chip test program, the corresponding test hardware, and the hardware connection relationship of the test hardware in each of the target test devices; Test method information, indicating the method to be performed by the test hardware when each of the target test devices executes the chip test program; The test sequence information indicates the execution sequence of the method to be executed by each target test device.

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