Vector computing device

Abstract

The present disclosure provides a vector computing device, comprising: an instruction scheduling unit, an instruction decoding unit connected to the instruction scheduling unit, and multiple vector core execution modules connected to the instruction decoding unit, wherein the multiple vector core execution modules are connected in series and only one first vector core execution module is connected to the instruction decoding unit, wherein the instruction scheduling unit is configured to schedule single-instruction multi-threaded instructions and send the SIMT instructions to the instruction decoding unit, and the instruction decoding unit is configured to decode the SIMT instructions to determine the operand addresses of the SIMT instruction operands, and instruct the multiple vector core execution modules to perform vector operations of the SIMT instructions on the operands in multiple clock cycles respectively.

Description

Technical Field

[0001] The present disclosure generally relates to the field of processors, and more particularly, to a vector computing device. Background Art

[0002] Single Instruction Multiple Threads (SIMT) instructions are common programming instructions for graphics processing units (GPUs) and have been widely used for large-scale parallel computing tasks such as graphics rendering and artificial intelligence (AI) operations. SIMT instructions perform parallel operations using warps as the basic unit. A warp contains multiple threads. For example, a SIMT32 instruction represents an instruction for 32 threads. A single SIMT32 instruction enables all threads in a warp of 32 threads to execute the same operation in parallel. This allows GPUs or AI chips to process multiple data points or computing tasks simultaneously, thereby improving computing efficiency.

[0003] In GPUs, SIMT instructions are executed through vector cores to perform corresponding vector operations, including but not limited to floating-point operations, fixed-point operations, and logical operations. Vector cores, also called vector execution units, are often combined with pipeline architectures to support large-scale parallel computing tasks.

[0004] A vector core can include multiple compute units, each of which processes data for one thread in a warp. Currently, only a portion of a SIMT instruction, such as half the threads, is instantiated in a single vector core. This allows two vector cores to perform all the operational stages of a SIMT instruction in a ping-pong fashion, including instruction fetch, resource checking, instruction scheduling, decoding, operand fetching, operation execution, and result writeback.

[0005] However, in this ping-pong approach, scheduling multiple SIMT instructions requires considering the resource usage of previous instructions to avoid conflicts. Furthermore, complex gating logic is required to determine when registers are read or written by two vector cores. Furthermore, the different instructions being scheduled can lead to power imbalances and heat dissipation issues. Summary of the Invention

[0006] In response to at least one of the above problems, the solution disclosed in the present invention designs the structure of the vector computing device so that the instruction scheduling and instruction decoding of a single instruction can be targeted only at a single vector core, thereby reducing the logical complexity of instruction scheduling and instruction decoding, and can also significantly reduce the chip area.

[0007] According to one aspect of the present disclosure, a vector computing device is provided. The vector computing device includes: an instruction scheduling unit, an instruction decoding unit connected to the instruction scheduling unit, and multiple vector core execution modules, wherein the multiple vector core execution modules are connected in series and only one first vector core execution module is connected to the instruction decoding unit, wherein the instruction scheduling unit is configured to schedule a single instruction multiple thread (SIMT) instruction and send the SIMT instruction to the instruction decoding unit, and the instruction decoding unit is configured to decode the SIMT instruction to determine an operand address of an operand of the SIMT instruction and instruct the multiple vector core execution modules to respectively perform a vector operation of the SIMT instruction on the operand in multiple clock cycles.

[0008] In some embodiments, the instruction decoding unit is configured to enable the first vector core execution module to read the operand from the operand address in one clock cycle, and the first vector execution module is configured to enable the next vector execution module connected to the first vector execution module to read the operand from the operand address in a clock cycle next to the clock cycle.

[0009] In some embodiments, each vector core execution module includes: an operand acquisition unit, a register and a vector core computing unit, wherein the operand acquisition unit reads the operand from the register based on the operand address from the instruction decoding unit, and sends the read operand to the vector core computing unit, and the vector core computing unit uses the operand to perform the vector operation of the SIMT instruction and writes the operation result back to the register.

[0010] In some embodiments, the vector core computing unit of each vector core execution module in the plurality of vector core execution modules respectively starts the vector operations in the plurality of clock cycles in sequence based on the shared control information from the instruction decoding unit.

[0011] In some embodiments, each computing unit in the vector core computing unit is used to perform vector operations of one thread of the SIMT instruction.

[0012] In some embodiments, the multiple vector core execution modules include a first vector core execution module and a second vector core execution module, and the first vector core execution module includes a first operand acquisition unit, a first register and a first vector core calculation unit, the first operand acquisition unit reads the operands of the upper thread group of the SIMT instruction from the first register based on the operand address from the instruction decoding unit, and sends the read operands to the first vector core calculation unit, and the first vector core calculation unit uses the operands of the upper thread group to perform vector operations of the upper thread group of the SIMT instruction and writes the operation results back to the first register; the second vector core execution module includes a second operand acquisition unit, a second register and a second vector core calculation unit, the second operand acquisition unit reads the operands of the lower thread group of the SIMT instruction from the second register based on the operand address from the first operand acquisition unit, and sends the read operands to the second vector core calculation unit, and the second vector core calculation unit uses the operands of the lower thread group to perform vector operations of the lower thread group of the SIMT instruction and writes the operation results back to the second register.

[0013] In some embodiments, the vector computing device is configured as follows: in a first clock cycle, the instruction scheduling unit sends the SIMT instruction to the instruction decoding unit; in a second clock cycle, which is a clock cycle next to the first clock cycle, the instruction decoding unit decodes the SIMT instruction to obtain an operand address of an operand of the SIMT instruction; in a third clock cycle, which is a clock cycle next to the second clock cycle, the first operand acquisition unit reads an operand of the upper thread group of the SIMT instruction from the first register;

[0014] In the next clock cycle of the third clock cycle, the fourth clock cycle, the first vector core computing unit performs vector operations on the operands of the upper thread group of the SIMT instruction, and at the same time, the second operand acquisition unit reads the operands of the lower thread group of the SIMT instruction from the second register under the read enable control of the first operand acquisition unit; in the next clock cycle of the fourth clock cycle, the fifth clock cycle, the first vector core computing unit writes the result of the vector operation performed on the operands of the upper thread group of the SIMT instruction back to the first register, and at the same time, the second vector core computing unit performs vector operations on the operands of the lower thread group of the SIMT instruction; in the next clock cycle of the fifth clock cycle, the sixth clock cycle, the second vector core computing unit writes the result of the vector operation performed on the operands of the lower thread group of the SIMT instruction back to the second register.

[0015] In some embodiments, the multiple vector core execution modules include a first vector core execution module, a second vector core execution module, a third vector core execution module, and a fourth vector core execution module, and the first vector core execution module includes a first operand acquisition unit, a first register, and a first vector core calculation unit, the first operand acquisition unit reads the operands of the 1 / 4 thread group of the SIMT instruction from the first register based on the operand address from the instruction decoding unit, and sends the read operands to the first vector core calculation unit, and the first vector core calculation unit uses the operands of the 1 / 4 thread group to perform vector operations of the 1 / 4 thread group of the SIMT instruction and writes the operation results back to the first register; the second vector core execution module includes a second operand acquisition unit, a second register, and a second vector core calculation unit, the second operand acquisition unit reads the operands of the 2 / 4 thread group of the SIMT instruction from the second register based on the operand address from the first operand acquisition unit, and sends the read operands to the second vector core calculation unit, and the second vector core calculation unit uses the operands of the 2 / 4 thread group to execute the SIMT instruction. the vector operation of the 2 / 4 thread group of the SIMT instruction is performed by the processor, and the operation result is written back to the second register; the third vector core execution module includes a third operand acquisition unit, a third register and a third vector core calculation unit, the third operand acquisition unit reads the operands of the 3 / 4 thread group of the SIMT instruction from the third register based on the operand address from the second operand acquisition unit, and sends the read operands to the third vector core calculation unit, and the third vector core calculation unit performs the vector operation of the 3 / 4 thread group of the SIMT instruction using the operands of the 3 / 4 thread group, and writes the operation result back to the third register; and the fourth vector core execution module includes a fourth operand acquisition unit, a fourth register and a fourth vector core calculation unit, the fourth operand acquisition unit reads the operands of the 4 / 4 thread group of the SIMT instruction from the fourth register based on the operand address from the third operand acquisition unit, and sends the read operands to the fourth vector core calculation unit, and the fourth vector core calculation unit performs the vector operation of the 4 / 4 thread group of the SIMT instruction using the operands of the 4 / 4 thread group, and writes the operation result back to the fourth register.

[0016] In some embodiments, the vector computing device is configured as follows: in a first clock cycle, the instruction scheduling unit sends the SIMT instruction to the instruction decoding unit; in a second clock cycle, the next clock cycle of the first clock cycle, the instruction decoding unit decodes the SIMT instruction to obtain the operand address of the operand of the SIMT instruction; in a third clock cycle, the next clock cycle of the second clock cycle, the first operand acquisition unit reads the operand of 1 / 4 thread group of the SIMT instruction from the first register; in a fourth clock cycle, the next clock cycle of the third clock cycle, the first vector core computing unit performs a vector operation on the operand of 1 / 4 thread group of the SIMT instruction, and at the same time, the second operand acquisition unit reads the operand of 2 / 4 thread group of the SIMT instruction from the second register under the read enable control of the first operand acquisition unit; in a fifth clock cycle, the next clock cycle of the fourth clock cycle, the first vector core computing unit writes the result of the vector operation performed on the operand of 1 / 4 thread group of the SIMT instruction back to the first register, and at the same time, the second vector core computing unit performs a vector operation on the operand of 2 / 4 thread group of the SIMT instruction, and at the same time, The third operand acquisition unit reads the operands of the 3 / 4 thread groups of the SIMT instruction from the third register under the read enable control of the second operand acquisition unit; in the sixth clock cycle, the next clock cycle after the fifth clock cycle, the second vector core computing unit writes the result of the vector operation performed on the operands of the 2 / 4 thread groups of the SIMT instruction back to the second register, and at the same time, the third vector core computing unit performs the vector operation on the operands of the 3 / 4 thread groups of the SIMT instruction, and at the same time, the fourth operand acquisition unit reads the operands of the 3 / 4 thread groups of the SIMT instruction from the fourth register under the read enable control of the third operand acquisition unit. The first register reads the operands of the 4 / 4 thread groups of the SIMT instruction from the third register; in the seventh clock cycle, the next clock cycle after the sixth clock cycle, the third vector core computing unit writes back the result of the vector operation performed on the operands of the 3 / 4 thread groups of the SIMT instruction to the third register, and at the same time, the fourth vector core computing unit performs the vector operation on the operands of the 4 / 4 thread groups of the SIMT instruction; in the eighth clock cycle, the next clock cycle after the seventh clock cycle, the fourth vector core computing unit writes back the result of the vector operation performed on the operands of the 4 / 4 thread groups of the SIMT instruction to the fourth register. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present disclosure will be better understood and other objects, details, features and advantages of the present disclosure will become more apparent through the following description of specific embodiments of the present disclosure given with reference to the accompanying drawings.

[0018] Figure 1 A schematic structural diagram of a vector computing device is shown.

[0019] Figure 2 Shown Figure 1 An exemplary operational timing diagram of a vector computing device is shown.

[0020] Figure 3 A schematic structural diagram of a vector computing device according to an embodiment of the present invention is shown.

[0021] Figure 4 Shown Figure 3 A schematic diagram of a further detailed structure of a vector core execution module of a vector computing device is shown.

[0022] Figure 5 A schematic diagram of an exemplary vector computing device according to an embodiment of the present invention is shown.

[0023] Figure 6 Shown Figure 5 An exemplary operational timing diagram of a vector computing device is shown.

[0024] Figure 7 A schematic diagram of an exemplary vector computing device according to some other embodiments of the present invention is shown.

[0025] Figure 8 Shown Figure 7 An exemplary operational timing diagram of a vector computing device is shown. DETAILED DESCRIPTION

[0026] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0027] As used herein, the term "including" and its variations represent open inclusion, i.e., "including but not limited to." Unless otherwise stated, the term "or" means "and / or." The term "based on" means "based at least in part on." The terms "one embodiment" and "some embodiments" mean "at least one example embodiment." The term "another embodiment" means "at least one additional embodiment." The terms "first," "second," etc. may refer to different or identical objects.

[0028] Figure 1 A schematic structural diagram of a vector computing device 100 is shown. Figure 2 Shown Figure 1An exemplary operation timing diagram of the vector computing device 100 is shown.

[0029] like Figure 1 As shown in FIG, the vector computing device 100 may include an instruction scheduling unit 110, which may be coupled with a plurality of vector core execution modules 120 ( Figure 1 , two vector core execution modules 120-1 and 120-2 are shown as connected, for dispatching instructions to multiple vector core execution modules 120. Here, it is assumed that the vector computing device 100 utilizes two vector core execution modules 120 to complete a SIMT instruction in a ping-pong manner. That is, each vector core execution module 120 instantiates N / 2 threads at a time (where N is the thread warp required for the SIMT instruction; for example, for a SIMT32 instruction, N=32).

[0030] Figure 1 In the figure, the two vector core execution modules 120 are represented as a first vector core execution module 120-1 and a second vector core execution module 120-2, respectively. It is assumed that the first vector core execution module 120-1 instantiates the upper thread group and the lower thread group of one SIMT instruction in a pipeline manner, and the second vector core execution module 120-2 instantiates the upper thread group and the lower thread group of another SIMT instruction in a pipeline manner.

[0031] like Figure 1 As shown in , the first vector core execution module 120-1 may include an instruction decoding unit 122-1, an upper-half thread group operand fetch unit 124-1, a lower-half thread group operand fetch unit 126-1, and a first vector core computing unit 128-1, wherein the first vector core computing unit 128-1 may include multiple computing units, each of which is used to execute operations on one thread. The second vector core execution module 120-2 may include an instruction decoding unit 122-2, an upper-half thread group operand fetch unit 124-2, a lower-half thread group operand fetch unit 126-2, and a second vector core computing unit 128-2, wherein the second vector core computing unit 128-2 may include multiple computing units, each of which is used to execute operations on one thread.

[0032] In addition, the vector computing device 100 further includes an upper-half thread group register 130 - 1 and a lower-half thread group register 130 - 2 to respectively store upper-half thread group data and lower-half thread group data.

[0033] exist Figure 1When executing SIMT instructions for N threads in the illustrated vector computing device 100, typically only N / 2 threads are instantiated at a time within a single vector core execution module 120. Specifically, the first vector core compute unit 128-1 and the second vector core compute unit 128-2 each include N / 2 compute units, each of which is configured to execute a single thread. For example, for one SIMT32 instruction, the first vector core compute unit 128-1, which includes 16 compute units, can instantiate the first 16 threads (herein referred to as the top thread group) and the last 16 threads (herein referred to as the bottom thread group) in different clock cycles. For another SIMT instruction, the second vector core compute unit 128-2, which includes 16 compute units, can instantiate the first 16 threads (herein referred to as the top thread group) and the last 16 threads (herein referred to as the bottom thread group) in different clock cycles. Accordingly, the top thread group register 130-1 and the bottom thread group register 130-2 can store the top thread group data and the bottom thread group data, respectively, for the two SIMT32 instructions.

[0034] The complete pipeline process of an instruction includes instruction issuance, instruction decoding, operand reading, operation execution, and result writing back, which are executed in several consecutive clock cycles. Assume that the first vector core execution module 120-1 and the second vector core execution module 120-2 execute multiple SIMT32 instructions (such as instruction 1, instruction 2, instruction 3, and instruction 4) in a ping-pong manner. Figure 2 As shown in , the execution process of these instructions can be described as:

[0035] For instruction 1:

[0036] In the first clock cycle T1, the instruction scheduling unit 110 sends instruction 1 to the instruction decoding unit 122-1 of the first vector core execution module 120-1;

[0037] In the second clock cycle T2, the instruction decoding unit 122-1 decodes instruction 1 to obtain the operand address of the operand of instruction 1;

[0038] In the third clock cycle T3, the upper-half thread group operand fetching unit 124-1 reads the operand of the upper-half thread group of instruction 1 from the upper-half thread group register 130-1;

[0039] In the fourth clock cycle T4, the first vector core computing unit 128-1 performs a vector operation on the operands of the upper-half thread group of instruction 1. At the same time, the lower-half thread group operand fetching unit 126-1 reads the operands of the lower-half thread group of instruction 1 from the lower-half thread group register 130-2.

[0040] In the fifth clock cycle T5, the first vector core computing unit 128-1 writes the result of the vector operation performed on the operands of the upper thread group of instruction 1 back to the upper thread group register 130-1. At the same time, the first vector core computing unit 128-1 performs the vector operation on the operands of the lower thread group of instruction 1.

[0041] In the sixth clock cycle T6 , the first vector core computing unit 128 - 1 writes the result of the vector operation performed on the operands of the lower-half thread group of instruction 1 back to the lower-half thread group register 130 - 2 .

[0042] For instruction 2:

[0043] In the second clock cycle T2, the instruction scheduling unit 110 sends instruction 2 to the instruction decoding unit 122-2 of the second vector core execution module 120-2;

[0044] In the third clock cycle T3, the instruction decoding unit 122-2 decodes instruction 2 to obtain the operand address of the operand of instruction 2;

[0045] In the fourth clock cycle T4, the upper-half thread group operand fetching unit 124-2 reads the operand of the upper-half thread group of instruction 2 from the upper-half thread group register 130-1;

[0046] In the fifth clock cycle T5, the second vector core computing unit 128-2 performs a vector operation on the operands of the upper-half thread group of instruction 2. At the same time, the lower-half thread group operand fetching unit 126-2 reads the operands of the lower-half thread group of instruction 2 from the lower-half thread group register 130-2.

[0047] In the sixth clock cycle T6, the second vector core computing unit 128-2 writes the result of the vector operation performed on the operands of the upper thread group of instruction 2 back to the upper thread group register 130-1. At the same time, the second vector core computing unit 128-2 performs the vector operation on the operands of the lower thread group of instruction 2.

[0048] In the seventh clock cycle T7 , the second vector core computing unit 128 - 2 writes the result of the vector operation performed on the operands of the lower-half thread group of instruction 2 back to the lower-half thread group register 130 - 2 .

[0049] For instruction 3:

[0050] In the third clock cycle T3, the instruction scheduling unit 110 sends instruction 3 to the instruction decoding unit 122-1 of the first vector core execution module 120-1;

[0051] In the fourth clock cycle T4, the instruction decoding unit 122-1 decodes instruction 3 to obtain the operand address of the operand of instruction 3;

[0052] In the fifth clock cycle T5, the upper-half thread group operand fetching unit 124-1 reads the operand of the upper-half thread group of instruction 3 from the upper-half thread group register 130-1;

[0053] At the sixth clock cycle T6, the first vector core computing unit 128-1 performs a vector operation on the operands of the upper-half thread group of instruction 3. Simultaneously, the lower-half thread group operand fetching unit 126-1 reads the operands of the lower-half thread group of instruction 3 from the lower-half thread group register 130-2.

[0054] In the seventh clock cycle T7, the first vector core computing unit 128-1 writes the result of the vector operation performed on the operands of the upper-half thread group of instruction 3 back to the upper-half thread group register 130-1. At the same time, the first vector core computing unit 128-1 performs the vector operation on the operands of the lower-half thread group of instruction 3.

[0055] In the eighth clock cycle T8 , the first vector core computing unit 128 - 1 writes the result of the vector operation performed on the operands of the lower-half thread group of instruction 3 back to the lower-half thread group register 130 - 2 .

[0056] For instruction 4:

[0057] In the fourth clock cycle T4, the instruction scheduling unit 110 sends instruction 4 to the instruction decoding unit 122-2 of the second vector core execution module 120-2;

[0058] In the fifth clock cycle T5, the instruction decoding unit 122-2 decodes instruction 4 to obtain the operand address of the operand of instruction 4;

[0059] In the sixth clock cycle T6, the upper-half thread group operand fetching unit 124-2 reads the operand of the upper-half thread group of instruction 4 from the upper-half thread group register 130-1;

[0060] At the seventh clock cycle T7, the second vector core computing unit 128-2 performs a vector operation on the operands of the upper-half thread group of instruction 4. Simultaneously, the lower-half thread group operand fetching unit 126-2 reads the operands of the lower-half thread group of instruction 4 from the lower-half thread group register 130-2.

[0061] In the eighth clock cycle T8, the second vector core computing unit 128-2 writes the result of the vector operation performed on the operands of the upper-half thread group of instruction 4 back to the upper-half thread group register 130-1. At the same time, the second vector core computing unit 128-2 performs the vector operation on the operands of the lower-half thread group of instruction 4.

[0062] In the ninth clock cycle T9, the second vector core computing unit 128-2 writes the result of the vector operation performed on the operands of the lower-half thread group of instruction 4 back to the lower-half thread group register 130-2.

[0063] As can be seen, the vector computing device 100 implements a ping-pong execution of multiple instructions by sequentially executing the various operations of the SIMT instruction pipeline process in different clock cycles. This approach can save resource area, reduce the risk of register access conflicts, and improve the overall computing power of the device.

[0064] However, in the above manner, the instruction scheduling unit 110 needs to consider the resource usage status of each vector core execution module 120 in advance when performing instruction scheduling, and avoid register conflicts. For example, the upper-half thread group operand fetch unit 124-1 and the lower-half thread group operand fetch unit 126-1 of the first vector core execution module 120-1 need to execute the upper-half thread group and lower-half thread group operand fetches of instruction 1 in clock cycles T3 and T4, respectively, and the first vector core calculation unit 128-1 needs to write the results back to the upper-half thread group register 130-1 and the lower-half thread group register 130-2, respectively, in clock cycles T5 and T6; the upper-half thread group operand fetch unit 124-2 and the lower-half thread group operand fetch unit 126-2 of the second vector core execution module 120-2 need to execute the upper-half thread group and lower-half thread group operand fetches of instruction 2 in clock cycles T4 and T5, respectively, and the second vector core calculation unit 128-2 needs to write the results back to the upper-half thread group register 130-1 and the lower-half thread group register 130-2, respectively, in clock cycles T6 and T7. In this case, the upper thread group registers 130-1 and the lower thread group registers 130-2 are accessed by the two vector core execution modules 120-1 and 120-2 for both read and write operations. Therefore, a gate is required to distinguish which vector core execution module the operation originates from. Furthermore, when the instruction dispatch unit 110 assigns instructions to the two vector core execution modules 120-1 and 120-2, a gate is also required to distinguish which vector core execution module the instruction dispatch should be dispatched to. The two vector core compute units also require data gates to distinguish whether the operands are from the upper thread group registers or the read return data from the lower thread group registers. Furthermore, the upper thread group registers and the lower thread group registers each require gates to distinguish which vector core compute unit the enable signal and write data originate from. These gates must occupy chip area, thereby increasing chip area.

[0065] In addition, the instruction scheduling unit schedules instructions to the two vector core execution modules in a pipeline form. Due to the different power consumption between different instructions, it is difficult for the instruction scheduling unit to ensure the balance of instructions scheduled to the two vector core execution modules. Therefore, some vector core execution modules may execute instructions with high power consumption, such as executing floating-point multiplication and addition instructions, while some vector core execution modules may execute instructions with low power consumption, such as executing logical operations. This may cause different power consumption densities between different vector core execution modules, thereby causing local heating of the hardware and increasing the difficulty of heat dissipation.

[0066] In response to at least one of the above problems, the present disclosure designs the structure of a vector computing device so that instructions are sent only to a unified instruction decoding unit through an instruction scheduling unit, and the instruction decoding unit only sends the operand addresses of the decoded operands to a single vector core execution module, thereby eliminating the need for the instruction scheduling unit to perform register conflict checks in advance.

[0067] Figure 3 A schematic structural diagram of a vector computing device 200 according to an embodiment of the present invention is shown.

[0068] like Figure 3 As shown in FIG, the vector computing device 200 may include an instruction scheduling unit 210, an instruction decoding unit 220 connected to the instruction scheduling unit 210, and a plurality of vector core execution modules 230 ( Figure 3 4 vector core execution modules 230 - 1 , 230 - 2 , 230 - 3 and 230 - 4 are exemplarily shown in FIG. 4 . The multiple vector core execution modules 230 are connected in series and only one vector core execution module 230 (eg, the first vector core execution module 230 - 1 ) is connected to the instruction decoding unit 220 .

[0069] The instruction scheduling unit 210 is configured to schedule SIMT instructions and send the SIMT instructions to the instruction decoding unit 220 .

[0070] The instruction decoding unit 220 is configured to decode the SIMT instruction to determine operand addresses of operands of the SIMT instruction, and instruct the multiple vector core execution modules 230 to perform vector operations of the SIMT instruction on the operands in multiple clock cycles respectively.

[0071] It can be seen that, unlike the instruction scheduling unit 110 of the vector computing device 100, the instruction scheduling unit 210 of the vector computing device 200 schedules and sends one SIMT instruction to a single instruction decoding unit 220 each time, without having to decide which instruction decoding unit among the multiple instruction decoding units to send the instruction to.

[0072] The instruction decoding unit 220 is configured to enable the vector core execution module 230 (such as the first vector core execution module 230-1) connected thereto to read the operand from the operand address obtained through decoding in one clock cycle, and the vector core execution module 230 (such as the first vector core execution module 230-1) is configured to enable the next vector execution module 230 (such as the second vector core execution module 230-2) connected thereto to read the operand from the operand address in the next clock cycle after the clock cycle.

[0073] Furthermore, based on the relationship between the thread count requirement of the SIMT instruction and the number of computing units of each vector core execution module 230 (described below), in some cases (for example, a SIMT instruction requires more than two vector core execution modules 230 to execute collaboratively), the next vector execution module 230 (such as the second vector core execution module 230-2) is further configured to enable the vector execution module 230 connected to it (such as the third vector execution module 230-3) to read the operand from the operand address in the next clock cycle, and so on.

[0074] That is to say, among the multiple vector core execution modules 230, only the vector core execution module 230 connected to the instruction decoding unit 220 is enabled by the instruction decoding unit 220 to obtain operands, while the other vector core execution modules 230 are enabled in turn by the vector core execution modules 230 connected thereto to obtain operands.

[0075] Figure 4 Shown Figure 3 FIG. 2 is a schematic diagram of a further detailed structure of the vector core execution module 230 of the vector computing device 200 .

[0076] like Figure 4 As shown in , the vector core execution module 230 may include an operand acquisition unit 232, a register 234, and a vector core calculation unit 236. The operand acquisition unit 232 may read the operand from the register 234 based on the operand address from the instruction decoding unit 220, and send the read operand to the vector core calculation unit 236. Here, in the case where the vector core execution module 230 is directly connected to the instruction decoding unit 220, the vector core execution module 230 may directly obtain the operand address from the instruction decoding unit 220. In the case where the vector core execution module 230 is not directly connected to the instruction decoding unit 220 (i.e., in the case where the vector core execution module 230 is connected to another vector core execution module 230), the operand address is passed by the other vector core execution module 230 through a read enable.

[0077] The vector core computing unit 236 may use the operand to perform the vector operation of the SIMT instruction scheduled by the instruction scheduling unit 210 and write the operation result back to the register 234 .

[0078] The vector core computing unit 236 may include multiple computing units, where each computing unit is used to execute vector operations of one thread of SIMT instructions.

[0079] Figure 5 FIG. 2 is a schematic diagram of an exemplary vector computing device 200 according to an embodiment of the present invention. Figure 6 Shown Figure 5 An exemplary operation timing diagram of the vector computing device 200 is shown. Figure 5 In the example shown, two vector core execution modules 230 (ie, a first vector core execution module 230-1 and a second vector core execution module 230-2) are used to execute a SIMT instruction. Figure 1 Similarly, it is still assumed that for a SIMT instruction with N threads, only N / 2 threads are instantiated at a time in a single vector core execution module 230. For example, for a SIMT32 instruction, a first vector core compute unit 236-1 including 16 compute units may instantiate the first 16 threads (herein referred to as the upper half of the thread group) in a first clock cycle, and a second vector core compute unit 236-2 including 16 compute units may instantiate the last 16 threads (herein referred to as the lower half of the thread group) in a clock cycle following the first clock cycle.

[0080] like Figure 5 As shown in FIG, the first vector core execution module 230-1 includes a first operand fetch unit 232-1, a first register 234-1, and a first vector core calculation unit 236-1. The first operand fetch unit 232-1 reads the operands of the upper thread group of the SIMT instruction from the first register 234-1 based on the operand address from the instruction decoding unit 220, and sends the read operands to the first vector core calculation unit 236-1. The first vector core calculation unit 236-1 uses the operands of the upper thread group to perform vector operations on the upper thread group of the SIMT instruction and writes the operation results back to the first register 234-1.

[0081] The second vector core execution module 230-2 includes a second operand fetch unit 232-2, a second register 234-2, and a second vector core computation unit 236-2. The second operand fetch unit 232-2 reads the operands for the lower thread group of the SIMT instruction from the second register 234-2 based on the operand address from the first operand fetch unit 232-1, and sends the read operands to the second vector core computation unit 236-2. The second vector core computation unit 236-2 performs vector operations for the lower thread group of the SIMT instruction using the operands for the lower thread group, and writes the results back to the second register 234-2.

[0082] In addition, the vector core calculation unit 236 of each vector core execution module 230 also starts vector operations in sequence in multiple clock cycles based on the shared control information from the instruction decoding unit 220. Figure 5 In the example of , the first vector core computing unit 236-1 and the second vector core computing unit 236-2 can respectively execute the operations in two consecutive clock cycles (eg, Figure 6 Clock cycles T4 and T5 shown in FIG5 start vector operations for the upper and lower thread groups.

[0083] like Figure 6 As shown in Figure 2 Taking the execution of multiple SIMT32 instructions (such as instruction 1, instruction 2, instruction 3, and instruction 4) as an example, the execution process of these instructions can be described as follows:

[0084] For instruction 1:

[0085] In the first clock cycle T1, the instruction dispatch unit 210 sends instruction 1 to the instruction decode unit 220;

[0086] In the second clock cycle T2, the instruction decoding unit 220 decodes instruction 1 to obtain the operand address of the operand of instruction 1;

[0087] In the third clock cycle T3, the first operand fetching unit 232-1 reads the operand of the upper half thread group of instruction 1 from the first register 234-1;

[0088] In the fourth clock cycle T4, the first vector core computing unit 236-1 performs a vector operation on the operands of the upper thread group of instruction 1. Simultaneously, the second operand fetching unit 232-2 reads the operands of the lower thread group of instruction 1 from the second register 234-2 under the read enable control of the first operand fetching unit 232-1.

[0089] In the fifth clock cycle T5, the first vector core computing unit 236-1 writes the result of the vector operation performed on the operands of the upper thread group of instruction 1 back to the first register 234-1. At the same time, the second vector core computing unit 236-2 performs the vector operation on the operands of the lower thread group of instruction 1.

[0090] In the sixth clock cycle T6 , the second vector core computing unit 236 - 2 writes the result of the vector operation performed on the operands of the lower half thread group of instruction 1 back to the second register 234 - 2 .

[0091] For instruction 2:

[0092] In the second clock cycle T2, the instruction dispatch unit 210 sends instruction 2 to the instruction decode unit 220;

[0093] In the third clock cycle T3, the instruction decoding unit 220 decodes instruction 2 to obtain the operand address of the operand of instruction 2;

[0094] In the fourth clock cycle T4, the first operand fetching unit 232-1 reads the operand of the upper half thread group of instruction 2 from the first register 234-1;

[0095] In the fifth clock cycle T5, the first vector core computing unit 236-1 performs a vector operation on the operands of the upper thread group of instruction 2. At the same time, the second operand fetching unit 232-2 reads the operands of the lower thread group of instruction 2 from the second register 234-2 under the read enable control of the first operand fetching unit 232-1.

[0096] In the sixth clock cycle T6, the first vector core computing unit 236-1 writes the result of the vector operation performed on the operands of the upper thread group of instruction 2 back to the first register 234-1. At the same time, the second vector core computing unit 236-2 performs the vector operation on the operands of the lower thread group of instruction 2.

[0097] In the seventh clock cycle T7 , the second vector core computing unit 236 - 2 writes the result of the vector operation performed on the operands of the lower half thread group of instruction 2 back to the second register 234 - 2 .

[0098] For instruction 3:

[0099] In the third clock cycle T3, the instruction dispatch unit 210 sends instruction 3 to the instruction decoding unit 220;

[0100] In the fourth clock cycle T4, the instruction decoding unit 220 decodes instruction 3 to obtain the operand address of the operand of instruction 3;

[0101] In the fifth clock cycle T5, the first operand fetch unit 232-1 reads the operand of the upper thread group of instruction 3 from the first register 234-1;

[0102] In the sixth clock cycle T6, the first vector core computing unit 236-1 performs a vector operation on the operands of the upper thread group of instruction 3. At the same time, the second operand fetching unit 232-2 reads the operands of the lower thread group of instruction 3 from the second register 234-2 under the read enable control of the first operand fetching unit 232-1.

[0103] In the seventh clock cycle T7, the first vector core computing unit 236-1 writes the result of the vector operation performed on the operands of the upper thread group of instruction 3 back to the first register 234-1. At the same time, the second vector core computing unit 236-2 performs the vector operation on the operands of the lower thread group of instruction 3.

[0104] In the eighth clock cycle T8 , the second vector core computing unit 236 - 2 writes the result of the vector operation performed on the operands of the lower half thread group of instruction 3 back to the second register 234 - 2 .

[0105] For instruction 4:

[0106] In the fourth clock cycle T4, the instruction dispatch unit 210 sends instruction 4 to the instruction decoding unit 220;

[0107] In the fifth clock cycle T5, the instruction decoding unit 220 decodes instruction 4 to obtain the operand address of the operand of instruction 4;

[0108] In the sixth clock cycle T6, the first operand fetch unit 232-1 reads the operand of the upper thread group of instruction 4 from the first register 234-1;

[0109] In the seventh clock cycle T7, the first vector core computing unit 236-1 performs a vector operation on the operands of the upper thread group of instruction 4. At the same time, the second operand fetching unit 232-2 reads the operands of the lower thread group of instruction 4 from the second register 234-2 under the read enable control of the first operand fetching unit 232-1.

[0110] In the eighth clock cycle T8, the first vector core computing unit 236-1 writes the result of the vector operation performed on the operands of the upper thread group of instruction 4 back to the first register 234-1. At the same time, the second vector core computing unit 236-2 performs the vector operation on the operands of the lower thread group of instruction 4.

[0111] In the ninth clock cycle T9, the second vector core computing unit 236-2 writes the result of the vector operation performed on the operands of the lower half thread group of instruction 4 back to the second register 234-2.

[0112] Here, the timing of the vector operations of the first vector core computing unit 236 - 1 and the second vector core computing unit 236 - 2 is controlled by the shared control information of the instruction decoding unit 220 .

[0113] It can be seen that in the pipeline operation of this SIMT instruction, the instruction scheduling unit 210 only needs to send instructions to the only instruction decoding unit 220, and the instruction decoding unit 220 only needs to send operand addresses to the vector core execution module 230 connected to it, and the above operations can be repeated cycle by cycle to send and decode different instructions.

[0114] Figure 7 FIG. 2 is a schematic diagram showing an exemplary vector computing device 200 according to some other embodiments of the present invention. Figure 8 Shown Figure 7 An exemplary operation timing diagram of the vector computing device 200 is shown. Figure 7 In the example shown, four vector core execution modules 230 (ie, a first vector core execution module 230-1, a second vector core execution module 230-2, a third vector core execution module 230-3, and a fourth vector core execution module 230-4) execute one SIMT instruction. Figure 1 and Figure 5 Unlike the above, it is assumed that for a SIMT instruction with N threads, only N / 4 threads are instantiated at a time in a single vector core execution module 230. For example, for a SIMT32 instruction, a first vector core compute unit 236-1, which includes 8 compute units, may instantiate the first N / 4 threads (herein referred to as a 1 / 4 thread group) in a first clock cycle. A second vector core compute unit 236-2, which includes 8 compute units, may instantiate the second N / 4 threads (herein referred to as a 2 / 4 thread group) in a clock cycle following the first clock cycle (a second clock cycle). A third vector core compute unit 236-3, which includes 8 compute units, may instantiate the third N / 4 threads (herein referred to as a 3 / 4 thread group) in a next clock cycle (a third clock cycle). A fourth vector core compute unit 236-4, which includes 8 compute units, may instantiate the fourth N / 4 threads (herein referred to as a 4 / 4 thread group) in a next clock cycle (a fourth clock cycle).

[0115] like Figure 7As shown in FIG, the first vector core execution module 230-1 includes a first operand fetch unit 232-1, a first register 234-1, and a first vector core calculation unit 236-1. The first operand fetch unit 232-1 reads the operands of the 1 / 4 thread group of the SIMT instruction from the first register 234-1 based on the operand address from the instruction decoding unit 220, and sends the read operands to the first vector core calculation unit 236-1. The first vector core calculation unit 236-1 performs the vector operation of the 1 / 4 thread group of the SIMT instruction using the operands of the 1 / 4 thread group, and writes the operation results back to the first register 234-1.

[0116] The second vector core execution module 230-2 includes a second operand fetch unit 232-2, a second register 234-2, and a second vector core computation unit 236-2. The second operand fetch unit 232-2 reads the operands for the 2 / 4 thread group of the SIMT instruction from the second register 234-2 based on the operand address from the first operand fetch unit 232-1, and sends the read operands to the second vector core computation unit 236-2. The second vector core computation unit 236-2 performs the vector operation for the 2 / 4 thread group of the SIMT instruction using the operands for the 2 / 4 thread group, and writes the operation results back to the second register 234-2.

[0117] The third vector core execution module 230-3 includes a third operand fetch unit 232-3, a third register 234-3, and a third vector core computation unit 236-3. Based on the operand address from the second operand fetch unit 232-2, the third operand fetch unit 232-3 reads the operands for the ¾ thread group of the SIMT instruction from the third register 234-3 and sends the read operands to the third vector core computation unit 236-3. The third vector core computation unit 236-3 performs vector operations for the ¾ thread group of the SIMT instruction using the operands for the ¾ thread group and writes the results back to the second register 234-2.

[0118] The fourth vector core execution module 230-4 includes a fourth operand fetch unit 232-4, a fourth register 234-4, and a fourth vector core computation unit 236-4. Based on the operand address from the third operand fetch unit 232-3, the fourth operand fetch unit 232-4 reads the operands for the 4 / 4 thread group of the SIMT instruction from the fourth register 234-4 and sends the read operands to the fourth vector core computation unit 236-4. The fourth vector core computation unit 236-4 performs the vector operation for the 4 / 4 thread group of the SIMT instruction using the operands for the 4 / 4 thread group and writes the operation results back to the fourth register 234-4.

[0119] In addition, the vector core calculation unit 236 of each vector core execution module 230 also starts vector operations in sequence in multiple clock cycles based on the shared control information from the instruction decoding unit 220. Figure 7 In the example of , the first vector core computing unit 236-1, the second vector core computing unit 236-2, the third vector core computing unit 236-3 and the fourth vector core computing unit 236-4 can be respectively executed in four consecutive clock cycles (such as Figure 8 The clock cycles T4-T7 shown in FIG1 start the vector operations of the 1 / 4 thread group, the 2 / 4 thread group, the 3 / 4 thread group and the 4 / 4 thread group.

[0120] Still Figure 2 and Figure 6 Taking the execution of multiple SIMT32 instructions (such as instruction 1, instruction 2, instruction 3, and instruction 4) as an example, the execution process of these instructions can be described as follows:

[0121] For instruction 1:

[0122] In the first clock cycle T1, the instruction dispatch unit 210 sends instruction 1 to the instruction decode unit 220;

[0123] In the second clock cycle T2, the instruction decoding unit 220 decodes instruction 1 to obtain the operand address of the operand of instruction 1;

[0124] In the third clock cycle T3, the first operand fetching unit 232-1 reads the operand of the 1 / 4 thread group of instruction 1 from the first register 234-1;

[0125] In the fourth clock cycle T4, the first vector core computing unit 236-1 performs a vector operation on the operands of the 1 / 4 thread group of instruction 1. At the same time, the second operand fetching unit 232-2 reads the operands of the 2 / 4 thread group of instruction 1 from the second register 234-2 under the read enable control of the first operand fetching unit 232-1.

[0126] In the fifth clock cycle T5, the first vector core computing unit 236-1 writes the result of the vector operation performed on the operands of the 1 / 4 thread group of instruction 1 back to the first register 234-1. At the same time, the second vector core computing unit 236-2 performs the vector operation on the operands of the 2 / 4 thread group of instruction 1. At the same time, the third operand fetching unit 232-2 reads the operands of the 3 / 4 thread group of instruction 1 from the third register 234-3 under the read enable control of the second operand fetching unit 232-2.

[0127] In the sixth clock cycle T6, the second vector core computing unit 236-2 writes the result of the vector operation performed on the operands of the 2 / 4 thread group of instruction 1 back to the second register 234-2. At the same time, the third vector core computing unit 236-3 performs the vector operation on the operands of the 3 / 4 thread group of instruction 1. At the same time, the fourth operand fetching unit 232-4 reads the operands of the 4 / 4 thread group of instruction 1 from the fourth register 234-4 under the read enable control of the third operand fetching unit 232-3.

[0128] In the seventh clock cycle T7, the third vector core computing unit 236-3 writes the result of the vector operation performed on the operands of the ¾ thread group of instruction 1 back to the third register 234-3. At the same time, the fourth vector core computing unit 236-4 performs the vector operation on the operands of the ¾ thread group of instruction 1.

[0129] In the eighth clock cycle T8 , the fourth vector core computing unit 236 - 4 writes the result of the vector operation performed on the operands of the 4 / 4 thread group of instruction 1 back to the fourth register 234 - 4 .

[0130] For instruction 2:

[0131] In the second clock cycle T2, the instruction dispatch unit 210 sends instruction 2 to the instruction decode unit 220;

[0132] In the third clock cycle T3, the instruction decoding unit 220 decodes instruction 2 to obtain the operand address of the operand of instruction 2;

[0133] In the fourth clock cycle T4, the first operand fetching unit 232-1 reads the operand of the 1 / 4 thread group of instruction 2 from the first register 234-1;

[0134] In the fifth clock cycle T5, the first vector core computing unit 236-1 performs a vector operation on the operands of the 1 / 4 thread group of instruction 2. At the same time, the second operand fetching unit 232-2 reads the operands of the 2 / 4 thread group of instruction 2 from the second register 234-2 under the read enable control of the first operand fetching unit 232-1.

[0135] In the sixth clock cycle T6, the first vector core computing unit 236-1 writes the result of the vector operation performed on the operands of the 1 / 4 thread group of instruction 2 back to the first register 234-1. At the same time, the second vector core computing unit 236-2 performs the vector operation on the operands of the 2 / 4 thread group of instruction 2. At the same time, the third operand fetching unit 232-2 reads the operands of the 3 / 4 thread group of instruction 2 from the third register 234-3 under the read enable control of the second operand fetching unit 232-2.

[0136] In the seventh clock cycle T7, the second vector core computing unit 236-2 writes the result of the vector operation performed on the operands of the 2 / 4 thread group of instruction 2 back to the second register 234-2. At the same time, the third vector core computing unit 236-3 performs the vector operation on the operands of the 3 / 4 thread group of instruction 2. At the same time, the fourth operand fetching unit 232-4 reads the operands of the 4 / 4 thread group of instruction 2 from the fourth register 234-4 under the read enable control of the third operand fetching unit 232-3.

[0137] In the eighth clock cycle T8, the third vector core computing unit 236-3 writes the result of the vector operation performed on the operands of the ¾ thread group of instruction 2 back to the third register 234-3. At the same time, the fourth vector core computing unit 236-4 performs the vector operation on the operands of the ¾ thread group of instruction 2.

[0138] In the ninth clock cycle T9, the fourth vector core computing unit 236-4 writes the result of the vector operation performed on the operands of the 4 / 4 thread group of instruction 2 back to the fourth register 234-4.

[0139] For instruction 3:

[0140] In the third clock cycle T3, the instruction dispatch unit 210 sends instruction 3 to the instruction decoding unit 220;

[0141] In the fourth clock cycle T4, the instruction decoding unit 220 decodes instruction 3 to obtain the operand address of the operand of instruction 3;

[0142] In the fifth clock cycle T5, the first operand fetching unit 232-1 reads the operand of the 1 / 4 thread group of instruction 3 from the first register 234-1;

[0143] In the sixth clock cycle T6, the first vector core computing unit 236-1 performs a vector operation on the operands of the 1 / 4 thread group of instruction 3. At the same time, the second operand fetching unit 232-2 reads the operands of the 2 / 4 thread group of instruction 3 from the second register 234-2 under the read enable control of the first operand fetching unit 232-1.

[0144] In the seventh clock cycle T7, the first vector core computing unit 236-1 writes the result of the vector operation performed on the operands of the 1 / 4 thread group of instruction 3 back to the first register 234-1. At the same time, the second vector core computing unit 236-2 performs the vector operation on the operands of the 2 / 4 thread group of instruction 3. At the same time, the third operand fetching unit 232-2 reads the operands of the 3 / 4 thread group of instruction 3 from the third register 234-3 under the read enable control of the second operand fetching unit 232-2.

[0145] In the eighth clock cycle T8, the second vector core computing unit 236-2 writes the result of the vector operation performed on the operands of the 2 / 4 thread group of instruction 3 back to the second register 234-2. At the same time, the third vector core computing unit 236-3 performs the vector operation on the operands of the 3 / 4 thread group of instruction 3. At the same time, the fourth operand fetching unit 232-4 reads the operands of the 4 / 4 thread group of instruction 3 from the fourth register 234-4 under the read enable control of the third operand fetching unit 232-3.

[0146] At the ninth clock cycle T9, the third vector core computing unit 236-3 writes the result of the vector operation performed on the operands of the 3 / 4 thread group of instruction 3 back to the third register 234-3. At the same time, the fourth vector core computing unit 236-4 performs the vector operation on the operands of the 4 / 4 thread group of instruction 3.

[0147] In the tenth clock cycle T10 , the fourth vector core computing unit 236 - 4 writes the result of the vector operation performed on the operands of the 4 / 4 thread group of instruction 3 back to the fourth register 234 - 4 .

[0148] For instruction 4:

[0149] In the fourth clock cycle T4, the instruction dispatch unit 210 sends instruction 4 to the instruction decoding unit 220;

[0150] In the fifth clock cycle T5, the instruction decoding unit 220 decodes instruction 4 to obtain the operand address of the operand of instruction 4;

[0151] In the sixth clock cycle T6, the first operand fetching unit 232-1 reads the operand of the 1 / 4 thread group of instruction 4 from the first register 234-1;

[0152] In the seventh clock cycle T7, the first vector core computing unit 236-1 performs a vector operation on the operands of the 1 / 4 thread group of instruction 4. At the same time, the second operand fetching unit 232-2 reads the operands of the 2 / 4 thread group of instruction 4 from the second register 234-2 under the read enable control of the first operand fetching unit 232-1.

[0153] In the eighth clock cycle T8, the first vector core computing unit 236-1 writes the result of the vector operation performed on the operands of the 1 / 4 thread group of instruction 4 back to the first register 234-1. At the same time, the second vector core computing unit 236-2 performs the vector operation on the operands of the 2 / 4 thread group of instruction 4. At the same time, the third operand fetching unit 232-2 reads the operands of the 3 / 4 thread group of instruction 4 from the third register 234-3 under the read enable control of the second operand fetching unit 232-2.

[0154] In the ninth clock cycle T9, the second vector core computing unit 236-2 writes the result of the vector operation performed on the operands of the 2 / 4 thread group of instruction 4 back to the second register 234-2. At the same time, the third vector core computing unit 236-3 performs the vector operation on the operands of the 3 / 4 thread group of instruction 4. At the same time, the fourth operand fetching unit 232-4 reads the operands of the 4 / 4 thread group of instruction 4 from the fourth register 234-4 under the read enable control of the third operand fetching unit 232-3.

[0155] At the tenth clock cycle T10, the third vector core computing unit 236-3 writes the result of the vector operation performed on the operands of the 3 / 4 thread group of instruction 4 back to the third register 234-3. At the same time, the fourth vector core computing unit 236-4 performs the vector operation on the operands of the 4 / 4 thread group of instruction 4.

[0156] In the eleventh clock cycle T11 , the fourth vector core computing unit 236 - 4 writes the result of the vector operation performed on the operands of the 4 / 4 thread group of instruction 4 back to the fourth register 234 - 4 .

[0157] Here, the timing of the vector operations of the first vector core computing unit 236 - 1 , the second vector core computing unit 236 - 2 , the third vector core computing unit 236 - 3 and the fourth vector core computing unit 236 - 4 is controlled by the shared control information of the instruction decoding unit 220 .

[0158] It can be seen that in the pipeline operation of this SIMT instruction, the instruction scheduling unit 210 only needs to send instructions to the only instruction decoding unit 220, and the instruction decoding unit 220 only needs to send operand addresses to the vector core execution module 230 connected to it, and the above operations can be repeated cycle by cycle to send and decode different instructions.

[0159] Utilizing the solution of the present invention, the instruction scheduling unit of a vector computing device only needs to send instructions to a single instruction decoding unit, without having to determine which vector core the instruction should be scheduled to. This simplifies the logic, and by controlling the pipeline operation of multiple vector core execution modules through a single instruction decoding unit, the chip area can be significantly reduced. Furthermore, compared to existing vector computing devices, fewer gates are required, further reducing the chip area. Multiple vector core execution modules fixedly execute different thread group portions of the same instruction, resulting in more balanced power consumption, avoiding power consumption or heat concentration, and facilitating heat dissipation.

[0160] Those skilled in the art should also understand that the various illustrative logical blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments of the present disclosure may be implemented as electronic hardware, computer software, or a combination of both.

[0161] The above description of the present disclosure is intended to enable any person skilled in the art to implement or use the present disclosure. Various modifications of the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is intended to be consistent with the widest scope of the principles and novel features disclosed herein.

Claims

1. A vector computing device, comprising: an instruction scheduling unit, an instruction decoding unit connected to the instruction scheduling unit, and a plurality of vector core execution modules, wherein the plurality of vector core execution modules are connected in series and only one first vector core execution module is connected to the instruction decoding unit, The instruction scheduling unit is configured to schedule single instruction multiple thread (SIMT) instructions and send the SIMT instructions to the instruction decoding unit, and The instruction decoding unit is configured to decode the SIMT instruction to determine operand addresses of operands of the SIMT instruction, and instruct the multiple vector core execution modules to perform vector operations of the SIMT instruction on the operands in multiple clock cycles respectively.

2. The vector computing device of claim 1 , wherein the instruction decoding unit is configured to enable the first vector core execution module to read the operand from the operand address in one clock cycle, and the first vector core execution module is configured to enable a next vector execution module connected to the first vector core execution module to read the operand from the operand address in a clock cycle next to the clock cycle.

3. The vector computing device of claim 1 , wherein each vector core execution module comprises: Operand acquisition unit, register and vector core calculation unit, where The operand acquisition unit reads the operand from the register based on the operand address from the instruction decoding unit, and sends the read operand to the vector core computing unit, and The vector core computing unit performs the vector operation of the SIMT instruction using the operands and writes the operation result back to the register.

4. The vector computing device according to claim 3, wherein The vector core computing unit of each vector core execution module in the plurality of vector core execution modules respectively starts the vector operations in the plurality of clock cycles in sequence based on the shared control information from the instruction decoding unit.

5. The vector computing device according to claim 3, wherein Each computing unit in the vector core computing unit is used to execute vector operations of one thread of the SIMT instruction.

6. The vector computing device according to claim 2, wherein the plurality of vector core execution modules include a first vector core execution module and a second vector core execution module, and The first vector core execution module includes a first operand acquisition unit, a first register, and a first vector core calculation unit. The first operand acquisition unit reads operands of the upper thread group of the SIMT instruction from the first register based on the operand address from the instruction decoding unit, and sends the read operands to the first vector core calculation unit. The first vector core calculation unit performs a vector operation of the upper thread group of the SIMT instruction using the operands of the upper thread group, and writes the operation results back to the first register. The second vector core execution module includes a second operand acquisition unit, a second register, and a second vector core computing unit. The second operand acquisition unit reads the operands of the lower half thread group of the SIMT instruction from the second register based on the operand address from the first operand acquisition unit, and sends the read operands to the second vector core computing unit. The second vector core computing unit uses the operands of the lower half thread group to perform vector operations of the lower half thread group of the SIMT instruction, and writes the operation results back to the second register.

7. The vector computing device according to claim 6, wherein the vector computing device is configured to: In a first clock cycle, the instruction scheduling unit sends the SIMT instruction to the instruction decoding unit; In a second clock cycle, which is a next clock cycle of the first clock cycle, the instruction decoding unit decodes the SIMT instruction to obtain an operand address of an operand of the SIMT instruction; In a third clock cycle, which is a next clock cycle of the second clock cycle, the first operand acquisition unit reads the operand of the upper thread group of the SIMT instruction from the first register; In a fourth clock cycle, which is the next clock cycle after the third clock cycle, the first vector core computing unit performs a vector operation on the operands of the upper thread group of the SIMT instruction, and at the same time, the second operand acquisition unit reads the operands of the lower thread group of the SIMT instruction from the second register under the read enable control of the first operand acquisition unit; In a fifth clock cycle, which is the next clock cycle after the fourth clock cycle, the first vector core computing unit writes a result of a vector operation performed on the operands of the upper thread group of the SIMT instruction back to the first register, and at the same time, the second vector core computing unit performs a vector operation on the operands of the lower thread group of the SIMT instruction; In a sixth clock cycle, which is the next clock cycle after the fifth clock cycle, the second vector core computing unit writes back to the second register a result of a vector operation performed on operands of the lower half thread group of the SIMT instruction.

8. The vector computing device of claim 2 , wherein the plurality of vector core execution modules include a first vector core execution module, a second vector core execution module, a third vector core execution module, and a fourth vector core execution module, and The first vector core execution module includes a first operand acquisition unit, a first register, and a first vector core calculation unit. The first operand acquisition unit reads operands of the 1 / 4 thread group of the SIMT instruction from the first register based on the operand address from the instruction decoding unit, and sends the read operands to the first vector core calculation unit. The first vector core calculation unit performs a vector operation of the 1 / 4 thread group of the SIMT instruction using the operands of the 1 / 4 thread group, and writes the operation results back to the first register. The second vector core execution module includes a second operand acquisition unit, a second register, and a second vector core calculation unit. The second operand acquisition unit reads operands of the 2 / 4 thread group of the SIMT instruction from the second register based on the operand address from the first operand acquisition unit, and sends the read operands to the second vector core calculation unit. The second vector core calculation unit performs a vector operation of the 2 / 4 thread group of the SIMT instruction using the operands of the 2 / 4 thread group, and writes the operation results back to the second register. The third vector core execution module includes a third operand acquisition unit, a third register, and a third vector core calculation unit. The third operand acquisition unit reads operands of the 3 / 4 thread group of the SIMT instruction from the third register based on the operand address from the second operand acquisition unit, and sends the read operands to the third vector core calculation unit. The third vector core calculation unit performs a vector operation of the 3 / 4 thread group of the SIMT instruction using the operands of the 3 / 4 thread group, and writes the operation results back to the third register. The fourth vector core execution module includes a fourth operand acquisition unit, a fourth register and a fourth vector core calculation unit. The fourth operand acquisition unit reads the operands of the 4 / 4 thread group of the SIMT instruction from the fourth register based on the operand address from the third operand acquisition unit, and sends the read operands to the fourth vector core calculation unit. The fourth vector core calculation unit uses the operands of the 4 / 4 thread group to perform vector operations of the 4 / 4 thread group of the SIMT instruction, and writes the operation results back to the fourth register.

9. The vector computing device according to claim 8, wherein the vector computing device is configured to: In a first clock cycle, the instruction scheduling unit sends the SIMT instruction to the instruction decoding unit; In a second clock cycle, which is a next clock cycle of the first clock cycle, the instruction decoding unit decodes the SIMT instruction to obtain an operand address of an operand of the SIMT instruction; In a third clock cycle, which is a next clock cycle of the second clock cycle, the first operand acquisition unit reads the operand of the 1 / 4 thread group of the SIMT instruction from the first register; In a fourth clock cycle, which is a clock cycle next to the third clock cycle, the first vector core computing unit performs a vector operation on the operands of the 1 / 4 thread group of the SIMT instruction, and at the same time, the second operand acquisition unit reads the operands of the 2 / 4 thread group of the SIMT instruction from the second register under the read enable control of the first operand acquisition unit; In a fifth clock cycle, which is the next clock cycle after the fourth clock cycle, the first vector core computing unit writes a result of a vector operation performed on the operands of the 1 / 4 thread group of the SIMT instruction back to the first register. Simultaneously, the second vector core computing unit performs a vector operation on the operands of the 2 / 4 thread group of the SIMT instruction. Simultaneously, the third operand acquisition unit reads the operands of the 3 / 4 thread group of the SIMT instruction from the third register under the read enable control of the second operand acquisition unit. In a sixth clock cycle, which is the next clock cycle after the fifth clock cycle, the second vector core computing unit writes the result of the vector operation performed on the operands of the 2 / 4 thread groups of the SIMT instruction back to the second register. Simultaneously, the third vector core computing unit performs the vector operation on the operands of the 3 / 4 thread groups of the SIMT instruction. Simultaneously, the fourth operand acquisition unit reads the operands of the 4 / 4 thread groups of the SIMT instruction from the fourth register under the read enable control of the third operand acquisition unit. In a seventh clock cycle, which is the next clock cycle after the sixth clock cycle, the third vector core computing unit writes a result of the vector operation performed on the operands of the 3 / 4 thread groups of the SIMT instruction back to the third register, and at the same time, the fourth vector core computing unit performs the vector operation on the operands of the 4 / 4 thread groups of the SIMT instruction; In the eighth clock cycle, which is the next clock cycle after the seventh clock cycle, the fourth vector core computing unit writes back to the fourth register the result of the vector operation performed on the operands of the 4 / 4 thread group of the SIMT instruction.

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