Display method, chip, electronic device, readable medium and program product

Abstract

The invention relates to the technical field of terminals, in particular to a display method, a chip, electronic equipment, a readable medium and a program product. According to the method, in the process of displaying interfaces such as a dial plate, a plurality of interface elements included in the interfaces can be distributed to a first processor and a second processor to execute rendering according to the complexity of a first processing task including a drawing process and a rendering process; and the interface elements which are rendered on the corresponding processors are stored through a frame buffer in the cache region. And after rendering is completed, one processor synthesizes each part of interface elements rendered by the two processors and then displays the synthesized interface elements. Therefore, the performance and endurance of the device can be considered on the double-chip electronic device at the same time, the two or more processors can be coordinated to process drawing and rendering of the interface elements of the to-be-displayed interface in a labor division mode, the rendering capacity of the device is improved, maximum energy conservation and consumption reduction can be achieved, and the endurance capacity of the electronic device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of terminals, and in particular, to a display method, a chip, an electronic device, a readable medium, and a program product. Background Art

[0002] Currently, there are already electronic devices equipped with dual chips on the market, such as watches, bracelets, etc. One of the chips can be a co-processor with low power consumption and low computing power (such as a micro-controller unit (MCU)); the other chip can be a main processor with high power consumption and high computing power (such as an application processor (AP)). During the operation of the electronic device, the main and co-processors work together.

[0003] How to balance both the device performance and battery life on a dual-chip electronic device is an urgent problem to be solved. Summary of the Invention

[0004] In view of this, the present application provides a display method, a chip, an electronic device, a readable medium, and a program product, which can balance both the device performance and battery life on a dual-chip electronic device. It can not only coordinate two or more processors to divide the work of drawing and rendering the interface elements of the interface to be displayed, improve the device rendering ability, but also achieve maximum energy saving and consumption reduction, and improve the battery life of the electronic device.

[0005] In a first aspect, the present application provides a display method, which is applied to an electronic device. The electronic device includes a first processor and a second processor. The method includes: when the electronic device detects a display instruction for a first interface, determining the interface elements of the first interface, where the interface elements of the first interface include a first part of interface elements and a second part of interface elements; the first processor draws and renders the first part of interface elements, and the second processor draws and renders the second part of interface elements; the first processor or the second processor synthesizes the rendered first part of interface elements and the rendered second part of interface elements; the electronic device displays the first interface.

[0006] For example, the above-mentioned electronic device can be a watch, a bracelet, or other electronic devices with dual chips worn by the user, that is, a dual-chip device. Correspondingly, the above-mentioned first interface can be, for example, a watch face interface, etc. The interface elements of the first part can be, for example, the more complex interface elements among the interface elements of the watch face interface, including some complex vector graphic charts, video animations, animated gifs, and 3D effect pictures (which need to be rendered using resources such as 3D rendering models), etc. These interface elements require the first processor to execute more complex drawing algorithms or rendering models for drawing and rendering. The interface elements of the second part can be, for example, the simple interface elements among the interface elements of the watch face interface, and can be drawn and rendered by the second processor by executing simple drawing algorithms, etc.

[0007] After a dual-chip device such as a watch renders the interface elements of the watch face interface to be displayed based on the display method provided in the above first aspect, the first processor or the second processor in the device can be used to synthesize the two parts of the rendered interface elements, and then display the synthesized watch face interface and other interfaces.

[0008] It can be understood that the above-mentioned first processor can be the main processor of a dual-chip device such as a watch, with relatively strong computing and processing capabilities during operation, such as an AP, etc. The second processor can be the coprocessor of a dual-chip device such as a watch, with relatively low power consumption during operation, such as an MCU, etc., and there is no limitation here.

[0009] In a possible implementation of the above first aspect, the electronic device detects a display instruction for the first interface, including: the electronic device detects that the first processor powers on and works; or, the electronic device detects a user operation indicating the display of the first interface.

[0010] For example, the above-mentioned first processor powering on and working can include scenarios such as when a dual-chip device such as a watch is powered on or switched from the power-saving mode to the normal mode. Correspondingly, a dual-chip device such as a watch can determine that the first processor is detected to power on and work based on the detected event, such as the first event in the following text. It can be understood that when the first processor powers on and works, the display method provided in the present application can be continued, such as the display method implementation process shown in Embodiment 1 below Figure 4 to display relevant interfaces such as the watch face interface.

[0011] The above-mentioned user operation indicating the display of the first interface can include, for example, the operation of the user switching from the settings or other function interfaces of an electronic device such as a watch to relevant interfaces such as the watch face interface or the desktop, and there is no limitation here. Correspondingly, a dual-chip device such as a watch can determine that a user operation indicating the display of the first interface is detected based on the detected event, such as the second event in the following text. It can be understood that when an electronic device such as a watch receives a user operation, the display method provided in the present application can be continued, such as implementing the following Embodiment 2 Figure 6The implementation process of the display method shown, display the first interface, which is a relevant interface such as a dial interface.

[0012] In a possible implementation of the above first aspect, the electronic device determines the interface elements of the first interface, including: the first processor determines the interface elements of the first interface; and, the second processor draws and renders the second part of the interface elements, including: the first processor sends a first instruction to the second processor; the second processor draws and renders the second part of the interface elements in response to the first instruction.

[0013] For example, in some scenarios where the first processor is powered on and working, electronic devices such as watches can determine the interface elements of the first interface through the first processor that is powered on and working, and the first processor assigns the executors of the first processing tasks corresponding to the first part and the second part of the interface elements of the first interface respectively. At this time, the first processor can send a processing instruction corresponding to the second part of the interface elements to the second processor, instructing the second processor to draw and render the second part of the interface elements.

[0014] In a possible implementation of the above first aspect, the first processor or the second processor synthesizes the rendered first part of the interface elements and the rendered second part of the interface elements, including: the first processor reads the rendered second part of the interface elements stored in the first graphics cache, where the first processor has the read permission for the first graphics cache, and the second processor has the write permission for the first graphics cache; the first processor synthesizes the rendered first part of the interface elements and the rendered second part of the interface elements.

[0015] For example, in some scenarios where the first processor is powered on and working, electronic devices such as watches can perform synthesis processing on the partial interface elements rendered by each processor through the first processor that is powered on and working. At this time, the first processor can read the partial interface elements rendered by the second processor from the first graphics cache based on the read permission for interface synthesis. The first graphics cache can be a shared cache registered to the first processor, including a shared cache read by the first processor and written by the second processor, and a shared cache read by the first processor and written by the first processor, etc. In this way, the electronic device can prevent processors without read permission from reading or tampering with the data related to the interface elements stored in the first graphics cache, which is beneficial to ensuring the consistency of the interface synthesized based on the interface elements in the first graphics cache.

[0016] In a possible implementation of the above first aspect, the above method further includes: after the second processor draws and renders the second part of the interface elements, the second processor writes the rendered second part of the interface elements into the first graphics cache.

[0017] For example, before the first processor reads the first graphics cache, the second processor may store the rendered second part of the interface elements in the first graphics cache. It can be understood that the second processor may store the second part of the interface elements in the first graphics cache after rendering them, or may store the rendered second part of the interface elements in the first graphics cache when it is determined that the first processor will continue to synthesize the rendered first part and the second part of the interface elements. There is no limitation here.

[0018] In a possible implementation of the first aspect above, the first processor or the second processor synthesizes the rendered first part of the interface elements and the rendered second part of the interface elements, including: the electronic device obtains a first parameter of the first processor and a second parameter of the second processor; the electronic device determines, based on the first parameter and the second parameter, whether to synthesize the rendered first part of the interface elements and the rendered second part of the interface elements by the first processor or by the second processor.

[0019] For example, the first parameter may be a parameter related to the size of the task load or resource consumption currently processed by the first processor, and the second parameter may be a parameter related to the size of the task load or resource consumption currently processed by the second processor. The electronic device, or the first processor and the second processor, may negotiate and determine whether the first processor or the second processor will continue to execute the synthesis task of the rendered first part of the interface elements and the rendered second part of the interface elements based on the first parameter and the second parameter. It can be understood that if the electronic device determines that both the first processor and the second processor are suitable for executing the synthesis task, for the purpose of reducing power consumption, a processor with lower power consumption, such as the second processor, may be used to continue executing the synthesis task.

[0020] In some embodiments, the electronic device may also only obtain the parameter of one end processor, for example, only obtain the first parameter of the first processor or only obtain the second parameter of the second processor, and determine whether the end processor is suitable for executing the synthesis task based on the obtained relevant parameter. If it is suitable, the end processor that obtains the parameter is used to continue executing the synthesis task; if it is not suitable, the other end processor may be used to continue executing the synthesis task. There is no limitation here.

[0021] In a possible implementation of the first aspect described above, the first parameter includes the first load and / or the first resource occupancy, and the second parameter includes the second load and / or the second resource occupancy. Wherein, the first load includes the number of tasks currently processed by the first processor, and the first resource occupancy includes the current occupancy of the first processor on the system memory resources and / or computing power resources; the second load includes the number of tasks currently processed by the second processor, and the second resource occupancy includes the current occupancy of the second processor on the system memory resources and / or computing power resources.

[0022] In a possible implementation of the first aspect described above, the first interface includes a dial interface.

[0023] In a possible implementation of the first aspect described above, the first processor includes an application processor (AP), and the second processor includes a microcontroller unit (MCU); or, the first processor includes an application processor (AP), and the second processor includes a microcontroller unit (MCU).

[0024] In a possible implementation of the first aspect described above, the electronic device further includes a second graphics cache and a third cache. Wherein, the first processor has read and write permissions for the second graphics cache; the second processor has read and write permissions for the third cache.

[0025] For example, the above-mentioned second graphics cache can be a cache area in the shared cache of a dual-core device such as a watch, which is read and written by the first processor; the above-mentioned third cache can be a cache area in the shared cache of a dual-core device such as a watch, which is read and written by the second processor.

[0026] In a possible implementation of the first aspect described above, the electronic device is a watch or a bracelet.

[0027] It can be understood that in other embodiments, the above-mentioned electronic device can also be other dual-chip or multi-chip electronic devices other than watches or bracelets, which are not limited herein.

[0028] In a second aspect, the present application provides a display method, including: the first processor draws and renders the first partial interface elements of the first interface, where the first interface is the interface indicated by the display instruction detected by the electronic device, and the electronic device includes the first processor; the first processor obtains the second partial interface elements of the first interface drawn and rendered by the second processor; the first processor synthesizes the rendered first partial interface elements and the rendered second partial interface elements, and sends the synthesized first interface for display.

[0029] In a possible implementation of the second aspect described above, before the first processor draws and renders the first part of the interface elements of the first interface, the method further includes: the first processor determines that the interface elements of the first interface include the first part of the interface elements and the second part of the interface elements; and the first processor sends a first instruction to the second processor, where the first instruction is used to instruct the second processor to draw and render the second part of the interface elements of the first interface.

[0030] In a possible implementation of the second aspect described above, the first processor obtains the second part of the interface elements of the first interface drawn and rendered by the second processor, including: the first processor reads from the first graphics cache the second part of the interface elements of the first interface drawn and rendered by the second processor, where the first processor has the read permission for the first graphics cache, and the second processor has the write permission for the first graphics cache.

[0031] In a possible implementation of the second aspect described above, the first processor synthesizes the rendered first part of the interface elements and the rendered second part of the interface elements, including: the first processor obtains the first parameter of the first processor and the second parameter of the second processor; the first processor synthesizes the rendered first part of the interface elements and the rendered second part of the interface elements according to the first parameter and the second parameter.

[0032] In a possible implementation of the second aspect described above, the first parameter includes the first load and / or the first resource occupancy, and the second parameter includes the second load and / or the second resource occupancy. Among them, the first load includes the number of tasks currently processed by the first processor, and the first resource occupancy includes the current occupancy of the first processor for system memory resources and / or computing power resources; the second load includes the number of tasks currently processed by the second processor, and the second resource occupancy includes the current occupancy of the second processor for system memory resources and / or computing power resources.

[0033] In a third aspect, the present application provides a chip for executing the display method provided in the second aspect and various possible implementations of the second aspect.

[0034] In a fourth aspect, the present application provides an electronic device, characterized by including: one or more processors; one or more memories; one or more programs are stored in one or more memories, and when the one or more programs are executed by the one or more processors, the electronic device is enabled to execute the display method provided in the first aspect and various possible implementations of the first aspect, or the second aspect and various possible implementations of the second aspect.

[0035] In a fifth aspect, the present application provides a computer-readable medium, on which instructions are stored. When the instructions are executed on a computer, the computer is caused to execute the display method provided in the above first aspect and various possible implementations of the first aspect, or the above second aspect and various possible implementations of the second aspect.

[0036] In a sixth aspect, the present application provides a computer program product, characterized by including a computer program / instructions. When the computer program / instructions are executed by a processor, they are used to implement the display method provided in the above first aspect and various possible implementations of the first aspect, or the above second aspect and various possible implementations of the second aspect.

[0037] For the beneficial effects of the above second aspect to the sixth aspect, reference can be made to the relevant descriptions in the above first aspect and various possible implementations of the first aspect, and details are not elaborated herein. Description of the Drawings

[0038] Figure 1a A schematic diagram of an application scenario of a display method is shown.

[0039] Figure 1b A schematic diagram of the process of an electronic device completing interface display is shown.

[0040] Figure 1c A schematic diagram of the process of another electronic device completing interface display provided by an embodiment of the present application is shown.

[0041] Figure 2a A schematic diagram of the composition of interface elements of a "planet dial" provided by an embodiment of the present application is shown.

[0042] Figure 2b A schematic diagram of interface elements arranged in Z-order provided by an embodiment of the present application is shown.

[0043] Figure 3a A schematic diagram of the hardware structure of a dual-core device provided by an embodiment of the present application is shown.

[0044] Figure 3b A schematic diagram of the dual-system structure of a dual-core device running provided by an embodiment of the present application is shown.

[0045] Figure 4 A schematic diagram of the implementation process of a display method in a power-on or working mode switching scenario provided by an embodiment of the present application is shown.

[0046] Figure 5 A schematic diagram of the implementation principle of the write and read processes of a shared cache provided by an embodiment of the present application is shown.

[0047] Figure 6The figure shows a schematic flowchart of an implementation process of a display method provided by an embodiment of the present application in an interface switching scenario.

[0048] Figure 7 The figure shows a schematic flowchart of an implementation process of another display method provided by an embodiment of the present application. Detailed implementation manners

[0049] In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described in detail below with reference to the accompanying drawings of the specification and specific implementation manners.

[0050] It can be understood that the electronic device in the embodiments of the present application can also be referred to as a terminal or terminal device, user equipment (UE), mobile station (MS), mobile terminal (MT), etc. The electronic device can be a mobile phone, smart TV, wearable device, tablet computer (Pad), computer with wireless transceiver function, virtual reality (VR) electronic device, augmented reality (AR) electronic device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, and so on.

[0051] Exemplarily, the wearable device in the embodiments of the present application can be a smart watch, smart bracelet, smart glasses, smart ankle ring, smart ring, smart necklace, augmented reality (AR) device, virtual reality (VR) device, etc. The present application does not impose special restrictions on the specific form of the wearable device.

[0052] To facilitate understanding of the solutions in the embodiments of the present application by those skilled in the art, some concepts and terms related to the embodiments of the present application will be explained below.

[0053] Z-order refers to a stack where multiple layers or windows overlap. Each layer or window has a unique position in the Z-order. This stack extends vertically out of the screen along a virtual axis, the "Z-axis". The layer or window at the top of the Z-order covers other layers or windows at the bottom in the Z-order. The layer or window at the bottom of the Z-order is covered by other layers or windows at the top in the Z-order.

[0054] Figure 1a The figure shows a schematic diagram of an application scenario of a display method.

[0055] As Figure 1a shown, this scenario includes a watch 10, which is an electronic device with dual chips and can hereinafter be simply referred to as a dual-chip device. As an example, one chip included in the watch 10, such as an AP, can be the main processor, and the other chip included in the watch 10, such as an MCU, can be the coprocessor. During the period when the user wears the watch 10, the user can use the style of the dial interface set by default when the watch 10 is powered on, or can also set the style of the dial interface of the watch 10 by himself / herself.

[0056] For the above Figure 1a example of the watch 10 and other dual-chip devices, during the process of displaying interfaces such as the dial, the watch 10 can usually use the MCU to draw and render some relatively simple interface elements. For example, if all the interface elements of the dial interface displayed by the watch 10 are relatively simple interface elements supported by the MCU for drawing and rendering processors, the watch 10 can draw and render all the interface elements through the MCU, and the MCU can synthesize and send all the rendered interface elements for display. However, if the interface elements of the dial interface displayed by the watch 10 are relatively complex and need to be drawn and rendered by the AP running relevant algorithms or models, for example, the above interface elements may include some complex vector graphic charts, video animations, animated gifs, 3D effect pictures (which need to be rendered using 3D rendering model and other resources), etc., relatively complex interface elements, then the watch 10 may draw and render all the interface elements through the AP. And the watch 10 can also synthesize and send all the rendered interface elements for display through the AP.

[0057] As an example, the style of the dial interface displayed by the watch 10 can be, for example, Figure 1a the "planet dial" shown. The "planet" image among the interface elements included in the style of this dial interface may be a 3D effect planet picture or an animated gif, and only the AP can perform 3D rendering models or other relevant algorithms for rendering.

[0058] To facilitate understanding of the display solution provided by this application, the following will be combined with Figure 1b to introduce the execution process of the rendering task corresponding to the "planet dial" interface in the above Figure 1a shown scenario.

[0059] refer to Figure 1b As shown, the process of displaying the dial interface of the watch 10 may include a drawing process, a rendering process, and a synthesis and display process, and each process may include one or more steps. Among them, the drawing process is used to draw the graphic data of each layer of interface elements of the interface according to the interface drawing request of the application; the rendering process is used to render (such as shading, rasterization, ray tracing, etc.) according to the graphic data of each layer of interface elements to obtain each layer of interface elements after rendering; the display process is used to display each layer of interface elements on the display screen of the watch 10 frame by frame. In other words, for a frame of interface, such as a dial interface, it can be displayed on the display screen of the watch 10 through drawing, rendering, and synthesis and display in sequence.

[0060] Continue to refer Figure 1b , assuming that the display screen of watch 10 generates a VSync signal every 16.6ms, and a certain dial interface includes 5 layers of interface elements, such as background element S1, background element S2, data component element S3, date element S4, time element S5, etc., when receiving the VSync signal at each moment that triggers the start of the drawing process, watch 10 can start drawing the graphic data of the interface elements S1, S2, S3, S4, and S5 of the image in sequence through the drawing process. After obtaining the graphic data of the drawn interface elements S1, S2, S3, S4, and S5, watch 10 can also continue to complete the rendering, synthesis, and display of the interface elements S1, S2, S3, S4, and S5 through the rendering process. The display process displays the dial interface after the synthesis process. Among them, Figure 1b The drawing, rendering, synthesis, and display sending processes shown are all executed by the first processor, which may be an MCU or an AP.

[0061] It is understood that before executing the above drawing process, the watch 10 can determine whether the interface elements to be rendered include more complex elements that the MCU cannot support rendering processing, such as the above Figure 1a The planetary animated image or animated background of the "planetary dial" interface in the scene shown. If it is determined that more complex elements are included, the style of the dial interface of the watch 10 is based on the above-mentioned "planetary dial" when displaying the above-mentioned "planetary dial". Figure 1b The drawing, rendering, and synthesis and display processes shown in the figure will all be handed over to the AP for execution. However, the dial interface including more complex interface elements mentioned above usually also includes some simpler elements, such as time, date, pointers, and some simple data text elements. Although the AP has strong processing capabilities, the power consumption corresponding to the rendering process executed by the AP is also high. If the entire dial interface is drawn and rendered by the AP, it will lead to an increase in the power consumption of the watch 10, and then cause the battery life of electronic devices such as the watch 10 to deteriorate.

[0062] To solve the above problems, an embodiment of the present application provides a display method. Specifically, during the process of displaying an interface such as a dial, the method can allocate multiple interface elements included in the interface to the first processor and the second processor for rendering respectively according to the complexity of the first processing task including rendering, and store the interface elements that have completed rendering on the corresponding processor through a shared cache (framebuffer) in the buffer. The above first processing task may include processing tasks corresponding to the drawing process and the rendering process. After the rendering is completed, one of the processors synthesizes the interface elements separately rendered by the two processors and then performs the display.

[0063] For example, referring to Figure 1c As shown, continuing with the above interface elements S1, S2, S3, S4, S5 as an example, and a dual-core watch including a first processor and a second processor as an example. The interface element S2 is, for example, an interface element with a relatively complex rendering process and needs to be drawn and rendered by the first processor with high computing power. Based on the above display method provided by the present application, the watch 10 can complete the drawing process and the rendering process of the interface element S2 through the first processor; and the watch 10 can complete the drawing process and the rendering process of the interface elements S1, S3, S4, S5 through the second processor. It can be understood that the elements drawn and rendered by the first processor may include elements that need to be drawn by executing relatively complex drawing algorithms, such as some complex vector graphic charts, and interface elements that need to be rendered by running relatively complex 3D rendering model resources, such as video animations, animated gifs, 3D effect pictures (rendered using 3D rendering models), etc. The drawing and rendering of these elements often require a large amount of calculations, so a processor with higher computing power is needed to draw and render. The watch 10 can determine the partial interface elements drawn and rendered by the first processor and the partial interface elements drawn and rendered by the second processor according to the operation complexity of the drawing algorithms, rendering models, etc. corresponding to the interface elements of the relevant interface.

[0064] In some embodiments, electronic devices such as the watch 10 can also add classification labels indicating drawing and rendering by the first processor, and / or classification labels indicating drawing and rendering by the second processor, etc. to the interface elements of each interface that supports display according to the operation complexity of relevant drawing algorithms, rendering models, etc., which is not limited here.

[0065] Furthermore, the second processor can cache the data related to the interface elements S1, S3, S4, and S5 after rendering into a shared cache (framebuffer) accessible by the first processor. In this way, the first processor can read the data related to the interface elements S1, S3, S4, and S5 in the shared cache, synthesize the dial interface composed of the interface elements S1, S2, S3, S4, and S5, and perform interface display, that is, display the dial interface on the display screen of the watch 10.

[0066] In some other embodiments, the watch 10 can also perform the synthesis and display tasks through the second processor. At this time, the second processor can read the interface element S2 in the shared cache, synthesize the dial interface composed of the interface elements S1, S2, S3, S4, and S5, and perform interface display, that is, display the dial interface on the display screen of the watch 10.

[0067] It can be understood that the above-mentioned first processor can be the main processor with high computing power, such as an AP, etc., and the above-mentioned second processor can be the co-processor with low power consumption, such as an MCU, etc. For example, during the process of displaying the dial interface, if it is determined that the interface element to be drawn and rendered is an element that the MCU can support the rendering processing task, the drawing and rendering processing task of this interface element is handed over to the MCU for execution. If it is determined that the interface element to be drawn and rendered is an element that the MCU cannot support rendering, such as relatively complex video, animated image and other interface elements, the drawing and rendering tasks of this interface element are handed over to the AP for execution. After the drawing and rendering are completed, the AP or the MCU can continue to perform the synthesis and display tasks. Among them, the processor that executes the synthesis and display tasks can obtain the interface elements rendered by the other processor from the shared cache.

[0068] It can be understood that the above-mentioned shared cache can be a part of the cache space of the watch 10. This part of the cache space can support the two processors to complete reading and / or writing respectively, and is used to store the rendered interface elements of the relevant interfaces displayed by the watch 10. Therefore, it is called a shared cache in this application. In some other embodiments, the above-mentioned shared cache can also be described by other names. In the following text of the embodiments of this application, the shared cache can include a first graphics cache and a second graphics cache, etc. For specific details, reference can be made to the relevant descriptions in the following text, and no limitation is made here.

[0069] In this way, based on the rendering solution provided by this application, electronic devices such as watches can preferentially use the second processor with low power consumption (such as an MCU) to draw and render simple interface elements of interfaces such as dials, while for relatively complex interface elements that the second processor cannot support rendering, they can be partially scheduled to the first processor with high computing power (such as an AP) side to execute the drawing and rendering process. This is beneficial to reducing the power consumption of electronic devices such as watches and achieving the purpose of maximizing power savings.

[0070] In some other embodiments, the above-mentioned first processor may also be a co-processor with low power consumption, and the above-mentioned second processor may be a main processor with high computing power. Correspondingly, the processor for executing the drawing process and rendering process of the above-mentioned relatively complex interface elements may be the above-mentioned second processor, and the processor for executing the drawing process and rendering process of the above-mentioned simple interface elements may be the above-mentioned first processor, which is not limited herein.

[0071] Taking the dial interface as an example, and taking the first processor of the watch 10 as an AP and the second processor as an MCU as an example, refer to Figure 2a As shown, for the interface elements of the "planet dial" exemplified above Figure 1a it may include, but is not limited to, different types of interface elements such as time, date, data components, and background. Based on the above-mentioned rendering solution provided by the present application, the watch 10 may first execute the drawing and rendering processing tasks of the background element S1 (such as the background layer of the "planet dial") through the MCU. Then, the watch 10 may execute the drawing and rendering processing tasks of the background element S2 (such as the planet animation or animated background of the "planet dial") through the AP. Furthermore, the watch 10 may continue to execute the drawing and rendering of the data component element S3, date element S4, time element S5, etc. through the MCU.

[0072] After completing the drawing and rendering processing of each interface element, the MCU or AP may cache the rendered interface elements into a shared cache that can be read by the other party, so as to facilitate the AP or MCU to call them when continuing to execute the subsequent composite display task. For example, when the AP executes the composite display task of the dial interface, it may call the above-mentioned background element S1, data component element S3, date element S4, time element S5, etc. rendered by the MCU cached in the shared cache from the shared cache, and synthesize them in order with the background element S2 rendered by the AP itself into the dial interface. Among them, the shared cache that the AP can read may be a shared cache pre-registered for the AP to read and written by the MCU, which may be referred to as the first graphics cache hereinafter. The shared cache that the MCU can read may be a shared cache pre-registered for the MCU to read and written by the AP, which may be referred to as the second graphics cache hereinafter. The two may be the same part of the cache or different parts of the cache, which is not limited herein.

[0073] In some other embodiments, the above-mentioned interface elements may further include scale elements, pointer elements, etc., which are not limited herein. When the above-mentioned interface elements are synthesized, they may be synthesized and sent for display according to the Z-order. During the implementation of the display method provided by the present application, the above-mentioned interface elements may be hierarchically decomposed according to the Z-order in advance to obtain Figure 2bThe table of interface elements arranged in the Z-order as shown. Further, during the process of being drawn and rendered in the Z-order, each layer of interface elements can respectively assign the drawing and rendering processing tasks of each interface element to the first processor or the second processor to execute based on the display method provided in this application. It can be understood that the interface elements at the top in the Z-order can be located in a layer higher than those at the bottom.

[0074] Specifically, referring to Figure 2b as shown, the arrangement order of the above-mentioned interface elements from the bottom layer to the top layer in the Z-order can include:

[0075] Background elements: including background layers, background images, etc. Among them, the background layer can be, for example, the above-mentioned background element S1, and the background image can be the above-mentioned background element S2. The background image can be a graphic, an image with 2D or 3D effects, an animated image, etc., which are not limited here.

[0076] Scale elements: including some graphics indicating scales on a dial with clock, minute, and second scale lines, including some complex vector graphics, etc., which are not limited here.

[0077] Data component elements: including texts corresponding to longitude and latitude data, sunrise data, sunset data, moonrise data, moonset data, etc., and also including texts corresponding to motion data, heart rate data, pressure data, etc., which are not limited here.

[0078] Date elements: including texts related to calendar data such as year, month, date, week, etc., and also including texts related to lunar month, date, etc., which are not limited here.

[0079] Time elements: including the time text indicating time zone and hour, minute, and second. The style-related data such as the font, color, and layout position adopted by the time text can also belong to the related data of the time elements.

[0080] Pointer elements: including some graphics on a dial with scales for indicating the readable position corresponding to the current time. In some embodiments, the pointer elements can be embedded in other interface elements. For example, Figure 2b as shown, the date element can include a pointer indicating the date "18".

[0081] In the embodiments of this application, among the above-mentioned Figure 2b multiple interface elements arranged in the Z-order, the interface elements drawn and rendered by the second processor can include the background layer in the background elements, the graphics or 2D images in the background elements, scale elements, data component elements, date elements, time elements, pointer elements, etc.; the interface elements drawn and rendered by the first processor can include 3D images or animated images in the background elements.

[0082] After the second processor finishes rendering the above interface elements, the rendered interface elements can be cached in a shared cache, i.e., the first graphics cache. Subsequently, if the first processor executes the composite display task for the dial, it can read the interface elements rendered by the second processor in the shared cache and perform composition and display together with the interface elements rendered on the first processor side, i.e., the display process shown above. Similarly, after the first processor finishes rendering relatively complex interface elements such as 3D images or animated graphics, it can also cache the rendered interface elements in a shared cache, i.e., the second graphics cache. Subsequently, if the second processor executes the composite display task for the dial, it can read the interface elements rendered by the first processor in the shared cache and perform composition and display together with the interface elements rendered on the second processor side. For ease of description, the first processor, such as an AP, can also be described as the main processor hereinafter. The operating system running on the main processor or the first processor can be called the main system or the first system; the second processor, such as an MCU, can also be described as the coprocessor hereinafter. The operating system running on the coprocessor or the second processor can be called the co-system or the second system. Figure 1c As can be understood, based on the rendering solution provided in this application, there is no need to separately deploy the complete rendering capabilities for different interface elements on the main processor and the coprocessor, but only need to deploy the rendering capabilities matching the computing power of each processor. For example, on the second system running on the coprocessor, rendering components corresponding to rendering the above scale elements, data component elements, date elements, time elements, pointer elements, etc. can be deployed to provide corresponding rendering capabilities; on the main system running on the main processor, some 3D rendering models, animated graphic rendering components or video rendering components, etc. can be deployed to provide the rendering capabilities for the corresponding interface elements. In this way, the workload of the main and coprocessors can also be reduced, and the memory occupation and waste of each chip by the repeatedly deployed components can also be reduced accordingly. Moreover, the interface display effects of the composite display executed by the main processor or the coprocessor can maintain consistency, avoiding the inconsistency that may be brought about by rendering the same interface elements using different rendering capabilities on the two chips.

[0083] As an example, the hardware structure and system software structure of the dual-core device will be introduced in detail below with reference to the accompanying drawings.

[0084] According to an embodiment of the present application, a schematic diagram of the hardware structure of a dual-core device is shown. In the embodiment of the present application, the dual-core device can be exemplified by a watch 10.

[0085] Figure 3a As shown in

[0086] As Figure 3aAs shown, the watch 10 can be a dual-core device, for example, including a first processor 110 and a second processor 120. In the embodiments of this application, the above-mentioned first processor 110 can be the main processor of the watch 10, with relatively high computing power, such as an AP, etc. The above-mentioned second processor 120 can be the coprocessor of the watch 20, with lower power consumption during operation, such as an MCU, etc.

[0087] In some other embodiments, the above-mentioned first processor 110 can also be a coprocessor with lower power consumption, such as an MCU, etc.; the above-mentioned second processor 120 can also be a main processor with high computing power, such as an AP, etc., which is not limited herein.

[0088] Continuing to refer to Figure 3a , the input device of the watch 10 can include a touch screen 101, a sensor module 102, and a button 103 to receive user input operations or input information. Among them, the touch screen 101 and the button 103 can be used to receive user operations and interact with the user. The sensor module 102 can include a gyroscope sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a temperature sensor, a touch sensor, an ambient light sensor, etc., and is used to collect relevant sensing data and provide it to the first processor 110 and / or the second processor 120 to realize the perception function of the watch 20 for the environment and the user's wearing behavior or other behaviors.

[0089] In some embodiments, the input device of the watch 10 can also include a crown 104 and / or a camera 105, etc., which is not limited herein. Among them, the crown 104 is used to adjust the date and time of the watch 10, etc. The camera 105 can be used to support the watch 10 for video calls, etc., and can also be used to collect environmental information to realize some scene perception functions of the watch 10, which is not limited herein. In some other embodiments, the watch 10 may not include structures such as the crown 104 and / or the camera 105, etc., which is not limited herein.

[0090] It can be understood that the above-mentioned input device can be connected to at least one of the first processor 110 and the second processor 120. Taking the AP and the MCU as an example, that is, the above-mentioned input device, such as the touch screen 101, the sensor module 102, the button 103, the crown 104, and / or the camera 105, etc., can be electrically connected only to the AP, can be electrically connected only to the MCU, or can be electrically connected to both the AP and the MCU, which is not limited herein. In some embodiments, it can also be that the touch screen 101, the button 103, and the crown 104 are respectively electrically connected to both the AP and the MCU, and the sensor module 102 or the camera 105, etc., can be electrically connected only to the AP, electrically connected only to the MCU, or electrically connected to both the AP and the MCU, which is not limited herein.

[0091] Continuing to refer to Figure 3a, the smartwatch 10 may also include a wireless fidelity (Wi-Fi) chip, a modem, a Bluetooth (BT) chip, etc., for implementing the communication and Internet access functions of the smartwatch 10. For example, the smartwatch 10 may access a Wi-Fi network based on the Wi-Fi chip, connect to a time service server to complete time calibration and update system software, etc. For another example, the smartwatch 10 may perform modulation / demodulation processing on communication data of a subscriber identity module (SIM card for short) or an embedded SIM card (eSIM card) installed based on the modem, to implement functions such as calls and data communication. For another example, the smartwatch 10 may also establish a Bluetooth connection with other electronic devices based on the Bluetooth chip, transmit data and instructions to each other, and implement cross-device collaboration functions, etc., which will not be elaborated here.

[0092] In some embodiments, the smartwatch 10 may also include an embedded multimedia card (eMMC) or other forms of memory, which may also be referred to as external memory in some embodiments, for implementing the storage function of quickly storing and reading data of the smartwatch 10. For example, files such as music are saved in the eMMC. It can be understood that the above structures such as the Wi-Fi chip, the modem, the Bluetooth chip, and the eMMC may be connected only to the main processor (such as the AP), or only to the coprocessor (such as the MCU), or may also be connected to both the AP and the MCU, which will not be limited or elaborated here.

[0093] Continuing to refer to Figure 3a , the smartwatch 10 may also include a cache 130, which may also be referred to as internal storage in some embodiments, for storing computer-executable program codes, and the executable program codes include instructions. The cache 130 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, application programs required for at least one function (such as a sound playback function, an image playback function, etc.). The data storage area may store data created during the use of the smartwatch 10 (such as audio data, a phone book, etc.). In addition, the cache 130 may include a high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0094] It can be understood that the cache 130 may be connected to the first processor 110 and the second processor 120. The first processor 110 or the second processor 120 executes various functional applications and data processing of the smartwatch 10 by running the instructions stored in the cache 130, and / or the cache instructions set in the processor.

[0095] In the embodiments of the present application, the cache 130 may include a storage area that can only be read and written by the first processor 110 and a storage area that can only be read and written by the second processor 120, such as Figure 3a the cache dedicated to the first processor and the cache dedicated to the second processor as shown. The cache 130 may also include a storage area that can be read and written by both the first processor 110 and the second processor 120, such as Figure 3a the shared cache as shown. In the embodiments of the present application, taking the AP and the MCU as examples, the shared cache in the cache 130 may include a first graphics cache read by the AP and written by the MCU, and a second graphics cache read by the MCU and written by the AP.

[0096] In some embodiments, the above-mentioned shared cache may also include a cache read and written by the MCU and / or a cache read and written by the AP. It can be understood that in some embodiments, the cache in the above-mentioned shared cache that the AP has read permission, including the cache read by the AP and written by the MCU and the cache read and written by the AP, can all be referred to as the above-mentioned first graphics cache. Similarly, the cache in the above-mentioned shared cache that the MCU has read permission, including the cache read by the MCU and written by the AP and the cache read and written by the MCU, can all be referred to as the above-mentioned second graphics cache. In view of the fact that the above-mentioned first graphics cache only provides read permission to the main processor (such as the AP), and the second graphics cache only provides read permission to the coprocessor (such as the MCU), in this way, it can prevent the data written into the corresponding cache, such as the data related to the rendered interface elements in the embodiments of the present application, from being tampered with by other processors without read permission, and can ensure the relative independence of the cache data that the main and coprocessors can read, so that the subsequent composite display task can be executed accurately and problems such as interface composition errors can be avoided.

[0097] Based on the above Figure 3a hardware structure shown, Figure 3b According to the embodiments of the present application, a schematic diagram of a dual-system structure for a dual-core device to operate is shown.

[0098] As mentioned above, the operating system running on the above-mentioned main processor or the first processor can be called the main system or the first system; the operating system running on the above-mentioned coprocessor or the second processor can be called the coprocessor system or the second system. Below, taking the first system and the second system as examples, in combination with Figure 3b exemplarily illustrate the software structure of the dual systems running on a dual-core device such as the watch 10.

[0099] As Figure 3bAs shown, the dual systems running on dual-core devices such as the watch 10 may include a first system 300a and a second system 300b. It can be understood that in some embodiments, the first system 300a and the second system 300b may be two different systems, or they may be the same two systems. In other embodiments, the first system 300a and the second system 300b may also be two parts of the system architecture of the same system, which is not limited herein.

[0100] It can be understood that the operating system of dual-core devices such as the watch 10 may adopt a layered architecture, an event-driven architecture, a microkernel architecture, a microservices architecture, or a cloud architecture. Among them, the layered architecture divides software into several layers, and each layer has a clear role and division of labor. The layers communicate with each other through software interfaces. In some embodiments, as Figure 3b shown, the first system 300a from top to bottom is respectively an application layer 310a, a framework layer 320a, a system service layer 330a, and a kernel layer 340a.

[0101] Among them, the application layer 310a can run the first type of applications adapted to the first system 300a and the system user interface (SystemUI). Among them, SystemUI can be used to call the display framework 321a of the framework layer 320a to negotiate the drawing and rendering of interface elements of relevant interfaces, and call the scheduling module 331a of the system service layer 330a to negotiate the composition and display of the rendered interface elements, that is, SystemUI is used to provide an interaction interface with the user and trigger the display process of relevant interfaces. The implementation of the specific display process can be referred to the relevant description below, and will not be elaborated herein.

[0102] The framework layer 320a may include a display framework 321a, which is used to communicate with the display framework 321b of the second system 300b to negotiate and decide which of the first processor 110 or the second processor 120 will draw and render the interface elements of relevant interfaces. The specific negotiation and decision-making process can refer to the relevant description in the specific implementation process below, and will not be elaborated herein. Taking the watch 10 as an example, the display framework 321a may be a dial framework, which is used to negotiate and decide the executor of the interface elements for drawing and rendering relevant dial interfaces with the system running on another processor, for example, deciding that the AP will draw and render some interface elements and the MCU will draw and render some interface elements.

[0103] The system service layer 330a may include a scheduling module 331a, which is used to communicate with the scheduling module 331b of the second system 300b to negotiate which of the first processor 110 or the second processor 120 will compose the interface elements of relevant interfaces and send them for display. The specific negotiation process can refer to the relevant description in the specific implementation process below, and will not be elaborated herein.

[0104] In some embodiments, the above-mentioned scheduling module 331a may be, for example, a hybrid scheduling module based on a hybrid interface, where the hybrid interface can be used to schedule the graphics synthesizer connected or run by the first processor 110 or the second processor 120, synthesize each part of the rendered interface elements, and then send the synthesized interface-related data to the above-mentioned touch screen 101 for display, that is, send for display.

[0105] The kernel layer 340a is the layer between hardware and software. The kernel layer of the distributed operating system may include: a kernel subsystem and a driver subsystem.

[0106] Among them, the kernel subsystem can adopt a multi-kernel design for the distributed operating system. Therefore, the kernel subsystem supports selecting a suitable OS kernel for different resource-constrained devices. The kernel abstract layer (KAL) on the kernel subsystem provides basic kernel capabilities to the upper layer by shielding the multi-kernel differences, including process / thread management, memory management, file system, network management, and peripheral management, etc.

[0107] The driver framework provided by the driver subsystem is the basis for the opening of the distributed system hardware ecosystem, providing a unified peripheral access capability and a driver development and management framework. In some embodiments, the driver subsystem may include device drivers such as a display driver and an audio driver, which are used to drive the corresponding devices to work and provide corresponding hardware capabilities, etc.

[0108] Continue to refer to Figure 3b , similarly, the second system 300b from top to bottom is respectively an application layer 310b, a framework layer 320b, a system service layer 330b, and a kernel layer 340b.

[0109] Among them, the application layer 310b can run a second type of application adapted to the second system 300b and SystemUI. Among them, SystemUI can be used to call the display framework 321b of the framework layer 320b to negotiate the drawing and rendering of the interface elements of the relevant interface, and call the scheduling module 331b of the system service layer 330b to negotiate the synthesis and sending for display of the rendered interface elements, etc. The implementation of the specific display process can be referred to the relevant description below and will not be elaborated here.

[0110] It can be understood that the above-mentioned second type of application may be a simpler application program than the first type of application. Among them, the above-mentioned first type of application may be an application program deployed on the main processor, and the above-mentioned second type of application may be an application program deployed on the coprocessor to run.

[0111] The framework layer 320b may include a display framework 321b for communicating with the display framework 321a of the first system 300a to negotiate and decide which of the first processor 110 or the second processor 120 will draw and render the interface elements of the relevant interface. The specific negotiation and decision-making process can refer to the relevant descriptions in the following specific implementation process and will not be elaborated here. Taking the watch 10 as an example, the display framework 321b may be a dial framework for negotiating and deciding the executor of the interface elements for drawing and rendering the relevant dial interface with the system running on another processor. For example, it decides that the AP will draw and render some interface elements and the MCU will draw and render some interface elements.

[0112] The system service layer 330b may include a scheduling module 331b for communicating with the scheduling module 331a of the first system 300a to negotiate which of the first processor 110 or the second processor 120 will synthesize the interface elements of the relevant interface and send them for display. The specific negotiation process can refer to the relevant descriptions in the following specific implementation process and will not be elaborated here.

[0113] The kernel layer 340b is the layer between hardware and software. The specific structure and functions can refer to the relevant descriptions of the above kernel layer 340a. In some embodiments, the kernel subsystems and driver subsystems of the kernel layer 340b may have fewer kernel capabilities and driver structures, etc. than those of the kernel layer 340a, which is not limited here.

[0114] Based on the above Figure 3a and Figure 3b shown structure, the following will introduce in detail the specific implementation process of the display method provided by this application in combination with the embodiments in different scenarios.

[0115] First, in combination with Embodiment 1, the detailed process of implementing the display method provided by this application in the boot scenario of dual-core devices such as the watch 10 will be introduced.

[0116] Embodiment 1

[0117] Figure 4 According to the embodiments of this application, a schematic diagram of the implementation process of a display method in the boot or working mode switching scenario is shown.

[0118] As Figure 4 shown, this implementation process involves the interaction between two processors of dual-core devices such as the watch 10, for example, the interaction between the first processor 110 and the second processor 120. In some other embodiments, Figure 4 the shown process may also involve the interaction between more than two processors, which is not limited here.

[0119] It should be noted here that the numbering of steps in the methods and processes in the embodiments of this application is for the convenience of reference, rather than limiting the order. If there is an order between steps, it shall be subject to the written description.

[0120] As Figure 4 shown, the implementation process may include the following steps:

[0121] 401: The first processor 110 detects a first event. Among them, the first event may include a power-on event.

[0122] Exemplarily, taking the power-on scenario as an example, corresponding to detecting the first event, the first processor 110 may detect the power-on scenario. It can be understood that the power-on scenario may include the scenario where the power supply of a dual-core device such as the watch 10 changes from off to on; or, the power-on scenario may also include the scenario where the main processor of an electronic device such as the watch 10 changes from power-off to power-on working state, that is, the scenario where an electronic device such as the watch 10 switches from the power-saving mode or the super power-saving mode to the normal mode (or called the all-round mode), which is not limited here. In the first system 300a run by the first processor 110, SystemUI may respond to user operations and call the display framework 321a to detect the above-mentioned power-on event or other first events.

[0123] In the embodiments of this application, the main processor of an electronic device such as the watch 10, for example, the above-mentioned first processor 110, may be an AP, and the second processor 120 may be an MCU. In some other embodiments, the first processor 110 may also be an MCU, and the second processor 120 is an AP, which is not limited here.

[0124] 402: The first processor 110 obtains the interface elements included in the first interface triggered by the first event.

[0125] Exemplarily, after the first processor 110 detects the above-mentioned first events such as the power-on event, it may obtain the first interface triggered by the first event, such as the dial interface displayed when the watch 10 is powered on. In the first system 300a run by the first processor 110, the display framework 321a may obtain the interface elements included in the first interface triggered by the detected first event.

[0126] Refer to Figure 4As shown, the process of the first processor 110 executing this step 401 may include the first processor 110 running the display framework 321 to execute the process of detecting the first event such as the above-mentioned power-on event, which is not limited herein. In the embodiment of the present application, taking the watch 10 as an example, the display framework 321 run by the first processor 110 may be the dial framework run by a chip such as an AP. Correspondingly, the first interface triggered by the above-mentioned first event may be the dial interface. In some other embodiments, if the above-mentioned dual-chip device is other devices, such as a smart bracelet, etc., the display framework 321 run by the first processor 110 may also be other frameworks run by other chips or processors, which is not limited herein.

[0127] 403: The first processor 110 negotiates with the second processor 120 to determine the first part of the interface elements to be processed by the first processor and the second part of the interface elements to be processed by the second processor.

[0128] Exemplarily, the interface elements of the above-mentioned first interface may include some interface elements drawn and rendered by the first processor 110, that is, the above-mentioned first part of the interface elements. For example, the relatively complex animations, gifs, etc. that need to be drawn and rendered by a main processor with high computing power such as an AP. The interface elements of the above-mentioned first interface may also include some or all of the interface elements drawn and rendered by the second processor 120, that is, the above-mentioned second part of the interface elements. For example, the simple time, date, pointers, etc. that can be drawn and rendered by a coprocessor with low power consumption such as an MCU. In some embodiments, the above-mentioned first interface may only include the above-mentioned second part of the interface elements, which is not limited herein.

[0129] Reference Figure 4 As shown, the process of the first processor 110 executing this step 403 may include negotiation and decision-making between the display framework 321 run by the first processor 110 and the display framework 321b run by the second processor to determine the first part of the interface elements to be processed by the first processor and the second part of the interface elements to be processed by the second processor, etc., which will not be elaborated herein.

[0130] It can be understood that in some other embodiments, the above-mentioned first processor 110 may also be a coprocessor with low power consumption such as an MCU, and the corresponding second processor 120 may also be a main processor with high computing power such as an AP, which is not limited herein. In some embodiments, electronic devices such as the watch 10 may also draw and render the above-mentioned second part of the interface elements through the above-mentioned first processor 110, and draw and render the above-mentioned first part of the interface elements through the above-mentioned second processor 120, etc., which is not limited herein.

[0131] In some other embodiments, after the first processor 110 finishes executing the above step 403, it may also allocate a first processing task regarding the second part of the interface elements to the second processor 120 based on the decision result and send relevant processing instructions, etc. Among them, the first processor 110 may act as the main processor to allocate processor tasks to another processor. For example, after the first processor 110 determines the second part of the interface elements that can be drawn and rendered by the second processor 120 in the above step 403, it may allocate a processing task regarding the second part of the interface elements to the second processor 120, such as the first processing task described below. The first processing task may, for example, include the tasks of executing the drawing process and the rendering process described in step 404 below. For specific details, reference may be made to the relevant description in step 404 below, and no further elaboration will be provided here.

[0132] In some embodiments, after the first processor 110 allocates the above first processing task regarding the second part of the interface elements to the second processor 120, it may also send corresponding processing instructions to the second processor 120 to instruct the second processor 120 to execute the first processing task regarding the second part of the interface elements, that is, to instruct the second processor 120 to continue executing the following step 405.

[0133] 404: The first processor 110 executes the first processing task on the first part of the interface elements.

[0134] Exemplarily, the first processing task may include executing the above Figure 1c shown drawing process and rendering process tasks, which may also be referred to as drawing tasks and rendering tasks. The first processor 110, such as an AP, etc., may draw and render the first part of the interface elements allocated to the first processor 110 for processing by the decision. In some other embodiments, the above first processing task may also only include executing the above Figure 1c shown drawing process and rendering process tasks, and may also include other relevant processing tasks that need to be processed before the display process, which are not limited here.

[0135] 405: The second processor 120 executes the first processing task on the second part of the interface elements.

[0136] Exemplarily, the second processor 120 may execute the first processing task on the second part of the interface elements based on the negotiation decision result with the first processor 110 in the above step 403, such as drawing and rendering the second part of the interface elements. In some other embodiments, the second processor 120 may also execute the first processing task on the second part of the interface elements in response to the relevant processing instructions sent by the first processor 110, which are not limited here. As described above, the above first processing task may include executing the above Figure 1cTasks of the drawing process and the rendering process shown. In the second system 300b run by the second processor 120, the display framework 321b can perform a first processing task on the second part of the interface elements, such as drawing and rendering the second part of the interface elements.

[0137] It can be understood that this step 405 can be executed simultaneously with the above step 404, or can be executed successively, including the above step 404 being executed before this step 405 and this step 405 being executed before the above step 404, which is not limited here.

[0138] 406: The second processor 120 writes the processed second part of the interface elements into the first graphics cache registered to the first processor.

[0139] Exemplarily, in the boot-up scenario, dual-core devices such as the watch 10 can default to the first processor 110 to continue synthesizing the relevant interface based on the rendered interface elements and sending it for display. Thus, in this scenario, after the second processor 120 draws and renders the second part of the interface elements, it can cache the rendered second part of the interface elements in the shared cache. As described above, the shared cache can be a shared cache space registered to the first processor 110, that is, providing read permission to the first processor 110, which is called the first graphics cache in this application.

[0140] It can be understood that in some other embodiments, the boot-up scenario of dual-core devices such as the watch 10 can also be that the second processor 120 continues to synthesize the relevant interface based on the rendered interface elements and sends it for display. Correspondingly, the first processor 110 can also write the rendered first part of the interface elements into the second graphics cache registered to the second processor 120, that is, the second graphics cache to which the second processor 120 has read permission. This is not limited here.

[0141] 407: The first processor 110 reads the processed second part of the interface elements from the first graphics cache.

[0142] Exemplarily, the first processor 110, such as an AP, etc., can read the processed second part of the interface elements from the first graphics cache based on the read permission for the first graphics cache. The processed second part of the interface elements can be, for example, the rendered second part of the interface elements in this application.

[0143] It can be understood that the first graphics cache registered to the first processor 110 can only be read by the first processor 110, that is, the first processor 110 is the read end, and data can be written by a specified write end, for example, the processed second part of the interface elements can be written by the second processor 120. In this way, it can prevent other processors or frameworks running on other processors from tampering with the data related to the interface elements in the first graphics cache, ensure that the interface elements written into the first graphics cache can be combined with other relevant interface elements to form a relevant interface, and also enable electronic devices such as the watch 10 to stably and consistently display the relevant interface. In the embodiments of the present application, the relevant interface, such as the first interface above, can be a dial interface or the like.

[0144] As an example, the implementation principle of a shared cache supporting writing or reading by two or more processors will be introduced below with reference to the accompanying drawings.

[0145] Figure 5 According to the embodiments of the present application, a schematic diagram of the implementation principle of the writing and reading process of a shared cache is shown. Among them, the shared cache can be the first graphics cache registered to the first processor 110 above, or the second graphics cache registered to the second processor 120 in the following text, or the shared cache space registered to other processors in some other embodiments, which is not limited here.

[0146] As Figure 5 shown, the working states of the shared cache (framebuffer) can include an invalid state, a writing state, a reading state, and a ready state. Among them:

[0147] 1) The invalid state: refers to the state where the shared cache neither accepts the reading operation of the read end nor accepts the writing operation of the write end. For example, when the read end does not need to participate in the interface composition task, the write end can modify the storage state of the shared cache to the invalid state.

[0148] 2) The writing state: refers to the state where the shared cache accepts the writing operation of the write end. For example, before the write end writes data related to the interface elements into the shared cache, it can modify the storage state of the shared cache to the writing state. It can be understood that before being modified to the writing state, the state of the shared cache can be the above-mentioned invalid state or ready state. Taking the second processor 120 as the write end as an example, the second processor 120 can modify the storage state of the first graphics cache from the invalid state or ready state to the writing state before writing the rendered second part of the interface elements into the first graphics cache.

[0149] 3) reading state: It refers to the state in which the shared cache accepts the read operation of the read end. For example, before the read end writes the data related to the interface element into the shared cache, it can modify the storage state of the shared cache to the reading state. It can be understood that before being modified to the reading state, the state of the shared cache can be the above-mentioned invalid state or ready state. Taking the second processor 120 as the read end as an example, the second processor 120 can modify the storage state of the first graphics cache from the invalid state or ready state to the reading state before writing the rendered second part of the interface elements into the first graphics cache. The read end modifies the state to the reading state before reading the picture in the buffer.

[0150] 4) ready state: It refers to the ready state before the shared cache is switched to the reading state or writing state. After the write end completes the operation of writing data into the shared cache or the read end completes the operation of reading data from the shared cache, the storage state of the shared cache can be modified to the ready state, which indicates that the shared cache can be switched to the reading state or writing state at this time. For example, after the write end writes the rendered interface elements into the shared cache, it can modify the storage state of the shared cache from the writing state to the ready state. At this time, after the read end completes reading the data related to the interface elements in the shared cache, it can modify the storage state of the shared cache from the reading state to the ready state.

[0151] In the embodiment of the present application, the shared cache registered to the first processor 110, that is, the first graphics cache above, can be marked as "framebuffer1" for example. The first graphics cache can be registered to the first processor 110, such as the AP of the watch 10 or the graphics synthesizer called or run on the AP side. Continuing with the example of the watch 10, when the second processing task including the synthesis process and the display process is continued to be executed on the AP side, the MCU can cache the data related to the rendered interface elements into the above "framebuffer1" after drawing and rendering the interface elements of the first interface such as the watch face interface. At this time, the graphics synthesizer on the AP side can read the interface elements rendered by the MCU from "framebuffer1" to complete the synthesis process and the display process of the interface elements drawn and rendered by the AP and the interface elements drawn and rendered by the MCU.

[0152] In the embodiment of the present application, the shared cache registered to the second processor 120, that is, the above-mentioned first graphics cache can be marked as "framebuffer2" for example. The first graphics cache can be registered to the second processor 120, such as the AP of the watch 10 or the graphics synthesizer called or run on the MCU side. Continuing with the example of the watch 10, when the second processing task including the synthesis process and the display process is continued to be executed on the MCU side, after the AP draws and renders the interface elements of the first interface such as the dial interface, the data related to the rendered interface elements can be cached in the above-mentioned "framebuffer2". At this time, the graphics synthesizer on the MCU side can read the interface elements rendered by the AP from "framebuffer2" to complete the synthesis process and the display process of the interface elements drawn and rendered by the AP and the interface elements drawn and rendered by the MCU.

[0153] It can be understood that the above-mentioned read-write synchronization mechanism of the shared cache (framebuffer) can include: allocating two state variables in the shared memory to mark the read-write states of two or more framebuffers. When the first processor and the second processor perform read operations or write operations on each framebuffer respectively, they can first obtain the value of the state variable corresponding to the framebuffer and judge whether the current storage state of the framebuffer meets the read-write conditions.

[0154] Continuing with the example of the AP and the MCU, for example, before the MCU writes the data related to the rendered interface elements to the above-mentioned "framebuffer1", it can first obtain the value of the state variable of the "framebuffer1" and judge the current storage state of the "framebuffer1" based on this value. For example, if the value of the state variable of the "framebuffer1" is "writing = 1", it indicates that the current storage state of the "framebuffer1" is the writing state. At this time, the MCU can write data to the "framebuffer1". Another example is that if the value of the state variable of the "framebuffer1" is "ready = 1", it indicates that the current storage state of the "framebuffer1" is the ready state. At this time, the MCU can modify the value of the state variable of the "framebuffer1" to "writing = 1" and then write data to the "framebuffer1". After the AP or the MCU completes the read-write operation, it can notify the other party through an electrical signal, which will not be elaborated here.

[0155] 408: The first processor 110 executes a second processing task on the first part of the interface elements and the second part of the interface elements.

[0156] Exemplarily, the second processing task may include: Figure 1c The process of synthesizing the interface and the task of the display process shown can also be referred to as synthesis and display tasks. Taking watch 10 as an example, the first processor 110, such as AP, can synthesize the above-mentioned rendered first part of the interface elements and the rendered second part of the interface elements during the startup process of watch 10, and display the synthesized first interface, so that watch 10 displays the first interface. It can be understood that the drawing and rendering process of the above-mentioned first part of the interface elements can be completed during the execution of the above-mentioned step 404, and the drawing and rendering process of the above-mentioned second part of the interface elements can be completed during the execution of the above-mentioned step 405. Please refer to the description in the above-mentioned related steps for details, which will not be repeated here.

[0157] It can be understood that after the first processor 110 executes the above-mentioned second processing task, for example, after completing the synthesis of the first part of the interface elements and the second part of the interface elements and sending the synthesized first interface for display, electronic devices such as watch 10 can display the first interface, and the display method implementation process executed by watch 10 can be ended.

[0158] It can be understood that based on the display method provided in the embodiment of the present application, dual-core electronic devices such as watch 10 can assign the interfaces to be displayed to different processing chips for drawing and rendering, and the principle of allocation includes giving priority to assigning simple interface elements to low-power processors for drawing and rendering, and assigning more complex interface elements to processors with high computing power for drawing and rendering. Furthermore, based on the read-write synchronization mechanism of the shared cache, watch 10 can continue the process of synthesizing the interface and sending the synthesized interface for display on one of the processors. For example, watch 10 can hand over most of the simple interface elements included in the dial interface to the MCU for drawing and rendering, and hand over some of the more complex interface elements included in the dial interface to the AP for drawing and rendering, and then the AP of watch 10 can continue to synthesize the rendered interface elements of the two into a dial interface, and display it on the touch screen 101 of watch 10.

[0159] The following first introduces the detailed process of implementing the display method provided by the present application in an interface switching scenario on a dual-core device such as a watch 10 in conjunction with Example 2.

[0160] Example 2

[0161] Figure 6 According to an embodiment of the present application, a schematic diagram of an implementation flow of a display method in an interface switching scenario is shown.

[0162] like Figure 6 As shown, the implementation process involves the interaction between two processors of a dual-core device such as a watch 10, for example, the interaction between the first processor 110 and the second processor 120. In other embodiments,Figure 6 The process shown may also involve interactions between more than two processors, which is not limited herein.

[0163] As Figure 6 shown, the implementation process may include the following steps:

[0164] 601: The display framework 321a running on the first processor 110 detects a second event.

[0165] Exemplarily, the above-mentioned second event may include an interface switching event, including switching from the current interface to a second interface triggered by the second event for display. Taking the dial interface as an example, the above-mentioned interface switching event may include an event triggered by the user operating on the touch screen 101 of the watch 10 to return from the setting interface or other function interfaces to the dial interface or the desktop, etc., or may also include an event such as the dial interface after the style is changed triggered by the user operating on the touch screen 101 of the watch 10 to change the dial style. This is not limited herein. In the first system 300a run by the first processor 110, SystemUI may respond to the user operation and call the display framework 321a to detect the above-mentioned interface switching event or other second events.

[0166] In the embodiments of the present application, the main processor of an electronic device such as the watch 10, for example, the above-mentioned first processor 110, may be an AP, and the second processor 120 may be an MCU. In some other embodiments, the first processor 110 may also be an MCU, and the second processor 120 may be an AP, which is not limited herein.

[0167] 602: The display framework 321a running on the first processor 110 obtains the interface elements included in the second interface triggered by the second event for display.

[0168] Exemplarily, the second interface may be the same as the first interface in the above-mentioned Embodiment 1, or may be different from the first interface in the above-mentioned Embodiment 1, which is not limited herein. In the first system 300a run by the first processor 110, the display framework 321a may obtain the interface elements included in the second interface triggered by the above-mentioned second event based on the detected second event.

[0169] In the embodiments of the present application, taking the watch 10 as an example, the display framework 321 run by the first processor 110 may be a dial framework run by a chip such as an AP, and correspondingly, the first interface triggered by the above-mentioned second event for display may be a dial interface. In some other embodiments, if the above-mentioned dual-chip device is other devices, such as a smart bracelet, etc., the display framework 321 run by the first processor 110 may also be other frameworks run by other chips or processors, which is not limited herein.

[0170] 603: The display framework 321a run by the first processor 110 negotiates with the display framework 321b run by the second processor 120 to determine the first part of interface elements processed by the first processor and the second part of interface elements processed by the second processor.

[0171] Exemplarily, the interface elements of the second interface may include interface elements partially drawn and rendered by the first processor 110, and may also include interface elements partially or entirely drawn and rendered by the second processor 120. In the embodiments of the present application, the interface elements of the second interface drawn and rendered by the first processor 110 may also be referred to as the first part of interface elements, and the interface elements of the second interface drawn and rendered by the second processor 120 may also be referred to as the second part of interface elements. Among them, the first part of interface elements and the second part of interface elements are only used for the differential description of the interface elements processed by different processors included in the second interface, and the present application does not limit the specific types, styles, etc. of the interface elements included in the first part of interface elements and the second part of interface elements.

[0172] It can be understood that if the second interface is the same as the first interface, the first part of interface elements and the second part of interface elements included in the interface elements of the second interface may be the same as the first part of interface elements and the second part of interface elements included in the interface elements of the first interface, respectively. If the second interface is different from the first interface, the first part of interface elements and the second part of interface elements included in the interface elements of the second interface may be different from the first part of interface elements and the second part of interface elements included in the interface elements of the first interface, respectively, and no limitation is made here. The first part of interface elements may include, for example, relatively complex animations, moving pictures and other interface elements drawn and rendered by a main processor with high computing power such as the above-mentioned AP. The second part of interface elements may include, for example, simple time, date, pointer and other interface elements drawn and rendered by a coprocessor with low power consumption such as the MCU. In some embodiments, the second interface may also only include the second part of interface elements, and no limitation is made here.

[0173] Specifically, the detailed implementation process of the first processor 110 and the second processor 120 determining the first part of interface elements and the second part of interface elements based on the negotiation result may refer to the relevant description in step 403 of the above-mentioned embodiment 1, and will not be elaborated here.

[0174] 604: The display framework 321a run by the first processor 110 performs a first processing task on the first part of interface elements.

[0175] Exemplarily, the first processing task may include performing the above Figure 1cThe tasks of the drawing process and the rendering process shown can also be referred to as the drawing task and the rendering task. For the specific execution process, reference can be made to the relevant description in step 404 of the above-mentioned embodiment 1, which will not be elaborated here.

[0176] 605: The display framework 321b running on the second processor 120 performs a first processing task on the second part of the interface elements.

[0177] Specifically, for the process in which the second processor 120 performs the first processing task through the running display framework 321b, reference can be made to the relevant description in step 404 of the above-mentioned embodiment 1, which will not be elaborated here.

[0178] It can be understood that this step 605 can be executed simultaneously with the above step 604, or can be executed successively, including the case where the above step 604 is executed before this step 605 and the case where this step 605 is executed before the above step 604, which is not limited here.

[0179] 606: The scheduling module 331a running on the first processor 110 obtains the current task load and / or resource overhead of the first processor.

[0180] Exemplarily, the scheduling module 331a running on the first processor 110 and the scheduling module 331b running on the second processor 120 can negotiate and determine the executor for continuing to process the first part of the rendered interface elements and the second part of the rendered interface elements based on the current processing task load amount (abbreviated as task load) of each processor that has been executed, and / or the resource overheads such as memory and computing power consumed by the current processing tasks of each processor.

[0181] In some embodiments, a corresponding load amount threshold can be preset in the first system 300a running on the first processor 110 for the task load. The load amount of the processing tasks currently executed by the first processor 110 obtained by the scheduling module 331a when executing this step 606 can be recorded as the first load amount. This task load amount or the first load amount can be, for example, the number of tasks currently processed by the first processor 110, etc., which is not limited here.

[0182] When the scheduling module 331a detects that the first load amount obtained in this step 606 is lower than the load amount threshold, or meets other load size judgment conditions that can determine that the first processor 110 is currently suitable for processing the following second processing task, the following step 609 can be executed to determine that the first processor executes the second processing task. Conversely, when the scheduling module 331a detects that the first load amount obtained in this step 606 is higher than the load amount threshold, or meets other load size judgment conditions that can determine that the first processor 110 is currently not suitable for processing the following second processing task, the second processor 120 can be triggered to execute the following step 610 to determine that the second processor executes the second processing task.

[0183] Similarly, in some embodiments, in the first system 300a run by the first processor 110, a corresponding resource occupancy threshold may be preset for resource overhead. The processing resource overhead currently executed by the first processor 110 obtained by the scheduling module 331a in performing this step 606 may be recorded as the first resource occupancy. The resource overhead or the first resource occupancy may include the amount of system memory resources and / or computing power resources currently occupied by the first processor 110, etc.

[0184] When the scheduling module 331a detects that the first resource occupancy obtained in this step 606 is lower than the resource occupancy threshold, or meets other load size judgment conditions that can determine that the first processor 110 is currently suitable for processing the following second processing task, the following step 609 may be executed to determine that the second processing task is executed by the first processor. On the contrary, when the scheduling module 331a detects that the first resource occupancy obtained in this step 606 is higher than the resource occupancy threshold, or meets other load size judgment conditions that can determine that the first processor 110 is currently not suitable for processing the following second processing task, the second processor 120 may be triggered to execute the following step 610 to determine that the second processing task is executed by the second processor.

[0185] It can be understood that a processor with a higher task load will correspondingly consume a larger resource overhead. In some embodiments, the above-mentioned judgment conditions such as the threshold corresponding to the task load and / or resource overhead may be applied alone or jointly, and are not limited herein.

[0186] 607: The scheduling module 331b running on the second processor 120 obtains the current task load and / or resource overhead of the second processor.

[0187] Exemplarily, in the second system 300b run by the second processor 120, a corresponding load amount threshold may be preset for the task load. The processing task load amount currently executed by the second processor 120 obtained by the scheduling module 331b in performing this step 607 may be recorded as the second load amount. The task load amount or the second load amount may be, for example, the number of tasks currently processed by the second processor 120, etc., and is not limited herein.

[0188] When the scheduling module 331b detects that the second load amount obtained in this step 607 is lower than the load amount threshold, or meets other load size judgment conditions that can determine that the second processor 120 is currently suitable for processing the following second processing task, the following step 610 can be executed to determine that the second processor executes the second processing task. Conversely, when the scheduling module 331b detects that the second load amount obtained in this step 607 is higher than the load amount threshold, or meets other load size judgment conditions that can determine that the second processor 120 is currently not suitable for processing the following second processing task, the first processor 110 can be triggered to execute the following step 609 to determine that the first processor executes the second processing task.

[0189] Similarly, in some embodiments, a corresponding resource occupancy threshold can be preset for the resource overhead in the second system 300b run by the second processor 120, and the processing resource overhead currently executed by the second processor 120 obtained by the scheduling module 331b in executing this step 607 can be recorded as the second resource occupancy. The resource overhead or the second resource occupancy can include the current occupancy of the system memory resources and / or computing power resources by the second processor 110, etc.

[0190] When the scheduling module 331b detects that the second resource occupancy obtained in this step 607 is lower than the resource occupancy threshold, or meets other load size judgment conditions that can determine that the second processor 120 is currently suitable for processing the following second processing task, the following step 610 can be executed to determine that the second processor executes the second processing task. Conversely, when the scheduling module 331b detects that the second resource occupancy obtained in this step 607 is higher than the resource occupancy threshold, or meets other load size judgment conditions that can determine that the second processor 120 is currently not suitable for processing the following second processing task, the first processor 110 can be triggered to execute the following step 609 to determine that the first processor executes the second processing task.

[0191] 608: The scheduling module 331a running on the first processor 110 and the scheduling module 331b running on the second processor 120 negotiate to determine the executor of the second processing task.

[0192] 609: The scheduling module 331a running on the first processor 110 determines that the first processor executes the second processing task.

[0193] Exemplarily, the scheduling module 331a running on the first processor 110 can determine that the first processor executes the second processing task based on the negotiation result executed in the above step 608. As mentioned above, the above second processing task can, for example, include the process of synthesizing the interface and the task of the display sending process shown above, and can also be called the synthesis and display sending task. Figure 1c shown synthesis interface process and the task of the display sending process, and can also be called the synthesis and display sending task.

[0194] 609a: The scheduling module 331a running on the first processor 110 sends a task execution instruction to the display framework 321a.

[0195] Exemplarily, in the first system 300a running on the first processor 110, the scheduling module 331a sends a task execution instruction to the display framework 321a. This task execution instruction may instruct the display framework 321a to execute a second processing task, such as the above-mentioned composition and display task.

[0196] 609b: The display framework 321b running on the second processor 120 writes the processed second part of the interface elements to the first graphics cache registered to the first processor.

[0197] Exemplarily, based on the decision result fed back by the scheduling module 331b, the display framework 321b running on the second processor 120 may write the second part of the interface elements processed by the second processor 120 when executing the above-mentioned first processing task to the first graphics cache registered to the first processor 110.

[0198] It is worth noting here that after the scheduling module 331a running on the first processor 110 determines that the second processing task is to be executed by the first processor, in order to save storage resources, it may temporarily not cache the first part of the interface elements drawn and rendered by the first processor 110 to the shared cache (such as the first graphics cache). In subsequent implementation processes, the first processor 110 may continue the second processing task for the first part of the interface elements drawn and rendered by the first processor 110 and the processed second part of the interface elements obtained by reading from the first graphics cache, including performing subsequent steps 609c to 609d.

[0199] 609c: The display framework 321a running on the first processor 110 reads the processed second part of the interface elements from the first graphics cache.

[0200] For the specific process of the first processor 110 reading the processed second part of the interface elements from the first graphics cache based on the display framework 321a, reference can be made to the relevant description in step 407 in the above-mentioned embodiment 1, and details are not described here.

[0201] 609d: The display framework 321a running on the first processor 110 performs a second processing task on the first part of the interface elements and the second part of the interface.

[0202] For the specific process of the first processor 110 performing a second processing task on the first part of the interface elements and the second part of the interface based on the display framework 321a, reference can be made to the relevant description in step 408 in the above-mentioned embodiment 1, and details are not described here.

[0203] 610: The scheduling module 331b running on the second processor 120 determines that the second processing task is to be executed by the second processor.

[0204] 610a: The scheduling module 331b running on the second processor 120 sends a task execution instruction to the display framework 321b.

[0205] 610b: The display framework 321a running on the first processor 110 writes the processed first part of the interface elements to the second graphics cache registered to the second processor.

[0206] Exemplarily, in the first system 300a running on the first processor 110, the display framework 321a may, based on the decision result fed back by the scheduling module 331a, write the first part of the interface elements processed by the first processor 110 when executing the above first processing task to the second graphics cache registered to the second processor 120.

[0207] It should be noted here that after the scheduling module 331b running on the second processor determines that the second processing task is to be executed by the second processor, in order to save storage resources, the second part of the interface elements drawn and rendered by the second processor 120 may not be cached to the shared cache (such as the second graphics cache) temporarily. In the subsequent implementation process, the second processor 120 may continue the second processing task on the second part of the interface elements drawn and rendered by the second processor 120 and the processed first part of the interface elements read from the second graphics cache, including executing the subsequent steps 610c to 610d.

[0208] 610c: The display framework 321b running on the second processor 120 reads the processed first part of the interface elements from the second graphics cache.

[0209] For the specific process in which the second processor 120 reads the second part of the processed interface elements in the first graphics cache based on the display framework 321b, reference can be made to the relevant description in step 407 in the above-mentioned embodiment 1, and details will not be elaborated here.

[0210] 610d: The display framework 321b running on the second processor 120 performs the second processing task on the first part of the interface elements and the second part of the interface.

[0211] For the specific process in which the second processor 120 performs the second processing task on the first part of the interface elements and the second part of the interface based on the display framework 321b, reference can be made to the relevant description in step 408 in the above-mentioned embodiment 1, and details will not be elaborated here.

[0212] Taking the watch 10 as an example, the first processor 110, such as the AP, can synthesize the rendered first part of the interface elements and the rendered second part of the interface elements during the booting process of the watch 10, and send the synthesized first interface to display, so that the watch 10 displays the first interface. It can be understood that the drawing and rendering process of the first part of the interface elements can be completed during the execution of the above step 604, and the drawing and rendering process of the second part of the interface elements can be completed during the execution of the above step 605. For details, please refer to the description in the above related steps, which will not be repeated here.

[0213] It can be understood that the above steps 609 to 609d executed by the relevant structure in the first system 300a run by the above first processor 110 and the above steps 610 to 610d executed by the relevant structure in the second system 300b run by the above second processor 120 can be selective processes corresponding to the two processors processing the above second processing tasks respectively. That is, in some embodiments, the implementation process of the display method provided by the present application may only include the implementation process of the above steps 609 to 609d, but not the implementation process of the above steps 610 to 610d; or only include the implementation process of the above steps 610 to 610d, but not the implementation process of the above steps 609 to 609d.

[0214] It can be understood that after the first processor 110 completes the above-mentioned second processing task or the second processor 120 completes the above-mentioned second processing task, for example, after completing the synthesis of the first part of the interface elements and the second part of the interface elements and completing the display of the synthesized second interface, electronic devices such as watch 10 can display the above-mentioned second interface, and the implementation process of the display method executed by watch 10 can be ended.

[0215] It can be understood that, based on the display method provided in the embodiments of the present application, dual-core electronic devices such as the watch 10 can allocate the interfaces to be displayed to different processing chips for drawing and rendering respectively. The allocation principle includes preferentially allocating simple interface elements to the processor with low power consumption for drawing and rendering, and allocating more complex interface elements to the processor with high computing power for drawing and rendering. Furthermore, based on the read-write synchronization mechanism of the shared cache, the watch 10 can continue to perform the process of synthesizing the interface and sending the synthesized interface for display on one of the processors. In the embodiments of the present application, the watch 10 can determine the processor for continuing to execute the interface synthesis and display tasks according to the current task load and / or resource overhead of each processor. For example, the watch 10 can hand over the simple interface elements included in most of the dial interfaces to the MCU for drawing and rendering, and hand over the more complex interface elements included in some dial interfaces to the AP for drawing and rendering. Then, the watch 10 can use the AP or MCU with a smaller current task load or smaller resource overhead to continue to synthesize the interface elements rendered by the two into a dial interface and display it on the touch screen 101 of the watch 10.

[0216] It can be understood that for the above-mentioned dial interface or other interfaces to be displayed, dual-core devices such as the watch 10 can, based on the display method provided in the present application, fixedly allocate the first part of the interface elements on each interface to the first processor 110 for drawing and rendering at any time, and fixedly allocate the second part of the interface elements to the second processor 120 for drawing and rendering. In this way, the dial interface or other related interfaces displayed by dual-core devices such as the watch 10 at any time can ensure the consistency of the drawing, rendering effects and synthesis effects, which is beneficial to improving the user experience.

[0217] Figure 7 According to the embodiments of the present application, a schematic diagram of the implementation process of another display method is shown.

[0218] Different from the implementation processes of the display methods provided in the above-mentioned Embodiment 1 and Embodiment 2 of the present application, Figure 7 The execution subject of the shown process can be an electronic device such as the watch 10. To avoid repetition, the execution subject of each step will not be repeatedly described below when introducing each step.

[0219] As Figure 7 shown, the implementation process may include the following steps:

[0220] 701: Detect the first event or the second event.

[0221] The specific process of an electronic device such as the watch 10 executing this step can refer to the relevant descriptions in step 401 of the above-mentioned Embodiment 1 or step 601 of the above-mentioned Embodiment 2, and will not be elaborated here.

[0222] 702: Obtain the interface elements included in the interface triggered by the first event or the second event.

[0223] For the specific process of an electronic device such as the watch 10 to execute this step, reference can be made to the relevant descriptions in step 402 of the above-mentioned embodiment 1 or step 602 of the above-mentioned embodiment 2, and details will not be elaborated here.

[0224] 703: Determine the first part of the interface elements processed by the first processor and the second part of the interface elements processed by the second processor.

[0225] For the specific process of an electronic device such as the watch 10 to execute this step, reference can be made to the relevant descriptions in step 403 of the above-mentioned embodiment 1 or step 603 of the above-mentioned embodiment 2, and details will not be elaborated here.

[0226] 704: Execute the first processing task on the first part of the interface elements and the second part of the interface elements respectively.

[0227] Exemplarily, an electronic device such as the watch 10 can use the first processor to process the first processing task corresponding to the first part of the interface elements, and can use the second processor to process the first processing task corresponding to the second part of the interface elements.

[0228] For the specific process of an electronic device such as the watch 10 to execute this step, reference can be made to the relevant descriptions in steps 404 and 405 of the above-mentioned embodiment 1 or steps 604 and 605 of the above-mentioned embodiment 2, and details will not be elaborated here.

[0229] 705: Determine whether the first processor or the second processor executes the second processing task according to the first parameter of the first processor and the second parameter of the second processor.

[0230] Exemplarily, the above-mentioned first parameter may include the current task load of the first processor, such as the first load in the above-mentioned embodiment 2, and the resource consumption corresponding to the first processor executing the processing task, such as the first resource occupancy in the above-mentioned embodiment 2. Correspondingly, the above-mentioned second parameter may include the current task load of the second processor, such as the second load in the above-mentioned embodiment 2, and the resource consumption corresponding to the second processor executing the processing task, such as the second resource occupancy in the above-mentioned embodiment 2.

[0231] For the specific process of an electronic device such as the watch 10 to execute this step, reference can be made to the relevant descriptions in steps 606 to 610 of the above-mentioned embodiment 2, and details will not be elaborated here.

[0232] 706: Based on the execution result of the second processing task, display the relevant interface.

[0233] Exemplarily, an electronic device such as the watch 10 can display a relevant interface based on the results of the second processing task executed by the first processor or the second processor. For example, the relevant interface includes the results of combining the rendered first part of the interface elements and the rendered second part of the interface elements as described above, and sending the combined relevant interface for display. Among them, for the results of the second processing task executed by the first processor, reference can be made to the relevant descriptions in steps 609a to 609d in Embodiment 2 above, which will not be elaborated here. For the results of the second processing task executed by the second processor, reference can be made to the relevant descriptions in steps 610a to 610d in Embodiment 2 above, which will not be elaborated here.

[0234] The embodiments of the present application also provide a computer program product for implementing the display methods provided in the above embodiments.

[0235] The embodiments of the mechanism disclosed in the present application can be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present application can be implemented as computer program modules or module codes executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0236] The computer program modules or module codes can be applied to input instructions to execute the various functions described in the present application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of the present application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0237] The module codes can be implemented in a high-level modular language or an object-oriented programming language to communicate with the processing system. When needed, the module codes can also be implemented in assembly language or machine language. In fact, the mechanism described in the present application is not limited to the scope of any specific programming language. In any case, the language can be a compiled language or an interpreted language.

[0238] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more transient or non-transient machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or via other computer-readable media. Thus, machine-readable media may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to, floppy disks, optical disks, optical discs, magneto-optical discs, read only memory (ROM), random access memory (RAM), erasable programmable read only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or tangible machine-readable memories for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) in electrical, optical, acoustic, or other forms via the Internet. Thus, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0239] References in the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one exemplary implementation or technique disclosed in embodiments of the present application. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0240] The disclosure of embodiments of the present application also relates to an apparatus for performing the operations in the text. The apparatus may be specifically constructed for the required purposes or it may include a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, magneto-optical disks, read only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, application specific integrated circuit (ASIC), or any type of medium suitable for storing electronic instructions, and each may be coupled to a computer system bus. In addition, the computers mentioned in the specification may include a single processor or may be an architecture involving multiple processors for increased computing power.

[0241] Additionally, the language used in this specification has been principally selected for readability and instructional purposes and may not have been selected to delineate or circumscribe the disclosed subject matter. Accordingly, the disclosure of embodiments of this application is intended to be illustrative rather than to limit the scope of the concepts discussed herein.

Claims

1. A display method, applied to an electronic device, the electronic device comprising a first processor and a second processor, characterized in that, Including: The electronic device detects a display instruction for a first interface and determines the interface elements of the first interface, where the interface elements of the first interface include first partial interface elements and second partial interface elements; The first processor draws and renders the first partial interface elements, and the second processor draws and renders the second partial interface elements; The first processor or the second processor synthesizes the rendered first partial interface elements and the rendered second partial interface elements; The electronic device displays the first interface.

2. The method according to claim 1, characterized in that, The electronic device detecting a display instruction for a first interface includes: The electronic device detects that the first processor powers on and works; or, The electronic device detects a user operation indicating to display the first interface.

3. The method according to claim 2, wherein The electronic device determining the interface elements of the first interface includes: The first processor determines the interface elements of the first interface; and, The second processor drawing and rendering the second partial interface elements includes: The first processor sends a first instruction to the second processor; The second processor draws and renders the second partial interface elements in response to the first instruction.

4. The method according to claim 3, wherein The first processor or the second processor synthesizing the rendered first partial interface elements and the rendered second partial interface elements includes: The first processor reads the rendered second partial interface elements stored in a first graphics cache, where the first processor has the read permission for the first graphics cache, and the second processor has the write permission for the first graphics cache; The first processor synthesizes the rendered first partial interface elements and the rendered second partial interface elements.

5. The method according to claim 4, characterized in that The method further includes: After the second processor draws and renders the second partial interface elements, the second processor writes the rendered second partial interface elements into the first graphics cache.

6. The method according to claim 3, characterized in that, The first processor or the second processor synthesizing the rendered first partial interface elements and the rendered second partial interface elements includes: The electronic device obtains a first parameter of the first processor and a second parameter of the second processor; The electronic device determines, based on the first parameter and the second parameter, to synthesize the rendered first partial interface elements and the rendered second partial interface elements by the first processor, or to synthesize the rendered first partial interface elements and the rendered second partial interface elements by the second processor.

7. The method according to claim 6, characterized in that, The first parameter includes a first load and / or a first resource occupancy, and the second parameter includes a second load and / or a second resource occupancy, where The first load includes the number of tasks currently processed by the first processor, and the first resource occupancy includes the current occupancy of the first processor on system memory resources and / or computing power resources; The second load includes the number of tasks currently processed by the second processor, and the second resource occupancy includes the current occupancy of the second processor on system memory resources and / or computing power resources.

8. The method according to any one of claims 1 to 7, characterized in that, The first interface includes a dial interface.

9. The method according to any one of claims 1 to 7, characterized in that The first processor includes an application processor (AP), and the second processor includes a micro control unit (MCU); or, The first processor includes an application processor (AP), and the second processor includes a micro control unit (MCU).

10. The method according to any one of claims 5 to 8, characterized in that, The electronic device further includes a second graphics cache and a third cache, where The first processor has read and write permissions for the second graphics cache; The second processor has read and write permissions for the third cache.

11. The method according to any one of claims 1 to 10, characterized in that, The electronic device is a watch or a bracelet.

12. A display method, characterized in that, Including: The first processor draws and renders the first partial interface elements of the first interface, where the first interface is the interface indicated by the display instruction detected by the electronic device, and the electronic device includes the first processor; The first processor obtains the second partial interface elements of the first interface drawn and rendered by the second processor; The first processor synthesizes the rendered first partial interface elements and the rendered second partial interface elements, and sends the synthesized first interface for display.

13. The method according to claim 12, wherein Before the first processor draws and renders the first partial interface elements of the first interface, the method further includes: The first processor determines that the interface elements of the first interface include the first partial interface elements and the second partial interface elements; and The first processor sends a first instruction to the second processor, where the first instruction is used to instruct the second processor to draw and render the second partial interface elements of the first interface.

14. The method according to claim 12, wherein The first processor obtains the second partial interface elements of the first interface drawn and rendered by the second processor, including: The first processor reads the second partial interface elements of the first interface drawn and rendered by the second processor from the first graphics cache, where the first processor has read permission for the first graphics cache, and the second processor has write permission for the first graphics cache.

15. The method according to any one of claims 12 to 14, characterized in that, The first processor synthesizes the rendered first partial interface elements and the rendered second partial interface elements, including: The first processor obtains a first parameter of the first processor and a second parameter of the second processor; The first processor synthesizes the rendered first partial interface elements and the rendered second partial interface elements according to the first parameter and the second parameter.

16. The method according to claim 15, wherein The first parameter includes a first load and / or a first resource occupancy, and the second parameter includes a second load and / or a second resource occupancy, where The first load includes the number of tasks currently processed by the first processor, and the first resource occupancy includes the current occupancy of the first processor for system memory resources and / or computing power resources; The second load includes the number of tasks currently processed by the second processor, and the second resource occupancy includes the current occupancy of the second processor for system memory resources and / or computing power resources.

17. A chip, characterized in that, For executing the display method according to any one of claims 12 to 16.

18. An electronic device, characterized in that, Including: One or more processors; One or more memories; the one or more memories store one or more programs, which when executed by the one or more processors, cause the electronic device to perform the display method according to any one of claims 1 to 16.

19. A computer-readable medium, characterized in that, Instructions are stored on the readable medium, which when executed on a computer cause the computer to perform the display method according to any one of claims 1 to 16.

20. A computer program product, characterized in that, Comprising a computer program / instructions, which when executed by a processor, are used to implement the display method according to any one of claims 1 to 16.

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