Control unit, data storage device, host device, and computing system

Abstract

The invention relates to a control unit, a data storage device, a host device and a computing system. In an embodiment of the present disclosure, a processing order flag is set in a flit transmitted and received between a host device and a data storage device, and ordered processing or unordered processing is controlled based on the processing order flag. Accordingly, it is possible to provide a measure capable of simply preventing the occurrence of an error due to unordered processing of the flit without reducing the processing efficiency of the transmitted and received flit.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0193799, filed on December 28, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a control unit, a data storage device, a host device, and a computing system. Background Art

[0004] A computing system may include a host device and a locally - located storage device. The host device may use the locally - located storage device to perform processing on data.

[0005] In addition to the locally - located storage device, the host device may also perform data processing by additionally using a remotely - located storage device.

[0006] The host device may perform data processing while communicating with the remotely - located storage device. Since the host device performs data processing while sending commands and data to the remotely - located storage device and receiving commands and data from the remotely - located storage device through a communication device, there may be problems such that the data processing performance may deteriorate or data processing errors may occur. Summary of the Invention

[0007] Various embodiments of the present disclosure are directed to providing a device and a system capable of preventing or reducing errors in data processing while improving the data processing performance of a host device using a data storage device.

[0008] In an embodiment of the present disclosure, a data storage device may include: at least one memory device; a processing device configured to perform calculations related to the at least one memory device or output commands for controlling the at least one memory device; and an interface device configured to receive at least one first flit according to a first sub - protocol and at least one second flit according to a second sub - protocol from a host device, and based on a set value of a processing order flag included in each of the at least one first flit and the at least one second flit, prohibit, during at least a partial period, an operation of providing the at least one first flit and the at least one second flit to the processing device out of order different from the instruction order of the host device. The processing device performs calculations or outputs commands based on one of the at least one first flit and the at least one second flit.

[0009] In an embodiment of the present disclosure, a host device may include: a processor configured to provide data and commands; and an interface device configured to generate a first microchip based on the data according to a first sub - protocol, generate a second microchip based on the command according to a second sub - protocol, and send the first microchip and the second microchip to the outside by setting a processing order flag in each of the first microchip and the second microchip, the processing order flag indicating whether to prohibit out - of - order processing of the first microchip and the second microchip.

[0010] In an embodiment of the present disclosure, a control unit may include: a memory controller configured to control a memory device; an accelerator configured to communicate with the memory controller and perform calculations based on data stored in the memory device; and an interface device configured to receive a plurality of microchips from a host device, a processing order flag being set in each of the plurality of microchips, and based on the setting value of the processing order flag included in each of the plurality of microchips, prohibit, during at least a partial period, an operation of providing the plurality of microchips to the accelerator out of order differently from the instruction order of the host device.

[0011] In an embodiment of the present disclosure, a computing system may include: a host device configured to generate at least one first microchip according to a first sub - protocol and at least one second microchip according to a second sub - protocol, and output the at least one first microchip and the at least one second microchip by setting a processing order flag in each of the at least one first microchip and the at least one second microchip; and a data storage device configured to receive the at least one first microchip and the at least one second microchip from the host device, and based on the processing order flag set in each of the at least one first microchip and the at least one second microchip, prohibit, during at least a partial period, an operation of outputting the at least one first microchip and the at least one second microchip out of order differently from the instruction order of the host device.

[0012] According to an embodiment of the present disclosure, errors in data processing performed by a data storage device according to instructions from a host device can be reduced, and the data processing performance of the data storage device can be maintained. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram showing a schematic configuration of a data storage device based on an embodiment of the present disclosure.

[0014] Figure 2 is a diagram showing a schematic configuration of a computing system based on an embodiment of the present disclosure.

[0015] Figure 3 is a diagram showing a method for generating and sending microchips by an interface device included in a host device based on an embodiment of the present disclosure.

[0016] Figures 4 to 6 FIG. is a diagram showing a method of controlling the order of outputting received microchips by an interface device included in a data storage device according to an embodiment of the present disclosure.

[0017] Figure 7 and Figure 8 FIG. is a diagram showing a method of receiving and processing microchips by an interface device included in a data storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] In the following description of embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and even if the same reference signs and symbols are shown in different drawings, they can be used to represent the same or similar components. Further, in the following description of examples or embodiments of the present disclosure, when it is determined that the description may obscure the subject matter in some embodiments of the present disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted. Unless these terms such as "comprising", "having", "including", "constituting", "composing", "forming" are used together with the term "only", these terms are generally intended to allow the addition of other components. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0019] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, etc., but is only used to distinguish the corresponding element from other elements.

[0020] When referring to a first element being "connected or coupled", "in contact or overlapping" with a second element, etc., it should be interpreted that not only can the first element be "directly connected or coupled" or "directly in contact or overlapping" with the second element, but also a third element can be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled", "in contact or overlapping", etc. with each other through a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled", "in contact or overlapping", etc. with each other.

[0021] When relative time terms such as "after", "subsequent", "next", "before", etc. are used to describe a process or operation of an element or configuration or a flow or step in an operation, process, or manufacturing method, these terms can also be used to describe a non - continuous or non - sequential process or operation unless used together with the terms "directly" or "immediately".

[0022] In addition, when referring to any dimensions, relative sizes, etc., even if no relevant description is specified, the numerical values or corresponding information (e.g., levels, ranges, etc.) of elements or features should be considered to include the tolerance or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). Further, the term "can" fully encompasses all meanings of the term "able to".

[0023] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a diagram showing a schematic configuration of a data storage device 100 based on an embodiment of the present disclosure.

[0025] Referring to Figure 1 , a data storage device 100 based on an embodiment of the present disclosure may include, for example, a first interface device 110, a memory device 120, and a memory controller 130. The data storage device 100 may further include a processing device 140. For example, the components included in the data storage device 100 may communicate with each other through a bus 150.

[0026] The data storage device 100 may be used by at least one host device 200. The data storage device 100 and the host device 200 may be collectively referred to as a computing system.

[0027] The computing system may include, for example, a plurality of host devices 200, and Figure 1 as an example, shows a case where the computing system includes N host devices 200_1, 200_2, 200_3,..., 200_N.

[0028] For example, the host device 200 may be a computer, an ultra-mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, one of various electronic devices configured for a home network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, a mobile device (e.g., a vehicle, a robot, or a drone) capable of being driven manually or autonomously under human control, a wearable device, etc. Optionally, the host device 200 may be a virtual reality / augmented reality device that provides 2D or 3D virtual reality images or augmented reality images. The host device 200 is not limited to the above examples and may be one of various electronic devices that require a data storage device 100 capable of storing data.

[0029] The host device 200 may include at least one operating system. The operating system may manage and control the overall functions and operations of the host device 200. The operating system may control the interoperability between the host device 200 and the data storage device 100. According to the mobility of the host device 200, the operating system may be classified into a general operating system and a mobile operating system.

[0030] The host device 200 may use the memory included in the host device 200 to perform data processing. The host device 200 may also use the data storage device 100 located outside the host device 200 to perform data processing.

[0031] The host device 200 may communicate with the data storage device 100 through a preset interface.

[0032] For example, the host device 200 may communicate with the data storage device 100 through a Compute Express Link (CXL) interface. The host device 200 may be set as a CXL root port, and the data storage device 100 may be set as a CXL endpoint. Since the host device 200 communicates with the data storage device 100 through the CXL interface, a low-latency high-bandwidth access environment may be realized in a structure for communicating with the high-capacity data storage device 100.

[0033] Optionally, depending on the situation, the host device 200 may communicate with the data storage device 100 through an interface other than the CXL interface.

[0034] For example, the host device 200 and the data storage device 100 may communicate through at least one of various communication interfaces or standards such as: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High-Speed PCI (PCIe) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol, but not limited thereto.

[0035] In this way, the type and number of host devices 200 communicating with the data storage device 100 according to the embodiments of the present disclosure and the communication interface between the host device 200 and the data storage device 100 may vary. However, hereinafter, as an example, the case where at least one host device 200 communicates with the data storage device 100 through the CXL interface will be described.

[0036] The data storage device 100 may include at least one memory device 120. As an example, Figure 1Illustrates a case where the data storage device 100 includes four memory devices 120. The data storage device 100 may also be referred to as a data storage system.

[0037] The memory device 120 may be, for example, a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, but embodiments of the present disclosure are not limited thereto. Depending on the situation, the memory device 120 may be a non-volatile memory. Some of the plurality of memory devices 120 may be volatile memories, while other memory devices may be non-volatile memories. Even when only one memory device 120 is included in the data storage device 100, embodiments of the disclosed technology may be applied.

[0038] The data storage device 100 may include a memory controller 130 that controls the operation of the memory device 120. Figure 1 Illustrates a case where the data storage device 100 includes four memory controllers 130 that respectively control four memory devices 120. Depending on the situation, one memory controller 130 may control the operation of at least two memory devices 120.

[0039] The memory controller 130 may control an operation of writing data to the memory device 120 or an operation of reading data from the memory device 120 according to a command input from the outside (e.g., the host device 200). The memory controller 130 may control a refresh operation of memory cells included in the memory device 120 according to the type of the memory device 120. The memory controller 130 may control an operation of erasing data written to the memory device 120 according to the type of the memory device 120.

[0040] The data storage device 100 may further include a processing device 140 that performs calculations related to the memory device 120 or outputs commands for controlling the memory device 120. For example, the processing device 140 may perform functions for managing or controlling the memory device 120 and the memory controller 130. The processing device 140 may allocate or deallocate memory areas included in the memory device 120 according to requests from the host device 200. The processing device 140 may perform calculations using the data stored in the memory device 120 according to commands received from the host device 200, and may provide a result value. For example, the data storage device 100 may only provide or store data and may not perform calculations. In this case, the host device 200 may perform calculations based on the data read from the data storage device 100. In some cases, some calculations may be performed in the data storage device 100 (e.g., by the processing device). The data sent and received between the host device 200 and the data storage device 100 may be reduced. For example, the host device 200 may send instructions for indicating calculations and returning the calculation results to the data storage device 100. The processing device 140 in the data storage device 100 may perform calculations based on the instructions received from the host device 200 without sending the data for the calculations outside the data storage device 100.

[0041] The processing device 140 is not limited to the above examples. Inside or outside the data storage device 100, when the processing device performs operations related to the memory device 120 while communicating with the memory device 120 and the memory controller 130 included in the data storage device 100, the processing device may correspond to the processing device 140 according to an embodiment of the present disclosure.

[0042] The data storage device 100 may further include an auxiliary memory capable of storing data required for the operation of the processing device 140. The auxiliary memory may be different from the memory device 120 and may be, for example, a volatile memory such as SRAM, but the embodiment is not limited thereto.

[0043] The memory device 120, the memory controller 130, and the processing device 140 included in the data storage device 100 may be respectively provided as separate components, or at least some of them may be integrated to be provided as one component. According to circumstances, the memory controller 130, the processing device 140, and the auxiliary memory may be respectively implemented as dies and may be packaged. In this case, the components other than the memory device 120 may be provided in a single package form.

[0044] The processing device 140 may be provided separately from the memory controller 130, but may be provided by integration with the memory controller 130 according to circumstances. In addition, some functions of the memory controller 130 may be provided by being implemented in the processing device 140.

[0045] The processing device 140 and the memory controller 130 may communicate with each other via a bus 150. Signals to be received from the host device 200 or signals to be transmitted to the host device 200 may be transmitted via the bus 150.

[0046] As mentioned in the above example, the data storage device 100 and the host device 200 may communicate with each other via a CXL interface.

[0047] The data storage device 100 may include a first interface device CXL EP 110 for communicating according to the CXL interface, and the host device 200 may include a second interface device CXL RP 210 according to the CXL interface.

[0048] The data storage device 100 and the host device 200 may send and receive signals according to a determined CXL protocol. For example, the data storage device 100 and the host device 200 may send and receive signals according to sub - protocols such as CXL.io, CXL.cache, and CXL.mem.

[0049] The CXL.io protocol may be a protocol for searching, connecting, setting, and managing the data storage device 100. The CXL.cache protocol may be a protocol that allows the data storage device 100 to access the host device 200. The CXL.mem protocol may be a protocol that allows the host device 200 to access the data storage device 100. In this specification, the CXL.cache protocol and the CXL.mem protocol regarding data may be referred to as the first sub - protocol, and the CXL.io protocol regarding command processing may be referred to as the second sub - protocol.

[0050] The host device 200 and the data storage device 100 may perform data processing by sending and receiving micro - slices (or data packets) according to the above - mentioned protocols. The sending and receiving of micro - slices may be performed by the second interface device 210 included in the host device 200 and the first interface device 110 included in the data storage device 100.

[0051] Figure 2 It is a diagram showing a schematic configuration of a computing system according to an embodiment of the present disclosure.

[0052] Refer to Figure 2, the first interface device 110 included in the data storage device 100 may include, for example, a physical layer 111, a multiplexer 112, a data link layer 113, and a conversion layer 114. The first interface device 110 may receive microtiles according to the CXL protocol, process the received microtiles, and provide the processed microtiles to the memory controller 130 or the processing device 140 via the bus 150.

[0053] Figure 2 The case where the processing device 140 is an accelerator is shown, but embodiments of the present disclosure are not limited thereto. In addition to the accelerator, the processing device 140 may be a unit that performs operations related to the memory device 120 when communicating with the memory device 120 or the memory controller 130, such as a microcontroller unit.

[0054] The processing device 140 or the memory controller 130 that receives the microtiles via the first interface device 110 may perform operations based on the microtiles.

[0055] Depending on the situation, the first interface device 110 may be implemented by integrating with at least one of the memory controller 130 and the processing device 140. For example, the first interface device 110, the memory controller 130, and the processing device 140 may configure a control unit 300. For example, the control unit 300 may be provided in the form of a module implemented separately from the memory device 120. Depending on the situation, the memory controller 130 and the memory device 120 may be implemented together, and the first interface device 110 and the processing device 140 may be implemented together.

[0056] The microtiles sent to the data storage device 100 may be generated and sent by the second interface device 210 of the host device 200.

[0057] The second interface device 210 included in the host device 200 may include, for example, a physical layer 211, a multiplexer 212, a data link layer 213, and a conversion layer 214. The components included in the second interface device 210 may correspond to the components included in the first interface device 110.

[0058] The host device 200 may include a kernel processor 220 and an input / output (I / O) device 230. The kernel processor 220 and the input / output device 230 may provide commands or data to be sent to the second interface device 210 according to a user's input. The second interface device 210 may generate microtiles based on the commands and data received from the kernel processor 220 and the input / output device 230, and may send the generated microtiles to the data storage device 100.

[0059] The conversion layer 214 included in the second interface device 210 may generate data packets based on commands and data, and the data link layer 213 may add a header, etc. to the generated data packets. A first microchip may be generated according to a first sub-protocol such as the CXL.cache protocol or the CXL.mem protocol, and a second microchip may be generated according to a second sub-protocol such as the CXL.io protocol, and the first microchip and the second microchip may be transmitted to a multiplexer (i.e., CXL ARB / MUX) 212. The ARB may be an arbitration circuit for controlling access when using (shared) resources. The first microchip and the second microchip transmitted to the physical layer 211 through the multiplexer 212 may be sent to the physical layer 111 of the first interface device 110 included in the data storage device 100. The physical layer 211 may send (TX) microchips to the physical layer 111 and may receive (RX) microchips from the physical layer 111.

[0060] The physical layer 111 of the first interface device 110 may transmit the microchips received from the host device 200 to the multiplexer 112. The multiplexer 112 may output the received microchips separately according to the sub-protocol, and may provide the output microchips to the processing device 140 or the memory controller 130 through the data link layer 113 and the conversion layer 114.

[0061] Depending on the situation, for the efficiency of microchip transmission, the first interface device 110 may provide microchips differently from the instruction order or reception order of the microchips (allowing out-of-order processing or out-of-order output). In a case where an error may occur due to a change in the output order of the microchips, the change in the output order of the microchips may be prohibited (prohibiting out-of-order processing or out-of-order output). By doing so, errors in data transmission and reception according to the CXL protocol between the host device 200 and the data storage device 100 can be prevented or reduced, and data transmission and reception performance can be improved.

[0062] For example, the first interface device 110 may process microchips by determining whether to adjust the processing order of the microchips based on the values set in the microchips by the second interface device 210.

[0063] Figure 3 It is a diagram showing a method of generating and transmitting microchips by the second interface device 210 included in the host device 200 according to an embodiment of the present disclosure.

[0064] Refer to Figure 3 , the second interface device 210 of the host device 200 may generate microchips according to commands or data provided by the kernel processor 220 or the input / output (I / O) device 230.

[0065] For example, the conversion layer 214 of the second interface device 210 may generate microtiles according to the CXL.cache protocol, the CXL.mem protocol, or the CXL.io protocol. The conversion layer 214 of the second interface device 210 may generate microtiles and may set a processing order flag (or order flag) in each microtile.

[0066] For example, when in-order processing of the generated microtiles is required and out-of-order processing is not allowed, the conversion layer 214 of the second interface device 210 may set the setting value of the processing order flag included in the corresponding microtile to a first value (e.g., "1"). When in-order processing of the generated microtiles is not required and out-of-order processing different from the instruction order of the host device 200 is allowed, the conversion layer 214 of the second interface device 210 may set the setting value of the processing order flag included in the corresponding microtile to a second value (e.g., "0"), or may not set the processing order flag. The processing order flag may indicate whether out-of-order processing of multiple microtiles is prohibited (or allowed).

[0067] The above method of setting the processing order flag is an example, and any reserved field in the microtile structure according to the CXL protocol may be used to set the processing order flag.

[0068] Referring to Figure 3 Shown in <Case 1> and <Case 2>, <Case 1> shows, as an example, a case of generating two microtiles according to the CXL.cache protocol and one microtile according to the CXL.io protocol.

[0069] The processing order flag may be set in each of the two microtiles according to the CXL.cache protocol and the one microtile according to the CXL.io protocol. <Case 1> shows a case where the processing order flags of all three microtiles are set to the second value ("0"). Since the processing order flag is set to the second value, out-of-order processing of the three corresponding microtiles may be allowed.

[0070] <Case 2> shows, as an example, a case of generating three microtiles according to the CXL.mem protocol and one microtile according to the CXL.io protocol.

[0071] The processing order flag may be set in each of the three microtiles according to the CXL.mem protocol and the one microtile according to the CXL.io protocol. <Case 2> shows a case where the processing order flags of all four microtiles are set to the first value ("1"). Since the processing order flag is set to the first value, in-order processing of the corresponding four microtiles may be required.

[0072] As in the above example, the processing order flag may be set by the conversion layer 214 of the second interface device 210. However, depending on the situation, the processing order flag may be set in the process of adding a header in the data link layer 213.

[0073] In this way, a microchip with the processing order flag set can be generated and sent to the outside (e.g., the data storage device 100). The data storage device 100 that receives the microchip with the processing order flag set can control the order of processing the received microchips based on the processing order flag.

[0074] Figures 4 to 6 FIG. is a diagram showing a method in which the first interface device 110 included in the data storage device 100 based on an embodiment of the present disclosure controls the order of outputting the received microchips.

[0075] Referring to Figure 4 , the data storage device 100 may receive at least one first microchip according to the first sub-protocol and at least one second microchip according to the second sub-protocol from the host device 200. The first sub-protocol may be the CXL.cache protocol or the CXL.mem protocol, and the second sub-protocol may be the CXL.io protocol.

[0076] The physical layer 111 of the first interface device 110 included in the data storage device 100 may receive the microchips. The microchips received by the physical layer 111 of the first interface device 110 may be transmitted to the multiplexer 112 of the first interface device 110.

[0077] The multiplexer 112 of the first interface device 110 may check the set value of the processing order flag included in each received microchip. The multiplexer 112 of the first interface device 110 may control the output order of the received microchips based on the set value of the processing order flag.

[0078] Referring to Figure 4 Shown in <Case 1>, it shows a case where the multiplexer 112 of the first interface device 110 receives two microchips according to the CXL.cache protocol and one microchip according to the CXL.io protocol.

[0079] Since the processing order flags included in the corresponding three microchips are all set to the second value ("0"), the multiplexer 112 of the first interface device 110 may determine the output order of the microchips when operating according to the second mode. For example, the second mode may be a mode that allows unordered processing (i.e., a mode that does not prohibit unordered processing), and the multiplexer 112 of the first interface device 110 may output the three microchips in order according to the instruction order of the host device 200, or may output the three microchips unordered differently from the instruction order of the host device 200.

[0080] The multiplexer 112 of the first interface device 110 can output three microchips in an orderly manner, or can output at least one of the three microchips in a disorderly manner.

[0081] Refer to Figure 5 , such as <ex1>In this case, even when the processing sequence flags included in the corresponding three microchips are all set to the second value ("0"), the three microchips can be output in order.

[0082] The three microchips orderly output by the multiplexer 112 of the first interface device 110 can be converted by the data link layer 113 and the conversion layer 114. According to the order in which the multiplexer 112 of the first interface device 110 outputs the three microchips, the three microchips can be converted, and the converted three microchips can be provided to the processing device 140 or the like. The order of the microchips provided to the processing device 140 can be adjusted by the multiplexer 112 of the first interface device 110.

[0083] For another example, as <ex2>In the case where all the processing sequence flags included in the corresponding three microtiles are set to the second value ("0"), at least one of the three microtiles can be output in an unordered manner. The third microtile according to the CXL.io protocol can be output earlier than the second microtile according to the CXL.cache protocol. The conversion of the third microtile according to the CXL.io protocol can be performed earlier. Commands, etc. corresponding to the third microtile according to the CXL.io protocol can be provided to the processing device 140 earlier than the data corresponding to the second microtile according to the CXL.cache protocol.

[0084] When there is a transmission delay or error in the second microtile according to the CXL.cache protocol, the multiplexer 112 of the first interface device 110 can output the third microtile according to the CXL.io protocol earlier. The first interface device 110 can prevent or reduce the degradation of the overall system performance caused by the processing delay of the microtiles received by the first interface device 110 due to the abnormality of the microtiles.

[0085] According to the set value of the processing sequence flag, the multiplexer 112 of the first interface device 110 can output the received microtiles in an ordered manner.

[0086] Refer back to Figure 4 As shown in <Case 2>, it shows the case where the multiplexer 112 of the first interface device 110 receives three microtiles according to the CXL.mem protocol and one microtile according to the CXL.io protocol.

[0087] Since the set values of the processing sequence flags included in the corresponding four microtiles are all set to the first value ("1"), the multiplexer 112 of the first interface device 110 can recognize that the four microtiles need to be output and processed in an ordered manner. Four microtiles that are set to the first value ("1") and need to be processed in an ordered manner can be received continuously.

[0088] The multiplexer 112 of the first interface device 110 can output the four microtiles in an ordered manner when operating according to the first mode. The first mode can be a mode for performing ordered processing and can be a mode for prohibiting unordered processing. The four microtiles output in an ordered manner can be converted by the data link layer 113 and the conversion layer 114.

[0089] Refer to Figure 6 , the order in which the multiplexer 112 of the first interface device 110 outputs the microtiles can be the same as the instruction order. The first microtile according to the CXL.mem protocol, the second microtile according to the CXL.mem protocol, the third microtile according to the CXL.mem protocol, and the fourth microtile according to the CXL.io protocol can be output in an ordered manner and can be converted according to the output order. The four microtiles can be converted and provided to the processing device 140, etc. in an ordered manner.

[0090] For example, in a case where the command corresponding to the fourth microchip according to the CXL.io protocol is a command indicating calculation using data corresponding to the first three microchips according to the CXL.mem protocol, if out-of-order processing is allowed, the command corresponding to the fourth microchip according to the CXL.io protocol can be provided to the processing device 140 earlier. The processing device 140 may perform calculation in a state where reception of at least one of the three microchips according to the CXL.mem protocol is not completed, and in this case, an operation error may occur.

[0091] Since the multiplexer 112 of the first interface device 110 controls the output order of microchips based on the processing order flag, the conversion of the data link layer 113 and the conversion layer 114 can also be performed in an orderly manner. Since the microchips are provided to the processing device 140 in an orderly manner, an error in the operation of the processing device 140 can be prevented.

[0092] The case where the processing device 140 calculates data has been described as an example. However, in addition to this example, in a case where an error may occur during out-of-order processing, orderly processing can be performed by setting a processing order flag. For example, the host device 200 may send a command that instructs to store data in a local memory of the host device 200 or another host device in a specific area of the memory device 120 included in the data storage device 100 and migrate the data stored in the corresponding area in the memory device 120 or the data storage device 100. In this case, since data storage and migration should be performed in an orderly manner, the processing order flag included in the corresponding microchips can be set to a first value ("1") and sent to the first interface device 110 of the data storage device 100.

[0093] Thus, according to an embodiment of the present disclosure, by setting a processing order flag in each microchip, a device and a system can be provided that can prevent an error from occurring due to a change in the conversion order of microchips and at the same time prevent or reduce deterioration of the microchip conversion efficiency in the first interface device 110 of the data storage device 100.

[0094] The multiplexer 112 of the first interface device 110 of the data storage device 100 can control the order and method of outputting microchips in various ways according to the set value of the processing order flag.

[0095] Figure 7 and Figure 8 are diagrams showing a method of receiving and processing microchips by the first interface device 110 included in the data storage device 100 based on an embodiment of the present disclosure.

[0096] Referring to Figure 7 , a case is shown as an example where all the processing order flags included in the microchips sent by the host device 200 are set to a second value ("0").

[0097] The multiplexer 112 of the first interface device 110 included in the data storage device 100 can control ordered processing or unordered processing based on the processing sequence flag included in the microchip received from the host device 200. Since the set values of the processing sequence flags included in the received nine microchips [1] to [9] are all the second value ("0"), the multiplexer 112 can output the microchips by changing the output order of the microchips as needed.

[0098] For example, the multiplexer 112 of the first interface device 110 can preferentially output the fifth microchip (i.e., [5] CXL.io) according to the CXL.io protocol earlier than the third and fourth microchips (i.e., [3], [4] CXL.mem) according to the CXL.mem protocol. The multiplexer 112 of the first interface device 110 can preferentially output the ninth microchip (i.e., [9] CXL.io) according to the CXL.io protocol earlier than the eighth microchip (i.e., [8] CXL.mem) according to the CXL.mem protocol. The conversion of the preferentially output microchips can be performed earlier. The earlier-converted microchips can be provided to the processing device 140 earlier.

[0099] In the case where the output of the third and fourth microchips according to the CXL.mem protocol or the eighth microchip according to the CXL.mem protocol is delayed, other microchips are preferentially output and converted. Therefore, it is possible to prevent or reduce the deterioration of data transmission and reception performance due to the output delay of the microchips.

[0100] According to the set value of the processing sequence flag included in the microchip, the multiplexer 112 of the first interface device 110 can operate according to the mode of performing ordered processing or according to the time period of the corresponding microchip, and can operate according to the modes of performing ordered processing and unordered processing.

[0101] Refer to Figure 8 , as an example, shows the case where the data storage device 100 receives 11 microchips [1]-

[11] from the host device 200.

[0102] The set values of the processing sequence flags included in the first, second, and third microchips [1]-[3] can be the second value ("0"). The set values of the processing sequence flags included in the fourth, fifth, sixth, seventh, and eighth microchips [4]-[8] can be the first value ("1"). The set values of the processing sequence flags included in the ninth, tenth, and eleventh microchips [9]-

[11] can be the second value ("0").

[0103] In each time period according to the set value of the processing sequence flag, the multiplexer 112 of the first interface device 110 can operate in the first mode for ordered processing, or can operate in the second mode allowing unordered processing.

[0104] The multiplexer 112 of the first interface device 110 can operate in the second mode during the period of receiving the first microchip, the second microchip, and the third microchips [1]-[3]. The multiplexer 112 of the first interface device 110 can output the three microchips in order, or can output the three microchips out of order as shown in the example Figure 8 shown.

[0105] The multiplexer 112 of the first interface device 110 can operate in the first mode during the period of receiving the fourth microchip, the fifth microchip, the sixth microchip, the seventh microchip, and the eighth microchips [4]-[8]. The multiplexer 112 of the first interface device 110 can output the microchips in order during the corresponding period while prohibiting out-of-order processing.

[0106] For example, after receiving a microchip whose set value of the processing sequence flag is not the first value ("1"), when receiving a microchip whose set value of the processing sequence flag is the first value ("1"), the multiplexer 112 of the first interface device 110 can output the received microchips in order until receiving a microchip whose set value of the processing sequence flag is not the first value ("1"). During the period of receiving a microchip whose set value of the processing sequence flag is the first value ("1"), the multiplexer 112 of the first interface device 110 can hold the corresponding microchip, and when receiving a microchip whose set value of the processing sequence flag is the second value ("0"), can output the held microchips in order.

[0107] Optionally, according to the situation, when receiving a microchip according to the second protocol during the period of receiving a microchip whose set value of the processing sequence flag is the first value ("1"), the multiplexer 112 of the first interface device 110 can output the microchips held during the corresponding period in order.

[0108] For example, a microchip according to the first sub-protocol whose set value of the processing sequence flag is the first value ("1") can be received. The multiplexer 112 of the first interface device 110 can hold the corresponding microchip according to the first sub-protocol, and then, when receiving a microchip according to the second sub-protocol whose set value of the processing sequence flag is the first value ("1"), can output the microchip received at that time in order. Since the command corresponding to the microchip according to the second sub-protocol can indicate processing of the data corresponding to the microchip according to the first sub-protocol, the data processing of the corresponding microchip can be normally executed.

[0109] Since it is possible to prevent the microchip according to the second sub-protocol from being output earlier than the microchip according to the first sub-protocol, it is also possible to prevent the occurrence of errors due to out-of-order processing.

[0110] The multiplexer 112 of the first interface device 110 may operate in the second mode during the period when the ninth microchip, the tenth microchip, and the eleventh microchip [9]-

[11] are received, and may output the corresponding microchips in an ordered or unordered manner. A conversion may be performed such that the efficiency of processing the microchips is not reduced while preventing errors from occurring.

[0111] According to the above embodiments of the present disclosure, by setting a processing sequence flag in the microchips transmitted and received between the host device 200 and the data storage device 100, ordered processing or unordered processing can be controlled. Therefore, a protocol can be provided that can prevent errors from occurring due to unordered processing of microchips while not reducing the processing efficiency of the transmitted and received microchips.

[0112] Although various embodiments of the present disclosure have been described using specific details and variations for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made based on the content disclosed or illustrated in the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims. In addition, embodiments can be combined to form additional embodiments.

Claims

1. A data storage system, comprising: at least one memory device; a processing device that performs calculations related to the at least one memory device or outputs commands for controlling the at least one memory device; as well as an interface device that receives at least one first flits according to a first subprotocol and at least one second flits according to a second subprotocol from a host device, and prohibits operations of providing the at least one first flits and the at least one second flits to the processing device out of order different from the instruction order of the host device based on a setting value of a processing order flag included in each of the at least one first flits and the at least one second flits, The processing device performs calculation or outputs the command based on one of the at least one first microchip and the at least one second microchip.

2. The data storage device according to claim 1, wherein: The interface device comprises: A physical layer, receiving the at least one first microchip and the at least one second microchip; a multiplexer that checks a setting value of the processing order flag included in each of the at least one first flits and the at least one second flits, and adjusts an output order of the at least one first flits and the at least one second flits; and The data link layer and the conversion layer convert the at least one first flint and the at least one second flint output by the multiplexer, and provide the converted at least one first flint and the at least one second flint to the processing device.

3. The data storage device according to claim 2, wherein: When the setting value of the processing order flag is a first value, the multiplexer operates in a first mode and outputs the at least one first flit and the at least one second flit in order according to the instruction sequence.

4. The data storage device according to claim 2, wherein: When the setting value of the processing sequence flag is a first value, the multiplexer maintains the output of the at least one first microchip and the at least one second microchip, and when the setting value of the processing sequence flag is not the first value, the maintained at least one first microchip and the at least one second microchip are output in order according to the instruction sequence.

5. The data storage device according to claim 2, wherein: After receiving at least one first microchip whose setting value is the first value, when receiving at least one second microchip whose setting value is the first value, the multiplexer outputs at least one first microchip received before receiving the at least one second microchip in an orderly manner according to the instruction sequence.

6. The data storage device according to claim 2, wherein: When the setting value of the processing order flag is a second value, the multiplexer operates in a second mode and outputs the at least one first microchip and the at least one second microchip out of order by comparing the at least one first microchip and the at least one second microchip with the instruction order.

7. The data storage device according to claim 6, wherein: The data link layer and the conversion layer convert the at least one first microchip and the at least one second microchip according to the order in which the at least one first microchip and the at least one second microchip are received from the multiplexer, and provide the converted at least one first microchip and the at least one second microchip to the processing device in an order different from the instruction order.

8. The data storage device according to claim 2, wherein: The multiplexer outputs a remainder of the at least one first flitter and the at least one second flitter, the remainder being obtained by excluding the processing order flag from the at least one first flitter and the at least one second flitter.

9. The data storage device according to claim 1, wherein: The processing device performs the calculation according to the data based on the at least one first microchip and outputs a command according to the at least one second microchip.

10. The data storage device according to claim 9, wherein: The processing device performs an operation corresponding to the command based on the data.

11. A control unit, comprising: A memory controller controls the memory device; an accelerator in communication with the memory controller and configured to perform computations based on data stored in the memory device; as well as An interface device receives a plurality of microchips from a host device, each of the plurality of microchips having a processing order flag set therein, and prohibits providing operations of the plurality of microchips to the accelerator out of order different from an instruction order of the host based on a setting value of the processing order flag included in each of the plurality of microchips.

12. The control unit according to claim 11, wherein: When a setting value of a processing order flag included in each of the plurality of flits is a first value, the interface device provides the plurality of flits to the accelerator in order according to the instruction sequence.

13. The control unit according to claim 11, wherein: When a setting value of a processing order flag included in each of the plurality of flits is a second value, the interface device allows the plurality of flits to be provided to the accelerator out of order different from the instruction order.

14. The control unit according to claim 11, wherein: The interface device comprises a physical layer, a conversion layer and a multiplexer between the physical layer and the conversion layer, and The multiplexer checks a setting value of a processing order flag included in each of the plurality of flits and controls an output order of the plurality of flits.

15. A computing system comprising: a host device that generates at least one first flits according to a first subprotocol and generates at least one second flits according to a second subprotocol, and outputs the at least one first flits and the at least one second flits by setting a processing order flag in the at least one first flits and the at least one second flits; as well as A data storage device receives the at least one first microchip and the at least one second microchip from the host device, and based on a processing order flag set in each of the at least one first microchip and the at least one second microchip, prohibits the operation of outputting the at least one first microchip and the at least one second microchip out of order that is different from the instruction order of the host device.

16. The computing system of claim 15, wherein: When the setting value of the processing sequence flag set in each of the at least one first microchip and the at least one second microchip is a first value, the data storage device sequentially outputs the at least one first microchip and the at least one second microchip according to the instruction sequence, and When the setting value of the processing order flag set in each of the at least one first microchip and the at least one second microchip is a second value, the data storage device allows the at least one first microchip and the at least one second microchip to be output out of order different from the instruction order.

17. The computing system of claim 15, wherein: The host device comprises: a processor, which provides data and commands; and An interface device generates and outputs the at least one first microchip and the at least one second microchip, and sets the processing order flag in each of the at least one first microchip and the at least one second microchip, wherein the processing order flag indicates whether out-of-order processing of the first microchip and the second microchip is prohibited.

18. The computing system of claim 17, wherein: The interface device comprises: a conversion layer and a data link layer, receiving the data and the command from the processor, and generating a first flitter and a second flitter in the form of data packets based on the data and the command, respectively; and The physical layer sends the first microchip and the second microchip to the outside. Wherein, the processing sequence flag is set in the conversion layer or the data link layer.

19. The computing system of claim 17, wherein: The interface device sets the setting value of the processing sequence flag included in each of the at least one first microchip and the at least one second microchip to a first value during a time period when orderly output is required, and sets the setting value of the processing sequence flag included in each of the at least one first microchip and the at least one second microchip to a second value during a time period when unordered output is allowed.

20. The computing system of claim 17, wherein: At least two of the at least one first microchip or the at least one second microchip in which the setting value of the processing order flag is set to the first value are continuous.

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