Broadband reconfigurable Non-Foster chip

Abstract

The invention discloses a broadband reconfigurable Non-Foster chip, which is applied to a radio frequency microwave integrated circuit technology, is based on a Non-Foster network capable of simulating negative capacitance or negative inductance, and comprises two groups of dual-port series circuits with the same structure, the equivalence with the ideal serial negative capacitance value in the frequency bands of 2-4.5 GHz and 4.5-6 GHz is realized respectively; a single-pole double-throw switch is used for switching a used dual-port series circuit, and a varactor is switched to control voltage so as to adjust an equivalent capacitance value, so that within the working frequency of 2GHz-6GHz, the equivalent capacitance value of the designed circuit is-1pF, the reconfigurable range of the capacitance value is as follows:-1pF is greater than or equal to 15%, and the capacitance value error of the circuit is less than or equal to 10% when the circuit is equivalent to a capacitor with a fixed value of-1pF.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency and microwave integrated circuits, and particularly relates to a positive group delay cancellation technique. Background Art

[0002] Modern wireless communication features low latency and low bit error rate. In the radio frequency transceiver system of wireless communication, the non-ideality of the phase-frequency characteristics of transmission links such as mixers, amplifiers, and antennas, especially the group delay fluctuation caused by the band-pass filter near its steep cut-off frequency. With the continuous increase in the transmission rate of wireless communication systems, the density and complexity of the interconnect structure have increased significantly. The group delay problem has become an important and difficult problem in signal integrity. Since traditional microwave components (capacitors, inductors, and transmission lines) generally exhibit the characteristic of decreasing phase with increasing frequency, when transmitting signals with broadband characteristics, there are inevitably differences in the phases of each frequency component. This difference is manifested as positive group delay on the signal envelope, which in turn causes signal distortion and severely weakens the communication quality. In view of this, the industry urgently needs a new type of circuit to cancel this positive group delay. It is precisely under such demand-driven that the research on NGD (negative group delay) circuits has emerged. With the continuous progress of technology, various innovative circuit structures based on NGD circuits have emerged. Among them, the Non-Foster network that can simulate negative capacitance or negative inductance is particularly remarkable. Theoretically, this network can compensate for the reactance generated by the parasitic effect of the transistor, thereby increasing the cut-off frequency of the transistor and broadening its operating bandwidth. Currently, the operating frequency range of existing Non-Foster circuits is mostly limited to a few hundred MHz, and most Non-Foster element structures are relatively complex. The structures in these studies can only achieve fixed negative capacitance values and negative inductance values. Therefore, the exploration of Non-Foster circuits and their applications has extremely high practical value. Summary of the Invention

[0003] To solve the above technical problems, the present invention proposes a dual-port series Non-Foster circuit architecture to implement a Non-Foster equivalent network with a specific series negative capacitance value.

[0004] The technical solution adopted by the present invention is as follows: a broadband reconfigurable Non-Foster chip, including: a first single-pole double-throw switch, a second single-pole double-throw switch, a first capacitor C1, a first resistor R1, and two sets of double-port series circuits with the same structure; the first end of the first capacitor C1 is connected to the voltage VDD, the second end of the first capacitor C1 is connected to the first end of the first single-pole double-throw switch, the first end of the first resistor R1 is connected to the first end of the first single-pole double-throw switch, the second end of the first resistor R1 is grounded, and the first end of the first single-pole double-throw switch serves as the input end of the chip; the second end of the first single-pole double-throw switch is connected to the input end of the first set of double-port series circuits, and the third end of the first single-pole double-throw switch is connected to the input end of the second set of double-port series circuits; the output end of the first set of double-port series circuits is connected to the first end of the second single-pole double-throw switch, the output end of the second set of double-port series circuits is connected to the second end of the second single-pole double-throw switch, and the third end of the second single-pole double-throw switch serves as the output end of the chip.

[0005] Further, both sets of double-port series circuits with the same structure include a pre-stage circuit and a post-stage circuit connected in series in sequence; the pre-stage circuit and the post-stage circuit have the same structure; the input ends of the pre-stage circuit and the post-stage circuit are grounded through a group of capacitors and resistors connected in series in sequence; the input ends of the pre-stage circuit and the post-stage circuit are also connected to the input end of a circuit unit composed of an inductor, a resistor, and a capacitor connected in parallel in sequence, and the output ends of the pre-stage circuit and the post-stage circuit are connected to the output end of this group of inductor, resistor, and capacitor connected in parallel in sequence.

[0006] The beneficial effects of the present invention: The present invention designs a broadband reconfigurable Non-Foster chip based on the SMIC 55nm CMOS process. The chip changes the circuit used through a single-pole double-throw switch to achieve that within the working frequency range of 2GHz - 6GHz, the equivalent capacitance value of the designed circuit is -1pF, the reconfigurable range of the capacitance value is around -1pF ≥ 15%, and the capacitance value error is ≤ 10% when the circuit is equivalent to a capacitor with a fixed value of -1pF. Description of the Drawings

[0007] Figure 1 It is the structure diagram of the Non-Foster circuit.

[0008] Figure 2 It is the simulation result diagram of the equivalent negative capacitance value of the circuit within the frequency bands of 2 - 4.5GHz and 4.5 - 6GHz when the control voltage VDD is 0.75V.

[0009] Figure 3 It is the simulation result diagram of the equivalent negative capacitance value of the Non-Foster circuit within the frequency band of 2 - 4.5GHz when the control voltage VDD is adjusted between 0 - 2.5V.

[0010] Figure 4The simulation result diagram of the equivalent negative capacitance value of the Non-Foster circuit in the 4.5 - 6 GHz frequency band when the control voltage VDD is adjusted between 0 - 2.5V.

[0011] Figure 5 It is the circuit diagram of a single-pole double-throw switch (SPDT). Specific implementation manners

[0012] For the convenience of those skilled in the art to understand the technical content of the present invention, the following further elaborates on the content of the present invention in conjunction with the accompanying drawings.

[0013] The chip of the present invention is designed based on the SMIC 55nm CMOS process. The specific structure of the chip of the present invention is as Figure 1 shown. The capacitor C1 at the input end is a varactor, and R1 is a resistor grounded. By adjusting the value of the DC voltage VDD, the voltage value across C1 is controlled, and thus the capacitance value of C1 is adjusted. The (Single pole double throw switch) SPDT switch is a single-pole double-throw switch, and by adjusting the control signals at both ends, the signal flows through one of the upper and lower paths. The upper and lower two sets of double-port series circuit structures are the same. Taking one set of circuits as an example for analysis, the capacitor C2 and the resistor R2 are in series, the other end of C2 is connected in parallel to the input end, and the other end of R2 is grounded. The inductor L1, the resistor R3, and the capacitor C3 are in parallel, one end is connected to the input end, and the other end is connected to the subsequent stage. The capacitor C4 and the resistor R4 are in series, the other end of C4 is connected in parallel to the previous stage, and the other end of R4 is grounded. The inductor L2, the resistor R5, and the capacitor C5 are in parallel, one end is connected to the previous stage, and the other end is connected to the output end.

[0014] The device values of the upper and lower two sets of double-port series circuit structures are different. The inductance values of the inductors L1, L2, L3, and L4 are 6nH. The resistance values of the resistors R2, R3, R4, and R5 in the upper circuit are 102Ω, 176Ω, 84Ω, and 107Ω respectively, and the capacitance values of the capacitors C2, C3, C4, and C5 are 4pF, 1.4pF, 4.3pF, and 360fF respectively. The resistance values of the resistors R6, R7, R8, and R9 in the lower circuit are 102Ω, 176Ω, 68Ω, and 147Ω respectively, and the capacitance values of the capacitors C6, C7, C8, and C9 are 4.3pF, 1.4pF, 4.3pF, and 283fF respectively. When the voltage value VDD of the varactor C1 is 0.75V, the S 21 phase values at the input and output ends in the 2 - 4.5 GHz and 4.5 - 6 GHz frequency bands are respectively 21 less than 10% different from the S Figure 2As shown, the red curve is the simulation result of the equivalent negative capacitance value of the circuit in the 2 - 4.5 GHz frequency band when the SPDT turns on the upper circuit with the control voltage VDD at 0.75V; the blue curve is the simulation result of the equivalent negative capacitance value of the circuit in the 4.5 - 6 GHz frequency band when the SPDT turns on the lower circuit with the control voltage VDD at 0.75V. From Figure 3 , 4 it can be seen that by adjusting the voltage VDD to change the voltage value within the range of 0 - 2.5V, and then changing the capacitance value of the varactor C1, the S 21 phase value at the input and output ends of the Non - Foster circuit can be adjusted to be close to the S 21 phase value of a negative capacitance with any required capacitance value within the range of - 0.85 pF to - 1.15 pF, that is, to be equivalent to the negative capacitance values within the range of - 0.85 pF to - 1.15 pF respectively, realizing a broadband reconfigurable Non - Foster circuit in the 2 - 6 GHz frequency band.

[0015] The single - pole double - throw switch (SPDT) adopts the Figure 5 structure shown. Port1, Port2, and Port3 are used as the input and output terminals of the signal. The drains of M1 and M2 are connected. The drains of M3 and M4 are respectively connected to the sources of M1 and M2, which are the output terminals Port2 and Port3, and the sources of M3 and M4 are grounded. The design of the MOS transistor switch adopts an AC floating technology, that is, a large resistor R10 to R17 is connected in series at the gates and Bulk terminals of the 4 MOS transistors for isolation, isolating the signal transmission between the gate and the substrate, reducing the leakage and crosstalk of high - frequency signals caused by the existence of parasitic capacitance, and reducing the insertion loss of the switch. Ctrl1 and Ctrl2 are used as control voltage terminals and are respectively connected to the gates of M1, M4 and M2, M3 to control the on - off of the MOS transistors. When Ctrl1 inputs a high level and Ctrl2 inputs a low level, the transistors M1 and M4 are turned on, and the transistors M2 and M3 are turned off. At this time, the single - pole double - throw switch circuit forms a signal path from Port1 to Port2; when Ctrl1 inputs a low level and Ctrl2 inputs a high level, the transistors M1 and M4 are turned off, and the transistors M2 and M3 are turned on. At this time, the single - pole double - throw switch circuit forms a signal path from Port1 to Port3. In this embodiment, the resistance values of the large resistors R10 to R17 are each 10 kΩ.

[0016] Those of ordinary skill in the art will realize that the embodiments described herein are provided to assist the reader in understanding the principles of the present invention, and it should be understood that the scope of protection of the present invention is not limited to such specific statements and embodiments. Various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims

1. Broadband reconfigurable Non-Foster chip, characterized by: include: A first single-pole double-throw switch, a second single-pole double-throw switch, a first capacitor C1, a first resistor R1, and two groups of dual-port series circuits with the same structure; the first end of the first capacitor C1 is connected to the voltage VDD, the second end of the first capacitor C1 is connected to the first end of the first single-pole double-throw switch, the first end of the first resistor R1 is connected to the first end of the first single-pole double-throw switch, the second end of the first resistor R1 is grounded, and the first end of the first single-pole double-throw switch serves as the input end of the chip; the second end of the first single-pole double-throw switch is connected to the input end of the first group of dual-port series circuits, and the third end of the first single-pole double-throw switch is connected to the input end of the second group of dual-port series circuits; the output end of the first group of dual-port series circuits is connected to the first end of the second single-pole double-throw switch, the output end of the second group of dual-port series circuits is connected to the second end of the second single-pole double-throw switch, and the third end of the second single-pole double-throw switch serves as the output end of the chip.

2. The broadband reconfigurable Non-Foster chip according to claim 1, characterized in that: Two groups of two-port series circuits with the same structure both include a front-stage circuit and a rear-stage circuit connected in series in sequence; the front-stage circuit and the rear-stage circuit have the same structure; the input ends of the front-stage circuit and the rear-stage circuit are respectively grounded through a group of capacitors and resistors connected in series in sequence; the input ends of the front-stage circuit and the rear-stage circuit are also connected to the input ends of a circuit unit of a group of inductors, resistors, and capacitors connected in parallel in sequence, and the output ends of the front-stage circuit and the rear-stage circuit are connected to the output ends of the circuit unit of the group of inductors, resistors, and capacitors connected in parallel in sequence.

3. The broadband reconfigurable Non-Foster chip according to claim 2, characterized in that: There are two groups of dual-port series circuits with the same structure, one group of dual-port series circuits operates in the 2-4.5 GHz frequency band, and the other group of dual-port series circuits operates in the 4.5-6 GHz frequency band.

4. The broadband reconfigurable Non-Foster chip according to claim 3, characterized in that: The first capacitor C1 is a varactor.

5. The broadband reconfigurable Non-Foster chip according to claim 4, characterized in that: By adjusting the voltage VDD connected to the first end of the first capacitor C1, the equivalent negative capacitance corresponding to the Non-Foster chip is adjusted.

6. The broadband reconfigurable Non-Foster chip according to claim 5, characterized in that: The equivalent negative capacitance range of the Non-Foster chip is -0.85pF to -1.15pF.

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