Synchronization unit verification method and device of digital circuit, equipment and medium

Abstract

The invention discloses a synchronization unit verification method and device of a digital circuit, equipment and a medium, and relates to the technical field of computers, and the method comprises the steps: embedding an assertion statement rule and an assertion coverage rate evaluation rule in a synchronization unit; the assertion statement rule is used for monitoring the operation state and signal characteristics of the synchronization unit in the data synchronization process, the assertion statement rule is implemented in a parameterization mode to adapt to the function requirements of different circuit units, and the assertion coverage rate evaluation rule is used for counting the execution condition of the assertion statement rule; executing front-end simulation verification of the synchronization unit by utilizing the plurality of test cases, and judging whether a violation condition which is not consistent with the assertion statement rule exists in a case execution result or not: if not, calculating an execution coverage rate of the assertion statement rule based on an assertion coverage rate evaluation rule; and evaluating whether the synchronization unit passes the front-end simulation verification according to the execution coverage rate. According to the method, the possibility of omission of problems due to incomplete verification is reduced, and the execution coverage rate is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly relates to a method, device, equipment and medium for verifying a synchronization unit of a digital circuit. Background Art

[0002] In digital circuit design, a synchronization unit (Sync Cell) is a very important and commonly used circuit structure, mainly used to achieve data synchronization across clock domains (Clock Domain Crossing, CDC). Its function is to ensure that data can be safely and accurately transmitted from one clock domain to another, even if the clock frequencies and phases of these two clock domains may be different. The main functions of the synchronization unit include: eliminating metastability: by introducing two or more flip-flops, solving the problem that the flip-flop cannot reach a definite state (0 or 1) within a predetermined time; data synchronization: ensuring that the input data is stable at the clock edge of the target clock domain, avoiding data errors caused by clock uncertainty; clock domain isolation: sampling the data through independent flip-flops to achieve logical isolation between two clock domains; improving system stability: reducing system instability and data inconsistency caused by cross-clock domain transmission.

[0003] The synchronization unit is a key means to ensure the correct transmission of data between different clock domains, so its verification is particularly important. Traditional front-end verification methods mainly rely on functional verification, covering by writing test cases for cross-clock domain signals. However, this method has limitations and cannot monitor the input and output signals of the synchronization unit in real time, especially in the case where the signals may flip multiple times, and it is easy to miss verification points. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a method, device, equipment and medium for verifying a synchronization unit of a digital circuit, which can reduce the possibility of missing problems due to incomplete verification and improve the execution coverage rate. The specific solutions are as follows:

[0005] In a first aspect, the present application discloses a method for verifying a synchronization unit of a digital circuit, including:

[0006] Embedding assertion statement rules and assertion coverage evaluation rules in the synchronization unit; wherein, the assertion statement rules are used to monitor the running state and signal characteristics of the synchronization unit during the data synchronization process, and the assertion statement rules adopt a parameterized implementation method to adapt to the functional requirements of different circuit units, and the assertion coverage evaluation rules are used to count the execution situation of the assertion statement rules;

[0007] Performing front-end simulation verification of the synchronization unit using multiple test cases to obtain the use case execution results, and judging whether there are violation situations that do not conform to the assertion statement rules in the use case execution results:

[0008] If there is no violation that does not conform to the assertion statement rule in the execution result of the use case, then based on the assertion coverage evaluation rule, calculate the execution coverage of the assertion statement rule, and evaluate whether the synchronization unit passes the front-end simulation verification according to the execution coverage.

[0009] Optionally, each test case includes a set of input data, a clock signal, and a reset signal. The assertion statement rule includes synchronous stability check and synchronous glitch check. Then, use multiple test cases to perform the front-end simulation verification of the synchronization unit to obtain the use case execution result, including:

[0010] If the reset signal is at a low level, disable the synchronous stability check;

[0011] If the reset signal is at a high level, enable the synchronous stability check;

[0012] Among them, the synchronous stability check includes:

[0013] If it is detected that the input data is unstable, generate a stability violation message when the input data does not remain stable in the subsequent clock cycle, otherwise determine that the input data meets the stability requirements;

[0014] If the reset signal is at a low level, disable the synchronous glitch check

[0015] If the reset signal is at a high level, enable the synchronous glitch check;

[0016] Among them, the synchronous glitch check includes:

[0017] If it is detected that the input data changes, then invert the input data and assign it to the data variable, and check whether the input data is equal to the data variable at the rising edge of the next clock signal;

[0018] If the input data is not equal to the data variable, determine that there is a glitch and generate a glitch violation message, otherwise determine that there is no glitch in the input data;

[0019] After the simulation is completed, generate the use case execution result; among them, the use case execution result includes the simulation result of each test case and the summary information of assertion violations.

[0020] Optionally, after determining whether there is a violation in the use case execution result that does not conform to the assertion statement rule, it further includes:

[0021] If there is a violation in the use case execution result that does not conform to the assertion statement rule, pre-analyze the simulation log of the violation situation to extract the violation information, and determine whether the violation situation meets the allowable passing judgment condition, so as to select a matching processing method according to the judgment result.

[0022] Optionally, determine whether the violation situation meets the condition for allowing passage of the judgment, so as to select a matching processing method according to the judgment result, including:

[0023] If the violation situation meets the condition for allowing passage of the judgment, add the violation situation to the filtering file, so that when performing the front-end simulation verification next time, filter the violations allowed to pass based on the filtering file.

[0024] Optionally, determine whether the violation situation meets the condition for allowing passage of the judgment, so as to select a matching processing method according to the judgment result, including:

[0025] If the violation situation does not meet the condition for allowing passage of the judgment, generate an error report based on the violation information, and sort the priorities of each violation according to the error report;

[0026] Perform waveform simulation on the violations according to the priority sorting, and detect whether there are abnormal situations in the simulation results, so as to perform corresponding repairs when abnormal situations are detected in the simulation results.

[0027] Optionally, the method for verifying the synchronization unit of the digital circuit further includes:

[0028] Integrate the pre-analysis function of the simulation log of the violation situation into the target graphical interface simulation tool, and configure a pre-analysis start button on the corresponding interface, so as to automatically execute the pre-analysis function of the simulation log of the violation situation through the pre-analysis start button.

[0029] Optionally, evaluate whether the synchronization unit passes the front-end simulation verification according to the execution coverage rate, including:

[0030] If the execution coverage rate reaches the target threshold, determine that the synchronization unit passes the front-end simulation verification;

[0031] If the execution coverage rate does not reach the target threshold, for the synchronization unit with the unachieved coverage rate threshold, add test cases, and jump to the step of performing the front-end simulation verification of the synchronization unit using multiple test cases.

[0032] In a second aspect, the present application discloses a device for verifying a synchronization unit of a digital circuit, including:

[0033] A rule embedding module for embedding an assertion statement rule and an assertion coverage rate evaluation rule in the synchronization unit; wherein, the assertion statement rule is used to monitor the running state and signal characteristics of the synchronization unit during the data synchronization process, and the assertion statement rule adopts a parameterized implementation method to adapt to the functional requirements of different circuit units, and the assertion coverage rate evaluation rule is used to count the execution situation of the assertion statement rule;

[0034] A simulation verification module is used to perform front-end simulation verification of the synchronization unit using multiple test cases, obtain the test case execution results, and determine whether there are any violations in the test case execution results that do not conform to the assertion statement rules:

[0035] A result evaluation module is used to, if there are no violations in the test case execution results that do not conform to the assertion statement rules, calculate the execution coverage rate of the assertion statement rules based on the assertion coverage rate evaluation rules, and evaluate whether the synchronization unit passes the front-end simulation verification according to the execution coverage rate.

[0036] Thirdly, the present application discloses an electronic device, including:

[0037] A memory for storing a computer program;

[0038] A processor for executing the computer program to implement the synchronization unit verification method of the digital circuit disclosed above.

[0039] Fourthly, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the synchronization unit verification method of the digital circuit disclosed above is implemented.

[0040] As can be seen, the present application proposes a method for verifying a synchronization unit of a digital circuit, including: embedding an assertion statement rule and an assertion coverage evaluation rule in the synchronization unit; the assertion statement rule is used to monitor the operating state and signal characteristics of the synchronization unit during data synchronization, and the assertion statement rule adopts a parameterized implementation method to adapt to the functional requirements of different circuit units. The assertion coverage evaluation rule is used to count the execution situation of the assertion statement rule; using multiple test cases to perform front-end simulation verification of the synchronization unit to obtain the use case execution result, and determining whether there is a violation situation that does not conform to the assertion statement rule in the use case execution result: if there is no violation situation that does not conform to the assertion statement rule in the use case execution result, then based on the assertion coverage evaluation rule, calculate the execution coverage rate of the assertion statement rule, and evaluate whether the synchronization unit passes the front-end simulation verification according to the execution coverage rate. As can be seen, the present application embeds an assertion statement rule with a parameterized implementation method in the synchronization unit. This rule can adapt to various situations by flexibly adjusting parameters according to the functional requirements of different circuit units. In this way, only one set of assertion statement rules needs to be developed, and different parameter values can be passed according to the specific requirements of different modules to achieve reuse among multiple modules, greatly avoiding the cumbersome process of developing assertion statements multiple times and significantly improving the development efficiency of assertion statements. In addition, the verification method of the present application introduces an assertion coverage evaluation rule, which is used to count the execution situation of the assertion statement rule. When the execution coverage rate reaches a relatively high level, it means that the operating state and signal characteristics of the synchronization unit in various possible situations have been relatively fully monitored and verified, greatly reducing the possibility of missing problems due to incomplete verification and improving the execution coverage rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to the provided drawings.

[0042] Figure 1 It is a flowchart of a method for verifying a synchronization unit of a digital circuit disclosed in the present application;

[0043] Figure 2 It is a flowchart of a specific method for verifying a synchronization unit of a digital circuit disclosed in the present application;

[0044] Figure 3 It is a schematic diagram of a pre-analysis script disclosed in the present application;

[0045] Figure 4 It is a schematic structural diagram of a device for verifying a synchronization unit of a digital circuit disclosed in the present application;

[0046] Figure 5 This is a structural diagram of an electronic device disclosed in this application. Specific embodiments

[0047] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0048] The synchronization unit is a key means to ensure the correct transmission of data between different clock domains, so its verification is particularly important. Traditional front-end verification methods mainly rely on functional verification, covering by writing test cases for cross-clock-domain signals. However, this method has limitations and cannot monitor the input and output signals of the synchronization unit in real time, especially in the case where the signal may flip multiple times, and it is easy to miss verification points.

[0049] For this reason, the embodiments of this application propose a verification scheme for the synchronization unit of a digital circuit, which can reduce the possibility of missing problems due to incomplete verification and improve the execution coverage rate.

[0050] The embodiments of this application disclose a verification method for the synchronization unit of a digital circuit. See Figure 1 As shown, the method includes:

[0051] Step S11: Embed assertion statement rules and assertion coverage evaluation rules in the synchronization unit; among them, the assertion statement rules are used to monitor the running state and signal characteristics of the synchronization unit during data synchronization, and the assertion statement rules adopt a parameterized implementation method to adapt to the functional requirements of different circuit units. The assertion coverage evaluation rule is used to count the execution situation of the assertion statement rules.

[0052] For the synchronization unit of the device under test (DUT, Design Under Test), embed assertion statement rules and assertion coverage evaluation rules. The assertion statement rules are used to monitor the running state and signal characteristics of the synchronization unit during data synchronization. The running state and signal characteristics specifically include signal stability and whether there are glitches in the signal. The assertion statement rules adopt a parameterized implementation method to adapt to the functional requirements of different circuit units. The assertion coverage evaluation rule is used to count the execution situation of the assertion statement rules. According to the functional requirements of different circuit units, flexibly adjust the parameters to adapt to various situations. In this way, only one set of assertion statement rules needs to be developed, and different parameter values can be passed according to the specific requirements of different modules to achieve reuse among multiple modules, thus greatly avoiding the cumbersome process of developing assertion statements multiple times.

[0053] Step S12: Perform front-end simulation verification of the synchronization unit using multiple test cases to obtain the test case execution results, and determine whether there are any violations that do not conform to the assertion statement rules in the test case execution results:

[0054] In this embodiment, each test case includes a set of input data, a clock signal, and a reset signal. The assertion statement rules include synchronous stability check and synchronous glitch check. On this basis, perform front-end simulation verification of the synchronization unit using multiple test cases to obtain the test case execution results, including: if the reset signal is at a low level, disable the synchronous stability check; if the reset signal is at a high level, enable the synchronous stability check. Among them, the synchronous stability check includes: if it is detected that the input data is unstable, generate a stability violation message when the input data does not remain stable in the subsequent clock cycles, otherwise determine that the input data meets the stability requirements. If the reset signal is at a low level, disable the synchronous glitch check; if the reset signal is at a high level, enable the synchronous glitch check. Among them, the synchronous glitch check includes: if it is detected that the input data changes, invert the input data and assign it to the data variable, and check whether the input data is equal to the data variable at the rising edge of the next clock signal. If the input data is not equal to the data variable, determine that there is a glitch and generate a glitch violation message, otherwise determine that there is no glitch in the input data. After the simulation is completed, generate the test case execution results; the test case execution results include the simulation results of each test case and the summary information of assertion violations. By performing front-end simulation verification on the synchronization unit, controlling the enabling and disabling of the two checks using the reset signal, and the targeted check rules, it is possible to comprehensively detect the stability of the input data in the synchronization unit and whether there are glitch problems. The finally generated test case execution results provide a clear situation of each test case and the summary of assertion violations, which helps to quickly locate and analyze the problems that may occur in the synchronization unit under different input conditions and ensure the correctness of the synchronization unit design.

[0055] Among them, the code related to the above assertion statement rules and assertion coverage evaluation rules is as follows:

[0056] sync_stability_cov: cover property(sync_stability(din,clk,resetn));

[0057] sync_glitch_cov: cover property(sync_glitch (din,clk,resetn))

[0058] Bind std_sync_cell sva_sync_cell_chk sync_cell_check_inst(

[0059] .din(din),

[0060] .clk(clk),

[0061] .resetn(resetn));

[0062] / / ======stability property=====

[0063] property sync_stability(din,clk,resetn, stable_cycle);

[0064] @(clk) disable iff(!resetn)

[0065] !stable(din)|=>$stable(din)[*stable_cycle]; / / din should stable for stable_cycle / 2 clk cycle

[0066] endproperty

[0067] / / ======glitch property======

[0068] property sync_glitch(din,clk,resetn);

[0069] logic data;

[0070] @(din) disable iff(!resetn)

[0071] (1,data=!din)|=>$(posedge clk) din==data; / / check glitch

[0072] Endproperty

[0073] Module sva_sync_cell_chk (

[0074] Input clk,

[0075] Intput resetn,

[0076] Input din,

[0077] Input stable_cycle)

[0078] / / ======stable sva======

[0079] sync_stability_sva: assert property(sync_stability(din,clk,resetn,stable_cycle))

[0080] else $display(“ERROR: sync_stability error,input data can not stablefor stable_cycle / 2 cycle!”);

[0081] / / ======glitch sva======

[0082] sync_glitch_sva: assert property(sync_glitch (din,clk,resetn))

[0083] else $display(“ERROR: sync_glitch error,input data is a glitch!”);

[0084] …

[0085] endmodule

[0086] The above code focuses on the property checks of the synchronization unit. First, the coverage properties sync_stability_cov (synchronization stability coverage) and sync_glitch_cov (synchronization glitch coverage) are declared to count the coverage of the synchronization stability check sync_stability and the synchronization glitch check sync_glitch. Then, the sva_sync_cell_chk module (synchronization verification unit check module) is bound to the std_sync_cell unit (standard synchronization unit) through the Bind statement, and the signals din (data input), clk (clock signal), and resetn (active-low reset signal) are passed to the sva_sync_cell_chk module instance sync_cell_check_inst (synchronization unit check instance). The synchronization stability property sync_stability is triggered on the rising edge of clk. When resetn is high, if din is unstable, it is required that din remains stable within the subsequent stable_cycle (stable period) clock cycles. The synchronization glitch property sync_glitch is triggered when din changes and resetn is high. The inverted value of din is assigned to data (data variable), and whether there is a glitch is judged by checking whether din is equal to data at the next clock rising edge. In the sva_sync_cell_chk module, the sync_stability_sva (synchronization stability assertion) asserts the sync_stability property, and prints a stability error message when the assertion fails; the sync_glitch_sva (synchronization glitch assertion) asserts the sync_glitch property, and prints a glitch error message when the assertion fails. Through these definitions and assertions, a comprehensive check of the synchronization unit's stability and glitch problems is achieved, helping to detect problems in a timely manner during the design phase and improving the design reliability.

[0087] Step S13: If there is no violation that does not conform to the assertion statement rule in the test case execution result, then based on the assertion coverage evaluation rule, calculate the execution coverage of the assertion statement rule, and evaluate whether the synchronization unit passes the front-end simulation verification according to the execution coverage.

[0088] For the execution result of the use case, if there are violations in the execution result of the use case that do not conform to the assertion statement rules, pre-analyze the simulation log of the violations to extract violation information, determine whether the violations meet the pass judgment conditions, and select a matching processing method. If the violations meet the pass judgment conditions, add the violations to the filtering file so that when the front-end simulation verification is performed next time, the violations that are allowed to pass can be filtered based on the filtering file. If the violations do not meet the pass judgment conditions, generate an error report based on the violation information, sort the priorities of each violation according to the error report; perform waveform simulation on the violations according to the priority sorting, and detect whether there are abnormal situations in the simulation results so as to perform corresponding repairs when abnormal situations are detected in the simulation results. If there are no violations in the execution result of the use case that do not conform to the assertion statement rules, calculate the execution coverage rate of the assertion statement rules based on the assertion coverage rate evaluation rules, and evaluate whether the synchronization unit passes the front-end simulation verification according to the execution coverage rate. Specifically, if the execution coverage rate reaches the target threshold, it is determined that the synchronization unit passes the front-end simulation verification; if the execution coverage rate does not reach the target threshold, for the synchronization unit whose coverage rate threshold is not reached, add test cases and jump to the front-end simulation verification of the synchronization unit using multiple test cases.

[0089] That is to say, for the execution result of the use case, if there are violations that do not conform to the assertion statement rules, first pre-analyze the simulation log to extract violation information, and then judge whether it meets the pass conditions. If it meets, add the violation situation to the filtering file so that when the front-end simulation verification is performed next time, the violations that are allowed to pass can be filtered based on the filtering file; if it does not meet, generate an error report based on the violation information and sort the priorities of each violation according to the error report. Subsequently, perform waveform simulation on the violations according to the priority sorting. If abnormal situations are detected in the simulation results, corresponding repairs are made. If there are no violations in the execution result of the use case that do not conform to the assertion statement rules, calculate the execution coverage rate of the assertion statement rules based on the assertion coverage rate evaluation rules. If the execution coverage rate reaches the target threshold, it is determined that the synchronization unit passes the front-end simulation verification; if the execution coverage rate does not reach the target threshold, for the synchronization unit whose coverage rate threshold is not reached, add test cases, and then jump to the front-end simulation verification of the synchronization unit using multiple test cases. In this way, this process can comprehensively and meticulously process the results of the front-end simulation verification of the synchronization unit. For violation situations, by differentiating and effectively managing them, on the one hand, unnecessary repeated verification can be reduced, and on the other hand, serious violations can be given priority to handling, thereby improving the repair efficiency. For the situation without violations, through assertion coverage rate evaluation, the verification integrity of the synchronization unit can be accurately judged. When the execution coverage rate does not reach the target threshold, adding test cases in a timely manner can ensure that the synchronization unit is fully tested, thereby improving the reliability and stability of the synchronization unit design.

[0090] Furthermore, integrate the pre-analysis function of the simulation log for violation cases into the target graphical interface simulation tool, and configure a pre-analysis start button on the interface so that the pre-analysis function of the simulation log for violation cases can be automatically executed through the pre-analysis start button. It can be understood that manual analysis of the simulation log is prone to missing important information or making analysis errors due to human negligence. Through the automatic pre-analysis function of the graphical interface, the consistency and accuracy of the analysis process can be ensured, errors caused by human factors can be reduced, the reliability of the verification results can be improved, and the operation difficulty can be greatly reduced, saving time costs. Exemplarily, in a digital chip design project, an engineer performs front-end simulation verification on a circuit containing a large number of synchronous units. After a certain simulation, multiple violation cases occurred in the test case execution results. In the past, the engineer needed to manually open the long simulation log file, view and analyze the information line by line, trying to find out the cause of the violation. Since the log file may contain thousands of lines of data and the information is complex, some key violation details were overlooked in the process. Now, after integrating the pre-analysis function into the graphical interface simulation tool and configuring the button, the engineer only needs to easily click the pre-analysis start button on the graphical interface, and the tool will automatically and quickly perform a comprehensive analysis of the simulation log. Compared with manual analysis, it not only avoids information omission and analysis errors caused by human negligence, but also the manual analysis work that originally took several hours can now be completed in just a few minutes, greatly improving work efficiency.

[0091] See Figure 2 and Figure 3 as shown Figure 2 is a flow chart of a verification method for synchronous units of a specific digital circuit. Figure 3It is a schematic diagram of a pre - analysis script. In the front - end verification of the chip for the verification work of synchronous units in larger modules, multiple verification personnel often face the problem of repeatedly analyzing the same error report, resulting in low efficiency. To effectively solve this dilemma, this embodiment constructs a comprehensive and systematic front - end verification strategy for synchronous units, and its key links are as follows: (1) Strengthening the function of the pre - analysis script: With the help of a script that takes the regression test folder path and an optional filter file as inputs, all synchronous unit assertion error reports are extracted and summarized from the simulation log. The generated pre - analysis document will record the error details so that verification personnel can comprehensively understand the relevant situation. Based on the pre - analysis results, verification personnel run the simulation waveforms targeted, carefully check whether there are unexpected glitches and whether the duration of the input signals of synchronous units meets the standards. Once a design defect is found, it is reported to the design personnel for repair in a timely manner. After the repair, the simulation analysis is carried out again until the defect is resolved. If there are allowable synchronous unit violations, such as the missed sampling of a specific cross - clock - domain relatively static signal at a non - inspection time, the hierarchical path of this synchronous unit can be filled in the filter file as the input of the pre - analysis script, and such violations can be filtered out when the script is executed next time. When the output document of the pre - analysis script is empty, it indicates that the analysis work of the covered synchronous units has been successfully completed. (2) Tolerable logic filtering mechanism: For tolerable synchronous unit logic such as the allowable missed sampling of relatively static signals, through subsequent processing scripts, corresponding operations can be executed only by filling in the input signal path of the synchronous unit, realizing the efficient filtering of relevant assertion violation situations. (3) Assertion coverage check: Checking the assertion coverage is the core means to ensure the integrity of synchronous unit verification. If the assertion coverage does not reach 100%, for synchronous units that have not flipped, test cases need to be added for coverage, and continuous analysis is carried out according to the above process. If the assertion coverage reaches 100% and the output document of the pre - analysis script is empty, it means that all synchronous units have been triggered and analyzed, and at this time, the synchronous unit analysis work is considered complete. (4) Unified assertion statement development: An innovative method combining sampling assertions and assertion coverage is adopted to uniformly develop assertion check statements. By flexibly setting the input signal stable time period through parameter passing, the reuse of this statement among different requirement modules is realized, which not only avoids repeated development but also effectively guarantees the completeness of verification. This verification strategy can clearly and intuitively display the whole process of front - end verification of synchronous units, effectively improve the efficiency and quality of verification work, and ensure the reliability of the front - end design of the chip.

[0092] Furthermore, to further optimize the front-end simulation verification process of the chip synchronization unit and improve the verification efficiency and quality, this application can also construct an intelligent-driven closed-loop verification system. After obtaining the use case execution result, the system will quickly enable the intelligent classification engine. If there is a violation, based on the preset semantic analysis model, this engine deeply analyzes the violation information in the simulation log to accurately identify the type of violation. For common and less influential violations, directly associate with the historical solution library, automatically match the processing solution and implement the repair; for complex or unknown violations, utilize knowledge graph technology to sort out the related signals, modules, and past similar cases to assist the verification personnel in locating the root cause of the problem. At the same time, the system monitors the assertion coverage rate in real-time. Once it is found that the coverage rate grows slowly or stagnates, immediately start the adaptive test case generator, and intelligently generate supplementary test cases based on the current verification status and potential risk areas.

[0093] It can be seen that this application proposes a verification method for the synchronization unit of a digital circuit, including: embedding assertion statement rules and assertion coverage rate evaluation rules in the synchronization unit; the assertion statement rules are used to monitor the operating state and signal characteristics of the synchronization unit during data synchronization, and the assertion statement rules adopt a parameterized implementation method to adapt to the functional requirements of different circuit units, and the assertion coverage rate evaluation rule is used to count the execution situation of the assertion statement rules; use multiple test cases to perform the front-end simulation verification of the synchronization unit to obtain the use case execution result, and judge whether there is a violation situation that does not conform to the assertion statement rules in the use case execution result: if there is no violation situation that does not conform to the assertion statement rules in the use case execution result, then based on the assertion coverage rate evaluation rule, calculate the execution coverage rate of the assertion statement rules, and evaluate whether the synchronization unit passes the front-end simulation verification according to the execution coverage rate. It can be seen that this application embeds assertion statement rules with a parameterized implementation method in the synchronization unit, and this rule can adapt to various situations by flexibly adjusting parameters according to the functional requirements of different circuit units. In this way, only one set of assertion statement rules needs to be developed, and different parameter values can be passed according to the specific requirements of different modules to achieve reuse among multiple modules, greatly avoiding the cumbersome process of developing assertion statements multiple times and significantly improving the development efficiency of assertion statements. In addition, the verification method of this application introduces an assertion coverage rate evaluation rule, which is used to count the execution situation of the assertion statement rules. When the execution coverage rate reaches a relatively high level, it means that the operating state and signal characteristics of the synchronization unit in various possible situations have been relatively fully monitored and verified, greatly reducing the possibility of missing problems due to incomplete verification and improving the execution coverage rate.

[0094] Correspondingly, the embodiment of this application also discloses a verification device for the synchronization unit of a digital circuit, as shown in Figure 4 shown, this device includes:

[0095] A rule embedding module 11 is used to embed assertion statement rules and assertion coverage evaluation rules in the synchronization unit. Among them, the assertion statement rules are used to monitor the operating status and signal characteristics of the synchronization unit during the data synchronization process, and the assertion statement rules adopt a parameterized implementation method to adapt to the functional requirements of different circuit units. The assertion coverage evaluation rules are used to count the execution of the assertion statement rules;

[0096] A simulation verification module 12 is used to perform front-end simulation verification of the synchronization unit using multiple test cases, obtain the test case execution results, and determine whether there are any violation situations that do not conform to the assertion statement rules in the test case execution results:

[0097] A result evaluation module 13 is used to, if there are no violation situations that do not conform to the assertion statement rules in the test case execution results, calculate the execution coverage rate of the assertion statement rules based on the assertion coverage evaluation rules, and evaluate whether the synchronization unit passes the front-end simulation verification according to the execution coverage rate.

[0098] Among them, for the more specific working processes of the above-mentioned various modules, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated herein.

[0099] Furthermore, an embodiment of the present application also provides an electronic device. Figure 5 It is a structural diagram of an electronic device 20 shown according to an exemplary embodiment. The content in the figure should not be considered as any limitation on the scope of use of the present application.

[0100] Figure 5 It is a schematic structural diagram of an electronic device 20 provided by an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the synchronization unit verification method of the digital circuit disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0101] In this embodiment, the power supply 26 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and specific limitations are not imposed herein; the input / output interface 24 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and specific limitations are not imposed herein.

[0102] In addition, as a carrier for storing resources, the memory 22 can be a read-only memory, a random access memory, a magnetic disk, an optical disc, etc. The resources stored thereon can include a computer program 221, and the storage method can be temporary storage or permanent storage. Among them, in addition to the computer program capable of implementing the synchronous unit verification method of the digital circuit executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 221 can further include a computer program capable of completing other specific tasks.

[0103] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the synchronous unit verification method of the digital circuit disclosed above is implemented.

[0104] For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.

[0105] The embodiments in this application are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts between the embodiments, reference can be made to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and reference can be made to the method part for the relevant parts.

[0106] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0107] The steps of the method or algorithm described in combination with the embodiments disclosed in this article can be directly implemented by hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0108] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0109] The above has introduced in detail a method, apparatus, device, and storage medium for verifying a synchronization unit of a digital circuit provided by the present application. Specific examples are used in this text to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A synchronization unit verification method for a digital circuit, characterized in that: include: Embedding assertion statement rules and assertion coverage evaluation rules in the synchronization unit; wherein the assertion statement rules are used to monitor the operation status and signal characteristics of the synchronization unit during the data synchronization process, and the assertion statement rules are implemented in a parameterized manner to adapt to the functional requirements of different circuit units, and the assertion coverage evaluation rules are used to count the execution status of the assertion statement rules; Utilize multiple test cases to perform front-end simulation verification of the synchronization unit, obtain test case execution results, and determine whether there are any violations in the test case execution results that do not conform to the assertion statement rules: If there is no violation that does not comply with the assertion statement rule in the use case execution result, the execution coverage of the assertion statement rule is calculated based on the assertion coverage evaluation rule, and whether the synchronization unit passes the front-end simulation verification is evaluated based on the execution coverage.

2. The synchronization unit verification method of a digital circuit according to claim 1, characterized in that: Each of the test cases includes a set of input data, a clock signal and a reset signal, and the assertion statement rule includes a synchronization stability check and a synchronization glitch check. Then, the front-end simulation verification of the synchronization unit is performed using multiple test cases to obtain the case execution results, including: If the reset signal is at a low level, disabling the synchronization stability check; If the reset signal is at a high level, the synchronization stability check is enabled; The synchronization stability check includes: If it is detected that the input data is unstable, generating stability violation information when the input data does not remain stable in a subsequent clock cycle, otherwise determining that the input data meets the stability requirement; If the reset signal is low, the synchronization glitch check is disabled If the reset signal is at a high level, the synchronization glitch check is enabled; Wherein, the synchronization burr inspection includes: If it is detected that the input data has changed, the input data is inverted and assigned to the data variable, and at the rising edge of the next clock signal, it is checked whether the input data is equal to the data variable; If the input data is not equal to the data variable, it is determined that a glitch exists, and glitch violation information is generated; otherwise, it is determined that the input data does not have a glitch; After the simulation is completed, the use case execution result is generated; wherein the use case execution result includes the simulation result of each of the test cases and the summary information of the assertion violation.

3. The synchronization unit verification method of a digital circuit according to claim 1, characterized in that: After determining whether there is a violation in the execution result of the use case that does not conform to the assertion statement rule, the method further includes: If there are violations in the execution result of the use case that do not conform to the assertion rule, the simulation log of the violation is pre-analyzed to extract the violation information and determine whether the violation satisfies the judgment condition to allow passing, so as to select a matching processing method according to the judgment result.

4. The synchronization unit verification method of a digital circuit according to claim 3, characterized in that: The determining whether the violation situation satisfies the judgment condition of allowing the user to pass, so as to select a matching processing method according to the judgment result, includes: If the violation meets the judgment condition of allowing passing, the violation is added to the filter file, so that during the next front-end simulation verification, the violation that is allowed to pass is filtered based on the filter file.

5. The synchronization unit verification method of a digital circuit according to claim 3, characterized in that: The determining whether the violation situation satisfies the judgment condition of allowing the user to pass, so as to select a matching processing method according to the judgment result, includes: If the violation does not satisfy the passing judgment condition, an error report is generated based on the violation information, and each violation is prioritized according to the error report; Waveform simulation is performed on the violations according to the priority sorting, and whether there are abnormal conditions in the simulation results is detected, so that corresponding repairs are performed when abnormal conditions are detected in the simulation results.

6. The synchronization unit verification method of a digital circuit according to claim 3, characterized in that: Also includes: The pre-analysis function of the simulation log of the violation is integrated into the target graphical interface simulation tool, and a pre-analysis start button is configured on the corresponding interface so that the pre-analysis function of the simulation log of the violation is automatically executed through the pre-analysis start button.

7. The synchronization unit verification method of a digital circuit according to any one of claims 1 to 6, characterized in that: The step of evaluating whether the synchronization unit passes the front-end simulation verification according to the execution coverage includes: If the execution coverage reaches a target threshold, it is determined that the synchronization unit passes the front-end simulation verification; If the execution coverage does not reach the target threshold, a test case is added for the synchronization unit that does not reach the coverage threshold, and the process jumps to the step of executing the front-end simulation verification of the synchronization unit using multiple test cases.

8. A synchronization unit verification device for a digital circuit, characterized in that: include: A rule embedding module, used to embed assertion statement rules and assertion coverage evaluation rules in the synchronization unit; wherein the assertion statement rules are used to monitor the operation status and signal characteristics of the synchronization unit during the data synchronization process, and the assertion statement rules are implemented in a parameterized manner to adapt to the functional requirements of different circuit units, and the assertion coverage evaluation rules are used to count the execution status of the assertion statement rules; A simulation verification module is used to perform front-end simulation verification of the synchronization unit using multiple test cases, obtain test case execution results, and determine whether there are any violations in the test case execution results that do not comply with the assertion statement rules: A result evaluation module is used to calculate the execution coverage of the assertion statement rule based on the assertion coverage evaluation rule if there is no violation that does not comply with the assertion statement rule in the use case execution result, and evaluate whether the synchronization unit has passed the front-end simulation verification based on the execution coverage.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the synchronization unit verification method for a digital circuit as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program; wherein, when the computer program is executed by a processor, the synchronous unit verification method of a digital circuit as claimed in any one of claims 1 to 7 is implemented.

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