Asynchronous path acquisition method and device for chip, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses an asynchronous path acquisition method and device for a chip, electronic equipment and a storage medium. According to the scheme, in the process of performing static time sequence analysis on the test chip, time sequence violation check can be performed on the test chip by adding the time sequence analysis command, the asynchronous path is obtained based on the time sequence violation check result, and the starting endpoint and the ending endpoint of the asynchronous path are traversed, so that the accuracy of the static time sequence analysis is improved. And carrying out preliminary screening on the asynchronous paths according to the traversed clock signals, and excluding associated registers in the asynchronous paths according to beating nodes of a synchronizer so as to realize secondary screening on the asynchronous paths. According to the method, the asynchronous path is captured from the time sequence report in a mode of constructing the time sequence violation, and screening is performed based on the end points of the asynchronous path, so that the capturing and screening efficiency of the asynchronous path is effectively improved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and specifically relates to a method, device, electronic device and storage medium for obtaining asynchronous paths for chips. Background Art

[0002] In the field of chip design, with the increasing complexity of chip functions and the continuous improvement of integration, clock domain management has become a crucial link. A chip usually contains multiple clock domains, and the interaction of signals between different clock domains is cross-clock domain (CDC, Clock Domain Crossing) communication.

[0003] In the front-end design stage of the chip, a special cdc tool is generally used to check whether there are design defects in the paths across asynchronous clock domains. Asynchronous path checks are also required in the back-end stage. In the prior art, the method of capturing asynchronous paths usually starts from the dimension of registers, traversing the fan-out or fan-in of each register in the chip to determine whether it is synchronous or asynchronous with the current register. The defect of this method is that there are generally tens of millions of registers in a large chip. Assuming that 10 registers are processed per second, it will take more than ten days; and most of the paths in the chip are synchronous paths, resulting in most of the time of this method being spent on ineffective processing, leading to extremely low efficiency in capturing asynchronous paths. Summary of the Invention

[0004] This application provides a method, device, electronic device and storage medium for obtaining asynchronous paths for chips. By constructing timing violations, asynchronous paths are captured from the timing report, and based on the endpoints of the asynchronous paths, screening is performed, effectively improving the efficiency of capturing and screening asynchronous paths.

[0005] This application provides a method for obtaining asynchronous paths for chips, including:

[0006] During the process of performing static timing analysis on the test chip, perform timing violation checks on the test chip by adding timing analysis commands;

[0007] Based on the timing violation check results, obtain asynchronous paths;

[0008] Traverse the start endpoint and end endpoint of the asynchronous path, and perform preliminary screening on the asynchronous path according to the clock signals traversed;

[0009] Exclude the registers associated with the asynchronous path according to the clock-beating nodes of the synchronizer to achieve secondary screening of the asynchronous path.

[0010] Optionally, the performing timing violation checks on the test chip by adding timing analysis commands includes:

[0011] Add an option for the timing analysis command in the clock constraint command;

[0012] Set a maximum delay constraint value between each clock group, and perform a timing violation check on the test chip with the maximum delay constraint value.

[0013] Optionally, the preliminary screening of the asynchronous path according to the traversed clock signal includes:

[0014] According to the clock signal of the end point of the current asynchronous path, traverse the clock signal corresponding to the start point of the current asynchronous path;

[0015] If the clock signal corresponding to the start point has been traversed by other asynchronous paths, exclude the current asynchronous path.

[0016] Optionally, the preliminary screening of the asynchronous path according to the traversed clock signal includes:

[0017] Judge whether the clock signals of the start point and the end point in the current asynchronous path are the same;

[0018] If so, exclude the current asynchronous path.

[0019] Optionally, the method further includes:

[0020] Obtain the port types and register types of the start point and the end point in the asynchronous path;

[0021] Exclude asynchronous paths with preset port types and preset register types.

[0022] Optionally, the exclusion of the registers associated with the asynchronous path according to the beating nodes of the synchronizer includes:

[0023] Obtain the fan-in number of the first beating node of the synchronizer in the asynchronous path;

[0024] If the fan-in number is greater than the preset fan-in number, exclude the register corresponding to the first beating node.

[0025] Optionally, the exclusion of the registers associated with the asynchronous path according to the beating nodes of the synchronizer includes:

[0026] Obtain the fan-out numbers of the first beating node and the second beating node of the synchronizer in the asynchronous path;

[0027] If the fan-out number is greater than 1, exclude the register corresponding to the first beating node or the second beating node.

[0028] The present application also provides an asynchronous path acquisition device for a chip, including:

[0029] An inspection module, configured to perform a timing violation inspection on the test chip by adding a timing analysis command during the static timing analysis of the test chip;

[0030] An acquisition module, configured to acquire an asynchronous path based on the timing violation inspection result;

[0031] A first screening module, configured to traverse the start endpoint and the end endpoint of the asynchronous path, and perform a preliminary screening on the asynchronous path according to the clock signal traversed;

[0032] A second screening module, configured to exclude the registers associated with the asynchronous path according to the flop nodes of the synchronizer, so as to perform a secondary screening on the asynchronous path.

[0033] The present application also provides an electronic device, characterized in that the electronic device includes a memory and a processor, a computer program is stored in the memory, and the processor executes the steps in any one of the asynchronous path acquisition methods for a chip provided by the present application by calling the computer program stored in the memory.

[0034] The present application also provides a storage medium, characterized in that the storage medium stores a computer program, and the computer program is suitable for being loaded by a processor to execute the steps in any one of the asynchronous path acquisition methods for a chip provided by the present application.

[0035] The asynchronous path acquisition method for a chip provided by the present application can perform a timing violation inspection on the test chip by adding a timing analysis command during the static timing analysis of the test chip, acquire an asynchronous path based on the timing violation inspection result, traverse the start endpoint and the end endpoint of the asynchronous path, and perform a preliminary screening on the asynchronous path according to the clock signal traversed, and exclude the registers associated with the asynchronous path according to the flop nodes of the synchronizer, so as to perform a secondary screening on the asynchronous path. The present application grabs the asynchronous path from the timing report by constructing a timing violation, and performs screening based on the endpoints of the asynchronous path, effectively improving the grabbing and screening efficiency of the asynchronous path. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 is a schematic flowchart of a method for obtaining an asynchronous path for a chip provided by an embodiment of the present application;

[0038] Figure 2 is a schematic diagram of the clock signal flow direction in the asynchronous path provided by an embodiment of the present application;

[0039] Figure 3 is the second schematic diagram of the clock signal flow direction in the asynchronous path provided by an embodiment of the present application;

[0040] Figure 4 is a schematic diagram of clock signal pipelining in the asynchronous path provided by an embodiment of the present application;

[0041] Figure 5 is another schematic flowchart of a method for obtaining an asynchronous path for a chip provided by an embodiment of the present application;

[0042] Figure 6 is a schematic structural diagram of an apparatus for obtaining an asynchronous path for a chip provided by an embodiment of the present application;

[0043] Figure 7 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed Embodiments

[0044] Here, exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0045] It should be noted that in this document, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including that element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0046] It should be understood that although the steps in the flowchart in the embodiments of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and they can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same moment, but can be executed at different moments, and their execution order is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0047] It should be noted that in this article, step codes such as 101 and 102 are used. The purpose is to more clearly and briefly express the corresponding content and do not constitute a substantial limitation in terms of order. Those skilled in the art may execute 102 first and then 101 when implementing specifically, but these should all be within the protection scope of the present application.

[0048] The mention of "embodiment" in this article means that the specific features, structures or characteristics described in combination with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0049] The embodiments of the present application provide a method for obtaining an asynchronous path for a chip. The execution subject of the method for obtaining an asynchronous path for a chip can be the device for obtaining an asynchronous path for a chip provided by the embodiments of the present application, or a server integrated with the device for obtaining an asynchronous path for a chip, where the device for obtaining an asynchronous path for a chip can be implemented in a hardware or software manner.

[0050] As Figure 1 shown, Figure 1 is the first flowchart of the method for obtaining an asynchronous path for a chip provided by the embodiments of the present application. The specific process of the method for obtaining an asynchronous path for a chip can be as follows:

[0051] 101. During the process of performing static timing analysis on the test chip, perform timing violation check on the test chip by adding timing analysis commands.

[0052] In one embodiment, Static Timing Analysis (STA) is a method used in electronic engineering to analyze and verify the timing of digital circuits. It ensures the ability of the circuit to operate at a specified rate by calculating and predicting the delays of the circuit at different operating stages. Based on the normal STA constraint definition process for the test chip, in this embodiment, the option of -allow_paths (a timing analysis command) is added to the set_clock_groups (clock constraint command) in the constraints to enable the timing violation check for asynchronous paths.

[0053] Specifically, in the constraint file, first use the set_clock_groups command to define asynchronous clock groups. This command is used to define two or more clocks as asynchronous relationships, so that the tool ignores the paths between these clocks during timing analysis. After defining the asynchronous clock groups, in order to enable the timing violation check for asynchronous paths, the -allow_paths option needs to be added to the set_clock_groups command. For asynchronous clocks, the STA tool will still perform timing checks on the paths between them to detect possible timing problems. After adding the above command to the constraint file, execute the corresponding command of the timing analysis tool to perform timing analysis on the entire design. Then the STA tool will comprehensively check all paths according to the defined constraints, including the newly added -allow_paths option, including the originally ignored asynchronous paths. After the timing analysis is completed, a timing report can be generated. The report will list in detail the timing margins, violation information, etc. of each path. Due to the addition of the -allow_paths option, the timing situation of the asynchronous paths will also be checked and reported, so that developers can clearly see whether there are timing violations in the asynchronous paths.

[0054] 102. Obtain asynchronous paths based on the timing violation check results.

[0055] In one embodiment, for example, when performing asynchronous path analysis on a large SoC with 10 million register levels, there will be a large number of endpoints caused by asynchronous path violations. To obtain these endpoints, it can be achieved through the reporting function of the timing analysis tool. The specific method can depend on the STA tool used. Generally, all violated endpoints will be listed in the timing violation report.

[0056] Further, after obtaining the endpoints, traverse these endpoints and use the get_timing_path command to obtain the corresponding asynchronous paths. The specific command format can be get_timing_path -to$endpoint -slack_lesser_than -1000, where -to$endpoint indicates that the specified end point is the currently traversed endpoint, and -slack_lesser_than -1000 indicates to filter out the paths with a timing margin less than -1000, so as to ensure that the asynchronous paths with timing problems are obtained. By executing this command, the detailed asynchronous path information corresponding to each endpoint can be obtained, and then the subsequent filtering of these asynchronous paths can be performed.

[0057] 103. Traverse the start and end points of the asynchronous paths, and perform a preliminary screening of the asynchronous paths according to the traversed clock signals.

[0058] Specifically, please refer to Figure 2 , which shows the connection relationship between clka and clkb, clkc, and the position of the mux (multiplexer). Among them, clka, clkb, and clkc are clock signals. When clka is asynchronous with clkb and clkc respectively, the paths from the same startpoint to the endpoint will be captured twice in the cases of clka to clkb and clka to clkc, which will cause data redundancy. Therefore, to avoid this situation, in this embodiment, for each endpoint, when traversing its paths, if a certain startpoint has been found, then if the subsequent paths encounter the same startpoint again, it will be ignored, so as to eliminate redundancy. That is, the above-mentioned action of performing a preliminary screening of the asynchronous paths according to the traversed clock signals can include: according to the clock signal of the end point of the current asynchronous path, traverse the clock signal corresponding to the start point of the current asynchronous path. If the clock signal corresponding to the start point has been traversed by other asynchronous paths, then the current asynchronous path is excluded.

[0059] In one embodiment, please continue to refer to Figure 3 In Figure 3In the circuit, CLKA and CLKB are connected to the start point through a MUX, and for the path from the start point to the end point, when CLKA and CLKB are asynchronous, but after being selected by the MUX, the clocks reaching the start point and the end point can only be CLKA simultaneously or CLKB simultaneously. However, the STA tool will mistakenly consider that there is an asynchronous path from CLKA to CLKB or from CLKB to CLKA, resulting in false alarms. Therefore, to avoid this situation, in this embodiment, a check can be performed. If the start point and the end point have the same set of clocks, then it will be excluded and not considered as a real asynchronous path. That is to say, the step of preliminarily screening the asynchronous path according to the traversed clock signals can further include: determining whether the clock signals of the start point and the end point in the current asynchronous path are the same. If so, the current asynchronous path will be excluded.

[0060] 104. Exclude the registers associated with the asynchronous path according to the flop nodes of the synchronizer to achieve a secondary screening of the asynchronous path.

[0061] In one embodiment, the synchronizer usually performs a 2-flop or 3-flop operation on the signals crossing the asynchronous clock domain. The flop operation here is to enable the asynchronous signals to be stably sampled and processed in the new clock domain. As Figure 4 shown, among them, the first flop corresponds to the endpoint (end point) of the asynchronous path mentioned above. Therefore, based on the previously obtained asynchronous path and the endpoint, the flop synchronizer can be further screened.

[0062] Specifically, in a normal cross-asynchronous flop design, there should be no combinational logic between the start point (start point) and the end point. This is because combinational logic may introduce some unstable factors, affecting the correct transmission and sampling of signals. Therefore, except for some static stable signals, the fan-in source of the end point should normally only be the start point. If the fan-in number of the end point is greater than a set threshold (for example, it can be set to 10), it indicates that there may be an abnormality and it needs to be excluded. That is to say, the step of excluding the registers associated with the asynchronous path according to the flop nodes of the synchronizer can include: obtaining the fan-in number of the first flop node of the synchronizer in the asynchronous path. If the fan-in number is greater than the preset fan-in number, the register corresponding to the first flop node will be excluded.

[0063] Furthermore, continue to refer to Figure 4, during the process from the first beat ff1 to the second beat ff2 of the beat, from the perspective of functional design, there should be no bifurcation. That is to say, the signal should be transmitted in a straight line without other branches. That is, the fan-out of ff1, except for the scan logic of DFT (design for testability), should normally have only one register ff2. Therefore, in this embodiment, if the fan-out number of ff1 is greater than 1, it does not meet the normal design requirements and needs to be excluded. Similarly, for the fan-out of ff2, the DFT logic should also be excluded. If its fan-out number is greater than 1, it also needs to be excluded. That is, the above step of excluding the registers associated with the asynchronous path according to the beat nodes of the synchronizer may further include: obtaining the fan-out numbers of the first beat node and the second beat node of the synchronizer in the asynchronous path. If the fan-out number is greater than 1, the register corresponding to the first beat node or the second beat node is excluded.

[0064] The embodiment of the present application uses the establishment of a timing violation report to find asynchronous paths. Set the constraint that the max_delay is less than a certain negative value between asynchronous clock groups, and use the -allow_paths option of the PrimeTime constraint command set_clock_groups to artificially construct a timing violation less than this negative value for all asynchronous paths. In this way, through one round of timing analysis (about 5 - 10 hours for a large chip), the asynchronous paths can be obtained through the endpoints in the timing violation report, greatly improving the capture efficiency. In addition, this embodiment also provides a corresponding filtering and screening method, which increases the speed and accuracy of screening and excluding redundant paths based on the endpoints, and further provides a method for filtering out the synchronizers of asynchronous beats.

[0065] As described above, the method for obtaining asynchronous paths of a chip proposed by the embodiment of the present application can, during the process of static timing analysis of a test chip, perform timing violation checks on the test chip by adding timing analysis commands, obtain asynchronous paths based on the timing violation check results, traverse the start endpoints and end endpoints of the asynchronous paths, and perform a preliminary screening of the asynchronous paths according to the clock signals traversed. Exclude the registers associated with the asynchronous path according to the beat nodes of the synchronizer to achieve a secondary screening of the asynchronous paths. The present application captures asynchronous paths from the timing report by constructing timing violations and screens based on the endpoints of the asynchronous paths, effectively improving the capture and screening efficiency of asynchronous paths.

[0066] According to the method described in the previous embodiments, the following will be further described in detail.

[0067] Please refer to Figure 5 , Figure 5 which is the second flow diagram of the method for obtaining asynchronous paths of a chip provided by the embodiment of the present application. The method includes:

[0068] 201. During the process of performing static timing analysis on a test chip, add an option for the timing analysis command in the clock constraint command.

[0069] Specifically, based on the normal STA constraint definition process, the -allow_paths option can be added to the set_clock_groups command in the constraint. The purpose of this operation is to enable the timing violation check for asynchronous paths and create conditions for constructing and detecting the timing violations of asynchronous paths in the subsequent process.

[0070] 202. Set a maximum delay constraint value between each clock group and perform a timing violation check on the test chip using the maximum delay constraint value.

[0071] In one embodiment, set a constraint where set_max_delay (maximum delay constraint) is less than a relatively large negative number (such as -1000 ns) for each clock group of set_clock_groups (i.e., between asynchronous clocks), artificially constructing a setup violation for the asynchronous path. At the initial stage of timing analysis, although there will be relatively large setup violations for normal synchronous paths, generally within -100 ns. Therefore, after one round of STA analysis, paths with setup violations ≤ -1000 ns can be identified as asynchronous paths, effectively distinguishing asynchronous paths from normal synchronous paths and improving the accuracy and pertinence of the analysis.

[0072] 203. Obtain asynchronous paths based on the timing violation check results.

[0073] Among them, for a large-scale SoC with 10 million registers, approximately 100,000 endpoints caused by asynchronous path violations will be generated. By traversing these endpoints and using commands such as get_timing_path -to $endpoint -slack_lesser_than -1000, the corresponding asynchronous paths can be obtained. This method of obtaining based on endpoints greatly reduces the processing time and computational volume compared to the traditional traversal method from the register or clock domain dimension, improving the capture efficiency.

[0074] 204. Traverse the start and end endpoints of the asynchronous path and perform a preliminary screening of the asynchronous path according to the clock signals traversed.

[0075] In one embodiment, for the same startpoint->endpoint path, if it is repeatedly captured in different asynchronous clock combinations (such as clka->clkb and clka->clkc), then in subsequent processing, when traversing to an already existing startpoint, this path can be ignored to eliminate redundancy. Additionally, if the startpoint and endpoint have the same set of clocks, it indicates that there may not be a true asynchronous path, and it should be excluded. For example, in some circuit structures, after mux selection, the clocks reaching the startpoint and endpoint should be a specific clock simultaneously. If the tool misjudges it as an asynchronous path, this rule is needed to correct it to ensure that the selected paths are indeed asynchronous paths and improve the accuracy of screening.

[0076] 205. Obtain the port types and register types of the startpoint and endpoint in the asynchronous path, and exclude the asynchronous paths for the preset port types and preset register types.

[0077] Specifically, when the endpoint or startpoint is the IO of the chip, it is excluded. Because the IO of the chip follows a dedicated interface transmission protocol based on its multiplexing function, and its asynchronous relationship is usually not within the scope of this analysis, which can reduce the complexity of the analysis and the interference of irrelevant paths.

[0078] In addition, if the endpoint or startpoint is a DFT-related register, it is also excluded. This is because the DFT logic has its own independent clock constraint system, which is different from the synchronous and asynchronous checking method of the functional clock, and there is no need to analyze it here, further focusing on the analysis of the core functional asynchronous paths.

[0079] 206. Exclude the registers associated with the asynchronous path according to the clock-beating nodes of the synchronizer to perform a secondary screening of the asynchronous path.

[0080] In one embodiment, the normal cross-asynchronous clock-beating design requires no combinational logic between the startpoint and the endpoint. Therefore, if the fan-in sources of the endpoint are more than the startpoint (such as the fan-in number is greater than the set threshold of 10) except for static stable signals, then this path is excluded. Additionally, during the clock-beating process, such as from the first clock-beating flip-flop ff1 to the second flip-flop ff2, there should be no bifurcation in the functional design, that is, the fan-out of ff1 should have only one register ff2 except for the dft scan logic. If the fan-out number > 1, it is excluded. Similarly, if the fan-out of ff2 is > 1 after excluding the dft logic, it also needs to be excluded to ensure the correctness and consistency of the clock-beating process.

[0081] In addition, if ff1 / ff2 / ff3 are not in the same synchronizer level (with a large difference in level names), they must not be the beats in the same synchronizer and should be excluded to ensure that the selected registers indeed belong to the beat path of the effective synchronizer, thereby improving the accuracy of the screening. Finally, according to the register naming rules, the remaining results can be classified into three levels: "confirmed", "doubtful", and "excluded" for reporting, which is convenient for subsequent further verification and analysis. Among them, those that conform to the general naming rules (such as those with ff1 / ff2 / sample_meta / sample_sync) are regarded as the "confirmed" beat registers, those with specific names (such as fifo_reg / mem_reg / data_reg, etc.) are asynchronous fifo storage units and are excluded, and the rest are analyzed manually as "doubtful" to further improve the reliability and effectiveness of the screening.

[0082] As described above, the method for obtaining the asynchronous path of a chip proposed in the embodiment of the present application can, during the process of performing static timing analysis on the test chip, add an option of a timing analysis command to the clock constraint command, set a maximum delay constraint value between each clock group, and perform a timing violation check on the test chip based on the maximum delay constraint value. Based on the timing violation check results, the asynchronous path is obtained, the start and end points of the asynchronous path are traversed, and the asynchronous path is initially screened according to the clock signals traversed to obtain the port types and register types of the start and end points in the asynchronous path. The asynchronous paths with preset port types and preset register types are excluded, and the registers associated with the asynchronous path are excluded according to the beat nodes of the synchronizer, so as to achieve a secondary screening of the asynchronous path. The present application grabs the asynchronous path from the timing report by constructing a timing violation, and screens based on the endpoints of the asynchronous path, effectively improving the grabbing and screening efficiency of the asynchronous path.

[0083] To implement the above method, the embodiment of the present application also provides an apparatus for obtaining the asynchronous path of a chip, and the apparatus for obtaining the asynchronous path of a chip can be specifically integrated in a terminal device such as a mobile phone, a tablet computer, etc.

[0084] For example, as Figure 6 shown, it is a schematic structural diagram of an apparatus for obtaining the asynchronous path of a chip provided by the embodiment of the present application. The apparatus for obtaining the asynchronous path of a chip may include:

[0085] An inspection module 301, configured to perform a timing violation check on the test chip by adding a timing analysis command during the process of performing static timing analysis on the test chip;

[0086] An obtaining module 302, configured to obtain an asynchronous path based on the timing violation check results;

[0087] The first screening module 303 is configured to traverse the start endpoint and the end endpoint of the asynchronous path, and perform a preliminary screening on the asynchronous path according to the clock signals traversed.

[0088] The second screening module 304 is configured to exclude the registers associated with the asynchronous path according to the clock-beating nodes of the synchronizer, so as to perform a secondary screening on the asynchronous path.

[0089] As can be seen from the above, the asynchronous path acquisition device for a chip proposed in the embodiment of the present application can, during the process of performing static timing analysis on a test chip, perform a timing violation check on the test chip by adding a timing analysis command. Based on the timing violation check result, an asynchronous path is acquired, the start endpoint and the end endpoint of the asynchronous path are traversed, and the asynchronous path is preliminarily screened according to the clock signals traversed. The registers associated with the asynchronous path are excluded according to the clock-beating nodes of the synchronizer, so as to perform a secondary screening on the asynchronous path. The present application captures the asynchronous path from the timing report by constructing a timing violation, and performs screening based on the endpoints of the asynchronous path, effectively improving the capture and screening efficiency of the asynchronous path.

[0090] Any combination of the above technical solutions can form an optional embodiment of the present application, which will not be elaborated herein one by one.

[0091] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0092] Therefore, the embodiment of the present application provides a computer-readable storage medium, in which multiple computer programs are stored. The computer programs can be loaded by a processor to execute the steps in any one of the methods for acquiring an asynchronous path for a chip provided by the embodiment of the present application. For example, the computer program can execute the following steps:

[0093] During the process of performing static timing analysis on a test chip, perform a timing violation check on the test chip by adding a timing analysis command;

[0094] Based on the timing violation check result, acquire an asynchronous path;

[0095] Traverse the start endpoint and the end endpoint of the asynchronous path, and perform a preliminary screening on the asynchronous path according to the clock signals traversed;

[0096] Exclude the registers associated with the asynchronous path according to the clock-beating nodes of the synchronizer, so as to perform a secondary screening on the asynchronous path.

[0097] For the specific implementation of each of the above operations, reference may be made to the foregoing embodiments, which will not be elaborated herein.

[0098] Among them, the storage medium may include: read-only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, etc.

[0099] Since the computer program stored in the storage medium can execute the steps in any of the asynchronous path acquisition methods for chips provided in the embodiments of the present application, the beneficial effects achievable by any of the asynchronous path acquisition methods for chips provided in the embodiments of the present application can be realized. For details, refer to the foregoing embodiments, which will not be elaborated herein.

[0100] The embodiments of the present application further provide an electronic device, including a memory and a processor. The memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the device installed with the chip executes the methods in the above various possible implementation manners.

[0101] For example, the above computer device may be a terminal device with corresponding functions such as a mobile phone, a tablet computer, a personal computer, a cloud computer, etc. Please refer to Figure 7 , Figure 7 which is the structural schematic diagram of the computer provided in the embodiments of the present application.

[0102] The computer device 400 may include components such as a memory 401 and a processor 402. Those skilled in the art can understand that Figure 7 the structure of the computer device shown in

[0103] does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0104] The memory 401 can be used to store application programs and data. The application programs stored in the memory 401 contain executable codes. The application programs can form various functional modules. The processor 402 executes various functional applications and data processing by running the application programs stored in the memory 401.

[0105] In this embodiment, the processor 402 in the computer device loads the executable code corresponding to the processes of one or more application programs into the memory 401 according to the following instructions, and the processor 402 runs the application programs stored in the memory 401 to perform:

[0106] During the static timing analysis of the test chip, timing violation checks are performed on the test chip by adding timing analysis commands;

[0107] Based on the timing violation check results, asynchronous paths are obtained;

[0108] Traverse the start and end points of the asynchronous path, and perform a preliminary screening of the asynchronous path according to the clock signals traversed;

[0109] Exclude the registers associated with the asynchronous path according to the flop nodes of the synchronizer to achieve a secondary screening of the asynchronous path.

[0110] It can be understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of the present application. The technical solutions of the present application can also be applied to other scenarios. For example, as is known to those of ordinary skill in the art, with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0111] The steps in the method of the embodiments of the present application can be adjusted, combined, and deleted according to actual needs. The modules in the devices of the embodiments of the present application can be combined, divided, and deleted according to actual needs.

[0112] In the present application, for the description of the same or similar term concepts, technical solutions, and / or application scenarios, generally only a detailed description is given when it first appears. When it appears repeatedly later, for the sake of brevity, it is generally not repeated. When understanding the technical solutions and other contents of the present application, for the same or similar term concepts, technical solutions, and / or application scenarios that are not described in detail later, reference can be made to the relevant detailed descriptions before.

[0113] In the present application, the descriptions of the various embodiments have their own emphases. For the parts not described or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0114] The technical features of the technical solutions of the present application can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope recorded in the present application.

[0115] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, a storage disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk).

[0116] The above has introduced in detail a method, apparatus, electronic device, and storage medium for obtaining an asynchronous path for a chip provided by the embodiments of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A method for asynchronous path acquisition for a chip, characterized in that: include: In the process of performing static timing analysis on the test chip, performing timing violation check on the test chip by adding a timing analysis command; Based on the timing violation check result, the asynchronous path is obtained; Traversing the start endpoint and the end endpoint of the asynchronous path, and preliminarily screening the asynchronous path according to the traversed clock signal; Registers associated with the asynchronous path are excluded according to the beat nodes of the synchronizer to achieve secondary screening of the asynchronous path.

2. The asynchronous path acquisition method for a chip according to claim 1, characterized in that: The step of performing a timing violation check on the test chip by adding a timing analysis command comprises: Added the option of timing analysis command in the clock constraint command; A maximum delay constraint value is set between each clock grouping, and a timing violation check is performed on the test chip using the maximum delay constraint value.

3. The asynchronous path acquisition method for a chip according to claim 1, characterized in that: The preliminary screening of the asynchronous path according to the traversed clock signal includes: According to the clock signal of the end endpoint of the current asynchronous path, traverse the clock signal corresponding to the start endpoint of the current asynchronous path; If the clock signal corresponding to the start endpoint has been traversed by other asynchronous paths, the current asynchronous path is excluded.

4. The asynchronous path acquisition method for a chip according to claim 3, characterized in that: The preliminary screening of the asynchronous path according to the traversed clock signal includes: Determine whether the clock signal of the starting endpoint and the clock signal of the ending endpoint in the current asynchronous path are the same; If so, the current asynchronous path is excluded.

5. The asynchronous path acquisition method for a chip according to claim 4, characterized in that: The method further comprises: Obtaining the port type and register type of the starting endpoint and the ending endpoint in the asynchronous path; Asynchronous paths of preset port types and preset register types are excluded.

6. The asynchronous path acquisition method for a chip according to claim 1, characterized in that: The step of excluding the associated registers in the asynchronous path according to the beat node of the synchronizer includes: Obtain the fan-in quantity of the first beat node of the synchronizer in the asynchronous path; If the fan-in number is greater than the preset fan-in number, the register corresponding to the first beat node is excluded.

7. The asynchronous path acquisition method for a chip according to claim 6, characterized in that: The step of excluding the associated registers in the asynchronous path according to the beat node of the synchronizer includes: Obtain the fan-out numbers of the first beat node and the second beat node of the synchronizer in the asynchronous path; If the fan-out quantity is greater than 1, the register corresponding to the first beat node or the second beat node is excluded.

8. An asynchronous path acquisition device for a chip, characterized in that: include: A checking module, used for performing a timing violation check on the test chip by adding a timing analysis command during a static timing analysis on the test chip; An acquisition module, used for acquiring an asynchronous path based on a timing violation check result; A first screening module, used for traversing the start endpoint and the end endpoint of the asynchronous path, and performing preliminary screening on the asynchronous path according to the traversed clock signal; The second screening module is used to exclude the registers associated with the asynchronous path according to the beat nodes of the synchronizer, so as to achieve secondary screening of the asynchronous path.

9. An electronic device, characterized in that: The electronic device includes a memory and a processor, wherein a computer program is stored in the memory, and the processor executes the steps in the asynchronous path acquisition method for a chip according to any one of claims 1 to 7 by calling the computer program stored in the memory.

10. A storage medium, characterized in that: The storage medium stores a computer program, and the computer program is suitable for being loaded by a processor to execute the steps in the asynchronous path acquisition method for a chip according to any one of claims 1 to 7.

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