Display panel and display device including same

Abstract

The present disclosure relates to a display panel and a display device including the same. The display panel may include a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixels. Further, each of the plurality of pixels may include a first light emitting element, a second light emitting element, a compensation section configured to supply a current to the first light emitting element and the second light emitting element, a switching circuit, and a mode control section. The switching circuit is configured to, in response to receiving the mode selection signal, provide a current to the first light emitting element in a first mode, provide a current to the second light emitting element in a second mode, or provide a current to both the first light emitting element and the second light emitting element in the second mode. Further, the mode control section is configured to supply a mode selection signal to the switching circuit.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0193989, filed on December 28, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display panel having a pixel - by - pixel variable viewing angle, and a display device including the display panel. Background art

[0004] Viewing - angle variable technologies are being applied to display devices. The variable viewing - angle technology allows video content or visual information reproduced on a display device to be visible only to users within a narrow viewing - angle range, or to multiple users within a wide viewing - angle range.

[0005] As the market for future vehicles such as electric vehicles and autonomous vehicles expands, the demand for in - vehicle display devices is rapidly increasing. Research is underway on how to divide the screen of an in - vehicle display device so that a part of the screen is controlled with a narrow viewing angle while another part is controlled with a wide viewing angle. This technology can display private content or information that only a specific user can see on pixels driven with a narrow viewing angle, while displaying shared content that multiple users can view together on pixels driven with a wide viewing angle. To achieve this, a pixel technology that can freely control each pixel with a narrow viewing angle and a wide viewing angle is needed. Summary of the invention

[0006] The present disclosure is made to solve the above - mentioned needs and / or disadvantages.

[0007] The present disclosure provides a display panel capable of selecting a viewing angle pixel - by - pixel, and a display device including the display panel.

[0008] The problems or limitations to be solved or addressed by the present disclosure are not limited to those described above, and other problems or limitations not mentioned will be clearly understood by those skilled in the art from the following description.

[0009] A display panel according to an embodiment of the present disclosure includes a display panel in which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixels are provided. Each of the pixels includes: a first light-emitting element; a second light-emitting element; a compensation unit configured to supply current to the first light-emitting element and the second light-emitting element; a switching circuit configured to supply the current to the first light-emitting element in a first mode and supply the current to the second light-emitting element in a second mode in response to a mode selection signal, or supply the current to the first light-emitting element and the second light-emitting element in the second mode; and a mode control unit configured to supply the mode selection signal to the switching circuit.

[0010] Each of the pixels may further include a plurality of sub-pixels. Each of the sub-pixels may include a first light-emitting element, a second light-emitting element, a compensation unit, and a switching circuit. The switching circuit may include a first pixel switching element connected between the compensation unit and the first light-emitting element and configured to be turned on / off in response to a first mode selection signal; and a second pixel switching element connected between the compensation unit and the second light-emitting element and configured to be turned on / off in response to a second mode selection signal. The mode control unit may output the first mode selection signal and the second mode selection signal. In the first mode, the first light-emitting element may emit light by the current supplied through the first pixel switching element. In the second mode, the second light-emitting element may emit light by the current supplied through the second pixel switching element.

[0011] The mode control unit may include a first switching element configured to apply the first mode selection signal to a gate electrode of the first pixel switching element in response to a scan signal; and a second switching element configured to apply the second mode selection signal to a gate electrode of the second pixel switching element in response to the scan signal.

[0012] The first switching element may include a first electrode connected to a first control signal line to which the first mode selection signal is applied, a gate electrode to which the scan signal is applied, and a second electrode connected to the gate electrode of the first pixel switching element. The second switching element may include a first electrode connected to a second control signal line to which the second mode selection signal is applied, a gate electrode to which the scan signal is applied, and a second electrode connected to the gate electrode of the second pixel switching element.

[0013] The mode control unit may further include a first capacitor connected between a power supply line to which a constant voltage is applied and a second electrode of the first switching element; and a second capacitor connected between the power supply line to which the constant voltage is applied and a second electrode of the second switching element.

[0014] Each of the pixels may further include a plurality of sub-pixels. Each of the sub-pixels may include a first light-emitting element, a second light-emitting element, a compensation unit, and a switching circuit. The switching circuit may include a pixel switching element connected between the compensation unit and the second light-emitting element and configured to be turned on / off in response to a second mode selection signal. The mode control unit may output the second mode selection signal. In the first mode, the first light-emitting element may emit light through a current from the compensation unit. In the second mode, the first light-emitting element may emit light through the current from the compensation unit, and the second light-emitting element may emit light through a current provided by the pixel switching element.

[0015] The mode control unit may include a switching element configured to apply the second mode selection signal to a gate electrode of the pixel switching element in response to a scan signal.

[0016] The switching element may include a first electrode connected to a control signal line to which the second mode selection signal is applied, a gate electrode to which the scan signal is applied, and a second electrode connected to the gate electrode of the pixel switching element.

[0017] The mode control unit may further include a capacitor connected between a power supply line to which a constant voltage is applied and the second electrode of the switching element.

[0018] The display panel may further include: an EVDD power supply line configured to supply a pixel driving voltage to the compensation unit; and a VDD power supply line configured to supply a constant voltage to the mode control unit.

[0019] The EVDD power supply line may include a first EVDD power supply line; and a second EVDD power supply line connected to the first EVDD power supply line at an intersection therewith. The VDD power supply line may be parallel to or cross the second EVDD power supply line and may be separated from the first EVDD power supply line and the second EVDD power supply line by an insulating layer therebetween.

[0020] The display panel may further include a short circuit line disposed in a non-display area of the display panel; and a plurality of EVSS power supply lines connected to the short circuit line and connected to the compensation unit across the display area of the display panel. The cathode voltage may be supplied to the compensation unit via the short circuit line and the EVSS power supply lines.

[0021] The compensation unit may include a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first compensation switching element connected between the second node and the third node and configured to be turned on in response to a first scan signal; a second compensation switching element connected between a data line to which a data voltage is applied and the first node and configured to be turned on in response to a second scan signal; a third compensation switching element connected between a power supply line to which a pixel driving voltage is applied and the first node and configured to be turned on / off in response to a light emission signal; a fourth compensation switching element connected between the third node and a fourth node and configured to be turned on / off in response to the light emission signal; and a storage capacitor connected between a power supply node to which a pixel driving voltage is applied and the second node. The mode control unit may include one or more switching elements configured to be turned on / off in response to the second scan signal.

[0022] The compensation unit may further include a fifth compensation switching element connected between the second node and a power supply line to which an initialization voltage is applied and configured to be turned on / off in response to a fourth scan signal; a sixth compensation switching element connected between the fifth node and a power supply line to which a first compensation voltage is applied and configured to be turned on / off in response to a third scan signal; a seventh compensation switching element connected between the sixth node and the power supply line to which the first compensation voltage is applied and configured to be turned on / off in response to the third scan signal; and an eighth compensation switching element connected between the first node and a power supply line to which a second compensation voltage is applied and configured to be turned on / off in response to the third scan signal. The switching circuit may include a first pixel switching element connected between the fourth node and the fifth node and configured to be turned on in the first mode to supply current from the driving element to the first light-emitting element; and a second pixel switching element connected between the fourth node and the sixth node and configured to be turned on in the second mode to supply current from the driving element to the second light-emitting element. The first light-emitting element may include an anode electrode connected to the fifth node and a cathode electrode connected to a power supply line to which a cathode voltage is applied. The second light-emitting element may include an anode electrode connected to the sixth node and a cathode electrode connected to the power supply line to which the cathode voltage is applied.

[0023] The compensation unit may further include a fifth compensation switching element connected between the second node and a power supply line to which an initialization voltage is applied and configured to be turned on / off in response to a fourth scan signal; a sixth compensation switching element connected between the fourth node and a power supply line to which a first compensation voltage is applied and configured to be turned on / off in response to a third scan signal; a seventh compensation switching element connected between the fifth node and a power supply line to which the first compensation voltage is applied and configured to be turned on / off in response to the third scan signal; and an eighth compensation switching element connected between the first node and a power supply line to which a second compensation voltage is applied and configured to be turned on / off in response to the third scan signal. The switching circuit may include a pixel switching element connected between the fourth node and the fifth node and configured to be turned on in the second mode to supply current from the driving element to the second light-emitting element. The first light-emitting element may include an anode electrode connected to the fourth node and a cathode electrode connected to a power supply line to which a cathode voltage is applied. The second light-emitting element may include an anode electrode connected to the fifth node and a cathode electrode connected to a power supply line to which the cathode voltage is applied.

[0024] A display device according to an embodiment includes: a display panel including a plurality of data lines, a plurality of gate lines, a plurality of power supply lines, and a plurality of pixels; a data driver configured to supply a data voltage to the data lines; and a gate driver configured to supply a scan signal and a light-emitting signal to the gate lines. Each of the pixels includes: a first light-emitting element; a second light-emitting element; a compensation unit configured to receive the data voltage, the scan signal, and the light-emitting signal and supply current to the first light-emitting element and the second light-emitting element; a switching circuit configured to supply the current to the first light-emitting element in a first mode and to the second light-emitting element in a second mode, or supply the current to the first light-emitting element and the second light-emitting element in the second mode, in response to a mode selection signal; and a mode control unit configured to supply the mode selection signal to the switching circuit in response to the scan signal.

[0025] The present disclosure can minimize circuit elements and wires for separately providing a mode selection signal to each pixel and can control the viewing angle pixel by pixel.

[0026] The present invention can optimize the process of a display panel that adjusts the viewing angle pixel by pixel, and improve the yield by minimizing the number of circuit elements and wirings used to drive each pixel at a narrow viewing angle and a wide viewing angle.

[0027] The present disclosure can reduce the power consumption of the display panel and increase its lifespan.

[0028] The present disclosure can reduce the interference of the constant voltage between the compensation unit and the mode control unit.

[0029] The present disclosure can freely control the size and shape of the pixel regions driven at a narrow viewing angle and the pixel regions driven at a wide viewing angle by changing the viewing angle pixel by pixel.

[0030] The effects of the present disclosure are not limited to the above effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by referring to the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein:

[0032] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0033] Figure 2 is a circuit diagram showing a pixel according to an embodiment of the present disclosure;

[0034] Figure 3 is a diagram showing an input to Figure 2 the signal waveform diagram of the mode control unit shown;

[0035] Figure 4 is a circuit diagram showing a pixel according to another embodiment of the present disclosure;

[0036] Figure 5 is a diagram showing an input to Figure 4 the signal waveform diagram of the mode control unit shown;

[0037] Figure 6 is a diagram showing an example of a lens disposed above the light-emitting element;

[0038] Figure 7 is a diagram showing an example of controlling the viewing angle pixel by pixel;

[0039] Figure 8 is a diagram showing Figure 2 the operation of the pixel circuit shown in Figure 7 for each pixel region shown in

[0040] Figure 9 is a diagram showing a transmission path of a mode selection signal;

[0041] Figure 10 is a circuit diagram showing in detail a compensation unit of a pixel circuit according to an embodiment of the present disclosure;

[0042] Figures 11A to 11C is showing an input to Figure 10 an example waveform diagram of a gate signal and a mode selection signal input to the pixel circuit shown;

[0043] Figure 12 is a circuit diagram showing in detail a compensation unit of a pixel circuit according to another embodiment of the present disclosure;

[0044] Figure 13 is showing an input to Figure 12 an example waveform diagram of a gate signal and a mode selection signal input to the pixel circuit shown;

[0045] Figure 14 is a plan view showing an example of electrical separation of a power supply line between a compensation unit and a mode control unit of a pixel circuit;

[0046] Figure 15 is showing along Figure 14 a cross-sectional view of the power supply line taken along line "I-I" in; and

[0047] Figure 16 is a plan view showing an example in which a power supply line to which a cathode voltage is applied overlaps a compensation unit of a pixel circuit. DETAILED DESCRIPTION

[0048] According to the embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and the method for realizing them will be more clearly understood. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, the present embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0049] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, the same reference numerals generally denote the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily making the subject matter of the present disclosure difficult to understand.

[0050] Terms such as "comprising", "including", "having", and "containing" used in this document are generally intended to allow the addition of other components, unless these terms are used with the term "only". Any reference to the singular may include the plural unless otherwise explicitly stated.

[0051] Even if not explicitly stated, components are interpreted as including a normal error range.

[0052] When describing the positional or interconnection relationship between two components, such as "on top of", "above", "below", "next to", "connected or coupled to", "across", "cross", etc., one or more other components may be inserted between them unless "immediately" or "directly" is used.

[0053] When describing the time precedence relationship, such as "after", "subsequent to", "immediately following", "before", etc., it may not be continuous on the time base unless "instantly" or "directly" is used.

[0054] Terms such as "first", "second", etc. may be used to distinguish elements from each other, but the function or structure of the component is not limited by the ordinal number or the component name in front of the component.

[0055] The following embodiments may be combined or combined partially or completely with each other, and may be connected and operated in various ways technically. The embodiments may be executed independently of each other or in association with each other.

[0056] The pixel circuit and the gate circuit of the display device may include a plurality of transistors. The transistors may be implemented as thin film transistors (TFTs). The transistors may be implemented as oxide thin film transistors (TFTs) including oxide semiconductors, low temperature polycrystalline silicon TFTs (LTPS TFTs) including low temperature polycrystalline silicon, etc.

[0057] A transistor is a three - electrode element including a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is the electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. The n - channel transistor has a current direction from the drain to the source. In the case of a p - channel transistor (p - channel metal - oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. Note that the source and drain of a transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of the transistor are referred to as the first electrode and the second electrode.

[0058] The gate signal swings between a gate - on voltage and a gate - off voltage. The transistor is turned on in response to the gate - on voltage and turned off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage can be a gate - high voltage VGH, and the gate - off voltage can be a gate - low voltage VGL. In the case of a p - channel transistor, the gate - on voltage can be a gate - low voltage VGL, and the gate - off voltage can be a gate - high voltage VGH.

[0059] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0060] Reference Figure 1 According to an embodiment of the present disclosure, a display device includes a display panel 100 and a display - panel driving circuit for writing pixel data to pixels of the display panel 100. The display device further includes a power supply 150.

[0061] The display panel 100 can be, but is not limited to, a panel having a rectangular structure with a length in the X - axis direction, a width in the Y - axis direction, and a thickness in the Z - axis direction. For example, the display panel 100 can be a deformed panel that is at least partially curved or elliptical.

[0062] The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include a plurality of power supply lines. The power supply lines are connected to the constant voltage nodes of the pixel circuits and supply the constant voltage required to drive the pixels 101. The power supply lines may be implemented as strip or grid-like wirings to commonly connect to the pixels 101 of the display panel 100.

[0063] The power supply lines may be commonly connected to the pixel circuits and supply the voltage required to drive the pixels 101.

[0064] Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to achieve color. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels includes a compensation unit for driving a light-emitting element. Each of the pixels 101 may further include a mode control unit to control the viewing angle. The light-emitting element may be a light-emitting element such as an organic light-emitting diode (OLED) or a micro light-emitting diode (micro LED). Hereinafter, the pixel may be interpreted as a sub-pixel.

[0065] Each of the sub-pixels may include one or more first light-emitting elements that emit light in a first mode and a second light-emitting element that emits light in a second mode. Each of the pixels 101 emits light from the first light-emitting elements with a wide viewing angle in the first mode and emits light from the second light-emitting elements with a narrow viewing angle in the second mode.

[0066] The display array AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged in the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel row may share the gate line 103. The sub-pixels arranged in the column direction (Y direction) may share the same data line 102. One horizontal period is the time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0067] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device, where an image is displayed on the screen and an actual object is visible outside the display panel. The display panel 100 may be manufactured as a flexible display panel that can be flexibly bent.

[0068] Power supply 150 receives an input voltage from the host system 200 and outputs voltages required to drive the pixels 101 of the display panel 100 and the display panel driving circuit. To this end, the power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 150 may output a constant voltage (or DC voltage) through the DC-DC converter, such as a gate high voltage, a gate low voltage, a pixel driving voltage, a cathode voltage, an initialization voltage, a first compensation voltage, a second compensation voltage, and an IC driving voltage for the display panel driving circuit. The gate high voltage and the gate low voltage may be supplied to the level shifter 140 and the gate driver 120. Voltages such as the pixel driving voltage, the cathode voltage, the initialization voltage, the first compensation voltage, and the second compensation voltage are supplied to the pixels 101 via power lines commonly connected to the pixels 101.

[0069] The power supply 150 may further include a gamma voltage generator. The gamma voltage generator receives a high potential reference voltage and a low potential reference voltage and outputs a plurality of gamma reference voltages divided at predetermined voltage intervals on a preset gamma curve (e.g., 2.2 gamma curve). The gamma reference voltages are supplied to the data driver 110. In the data driver 110, the gamma reference voltages are divided by a voltage dividing circuit and are subdivided into gray scale voltages. The gamma voltage generator may be implemented as a programmable gamma circuit capable of adjusting each gamma reference voltage according to digital data. The timing controller 130 or the host system 200 or a separate external device may update the digital data stored in the register of the programmable gamma circuit through a communication interface.

[0070] The display panel driving circuit writes the pixel data of the input image into the pixels 101 of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0071] The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver may be integrated into a source driver integrated circuit (IC).

[0072] The data driver 110 receives the pixel data of the input image received as a digital signal from the timing controller 130 and outputs a data voltage. The input image may be image data including various contents such as private content, shared content, etc. The data driver 110 may receive gamma reference voltages and generate gamma compensation voltages for each gray scale through a voltage dividing circuit. The gamma compensation voltages for each gray scale are supplied to digital-to-analog converters (“DACs”) provided on each channel of the data driver 110.

[0073] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data into the DAC. Here, the digital data includes pixel data of the input image. The DAC converts the pixel data into a gamma-compensated voltage and outputs the data voltage of the pixel data.

[0074] The gate driver 120 may be formed on the display panel 100 together with circuit elements and wirings in the display area AA. The gate driver 120 may be disposed in at least one of the left non-display area NA and the right non-display area NA outside the display area AA of the display panel 100, or at least a part thereof may be disposed within the display area AA.

[0075] The gate driver 120 may be disposed in the non-display areas NA on both sides of the display panel 100, with the display area AA of the display panel 100 therebetween, and may provide gate pulses from both sides of the gate line 103 in a dual-feed method. In another embodiment, the gate driver 120 may be disposed in at least one of the left non-display area NA and the right non-display area NA of the display panel 100, so as to provide a gate signal to the gate line 103 in a single-feed method. The gate driver 120 sequentially outputs pulses of the gate signal to the gate line 103 under the control of the timing controller 130. The gate driver 120 may sequentially provide the gate signal to the gate line 103 by shifting the pulses of the gate signal using a shift register and an edge trigger. When a plurality of gate signals are applied to each pixel, the gate driver 120 may include a plurality of shift registers. The gate signal may include a scan signal and a light emission signal (hereinafter referred to as an "EM signal") input to the pixel circuit via a plurality of gate lines.

[0076] The timing controller 130 receives digital video data of the input image and a timing signal synchronized with the data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a period of one horizontal period (1H).

[0077] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a gate timing control signal for controlling the operation timing of the gate driver 120, and a mode selection signal for controlling the viewing angle mode of each pixel 101 based on the timing signals Vsync, Hsync, and DE received from the host system 200, thereby controlling the pixel 101 and the display panel driving circuit. The timing controller 130 synchronizes the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0078] The timing control signal output from the timing controller 130 may be input to the shift register of the gate driver 120 through the level shifter 140. The level shifter 140 may convert the voltage level of the gate timing signal received from the timing controller 130 into a swing width between the gate high voltage and the gate low voltage and provide it to the gate driver 120.

[0079] The mode selection signal output from the timing controller 130 may be input to the level shifter 140. The level shifter 140 converts the mode selection signal received from the timing controller 130 into a first mode selection signal and a second mode selection signal having a swing width between the gate high voltage and the gate low voltage and outputs them.

[0080] The display panel driving circuit may be driven at a variable refresh rate (VRR) under the control of the timing controller 130 or the host system 200. For example, the timing controller 130 may reduce the power consumption of the display device by analyzing the input image and reducing the refresh rate when the input image does not change by a preset amount of time. For example, under the control of the timing controller 130, when a still image is input for a specific period or longer, the display panel driving circuit may reduce the refresh rate of the pixel P to control the data write cycle of the pixel P to be longer, thereby reducing the power consumption of the display device. The driving circuit of the display panel 100 may reduce the refresh rate when the display device operates in the standby mode or in response to a user command. Additionally, the refresh rate may be reduced on an always on display (AOD) screen. The AOD screen is a small pixel area in the display area AA that displays preset information, such as brief information such as the remaining battery level, time, etc., in the standby mode.

[0081] The host system 200 may scale an image signal from a video source to match the resolution of the display panel 100 and may transmit the same to the timing controller 130 together with a timing signal. The host system 200 may transmit a mode signal having different logic values in a first mode and a second mode to the timing controller 130 together with the image signal at least once per frame. The timing controller 130 may output a mode selection signal to select the first mode or the second mode in response to the mode signal from the host system 200.

[0082] As Figure 2 and Figure 4 shown, each of the pixels 101 may include a compensation unit for supplying current to a first light-emitting element and a second light-emitting element; a switching circuit for supplying current to the first light-emitting element in the first mode and supplying current to the second light-emitting element in the second mode in response to the mode selection signal; and a mode control unit for controlling the switching circuit by supplying the mode selection signal to the switching circuit.

[0083] Figure 2 is a circuit diagram showing a pixel according to an embodiment of the present disclosure. Figure 3 is a diagram showing an input to Figure 2 the waveform diagram of the signal input to the mode control unit shown in

[0084] Referring to Figure 2 and Figure 3 , each pixel PIX of the display panel 100 includes a first sub-pixel SPR, a second sub-pixel SPG, a third sub-pixel SPB, and a mode control unit 20. The first sub-pixel SPR may be a red sub-pixel that emits light having a red wavelength with a luminance corresponding to the gray level of the first pixel data. The second sub-pixel SPG may be a green sub-pixel that emits light having a green wavelength with a luminance corresponding to the gray level of the second pixel data. The third sub-pixel SPB may be a blue sub-pixel that emits light having a blue wavelength with a luminance corresponding to the gray level of the third pixel data.

[0085] The pixel circuit of each of the sub-pixels SPR, SPG, and SPB includes a first light-emitting element EL1 that emits light in a first mode (P mode), a second light-emitting element EL2 that emits light in a second mode (S mode), a compensation unit 10 that generates current required to drive the first light-emitting element EL1 and the second light-emitting element EL2, and a switching circuit. The switching circuit includes a first pixel switching element M01 that switches a current path between the compensation unit 10 and the first light-emitting element EL1 and a second pixel switching element M02 that switches a current path between the compensation unit 10 and the second light-emitting element EL2.

[0086] The mode control unit 20 includes a first switching element Tp, a second switching element Ts, a first mode capacitor Cp, and a second mode capacitor Cs.

[0087] The switching elements M01, M02, Tp, and Ts can be implemented as, but are not limited to, p-channel transistors. The gate turn-on voltage of a p-channel transistor is the gate low voltage VGL, and its gate turn-off voltage is the gate high voltage VGH.

[0088] The compensation unit 10 receives the data voltage of the pixel data, the scan signal, the EM signal, and the pixel driving voltage, and generates a current for driving the light-emitting elements EL1 and EL2. The compensation unit 10 can be connected to the data line, the gate line, and the power supply line.

[0089] The first light-emitting element EL1 is connected between the first pixel switching element M01 and the EVSS node to which the cathode voltage EVSS is applied, and emits light when driven by the current applied from the compensation unit 10 through the first pixel switching element M01 in the first mode (P mode). The first light-emitting element EL1 includes an anode electrode connected to the first pixel switching element M01 and a cathode electrode to which the cathode voltage VSS is applied.

[0090] The second light-emitting element EL2 is connected between the second pixel switching element M02 and the EVSS node, and emits light when driven by the current applied from the compensation unit 10 through the second pixel switching element M02 in the second mode (S mode). The second light-emitting element EL2 includes an anode electrode connected to the second pixel switching element M02 and a cathode electrode connected to the EVSS node.

[0091] The first pixel switching element M01 is connected between the compensation unit 10 and the first light-emitting element EL1, and is turned on in response to the gate low voltage VGL of the first mode selection signal P_SEL. When the first pixel switching element M01 is turned on, a current path is formed between the compensation unit 10 and the first light-emitting element EL1, so that the first light-emitting element EL1 can emit light. When the voltage of the first mode selection signal P_SEL is the gate low voltage VGL, the first pixel switching element M01 is turned on. The first pixel switching element M01 includes a first electrode connected to the compensation unit 10, a gate electrode to which the first mode selection signal P_SEL is applied, and a second electrode connected to the anode electrode of the first light-emitting element EL1.

[0092] The second pixel switching element M02 is connected between the compensation unit 10 and the second light-emitting element EL2, and is turned on in response to the gate low voltage VGL of the second mode selection signal S_SEL. When the second pixel switching element M02 is turned on, a current path is formed between the compensation unit 10 and the second light-emitting element EL2, so that the second light-emitting element EL2 can emit light. When the voltage of the second mode selection signal S_SEL is the gate low voltage VGL, the second pixel switching element M02 is turned on. The second pixel switching element M02 includes a first electrode connected to the compensation unit 10, a gate electrode to which the second mode selection signal S_SEL is applied, and a second electrode connected to the anode electrode of the second light-emitting element EL2.

[0093] The mode control unit 20 is synchronized with the compensation unit 10, and when a current is generated from the compensation unit 10, controls the first pixel switching element M01 or the second pixel switching element M02 according to the selected mode. The mode control unit 20 controls the conduction / turn-off of the first pixel switching element M01 using the first mode selection signal P_SEL, and controls the conduction / turn-off of the second pixel switching element M02 using the second mode selection signal S_SEL. Under the control of the mode control unit 20, in the first mode (P mode), the first light-emitting element EL1 can emit light, and in the second mode (S mode), the second light-emitting element EL2 can emit light.

[0094] The first switching element Tp is connected between the first control signal line 22 to which the first mode selection signal P_SEL is applied and the gate electrode of the first pixel switching element M01, and is turned on in response to the gate low voltage VGL of the scan signal SCAN. When the first switching element Tp is turned on, the first mode selection signal P_SEL is applied to the gate electrode of the first pixel switching element M01. Therefore, when the voltage of the first mode selection signal P_SEL is the gate low voltage VGL, the first switching element Tp controls the sub-pixels SPR, SPG, and SPB of the pixel PIX in the first mode (P mode). The first switching element Tp includes a first electrode connected to the first control signal line 22, a gate electrode connected to the gate line to which the scan signal SCAN is applied, and a second electrode connected to the gate electrode of the first pixel switching element M01 and the first mode capacitor Cp.

[0095] The second switching element Ts is connected between the second control signal line 23 to which the second mode selection signal S_SEL is applied and the gate electrode of the second pixel switching element M02, and is turned on in response to the gate low voltage VGL of the scan signal SCAN. When the second switching element Ts is turned on, the second mode selection signal S_SEL is applied to the gate electrode of the second pixel switching element M02. Therefore, when the voltage of the second mode selection signal S_SEL is the gate low voltage VGL, the second switching element Ts controls the sub-pixels SPR, SPG, and SPB of the pixel PIX in the second mode (S mode). The second switching element Ts includes a first electrode connected to the second control signal line 23, a gate electrode connected to the gate line to which the scan signal SCAN is applied, and a second electrode connected to the gate electrode of the second pixel switching element M02 and the second mode capacitor Cs.

[0096] The first mode capacitor Cp charges and holds the voltage of the first mode selection signal P_SEL for one frame period. The first electrode of the first mode capacitor Cp is connected to the second electrode of the first switching element Tp and is connected to the gate electrode of the first pixel switching element M01. The second electrode of the first mode capacitor Cp is connected to the power supply line 21 to which a constant voltage VDD is applied. The second mode capacitor Cs charges and holds the voltage of the second mode selection signal S_SEL for one frame period. The first electrode of the second mode capacitor Cs is connected to the second electrode of the second switching element Ts and is connected to the gate electrode of the second pixel switching element M02. The second electrode of the second mode capacitor Cs is connected to the power supply line 21 to which a constant voltage VDD is applied. The constant voltage VDD can be output from the power supply 150. The constant voltage VDD is not limited to a constant voltage having a specific voltage level. For example, the constant voltage VDD can be replaced with a constant voltage such as a pixel driving voltage, an initialization voltage, a first compensation voltage, a second compensation voltage, etc.

[0097] Figure 4 is a circuit diagram showing a pixel according to another embodiment of the present invention. Figure 5 is shown input to Figure 4Waveform diagram of the signal of the pattern control unit shown. In this embodiment, components that are substantially the same as those in the foregoing embodiment are denoted by the same reference numerals, and will not be described in detail. In this embodiment, the default mode is set to the first mode (P mode). The first light-emitting element EL1 emits light when operating in the first mode (P mode), and the first light-emitting element EL1 and the second light-emitting element EL2 emit light simultaneously when operating in the second mode (S mode). When the first light-emitting element EL1 and the second light-emitting element EL2 emit light simultaneously, the current density is reduced compared to the case where only the first light-emitting element EL1 emits light, whereby the deterioration of the light-emitting elements EL1 and EL2 can be retarded, and the life of the display device can be extended.

[0098] Reference Figure 4 and Figure 5 , the switching circuit includes a pixel switching element M. The pattern control unit 20 includes a switching element Ts and a pattern capacitor Cs. In the pixel circuit of this embodiment, some switching elements are omitted, thereby realizing a circuit structure simpler than the Figure 2 circuit structure shown.

[0099] The pattern control unit 20 is synchronized with the compensation unit 10, so that when a current is generated from the compensation unit 10, the pixel switching element M is controlled by applying the second mode selection signal S_SEL to the gate electrode of the pixel switching element M. Under the control of the pattern control unit 20, in the second mode (S mode), the first light-emitting element EL1 and the second light-emitting element EL2 can emit light.

[0100] The switching element Ts is connected between the control signal line 25 to which the mode selection signal S_SEL is applied and the gate electrode of the pixel switching element M, and is turned on in response to the gate low voltage VGL of the scan signal SCAN. When the switching element Ts is turned on, the mode selection signal S_SEL is applied to the gate electrode of the pixel switching element M. Therefore, when the voltage of the mode selection signal S_SEL is the gate low voltage VGL, the second switching element Ts controls the sub-pixels SPR, SPG, and SPB of the pixel PIX in the second mode (S mode). The switching element Ts includes a first electrode connected to the control signal line 25, a gate electrode connected to the gate line to which the scan signal SCAN is applied, and a second electrode connected to the gate electrode of the pixel switching element M and the pattern capacitor Cs.

[0101] The pattern capacitor Cs charges the voltage of the mode selection signal S_SEL and holds it for one frame period. The first electrode of the pattern capacitor Cs is connected to the second electrode of the switching element Ts and to the gate electrode of the pixel switching element M. The second electrode of the second pattern capacitor Cs is connected to the power supply line 21 to which a constant voltage VDD is applied.

[0102] The pixel switching element M is turned on in response to the gate low voltage VGL of the mode selection signal S_SEL. When the pixel switching element M is turned on, the second light-emitting element EL2 can emit light. When the voltage of the mode selection signal S_SEL is the gate high voltage VGH, the pixel switching element M is turned off to block the current path between the compensation unit 10 and the second light-emitting element EL2, so that the second light-emitting element EL2 does not emit light. The pixel switching element M includes a first electrode connected to the compensation unit 10, a gate electrode to which the second mode selection signal S_SEL is applied, and a second electrode connected to the anode electrode of the second light-emitting element EL2.

[0103] Figure 6 It is a diagram showing an example of a lens provided above the light-emitting element.

[0104] Reference Figure 6 , the first lens 32 can be provided above the first light-emitting element EL1. The second lens 32 can be a hemispherical lens that is thicker at the center and thinner toward the edge. The first lens 32 converges the light emitted from the first light-emitting element EL1 in the first mode (P mode).

[0105] The second lens 34 can be provided on the second light-emitting element EL2. The second lens 34 can be implemented as a semi-cylindrical lens to limit the vertical viewing angle while increasing the horizontal viewing angle. The second lens 34 is long in the left-right direction (or X-axis direction) of the display panel 100 and narrow in the up-down direction (Y-axis direction).

[0106] The first lens 32 and the second lens 34 can be implemented as, but not limited to, a transparent medium or a transparent insulating layer pattern provided in the display panel 100. The first lens 32 and the second lens 34 can achieve a narrow viewing angle and a wide viewing angle for the pixel PIX in the first mode (P mode) and the second mode (S mode). In a vehicle, the first lens 32 and the second lens 34 can limit the vertical viewing angle of the pixel PIX to prevent the light from the pixel from being visible by reflection from the windshield screen of the vehicle.

[0107] Figure 7 It is a diagram showing an example of controlling the viewing angle pixel by pixel. In Figure 7 , the "P-mode pixel region" refers to the first pixel region in the form of a window or a pop-up window driven in the first mode (P mode) within the display area AA. The "S-mode pixel region" refers to the second pixel region driven in the second mode (S mode) within the display area AA. Figure 8 It is a diagram showing Figure 2 the pixel circuit shown in Figure 7 for the operation of each pixel region shown in Figure 8Among them, "DT" represents a driving element used as a constant current source. In one example of the driving element, the driving element DT can be implemented as a transistor to which a pixel driving voltage EVDD is applied, as Figure 10 shown.

[0108] Refer to Figure 7 and 8 , each pixel PIX in the pixel array can be driven in a first mode (P mode) or a second mode (S mode) by the mode control unit 20. Therefore, within the display area AA, only a partial area where an image or private content that requires privacy protection is displayed can be displayed with a narrow viewing angle.

[0109] The pixels in the first pixel area can be driven in the first mode (P mode). Among these pixels PIX, as Figure 8 shown, the first switching element Tp and the first pixel switching element M01 can be turned on to allow the first light-emitting element EL1 to emit light with a narrow viewing angle.

[0110] The pixels in the second pixel area can be driven in the second mode (S mode). Among these pixels PIX, as Figure 8 shown, the second switching element Ts and the second pixel switching element M02 can be turned on to allow the second light-emitting element EL2 to emit light with a wide viewing angle.

[0111] Figure 9 is a diagram showing the transmission path of the mode selection signal. Figure 9 The pixels shown in Figure 2 are the pixels shown in Figure 4 . In the case of the pixels shown in

[0112] Refer to Figure 9 , the display panel 100 may include a plurality of control signal lines 22 and 23.

[0113] The control signal lines 22 and 23 can be implemented as metal lines parallel to the data lines in the Y-axis direction. Each of the control signal lines 22 and 23 can be connected to the pixels PIX arranged along the column direction (y-axis direction) parallel to the data lines.

[0114] The display device may include a circuit board (PCB) and a chip on film (COF) electrically connected to the display panel 100. The source driver IC DIC with the circuit in which the data driver 110 is integrated can be mounted on the flexible film of the COF.

[0115] The control board PCB may include a timing controller 130, a level shifter 140, and a power supply 150. The circuit board PCB can be electrically connected to the COF.

[0116] The COF can be connected between the printed circuit board (PCB) and the display panel 100 to electrically connect the PCB to the display panel 100 and supply the data voltage output from the source driver integrated circuit (DIC) to the data lines on the display panel 100.

[0117] The gate timing control signal and the mode selection signal output from the timing controller 130 can be supplied to the level shifter 140. The level shifter 140 receives the signals from the timing controller 130, the gate high voltage VGH, and the gate low voltage VGL. The level shifter 140 decodes the gate timing control signal to output a start pulse and a clock that swings between the gate high voltage VGH and the gate low voltage VGL. The start pulse and the clock are supplied to the gate driver 120. When the start pulse and the clock are input, the gate driver 120 can output pulses of the gate signal. The level shifter 140 decodes the mode selection signal and outputs a first mode selection signal P_SEL and a second mode selection signal S_SEL that swing between the gate high voltage VGH and the gate low voltage VGL. The first mode selection signal P_SEL is supplied to the pixel PIX via the first dummy line 91 and the first control signal line 22 of the COF. The second mode selection signal S_SEL is supplied to the pixel PIX via the second dummy line 92 and the second control signal line 23 of the COF. The dummy lines 91 and 92 of the COF can be provided on either side of the flexible film and are electrically connected to the control signal lines 22 and 23 of the display panel 100 without being connected to the source driver integrated circuit (DIC).

[0118] Figure 10 is a circuit diagram showing in detail a compensation unit of a pixel circuit according to an embodiment of the present disclosure. Figure 10 The compensation unit shown is only an example of the compensation unit applicable to the pixel circuit of the present disclosure, and the circuit of the compensation unit is not limited to Figure 10 the circuit shown. Figures 11A to 11C is a waveform diagram showing an example of the gate signal and the mode selection signal input to Figure 10 the pixel circuit shown. The mode control unit 20 is substantially the same as Figure 2 the mode selection unit shown, so redundant description thereof is omitted.

[0119] Referring to Figures 10 to 11C , the pixel circuit includes a light-emitting element EL, a driving element DT for supplying current to the light-emitting element EL, a plurality of switching elements T1 to T8, and a capacitor Cst.

[0120] Each of the first compensation switching element T1 and the fifth compensation switching element T5 can be implemented as an n-channel oxide TFT having a low cut-off current characteristic or leakage current in the cut-off state. Except for the first compensation switching element T1 and the fifth compensation switching element T5, the other compensation switching elements T2, T3, T4, T6, T7, and T8, and the driving element DT can be implemented as p-channel LTPS TFTs having good current characteristics in the on state.

[0121] The n-channel oxide TFT turns on in response to a high gate voltage VGH and turns off in response to a low gate voltage VGL. The p-channel LTPS TFT can turn on in response to a low gate voltage VGL and turn off in response to a high gate voltage VGH.

[0122] The compensation unit 10 can be connected to a data line to which a data voltage Vdata having pixel data applied thereto and a gate line to which gate signals SC1 to SC4 and EM are applied. The pixel circuit can be connected to power supply lines, such as a power supply line to which a first compensation voltage VAR is applied, a power supply line to which a second compensation voltage VOBS is applied, a power supply line to which a pixel driving voltage EVDD is applied, a power supply line to which a cathode voltage EVSS is applied, and a power supply line to which an initialization voltage Vinit is applied. On the display panel, the power supply lines can be commonly connected to all pixels PIX.

[0123] The pixel driving voltage EVDD and the cathode voltage EVSS can be set to voltages at which the driving element DT can operate in the saturation region. The pixel driving voltage EVDD can be set to a voltage between 2V and 3V, and the cathode voltage EVSS can be set to a voltage between -8V and -10V, but is not limited thereto. The high gate voltage VGH can be set to a voltage higher than the pixel driving voltage EVDD, and the low gate voltage VGL can be set to a voltage lower than the cathode voltage EVSS, but is not limited thereto.

[0124] The first compensation voltage VAR can be a voltage between -4V and -8V, but is not limited thereto. The first compensation voltage VAR can initialize the anode electrodes of the light-emitting elements EL1 and EL2. When changing the driving frequency of the pixel by applying a variable refresh rate VRR, the first compensation voltage VAR can reduce the visibility of pixel brightness variations. The first compensation voltage VAR can be interpreted as an anode reset voltage or an initialization voltage.

[0125] The second compensation voltage VOBS can be a voltage between 4V and 8V, but is not limited thereto. The second compensation voltage VOBS can increase the gate-source voltage of the driving element DT to change the direction of the current flowing through the channel of the driving element DT, thereby improving the hysteresis of the driving element DT. The second compensation voltage VOBS can be interpreted as a turn-on bias voltage.

[0126] The initialization voltage Vinit can be set to (but not limited to) a voltage lower than the lower limit of the data voltage Vdata and higher than the cathode voltage EVSS. For example, when the data voltage Vdata has a lower limit voltage of 2V and the cathode voltage EVSS is -9V, the initialization voltage Vinit can be set to a voltage between -5V and -7V. The data voltage Vdata can have a dynamic range between 2V and 6V. Within this dynamic range, the voltage level of the data voltage Vdata can be selected according to the gray level value of the pixel data.

[0127] The gate signals SC1 to SC4 and EM can provide pulses that swing between the gate high voltage VGH and the gate low voltage VGL. The gate signals SC1 to SC4 and EM can provide a first scan signal SC1, a second scan signal SC2, a third scan signal SC3, a fourth scan signal SC4, and an EM signal EM.

[0128] The driving element DT can generate a current according to the gate-source voltage to drive the first light-emitting element EL1 and the second light-emitting element EL2. The driving element DT includes a gate electrode connected to the second node N2, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The capacitor Cst is connected between the EVDD node to which the pixel driving voltage VDD is applied and the second node N2. The EVDD node can be connected to a power supply line to which the pixel driving voltage is applied.

[0129] The first light-emitting element EL1 emits light in the first mode (P mode) under the control of the mode control unit 20. The first light-emitting element EL1 includes an anode electrode connected to the fifth node N5 and a cathode electrode connected to the EVSS node to which the cathode voltage EVSS is applied. The second light-emitting element EL2 emits light in the second mode (S mode) under the control of the mode control unit 20. The second light-emitting element EL2 includes an anode electrode connected to the sixth node and a cathode electrode connected to the EVSS node. The EVSS node can be connected to a power supply line to which the cathode voltage is applied.

[0130] The first compensation switch element T1 is connected between the second node N2 and the third node N3. The first compensation switch element T1 is turned on in response to the gate high voltage VGH of the first scan signal SC1. When the first compensation switch element T1 is turned on, the second node N2 can be electrically connected to the third node N3. The first compensation switch element T1 includes a gate electrode connected to the gate line to which the first scan signal SC1 is applied, a first electrode connected to the second node N2, and a second electrode connected to the third node N3.

[0131] The second compensation switching element T2 is connected between the data line to which the data voltage Vdata is applied and the first node N1. The second compensation switching element T2 is turned on in response to the gate low voltage VGL of the second scan signal SC2. When the second compensation switching element T2 is turned on, the data line to which the data voltage Vdata of the pixel data is applied can be electrically connected to the first node N1, so that the data voltage Vdata is applied to the first node N1. The second compensation switching element T2 includes a gate electrode connected to the gate line to which the second scan signal SC2 is applied, a first electrode connected to the data line to which the data voltage Vdata is applied, and a second electrode connected to the first node N1.

[0132] The third compensation switching element T3 is connected between the EVDD node and the first node N1. The third compensation switching element T3 is turned on in response to the gate low voltage VGL of the EM signal EM. When the third compensation switching element T3 is turned on, the pixel driving voltage EVDD can be applied to the first node N1. The third compensation switching element T3 includes a gate electrode connected to the gate line to which the EM signal EM is applied, a first electrode connected to the EVDD node to which the pixel driving voltage EVDD is applied, and a second electrode connected to the first node N1.

[0133] The fourth compensation switching element T4 is connected between the third node N3 and the fourth node N4. The fourth compensation switching element T4 is turned on in response to the gate low voltage VGL of the EM signal EM to electrically connect the third node N3 to the fourth node N4. The fourth compensation switching element T4 includes a gate electrode connected to the gate line to which the EM signal EM is applied, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0134] The fifth compensation switching element T5 is connected between the second node N2 and the INI node to which the initialization voltage Vinit is applied. The fifth compensation switching element T5 is turned on in response to the gate high voltage VGH of the fourth scan signal SC4. When the fifth compensation switching element T5 is turned on, the initialization voltage Vinit can be applied to the second node N2. The fifth compensation switching element T5 includes a gate electrode connected to the gate line to which the fourth scan signal SC4 is applied, a first electrode connected to the second node N2, and a second electrode connected to the INI node to which the initialization voltage Vinit is applied. The INI node can be connected to the power supply line to which the initialization voltage Vinit is applied.

[0135] The sixth compensation switching element T6 is connected between the fifth node N5 and the VAR node to which a first compensation voltage VAR is applied. The sixth compensation switching element T6 is turned on in response to the gate low voltage VGL of the third scan signal SC3. When the sixth compensation switching element T6 is turned on, the first compensation voltage VAR can be applied to the anode electrode of the first light-emitting element EL1 connected to the fifth node N5. The sixth compensation switching element T6 includes a gate electrode connected to the gate line to which the third scan signal SC3 is applied, a first electrode connected to the fifth node N5, and a second electrode connected to the VAR node to which the first compensation voltage VAR is applied. The VAR node can be connected to the power supply line to which the first compensation voltage VAR is applied.

[0136] The seventh compensation switching element T7 is connected between the sixth node N6 and the VAR node. The seventh compensation switching element T7 is turned on in response to the gate low voltage VGL of the third scan signal SC3. When the seventh compensation switching element T7 is turned on, the first compensation voltage VAR can be applied to the anode electrode of the second light-emitting element EL2 connected to the sixth node N6. The seventh compensation switching element T7 includes a gate electrode connected to the gate line to which the third scan signal SC3 is applied, a first electrode connected to the sixth node N6, and a second electrode connected to the VAR node to which the first compensation voltage VAR is applied.

[0137] The eighth compensation switching element T8 is connected between the first node N1 and the OBS node to which a second compensation voltage VOBS is applied. The eighth compensation switching element T8 is turned on in response to the gate low voltage VGL of the third scan signal SC3. When the eighth compensation switching element T8 is turned on, the second compensation voltage VOBS can be applied to the first node N1. The eighth compensation switching element T8 includes a gate electrode connected to the gate line to which the third scan signal SC3 is applied, a first electrode connected to the first node N1, and a second electrode to which the second compensation voltage VOBS is applied.

[0138] The compensation voltages VOBS and VAR can be voltages for compensating for fluctuations in pixel brightness on the time axis when the refresh rate of the pixel is low. When driving the pixel at a constant high refresh rate, the compensation switching elements T6, T7, and T8 for applying the compensation voltages VOBS and VAR to the pixel can be omitted.

[0139] The first pixel switching element M01 is connected between the fourth node N4 and the fifth node N5 to turn on in response to the low gate voltage VGL of the first mode selection signal P_SEL in the first mode (P mode). When the first pixel switching element M01 is turned on, the fourth node N4 can be electrically connected to the fifth node N5, causing the first light-emitting element EL1 to emit light. The first pixel switching element M01 includes a first electrode connected to the fourth node N4, a gate electrode to which the first mode selection signal P_SEL is applied, and a second electrode connected to the fifth node N5.

[0140] The second pixel switching element M02 is connected between the fourth node N4 and the sixth node N6 to turn on in response to the low gate voltage VGL of the second mode selection signal S_SEL in the second mode (S mode). When the second pixel switching element M02 is turned on, the fourth node N4 can be electrically connected to the sixth node N6, causing the second light-emitting element EL2 to emit light. The second pixel switching element M02 includes a first electrode connected to the fourth node N4, a gate electrode to which the second mode selection signal S_SEL is applied, and a second electrode connected to the sixth node N6.

[0141] The mode control unit 20 is synchronized with the compensation unit 10 and controls the first pixel switching element M01 or the second pixel switching element M02 according to the selected mode when current is generated from the compensation unit 10. For example, in response to the low gate voltage VGL of the second scan signal SC2, the second compensation switching element T2, the first switching element Tp, and the second switching element Ts of the compensation unit 10 can be turned on simultaneously.

[0142] The driving period of the pixel can include a first conduction bias period OBS1, an initialization period INI, a sampling period SAM, a second conduction bias period OBS2, and a light-emitting period EMIS, as Figure 11A and Figure 11B shown. A first floating period can be set between the first conduction bias period OBS1 and the initialization period INI, during which the switching elements T1 to T8, M01, M02, Tp, and Ts are turned off. A second floating period can be set between the sampling period SAM and the second conduction bias period OBS2. A third floating period can be set between the second conduction bias period OBS2 and the light-emitting period EMIS. During the floating period, the switching elements T1 to T8, M01, M02, Tp, and Ts can be turned off to float the main nodes N1 to N6.

[0143] During the first conduction bias period OBS1, the voltages of the first scan signal SC1, the third scan signal SC3, and the fourth scan signal SC4 can be the gate low voltage VGL, and the voltages of the second scan signal SC2 and the EM signal EM can be the gate high voltage VGH. During the first conduction bias period OBS1, the sixth compensation switch element T6, the seventh compensation switch element T7, and the eighth compensation switch element T8 are turned on, thereby allowing the second compensation voltage VOBS to be applied to the first node N1 and the first compensation voltage VAR to be applied to the fifth node N5 and the sixth node N6.

[0144] During the first conduction bias period OBS1, the first compensation switch element T1, the second compensation switch element T2, the third compensation switch element T3, the fourth compensation switch element T4, and the fifth compensation switch element T5 can be in the off state. During the first conduction bias period OBS1, the driving element DT can be turned on, but since the fourth compensation switch element T4 is in the off state, no current is supplied to the light-emitting elements EL1 and EL2. Additionally, since the voltage difference between the first compensation voltage VAR and the cathode voltage EVSS is less than the threshold voltages of the light-emitting elements EL1 and EL2, the light-emitting elements EL1 and EL2 do not emit light during the first conduction bias period OBS1.

[0145] During the initialization period INI, the voltages of the first to fourth scan signals SC1, SC2, SC3, and SC4 and the EM signal EM can be the gate high voltage VGH. Thus, during the initialization period INI, the first compensation switch element T1 and the fifth compensation switch element T5 are turned on to apply the initialization voltage Vinit to the second node N2 and the third node N3, and the initialization voltage Vinit can also be applied to the first node N1 via the driving element DT that remains turned on. During the initialization period INI, the light-emitting elements EL1 and EL2 are in the off state and do not emit light.

[0146] During the initialization period INI, the voltages at the first node N1, the second node N2, and the third node N3 can be the initialization voltage Vinit. During the initialization period INI, the fourth node N4 can be floating and maintained in its previous state because the fourth compensation switch element T4 and the sixth compensation switch element T6 are in the off state.

[0147] During the sampling period SAM, the voltage of the second scan signal SC2 is the gate low voltage VGL synchronized with the data voltage Vdata of the pixel data. During the sampling period SAM, the voltages of the first scan signal SC1, the third scan signal SC3, and the EM signal EM can be the gate high voltage VGH, and the voltage of the fourth scan signal SC4 can be the gate low voltage VGL. When the second compensation switch element T2 is turned on during the sampling period SAM in response to the gate low voltage VGL of the scan pulse, the data voltage Vdata can be applied to the first node N1, and the data voltage Vdata can also be applied to the second node N2 and the third node N3 through the driving element DT in the on state. At the end of the sampling period SAM, the voltage at the first node N1 is the data voltage Vdata, and the voltage at each of the second node N2 and the third node N3 is the voltage of Vdata+Vth, which is the data voltage Vdata plus the threshold voltage (Vth) of the driving element DT. During the sampling period SAM, the fourth node N4 is in a floating state, and the light-emitting elements EL1 and EL2 are in an off state, so they do not emit light.

[0148] During the second conduction bias period OBS2, the voltages of the first scan signal SC1, the third scan signal SC3, and the fourth scan signal SC4 can be the gate low voltage VGL, and the voltages of the second scan signal SC2 and the EM signal EM can be the gate high voltage VGH. During the second conduction bias period OBS2, the sixth compensation switch element T6, the seventh compensation switch element T7, and the eighth compensation switch element T8 are turned on, thereby allowing the second compensation voltage VOBS to be applied to the first node N1 and allowing the first compensation voltage VAR to be applied to the fifth node N5 and the sixth node N6.

[0149] During the light-emitting period EMIS, the voltages of the first scan signal SC1, the fourth scan signal SC4, and the EM signal EM can be the gate low voltage VGL, and the voltages of the second scan signal SC2 and the third scan signal SC3 can be the gate high voltage VGH. During the emission period EMIS, the third compensation switch element T3 and the fourth compensation switch element T4 can be turned on in response to the gate low voltage VGL of the EM signal EM. Therefore, during the emission period EMIS, the first light-emitting element EL1 can emit light by providing current from the driving element DT in the first mode (P mode), and the second light-emitting element EL2 can emit light by providing current from the driving element DT in the second mode (S mode). It can be seen that Figure 11C the first mode (P mode) and the second mode (S mode) can be determined according to the voltage levels of the mode selection signals P_SEL and S_SEL applied to the gate electrodes of the first pixel switch element M01 and the second pixel switch element M02 via the mode control unit 20.

[0150] Figure 12 is a circuit diagram showing in detail a compensation unit of a pixel circuit according to another embodiment of the present disclosure. Figure 13 shows an input to Figure 12 is a waveform diagram showing examples of a gate signal and a mode selection signal input to the pixel circuit shown. In the present embodiment, elements substantially the same as those in the pixel circuit shown in Figure 10 will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted. The mode control unit 20 and the first pixel switching element M are substantially the same as those shown in Figure 4 , and thus redundant descriptions thereof are omitted.

[0151] Referring to Figure 12 and Figure 13 , the driving element DT includes a gate electrode connected to the second node N2, a first electrode connected to the first node N1, and a second electrode connected to the third node N3.

[0152] The first light-emitting element EL1 includes an anode electrode connected to the fourth node N42 and a cathode electrode connected to the EVSS node to which a cathode voltage EVSS is applied. The second light-emitting element EL2 includes an anode electrode connected to the fifth node N52 and a cathode electrode connected to the EVSS node.

[0153] The sixth compensation switching element T62 is connected between the fourth node N42 and the VAR node. The sixth compensation switching element T62 is turned on in response to a gate low voltage VGL of the third scan signal SC3. When the sixth compensation switching element T62 is turned on, the first compensation voltage VAR can be applied to the anode electrode of the first light-emitting element EL1 connected to the fourth node N42. The sixth compensation switching element T62 includes a gate electrode to which the third scan signal SC3 is applied, a first electrode connected to the fourth node N42, and a second electrode connected to the VAR node.

[0154] The seventh compensation switching element T72 is connected between the fifth node N52 and the VAR node. The seventh compensation switching element T72 is turned on in response to a gate low voltage VGL of the third scan signal SC3. When the seventh compensation switching element T72 is turned on, the first compensation voltage VAR can be applied to the anode electrode of the second light-emitting element EL2 connected to the fifth node N52. The seventh compensation switching element T72 includes a gate electrode to which the third scan signal SC3 is applied, a first electrode connected to the fifth node N52, and a second electrode connected to the VAR node.

[0155] The eighth compensation switching element T8 is connected between the first node N1 and the OBS node to which a second compensation voltage VOBS is applied. The eighth compensation switching element T8 is turned on in response to the gate low voltage VGL of the third scan signal SC3. When the eighth compensation switching element T8 is turned on, the second compensation voltage VOBS can be applied to the first node N1. The eighth compensation switching element T8 may include a gate electrode connected to a gate line to which the third scan signal SC3 is applied, a first electrode connected to the first node N1, and a second electrode to which the second compensation voltage VOBS is applied.

[0156] The pixel switching element M is connected between the fourth node N42 and the fifth node N52, and is turned on in the second mode (S mode) in response to the gate low voltage VGL of the second mode selection signal S_SEL. When the pixel switching element M is turned on, the fourth node N42 can be electrically connected to the fifth node N52, causing the second light-emitting element EL2 to emit light. The pixel switching element M includes a first electrode connected to the fourth node N42, a gate electrode to which the second mode selection signal S_SEL is applied, and a second electrode connected to the fifth node N52.

[0157] The driving period of the pixel may include a first conduction bias period OBS1, an initialization period INI, a sampling period SAM, a second conduction bias period OBS2, and a light-emitting period EMIS, as Figure 11A and Figure 11B shown. As can be seen from Figure 13 it is possible to determine the first mode (P mode) and the second mode (S mode) according to the voltage level of the mode selection signal S_SEL applied to the gate electrode of the pixel switching element M via the mode control unit 20. For example, when the pixel switching element M is turned off in response to the gate high voltage VGH of the mode selection signal S_SEL, only the first light-emitting element EL1 can be driven during the light-emitting period EMIS, causing the pixel PIX to emit light with a narrow viewing angle. On the other hand, when the pixel switching element M is turned on in response to the gate low voltage VGL of the mode selection signal S_SEL, the first light-emitting element EL1 and the second light-emitting element EL2 can be driven during the light-emitting period EMIS, causing the pixel PIX to emit light with a wide viewing angle.

[0158] When the pixel driving voltage EVDD applied to the compensation unit 10 and the constant voltage VDD applied to the mode control unit 20 are electrically connected, the deviation or fluctuation of the pixel driving voltage EVDD may be reflected in the gate voltages of the pixel switching elements M, M01, and M02 as shown in Figure 10 and Figure 12 shown. To prevent this, the pixel driving voltage EVDD and the constant voltage VDD can be electrically separated, as shown in Figure 14 and Figure 15 shown.

[0159] Figure 14 is a plan view showing an example of electrical separation of a power supply line between a compensation unit and a mode control unit of a pixel circuit, Figure 15 is a cross-sectional view showing a power supply line taken along line “I-I” in Figure 14 .

[0160] Referring to Figure 14 and Figure 15 , the display panel 100 may include EVDD power supply lines 131 and 132 that supply a pixel driving voltage EVDD to a plurality of compensation components 10, and a VDD power supply line 133 that supplies a constant voltage VDD to a plurality of mode control units 20.

[0161] The EVDD power supply lines 131 and 132 include a first EVDD power supply line 131 in a first direction X and a second EVDD power supply line 132 in a second direction Y. The first EVDD power supply line 131 and the second EVDD power supply line 132 are electrically connected at an intersection therebetween. The VDD power supply line 133 may be disposed on the display panel 100 along the second direction Y, parallel to the second EVDD power supply line 132. The VDD power supply line 133 is separated from the EVDD power supply lines 131 and 132 by an insulating layer 135. The insulating layer 135 may be an inorganic film or an organic film, or an insulating layer having an inorganic layer and an organic layer stacked thereon.

[0162] The first EVDD power supply line 131 may overlap a circuit region of the sub-pixels SPR, SPG, and SPB and the mode control unit 20 across the sub-pixels SPR, SPG, and SPB and the mode control unit 20. The second EVDD power supply line 132 may overlap a circuit region of the compensation unit 10 at each of the sub-pixels SPR, SPG, and SPB. The VDD power supply line 133 may overlap a circuit region of the mode control unit 20.

[0163] When viewed from a cross-section of the display panel 100, the insulating layer 135 covers the first EVDD power supply line 131, as Figure 15 shown. The second VDD power supply line 132 and the VDD power supply line 133 are disposed on the insulating layer 135. The second EVDD power supply line 132 is in contact with the first EVDD power supply line 131 through a contact hole 134 penetrating the insulating layer 135. Accordingly, the first EVDD power supply line 131 and the second EVDD power supply line 132 are electrically connected to each other and become equal in potential. In contrast, the VDD power supply line 133 may be electrically separated from the first EVDD power supply line 131 and the second EVDD power supply line 132, with the insulating layer 135 interposed therebetween, and thus is electrically separated from the first EVDD power supply line 131 and the second EVDD power supply line 132.

[0164] If the display panel 100 becomes larger and the resistance of the EVSS power line to which the cathode voltage EVSS is applied increases, deviation or voltage rise of the cathode voltage EVSS may occur depending on the pixel position. To avoid this, the EVSS power line can be arranged on the display panel 100 in the Figure 16 structure shown.

[0165] Figure 16 is a plan view showing an example in which a power line to which a cathode voltage is applied overlaps with a compensation unit of a pixel circuit.

[0166] Refer to Figure 16 , the display panel 100 may include a short circuit line 151 provided in the non-display area NA and a plurality of EVSS power lines 152. Both ends of the plurality of EVSS power lines 152 are connected to the short circuit line 151 and are connected to the pixels PIX across the display area AA.

[0167] The EVSS power line 152 is connected to the EVSS node of the compensation unit 10 in each pixel. The cathode voltage EVSS is applied to the short circuit line 151. Since the EVSS power line 152 is connected to the short circuit line 151, their resistance values can be reduced. Therefore, the rise of the cathode voltage EVSS can be minimized. The EVSS power line 152 may overlap with the mode control unit 20 with an insulating layer therebetween. The EVSS power line 152 overlapping with the mode control unit 20 can be used as a light-shielding layer to prevent the switching elements Tp and TS from being exposed to light. When the transistors implemented as the switching elements Tp and Ts are exposed to light in the off state, the leakage current may increase.

[0168] According to one or more embodiments of the present disclosure, the display device can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic organizers, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, operating stations, navigation, vehicle navigation, vehicle display devices, vehicle equipment, theater equipment, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, video cameras, and household appliances, etc. The display device according to one or more embodiments of the present disclosure can be applied to an organic light-emitting lighting device or an inorganic light-emitting lighting device.

[0169] The objects to be achieved by the present disclosure, the means for achieving the above objects of the present disclosure, and the effects do not specify the essential features of the claims. Therefore, the scope of the claims is not limited to the content disclosed in the present disclosure.

[0170] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A display panel, comprising: A plurality of data lines, a plurality of gate lines, a plurality of power lines and a plurality of pixels are arranged on the substrate, Wherein, each of the plurality of pixels comprises: a first light emitting element; a second light emitting element; a compensation unit configured to provide current to the first light emitting element and the second light emitting element; A switch circuit, wherein the switch circuit is configured to: In response to receiving a mode selection signal, supplying the current to the first light emitting element in a first mode and supplying the current to the second light emitting element in a second mode or supplying the current to both the first light emitting element and the second light emitting element in the second mode; and A mode control section is configured to provide the mode selection signal to the switch circuit.

2. The display panel according to claim 1, wherein each of the plurality of pixels further comprises: Multiple sub-pixels, Each of the plurality of sub-pixels includes: the first light emitting element, the second light emitting element, the compensation unit, and the switch circuit. The switch circuit comprises: a first pixel switching element connected between the compensation portion and the first light emitting element and configured to be turned on / off in response to a first mode selection signal; and a second pixel switching element connected between the compensation portion and the second light emitting element and configured to be turned on / off in response to a second mode selection signal, The mode control unit is further configured to: output the first mode selection signal and the second mode selection signal, and wherein in the first mode, the first light emitting element is activated to emit light by a current provided by the first pixel switching element, and In the second mode, the second light emitting element is activated to emit light by a current provided by the second pixel switching element.

3. The display panel according to claim 2, wherein the mode control unit comprises: a first switching element configured to apply the first mode selection signal to a gate electrode of the first pixel switching element in response to a scan signal; as well as A second switching element is configured to apply the second mode selection signal to a gate electrode of the second pixel switching element in response to the scan signal.

4. The display panel according to claim 3, wherein: The first switching element includes a first electrode connected to a first control signal line configured to receive the first mode selection signal, a gate electrode configured to receive the scan signal, and a second electrode connected to the gate electrode of the first pixel switching element, and The second switching element includes a first electrode connected to a second control signal line configured to receive the second mode selection signal, a gate electrode configured to receive the scan signal, and a second electrode connected to the gate electrode of the second pixel switching element.

5. The display panel according to claim 4, wherein the mode control unit further comprises: a first capacitor connected between a power line configured to receive a constant voltage and a second electrode of the first switching element; as well as A second capacitor is connected between the power line and a second electrode of the second switching element.

6. The display panel according to claim 1, wherein each of the plurality of pixels further comprises: Multiple sub-pixels, Each of the sub-pixels includes the first light-emitting element, the second light-emitting element, the compensation unit, and the switch circuit. wherein the switch circuit comprises a pixel switch element connected between the compensation portion and the second light emitting element and configured to be turned on / off in response to a second mode selection signal, The mode control unit is further configured to: output the second mode selection signal, and wherein in the first mode, the first light emitting element is activated to emit light by the current from the compensation part, and In the second mode, the first light emitting element is activated to emit light by the current from the compensation part, and the second light emitting element is activated to emit light by the current provided by the pixel switching element.

7. The display panel according to claim 6, wherein the mode control unit comprises: A switching element is configured to apply the second mode selection signal to a gate electrode of the pixel switching element in response to a scan signal.

8. The display panel according to claim 7, wherein the switching element comprises a first electrode connected to a control signal line configured to receive the second mode selection signal, a gate electrode configured to receive the scan signal, and a second electrode connected to the gate electrode of the pixel switching element.

9. The display panel according to claim 8, wherein the mode control unit further comprises: A capacitor is connected between a power line configured to receive a constant voltage and the second electrode of the switching element.

10. The display panel according to claim 1, wherein the display panel further comprises: an EVDD power line configured to provide a pixel driving voltage to the compensation part; as well as A VDD power line configured to provide a constant voltage to the mode control section, Wherein, the EVDD power line comprises: a first EVDD power supply line; and a second EVDD power line connected to the first EVDD power line, and The VDD power line crosses the second EVDD power line, and the VDD power line is separated from both the first EVDD power line and the second EVDD power line by an insulating layer.

11. The display panel according to claim 10, wherein the display panel further comprises: a short-circuit line, wherein the short-circuit line is arranged in a non-display area of ​​the display panel; as well as a plurality of EVSS power lines extending across a display area of ​​the display panel, the plurality of EVSS power lines connected to the short line and to the compensation portion in each of the plurality of pixels, and The compensation section is configured to receive a cathode voltage via the short-circuit line and the plurality of EVSS power lines.

12. The display panel according to claim 1, wherein the compensation portion comprises: a driving element including a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to a third node; a first compensation switching element connected between the second node and the third node and configured to be turned on in response to a first scan signal; a second compensation switching element connected between a data line configured to receive a data voltage and the first node, and configured to be turned on in response to a second scan signal; a third compensation switch element, the third compensation switch element being connected between a power line configured to receive a pixel driving voltage and the first node, and the third compensation switch element being configured to be turned on / off in response to a light emitting signal; a fourth compensation switch element, the fourth compensation switch element being connected between the third node and the fourth node and configured to be turned on / off in response to the light emitting signal; as well as a storage capacitor connected between a power supply node configured to receive a pixel driving voltage and the second node, Wherein, the mode control unit includes: One or more switching elements are configured to be turned on / off in response to the second scan signal.

13. The display panel according to claim 12, wherein the compensation part further comprises: a fifth compensation switching element connected between the second node and an initialization power line configured to receive an initialization voltage, and configured to be turned on / off in response to a fourth scan signal; a sixth compensation switching element connected between the fifth node and a first compensation power line configured to receive the first compensation voltage, and configured to be turned on / off in response to a third scan signal; a seventh compensation switching element, the seventh compensation switching element being connected between the sixth node and the first compensation power line, and the seventh compensation switching element being configured to be turned on / off in response to the third scan signal; as well as an eighth compensation switching element, the eighth compensation switching element being connected between the first node and a second compensation power line configured to receive a second compensation voltage, and the eighth compensation switching element being configured to be turned on / off in response to the third scan signal, Wherein, the switch circuit comprises: a first pixel switching element connected between the fourth node and the fifth node and configured to be turned on in the first mode to supply current from the driving element to the first light emitting element; and a second pixel switching element connected between the fourth node and the sixth node and configured to be turned on in the second mode to supply the current from the driving element to the second light emitting element, and wherein the first light emitting element comprises an anode electrode connected to the fifth node, and a cathode electrode connected to a cathode power supply line configured to receive a cathode voltage, and The second light emitting element includes an anode electrode connected to the sixth node, and a cathode electrode connected to the cathode power line.

14. The display panel according to claim 12, wherein the compensation part further comprises: a fifth compensation switching element connected between the second node and an initialization power line configured to receive an initialization voltage, and configured to be turned on / off in response to a fourth scan signal; a sixth compensation switching element connected between the fourth node and a first compensation power line configured to receive a first compensation voltage, and configured to be turned on / off in response to a third scan signal; a seventh compensation switch element, the seventh compensation switch element being connected between the fifth node and the first compensation power line, and the seventh compensation switch element being configured to be turned on / off in response to the third scan signal; as well as an eighth compensation switching element, the eighth compensation switching element being connected between the first node and a second compensation power line configured to receive a second compensation voltage, and the eighth compensation switching element being configured to be turned on / off in response to the third scan signal, Wherein, the switch circuit comprises: a pixel switching element connected between the fourth node and the fifth node and configured to be turned on in the second mode to supply current from the driving element to the second light emitting element, wherein the first light emitting element comprises an anode electrode connected to the fourth node, and a cathode electrode connected to a cathode power supply line configured to receive a cathode voltage, and The second light emitting element includes an anode electrode connected to the fifth node, and a cathode electrode connected to the cathode power line.

15. A display device, comprising: A display panel, the display panel comprising a plurality of data lines, a plurality of gate lines, a plurality of power lines and a plurality of pixels; a data driver configured to provide data voltages to the plurality of data lines; as well as a gate driver configured to provide a scanning signal and a light emitting signal to the plurality of gate lines, wherein each of the plurality of pixels comprises: a first light emitting element; a second light emitting element; a compensation unit configured to receive the data voltage, the scan signal, and the light emitting signal, and provide a current to the first light emitting element and the second light emitting element; A switch circuit, wherein the switch circuit is configured to: In response to a mode selection signal, supplying the current to the first light emitting element in a first mode and supplying the current to the second light emitting element in a second mode or supplying the current to both the first light emitting element and the second light emitting element in the second mode; and A mode control section is configured to provide the mode selection signal to the switch circuit in response to the scan signal.

16. A display panel, comprising: a sub-pixel, the sub-pixel comprising a first light-emitting element and a second light-emitting element, the first light-emitting element being configured to emit light of the same color at a narrow viewing angle, the second light-emitting element being configured to emit light of the same color at a wide viewing angle wider than the narrow viewing angle; as well as A controller, the controller being configured to: In response to a first mode, activating the first light emitting element to emit the same color light at the narrow viewing angle, and In response to a second mode, the second light emitting element is activated to emit the same color light at the wide viewing angle.

17. The display panel according to claim 16, further comprising: a hemispherical lens disposed above the first light emitting element; as well as A semi-cylindrical lens is disposed above the second light emitting element.

18. The display panel according to claim 16, wherein the controller is further configured to: In response to the first mode, activating the first light emitting element to emit the same color light at the narrow viewing angle, while the first light emitting element is deactivated, and In response to the second mode, both the first light emitting element and the second light emitting element are activated to emit the same color light.

19. The display panel according to claim 16, wherein the controller comprises at least one switching transistor having a gate configured to receive a scan signal, a first electrode connected to a capacitor, and a second electrode connected to a mode selection line, and, The capacitor is connected between the first power line and the at least one switching transistor.

20. The display panel according to claim 19, further comprising a second power line connected to the sub-pixel and configured to provide a pixel driving voltage to the sub-pixel, The first power line of the controller is electrically isolated from the second power line of the sub-pixel.

21. The display panel according to claim 16, further comprising: A plurality of sub-pixels including the sub-pixel having the first light emitting element and the second light emitting element. The controller is further configured to: A group of sub-pixels among the plurality of sub-pixels are selectively activated to operate in the first mode to display first content at the narrow viewing angle, while the remaining sub-pixels among the plurality of sub-pixels are operated in the second mode to display second content at the wide viewing angle.

22. The display panel according to claim 16, further comprising: a plurality of pixels, the plurality of pixels including a plurality of sub-pixels, the plurality of sub-pixels including the sub-pixels having the first light-emitting element and the second light-emitting element; The controller is further configured to selectively operate the plurality of sub-pixels in the first mode having the narrow viewing angle or in the second mode having the wide viewing angle on a pixel-by-pixel basis.

Images