Display device and data driver

Abstract

The present disclosure relates to a display device and a data driver, and more particularly, to a display device in which a noise characteristic of a transmission signal is improved by controlling image data output from a timing controller to the data driver. According to the present disclosure, a noise characteristic of a transmission signal may be improved by controlling image data output from a timing controller to a data driver.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0195422, filed on December 28, 2023, the entire contents of which are incorporated herein by reference for all purposes. Technical field

[0003] The present disclosure relates to a display device, and more particularly, to a display device that improves the noise characteristics of a transmission signal by controlling image data output from a timing controller to a data driver. Background art

[0004] Recently, with the advent of the information age, the display field for visually expressing electrical information signals has developed rapidly, and in response thereto, various display devices having excellent performance such as thin, light, and low power consumption have been developed.

[0005] Examples of display devices may include a liquid crystal display (LCD) device, an organic light - emitting diode (OLED) display device, a quantum dot display device, etc.

[0006] Such display devices use a data driving unit and a timing controller for driving. Summary of the invention

[0007] The present disclosure relates to providing a display device in which the noise characteristics of a transmission signal are improved by controlling image data output from a timing controller to a data driver.

[0008] A display device according to an embodiment may include: a timing controller configured to output image data and command data including a plurality of pseudo - bits, a display panel on which a plurality of pixels connected to data lines are provided, and a data driver configured to generate a data voltage based on the image data and apply the data voltage to the data lines, wherein the data driver may include a pseudo - shift register configured to generate a clock for latching the image data, a latch configured to hold and output image data per frame based on at least one channel, a pseudo - latch configured to store the pseudo - bits of the image data, and an output buffer configured to output the data voltage to the data lines.

[0009] In one embodiment, the pseudo - latch may be provided at the end of the pseudo - shift register.

[0010] In one embodiment, the pseudo - bits of the image data and the command data may be provided at the start end of the transmission unit.

[0011] In one embodiment, a pseudo-latch may be provided at the start of a pseudo-shift register.

[0012] In one embodiment, pseudo-bits of image data and command data may be provided at the end of a transmission unit.

[0013] In one embodiment, when a predetermined number of pseudo-bits are stored, the pseudo-latch may output a saturation signal to a timing controller.

[0014] In one embodiment, the timing controller may output image data and command data from which pseudo-bits have been removed based on the saturation signal.

[0015] In one embodiment, the timing controller may determine the maximum number of pseudo-bits based on the upper 4 bits of a source output activation signal and may determine the order of the pseudo-bits based on the lower 4 bits of the source output activation signal.

[0016] A data driver according to one embodiment may include: a pseudo-shift register configured to generate a clock for latching image data and command data including a plurality of pseudo-bits, a latch configured to hold and output image data per frame based on at least one channel, a pseudo-latch configured to store pseudo-bits of image data and command data, a level shifter configured to receive image data from the latch, a switch array configured to generate a data voltage based on the image data, and an output buffer configured to output the data voltage.

[0017] In one embodiment, the pseudo-latch may be provided at the end of the pseudo-shift register.

[0018] In one embodiment, pseudo-bits of image data and command data may be provided at the start of a transmission unit.

[0019] In one embodiment, a pseudo-latch may be provided at the start of a pseudo-shift register.

[0020] In one embodiment, pseudo-bits of image data and command data may be provided at the end of a transmission unit.

[0021] In one embodiment, when a predetermined number of pseudo-bits are stored, the pseudo-latch may output a saturation signal to a timing controller.

[0022] In one embodiment, when the saturation signal is input to the timing controller, the pseudo-shift register may generate a clock for latching image data and command data from which pseudo-bits have been removed.

[0023] Additional features and aspects of the present disclosure will be set forth in the following description, and in part will be obvious from the description, or may be learned by practice of the inventive concept provided herein. Other features and aspects of the inventive concept may be realized and obtained by the structures particularly pointed out or derivable from the written description, claims, and drawings.

[0024] It should be understood that the foregoing general description and the following detailed description of the present disclosure are both exemplary and intended to provide further explanation of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0026] Figure 1 is a block diagram showing a display device according to various embodiments of the present disclosure.

[0027] Figure 2 is a diagram showing pixels and sub-pixels according to various embodiments of the present disclosure.

[0028] Figure 3 is a circuit diagram showing a circuit of a sub-pixel according to various embodiments of the present disclosure.

[0029] Figure 4 is a timing diagram showing image data and command data output from a timing controller to a data driver according to a comparative example of the present disclosure.

[0030] Figure 5 is a timing diagram showing a packet structure of image data according to a comparative example of the present disclosure.

[0031] Figure 6 is a timing diagram showing a packet structure of command data according to a comparative example of the present disclosure.

[0032] Figure 7 is a block diagram showing an internal structure of a data driver according to a comparative example of the present disclosure.

[0033] Figure 8 is a timing diagram showing image data and command data output from a timing controller to a data driver according to a first embodiment of the present disclosure.

[0034] Figure 9 is a timing diagram showing a packet structure of image data according to a first embodiment of the present disclosure.

[0035] Figure 10It is a timing diagram showing the packet structure of command data according to the first embodiment of the present disclosure.

[0036] Figure 11 It is a block diagram showing the internal structure of a data driver according to the first embodiment of the present disclosure.

[0037] Figure 12 It is a timing diagram showing image data and command data output from a timing controller to a data driver according to the second embodiment of the present disclosure.

[0038] Figure 13 It is a timing diagram showing the packet structure of image data according to the second embodiment of the present disclosure.

[0039] Figure 14 It is a timing diagram showing the packet structure of command data according to the second embodiment of the present disclosure.

[0040] Figure 15 It is a block diagram showing the internal structure of a data driver according to the second embodiment of the present disclosure.

[0041] Figure 16 It is a block diagram showing the internal structure of a data driver according to the second embodiment of the present disclosure.

[0042] Figure 17 It is a timing diagram showing image data, command data, and a saturation signal output from a timing controller to a data driver according to the third embodiment of the present disclosure.

[0043] Figure 18 and Figure 19 It is a timing diagram showing the packet structure of image data, the packet structure of command data, and the saturation signal according to the third embodiment of the present disclosure.

[0044] Figure 20 It is a table showing the maximum number of pseudo bits according to the high-order 4 bits of a source output activation signal according to the fourth embodiment of the present disclosure.

[0045] Figure 21 It is a table showing the pseudo bit order according to the low-order 4 bits of a source output activation signal according to the fifth embodiment of the present disclosure. Detailed Description

[0046] The advantages and features of the present disclosure and the methods for realizing them will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure can be implemented in different ways and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0047] The shapes, sizes, areas, lengths, thicknesses, ratios, angles, quantities, etc. shown in the accompanying drawings for describing various exemplary embodiments of the present disclosure are given only as examples. Therefore, the present disclosure is not limited to these details shown in the accompanying drawings. Unless otherwise specified, throughout the specification, the same reference numerals generally denote the same elements.

[0048] In the following description, if the detailed description of a related known function or configuration may unnecessarily obscure aspects of the present disclosure, the detailed description of such known function or configuration may be omitted or briefly discussed.

[0049] When terms such as "comprising", "having", "including", "containing", or "consisting of" are used, one or more other elements may be added, unless the term is used with a more restrictive term such as "only", etc. Unless the context clearly indicates otherwise, an element described in the singular form may include a plurality of elements, and vice versa.

[0050] When interpreting an element, even if no explicit description of such an error or tolerance range is provided, the element should be interpreted as including an error or tolerance margin.

[0051] When the positional relationship between two elements is described using terms such as "on", "above", "under", "next to", etc., one or more other elements may be located between the two elements, unless the term is used with a more restrictive term such as "tight", "direct".

[0052] Although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be construed as being limited by these terms, because they are not used to define the specific nature, order, sequence, priority, or quantity of these elements. These terms are only used to refer to an element separately. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and the second element may similarly be referred to as the first element.

[0053] Those skilled in the art can fully understand that the features of various embodiments of the present disclosure can be partially or fully coupled or combined with each other, and can be operated, connected, or driven together in various ways. The embodiments of the present disclosure can be executed independently of each other or can be executed together in an associated manner.

[0054] The driving circuit of the display device writes the pixel data of the input image into the pixels. The driving circuit of the display device includes a data driver for supplying a data signal to the data line, a gate driver for supplying a gate signal to the gate line, and the like.

[0055] In the display device according to the present disclosure, each of the pixel circuit and the gate driver may include a plurality of transistors and may be directly formed on the substrate of the display panel. The transistors may be implemented as thin film transistors (TFTs) having a metal oxide semiconductor field effect transistor (MOSFET) structure, and may be oxide TFTs including an oxide semiconductor or LTPS TFTs including low temperature polycrystalline silicon (LTPS).

[0056] A transistor is a three - electrode element including a gate, a source, and a drain. The source is an electrode for supplying carriers to the transistor. Carriers start flowing from the source in the transistor. The drain is an electrode through which carriers move from the transistor to the outside. In the transistor, the flow of carriers is from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n - channel transistor, the direction of the current is from the drain to the source. In the case of a p - channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as "the first electrode and the second electrode".

[0057] The gate signal can swing between a gate - on voltage and a gate - off voltage. The gate - on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate - off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0058] While the transistor is turned on in response to the gate - on voltage, the transistor is turned off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage may be a gate high voltage VGH or VEH, and the gate - off voltage may be a gate low voltage VGL or VEL. In the case of a p - channel transistor, the gate - on voltage may be a gate low voltage VGL or VEL, and the gate - off voltage may be a gate high voltage VGH or VEH. In the following embodiments, although an example in which the transistors of the pixel circuit are mainly implemented as p - channel transistors will be mainly described, it should be noted that the present disclosure is not limited thereto.

[0059] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, although the device is shown as an OLED display device in the examples, the present disclosure is not limited thereto.

[0060] Figure 1 is a block diagram showing a display device according to various embodiments of the present disclosure.

[0061] Referring to Figure 1 , a display device according to various embodiments of the present disclosure may include a display panel 100, a timing controller 200, a gate driver 300, a data driver 400, a power driver 500, and a gamma (GMA) driver 600.

[0062] The display panel 100 includes a pixel array, in which an input image is displayed on the screen. The pixel array includes a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and sub-pixels SP arranged in a matrix form.

[0063] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The display panel 100 may be manufactured as a flexible display panel. The flexible display panel may be implemented as an OLED panel using a plastic substrate.

[0064] The timing controller 200 receives digital video data of an input image and a timing signal synchronized therewith from a setting system (or a host system). The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock Clk, etc. The setting system includes: a TV, a monitor, a set-top box, a navigation system, a personal computer, a home theater system, a mobile device, a wearable device, a vehicle system, etc.

[0065] The timing controller 200 may control the operation timing of the display panel 100 according to the input frequency (or the driving frequency). In the National Television Standards Committee (NTSC) format, the input frequency may be 60 Hz. Recently, display devices driven at a higher frequency of 120 Hz have become popular. Additionally, in some cases, a display device driven at 120 Hz may be controlled to be temporarily driven at 60 Hz. Additionally, recently, display devices supporting variable refresh rate (VRR) have been developed, and in the variable refresh rate, the display device operates by: in a low-speed driving mode, reducing the frame frequency to a frequency between 1 Hz and 30 Hz, and in the case of a high-resolution image (e.g., game mode), increasing the frame frequency to 144 Hz.

[0066] The timing controller 200 can output serial image data Sdata provided to the data driver 400, command data CMD for controlling the data driver 400, and a gate control signal GCS for controlling the gate driver 300 based on the received timing signals Vsync, Hsync, and MClk.

[0067] The gate driver 300 can be implemented as an in-panel gate (GIP) circuit, which is directly formed on the display panel 100 together with the TFT array and lines of the pixel array. The gate driver 300 sequentially outputs gate signals to the gate lines GL under the control of the timing controller 200. The gate driver 300 can shift the gate signals using a shift register unit and sequentially output the signals to a plurality of gate lines GL.

[0068] The data driver 400 uses a digital-to-analog converter (not shown) and gamma reference voltages GMAV1 to GMAV10 provided from the gamma driver 600 to convert pixel data of an input image received as a digital signal from the timing controller 200 during each frame period into gamma-compensated voltages and output data voltages. The data driver 400 can be implemented as a plurality of source driver integrated circuits. The data driver 400 can be electrically connected to the data lines DL of the display panel 100 through a chip-on-glass (COG) process or a tape automated bonding (TAB) process.

[0069] The power driver 500 can use a DC-DC converter to output the DC power required to drive the pixel array of the display panel 100 and the drivers 300, 400, and 600. The power driver 500 can receive a DC input voltage applied from a setting system or a main system and output DC voltages such as a gate high voltage VGH, a gate low voltage VGL, a high-potential power voltage ELVDD, a low-potential power voltage ELVSS, and a high-potential reference voltage VDD.

[0070] Specifically, the gate high voltage VGH is a voltage set to be equal to or higher than the threshold voltage of the transistors formed in the sub-pixel SP array. The gate high voltage VGH can be output to the gate driver 300 and supplied to the level shifter in the gate driver 300.

[0071] The gate low voltage VGL is a voltage lower than the threshold voltage of the transistors formed in the sub-pixel SP array. The gate low voltage VGL can be supplied to the level shifter in the gate driver 300.

[0072] The high-potential power voltage ELVDD is a voltage supplied to the anode of the light-emitting element and is a positive voltage for driving the light-emitting element. The high-potential power voltage ELVDD can be supplied to the high-potential power voltage lines connected to each sub-pixel SP in the display panel 100.

[0073] The low-potential power voltage ELVSS is the voltage supplied to the cathode of the light-emitting element and is a negative voltage for driving the light-emitting element. The low-potential power voltage ELVSS can be supplied to the low-potential power voltage lines connected to each sub-pixel SP in the display panel 100.

[0074] The high-potential reference voltage VDD is the voltage output to the gamma driver 600. The high-potential reference voltage VDD can be used as a reference voltage for generating the gamma reference voltages GMAV1 to GMAV10.

[0075] The gamma driver 600 receives the high-potential reference voltage VDD output from the power driver 500. The gamma driver 600 receives the gamma control signal GMCS from the timing controller 200. The gamma driver 600 generates the gamma reference voltages GMAV1 to GMAV10 having values between the high-potential reference voltage VDD and the ground voltage 0V in response to the gamma control signal GMCS, and the data driver 400 outputs data voltages based on the gamma reference voltages GMAV1 to GMAV10.

[0076] Figure 2 is a diagram showing pixels and sub-pixels according to various embodiments of the present disclosure.

[0077] A pixel may have Figure 2 the arrangement shown. Referring to Figure 2 , each pixel P may include a plurality of sub-pixels SP. The sub-pixel SP may include a red sub-pixel SP(R), a green sub-pixel SP(G), and a blue sub-pixel SP(B). In some cases, the pixel P may also include a white sub-pixel (not shown).

[0078] Each of the data lines DL1 to DL6 may transmit a data voltage Vdata for displaying an image to the sub-pixel SP. Gate signals, such as scan signals SC1 and SC2 for turning on and off transistors and emission signals EM1 and EM2 for controlling light emission, may be applied to the gate lines GL1 and GL2, respectively.

[0079] The gate signals may be in the form of pulses that swing between a gate-on voltage and a gate-off voltage. The scan signals SC1 and SC2 may select the pixels for writing data to the gate lines synchronously with the data voltage Vdata. The emission signals EM1 and EM2 may define the light-emitting time of the pixels.

[0080] Figure 3 is a circuit diagram showing the circuit of a sub-pixel according to various embodiments of the present disclosure.

[0081] Figure 3 shows a pixel PX ijConnected to the i-th first gate line GL1 i and the i-th second gate line GL2 i and the j-th data line DL j as an example.

[0082] Referring to Figure 3 , the pixel PX ij may include a switching transistor ST, a driving transistor DT, a sensing transistor SST, a storage capacitor Cst, and a light-emitting element LD.

[0083] A first electrode (e.g., a source electrode) of the switching transistor ST may be electrically connected to the j-th data line DL j , and a second electrode (e.g., a drain electrode) of the switching transistor ST may be electrically connected to the first node N1. A gate electrode of the switching transistor ST may be electrically connected to the i-th first gate line GL1 i . The switching transistor ST may be turned on when a gate signal at a gate-conducting level is applied to the i-th first gate line GL1 i to transmit a data signal applied to the j-th data line DL j to the first node N1.

[0084] A first electrode of the storage capacitor Cst may be electrically connected to the first node N1, and a second electrode of the storage capacitor Cst may be connected to the second node N2. A first electrode of the light-emitting element LD may be electrically connected to the second node N2. The storage capacitor Cst may be charged to a voltage corresponding to the difference between the voltage applied to the first node N1 and the voltage applied to the second node N2.

[0085] A first electrode (e.g., a source electrode) of the driving transistor DT may be configured to receive a high-potential driving voltage ELVDD, and a second electrode (e.g., a drain electrode) of the driving transistor DT may be electrically connected to the second node N2. A gate electrode of the driving transistor DT may be electrically connected to the first node N1. The driving transistor DT may be turned on when a voltage at a gate-conducting level is applied through the first node N1, and may control the amount of driving current flowing through the light-emitting element LD in response to the voltage supplied to the gate electrode.

[0086] A first electrode (e.g., a source electrode) of the sensing transistor SST may be electrically connected to the j-th sensing line SL j , and a second electrode (e.g., a drain electrode) of the sensing transistor SST may be electrically connected to the second node N2. A gate electrode of the sensing transistor SST may be electrically connected to the i-th second gate line GL2 i . The sensing transistor SST may be turned on when a sensing signal at a gate-conducting level is applied to the i-th second gate line GL2 i to apply the voltage applied to the j-th sensing line SLj The reference voltage is transmitted to the first electrode of the light-emitting element LD.

[0087] The light-emitting element LD can emit light corresponding to the drive current. The light-emitting element LD can output light corresponding to any one of red, green, blue, and white. The light-emitting element LD can be an OLED or an ultra-small inorganic light-emitting element having a size ranging from microns to nanometers, but the present embodiment is not limited thereto. Hereinafter, the technical spirit of the present embodiment will be described with reference to an embodiment in which the light-emitting element LD is configured as an OLED.

[0088] In the present embodiment, the pixel PX ij is not limited to the Figure 3 shown structure. According to an embodiment, the pixel PX ij may further include at least one element for compensating the threshold voltage of the drive transistor DT or initializing the voltage of the gate electrode of the drive transistor DT and / or the voltage of the first electrode of the light-emitting element LD. In this case, the sense transistor SST can be omitted from the pixel PX ij .

[0089] Figure 3 Illustrates an example in which the switch transistor ST, the drive transistor DT, and the sense transistor SST are NMOS transistors, but the present disclosure is not limited thereto. For example, at least some or all of the transistors forming each pixel PX can be formed as PMOS transistors. In various embodiments, the switch transistor ST, the drive transistor DT, and the sense transistor SST can each be implemented as an LTPS TFT, an oxide TFT, or a low-temperature polycrystalline oxide (LTPO) TFT.

[0090] Figure 4 is a timing diagram showing image data and command data output from the timing controller to the data driver according to a comparative example of the present disclosure.

[0091] Referring to Figure 4 , the timing controller 200 can output serial image data Sdata as a digital signal and command data CMD for controlling the data driver 400, and the serial image data Sdata is provided to the data driver 400. A predetermined number of transmission units N UI (see reference numeral 5000) can be used to transmit the image data Sdata and the command data CMD.

[0092] Figure 5 is a timing diagram showing the packet structure of image data according to a comparative example of the present disclosure.

[0093] Referring to Figure 4 and Figure 5, a predetermined number of transmission units NUI of the image data Sdata may include flag bits (00, 11). The image data Sdata may be 8-bit serial data. However, this embodiment is not limited thereto.

[0094] Figure 6 is a timing diagram showing the packet structure of command data according to a comparative example of the present disclosure.

[0095] Refer to Figure 4 and Figure 6 , a predetermined number of transmission units NUI of the command data CMD may include flag bits (00, 11). The command data CMD may be 8-bit serial data. However, this embodiment is not limited thereto.

[0096] Figure 7 is a block diagram showing the internal structure of a data driver according to a comparative example of the present disclosure.

[0097] Refer to Figure 1 and Figure 7 , the data driver 400 includes a shift register 410, a latch unit 420, a conversion unit 430, a voltage divider 440, and a buffer unit 450.

[0098] The shift register 410 may generate a latch clock Lclk for latching the serial image data Sdata received from the timing controller 200. The start end 415 of the shift register 410 is the point where the latch clock Lclk first operates, and the end 416 is the point where the latch clock Lclk operates by being shifted to reach the end. The image data Sdata is first latched by the latch clock Lclk at the start end 415 and input into the latch unit 420, and is sequentially input into the latch unit 420 by the shifted latch clock Lclk until the end 416.

[0099] The serial image data Sdata may be transmitted in the form of data packets that include pixel data of the input image, a clock, a source output activation signal, etc. The latch unit 420 samples the serial image data Sdata according to the latch clock Lclk provided by the shift register 410 and converts the sampled serial image data into parallel data. In other words, the latch unit 420 may hold the serial image data Sdata of each frame based on at least one channel and output the serial image data as parallel data. In Figure 7 , the shift register 410 is shown as a unit separate from the latch unit 420, but the latch unit 420 may include the shift register 410.

[0100] The latch unit 420 may include a latch start pulse Latch. The latch start pulse Latch may control the start time point at which the parallel data output of the latch unit 420 is supplied to the conversion unit 430. The parallel data output from the latch unit 420 may be data output simultaneously from multiple channels.

[0101] The conversion unit 430 may be a digital-to-analog converter DAC for converting a digital signal into an analog signal. The conversion unit 430 may convert digital parallel data into analog data using the gamma compensation voltages V0 to V1023 provided from the voltage divider 440 for each color. The conversion unit 430 may include independent digital-to-analog converters DAC for each color. The conversion unit 430 may include a level shifter 431 and a switch array 432. The level shifter 431 may receive image data Sdata from the latch unit 420. The switch array 432 may generate a data voltage Vdata from the image data Sdata.

[0102] The buffer unit 450 may output the data voltage Vdata to the data line through output buffers Output#1 to Output#N connected to the output nodes of the conversion units 430 of each channel of the data driver 400.

[0103] Since the light-emitting elements have different efficiencies for each color, different data voltages Vdata may be set for each color to achieve ideal optical compensation.

[0104] The voltage divider 440 receives gamma reference voltages GMAV1 to GMAV10 from the gamma driver 600 and outputs gamma compensation voltages V0 to V1023. The voltage divider 440 divides the gamma reference voltages GMAV1 to GMAV10 using a plurality of resistors connected in series and outputs the gamma compensation voltages V0 to V1023 set for each gray level 0G to 1023G. The gamma compensation voltages V0 to V1023 are voltages optimized for each color according to a predetermined color gamma curve. In order to independently generate the gamma compensation voltages for each color, each of the gamma reference voltages GMAV1 to GMAV10 (R / G / B) for each color may include N gamma reference voltages having different voltage levels. For example, N may be 10.

[0105] Figure 8 is a timing diagram showing image data and command data output from the timing controller to the data driver according to the first embodiment of the present disclosure.

[0106] Refer to Figure 8, the timing controller 200 can output the serial image data Sdata and the command data CMD for controlling the data driver 400 as digital signals of differential signals to the data driver 400. An irregular number of transmission units N UI, N+2UI, ……, N+1UI and N+3UI (see reference numeral 6000) can be used to transmit the image data Sdata and the command data CMD.

[0107] Figure 9 is a timing diagram showing the packet structure of the image data according to the first embodiment of the present disclosure.

[0108] Refer to Figure 8 and Figure 9 , an irregular number of transmission units N UI, N+2UI, ……, N+1UI and N+3UI of the image data Sdata can include flag bits (00, 11). An irregular number of transmission units N UI, N+2UI, ……, N+1UI and N+3UI of the image data Sdata can include dummy bits d. In this case, a plurality of dummy bits d can be set at the end 616 of one transmission unit N UI, N+2UI, ……, N+1UI or N+3UI. The start end 615 of one transmission unit N UI, N+2UI, ……, N+1UI or N+3UI is the starting point of the serial image data Sdata output from the timing controller 200 to the data driver 400, and the end 616 of one transmission unit N UI, N+2UI, ……, N+1UI or N+3UI is the last point of the serial image data Sdata. The image data Sdata can be 8-bit serial data. However, this embodiment is not limited thereto.

[0109] Figure 10 is a timing diagram showing the packet structure of the command data according to the first embodiment of the present disclosure.

[0110] Refer to Figure 8 and Figure 10 , an irregular number of transmission units N UI, N+2UI, ……, N+1UI and N+3UI of the command data CMD can include flag bits (00, 11). An irregular number of transmission units N UI, N+2UI, ……, N+1UI and N+3UI of the command data CMD can include dummy bits d. In this case, a plurality of dummy bits d can be set at the end 616 of one transmission unit N UI, N+2UI, ……, N+1UI or N+3UI. The command data CMD can be 8-bit serial data. However, this embodiment is not limited thereto.

[0111] Figure 11 is a block diagram showing the internal structure of the data driver according to the first embodiment of the present disclosure.

[0112] Refer to Figure 1 and Figure 11 As shown in FIGS. and, the data driver 400 includes a pseudo shift register 411, a latch unit 420, a pseudo latch 424, a conversion unit 430, and a buffer unit 450.

[0113] The pseudo shift register 411 can generate a latch clock Lclk for latching serial image data Sdata of differential signals received from the timing controller 200. The pseudo shift register 411 can generate a latch clock Lclk for latching command data CMD for controlling the data driver 400 received from the timing controller 200.

[0114] The latch unit 420 samples the serial image data Sdata received from the timing controller 200 according to the latch clock Lclk provided by the pseudo shift register 411, and converts the sampled serial image data into parallel data.

[0115] The pseudo latch 424 can be disposed at the end 416 of the pseudo shift register 411. In other words, the pseudo latch 424 can be disposed at a position where the last image data Sdata is filled when image data Sdata including a plurality of pseudo bits d is input to the data driver 400.

[0116] Refer to Figure 9 and Figure 11 As shown in FIGS. and, the image data Sdata including a plurality of pseudo bits d can be sampled according to the latch clock Lclk, sequentially assigned to the first latch 421, and then sequentially assigned to the pseudo latch 424. In other words, the pseudo latch 424 can store: the pseudo bits d at the end 616 in the first latch 421 that are not stored in the irregular number of transmission units N UI, N + 2UI,..., N + 1UI, and N + 3UI of the image data Sdata. Using the pseudo bits d, the periodic noise can be reduced by changing the length of the transmission unit N UI of the image data Sdata transmitted from the timing controller 200 to the data driver 400.

[0117] Figure 12 FIG. is a timing diagram showing image data and command data output from the timing controller to the data driver according to a second embodiment of the present disclosure.

[0118] Refer to Figure 12, the timing controller 200 can output the serial image data Sdata of the digital signal as a differential signal and the command data CMD for controlling the data driver 400 to the data driver 400. An irregular number of transmission units N UI, N+1UI, ……, N+4UI and N+3UI (see reference numeral 700) can be used to transmit the image data Sdata and the command data CMD.

[0119] Figure 13 is a timing diagram showing the packet structure of the image data according to the second embodiment of the present disclosure.

[0120] Referring to Figure 12 and Figure 13 , an irregular number of transmission units N UI, N+1UI, ……, N+4UI and N+3UI of the image data Sdata can include flag bits (00, 11). An irregular number of transmission units N UI, N+1UI, ……, N+4UI and N+3UI of the image data Sdata can include dummy bits d. In this case, a plurality of dummy bits d can be set at the start end 615 of one transmission unit N UI, N+1UI, ……, N+4UI or N+3UI. The image data Sdata can be 8-bit serial data. However, this embodiment is not limited thereto.

[0121] Figure 14 is a timing diagram showing the packet structure of the command data according to the second embodiment of the present disclosure.

[0122] Referring to Figure 14 , an irregular number of transmission units N UI, N+1UI, ……, N+4UI and N+3UI of the command data CMD can each include flag bits (00, 11). An irregular number of transmission units N UI, N+1UI, ……, N+4UI and N+3UI of the command data CMD can include dummy bits d. In this case, a plurality of dummy bits d can be set at the start end 615 of one transmission unit N UI, N+1UI, ……, N+4UI or N+3UI. The command data CMD can be 8-bit serial data. However, this embodiment is not limited thereto.

[0123] Figure 15 is a block diagram showing the internal structure of the data driver according to the second embodiment of the present disclosure.

[0124] Referring to Figure 1 and Figure 15 , the data driver 400 includes a dummy shift register 411, a latch unit 420, a dummy latch 424, a conversion unit 430, and a buffer unit 450.

[0125] The pseudo-latch 424 may be provided at the start end 415 of the pseudo-shift register 411. In other words, the pseudo-latch 424 may be provided at the position where the first image data Sdata is filled when the image data Sdata including a plurality of pseudo-bits d is input to the data driver 400.

[0126] Referring Figure 13 and Figure 15 , the image data Sdata including a plurality of pseudo-bits d may be sampled according to the latch clock Lclk, sequentially allocated to the pseudo-latch 424, and then sequentially allocated to the first latch 421. In other words, the pseudo-latch 424 may store the pseudo-bit d at the start end 615 before it is stored in the first latch 421 in the irregular number of transfer units N UI, N+1UI,..., N+4UI and N+3UI of the image data Sdata. Using the pseudo-bit d, the periodic noise may be reduced by changing the length of the transfer unit N UI of the image data Sdata transferred from the timing controller 200 to the data driver 400. In this case, when the pseudo-latch 424 does not store the pseudo-bit d at the start end 615 before it is stored in the first latch 421, the price may be reduced by omitting the pseudo-latch 424.

[0127] Figure 16 is a block diagram showing the internal structure of a data driver according to a second embodiment of the present disclosure.

[0128] Referring Figure 1 and Figure 16 , the data driver 400 includes a pseudo-shift register 411, a latch unit 420, a pseudo-latch 424, a conversion unit 430, and a buffer unit 450.

[0129] When a predetermined number of pseudo-bits d are stored, the pseudo-latch 424 may output a saturation signal SAT to the timing controller 200. When a predetermined number of pseudo-bits d are stored in the pseudo-latch 424, the saturation signal SAT may be transmitted to the timing controller 200 to stop the process of including the pseudo-bits d in the image data Sdata and the command data by the timing controller 200.

[0130] The saturation signal SAT may be initialized every 1 horizontal period (1H) or every 1 vertical period (1V). When the saturation signal SAT is initialized, the timing controller 200 may output the image data Sdata and the command data CMD in an irregular number of transfer units N UI, N+1UI,....

[0131] Figure 17It is a timing diagram showing image data, command data output from a timing controller to a data driver, and a saturation signal output from the data driver to the timing controller according to a third embodiment of the present disclosure.

[0132] Referring to Figure 17 , the timing controller 200 may output serial image data Sdata and command data CMD for controlling the data driver 400 to the data driver 400 as digital signals of differential signals. The timing controller 200 may output the image data Sdata and the command data CMD in an irregular number of transmission units N UI, N + 1UI, ……, and then, when receiving the saturation signal SAT from the pseudo latch 424, re - output the image data Sdata and the command data CMD with the pseudo bit d omitted in a predetermined number of transmission units N UI.

[0133] Figure 18 and Figure 19 It is a timing diagram showing the packet structure of image data, the packet structure of command data, and the saturation signal according to a third embodiment of the present disclosure.

[0134] Referring to Figure 18 and Figure 19 , the timing controller 200 may output the image data Sdata or the command data CMD in an irregular number of transmission units NUI, N + 1UI, ……, and then, when receiving the saturation signal SAT from the pseudo latch 424, re - output the image data Sdata or the command data CMD in a predetermined number of transmission units N UI.

[0135] Figure 20 It is a table showing the maximum number of pseudo bits according to the upper 4 bits of the source output activation signal SOE_START according to a fourth embodiment of the present disclosure.

[0136] Referring to Figure 20 , the source output activation signal SOE_START may be an 8 - bit binary signal. The default value of the source output activation signal SOE_START is low L, and it is applied as high H at the start point of a frame to control the source output. The source output activation signal SOE_START is updated at the data start point Data Start of the image data Sdata.

[0137] The timing controller may determine the maximum number of pseudo bits d according to the upper 4 bits of the source output activation signal SOE_START. For example, when the source output activation signal SOE_START is 8`b0101_XXXX (in this case, X represents don't care bits), the maximum number of pseudo bits d may be 5.

[0138] Figure 21 This is a table showing the order of the dummy bits d according to the lower 4 bits of the source output activation signal SOE_START in accordance with a fifth embodiment of the present disclosure.

[0139] Referring to Figure 21 , the source output activation signal SOE_START may be an 8-bit binary signal. The default value of the source output activation signal SOE_START is low L, and it is applied as high H at the start point of a frame to control the source output. The source output activation signal SOE_START is updated at the start point Data Start of the image data Sdata.

[0140] The timing controller may determine the number of dummy bits d included during one horizontal period (1H) according to the lower 4 bits of the source output activation signal SOE_START. For example, when the source output activation signal SOE_START is 8`b0101_0010, the number of dummy bits d during one horizontal period (1H) is 3 -> 2 -> 1 -> 0 -> 5 -> 4, and it may change every 1 horizontal period (1H). Additionally, when the source output activation signal SOE_START is 8`b0101_0111, the number of dummy bits d may change randomly every 1 horizontal period (1H).

[0141] According to an embodiment of the display device, by distributing the repetition signals of the image data and the command data and a plurality of dummy bits to the image data output from the timing controller to the data driver, the noise characteristics of the transmission signal can be improved.

[0142] It will be apparent to those skilled in the art that the present disclosure is not limited to the above exemplary embodiments and the drawings, and various substitutions, modifications, and changes can be made to the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the above exemplary embodiments of the present disclosure are provided for illustrative purposes and are not intended to limit the scope or technical concept of the present disclosure. The protection scope of the present disclosure should be interpreted based on the appended claims and their equivalents, and the present disclosure is intended to cover all modifications and changes of the present disclosure that fall within the scope of the claims and their equivalents.

Claims

1. A display device, comprising: a timing controller configured to output image data and command data including a plurality of dummy bits; A display panel, wherein a plurality of pixels connected to the data lines are arranged on the display panel; as well as a data driver configured to generate a data voltage based on the image data and apply the data voltage to the data line, Wherein, the data driver comprises: a dummy shift register configured to generate a clock for latching the image data and the command data; a latch configured to hold and output image data of each frame based on at least one channel; a dummy latch configured to store dummy bits of the image data and the command data; and An output buffer is configured to output the data voltage to the data line.

2. The display device according to claim 1, wherein: The dummy latch is disposed at an end of the dummy shift register.

3. The display device according to claim 2, wherein: The dummy bits of the image data and the command data are provided at the beginning end of one transmission unit.

4. The display device according to claim 1, wherein: The dummy latch is provided at a beginning end of the dummy shift register.

5. The display device according to claim 4, wherein: The dummy bits of the image data and the command data are provided at the end of one transmission unit.

6. The display device according to claim 1, wherein: The dummy latch outputs a saturation signal to the timing controller when a predetermined number of dummy bits are stored.

7. The display device according to claim 6, wherein: The timing controller outputs the image data and the command data from which the dummy bits are removed based on the saturation signal.

8. The display device according to claim 6, wherein: The timing controller determines a maximum number of dummy bits according to high-order 4 bits of a source output activation signal, and determines an order of the dummy bits according to low-order 4 bits of the source output activation signal.

9. A data driver comprising: a dummy shift register configured to generate a clock for latching image data and command data including a plurality of dummy bits; a latch configured to hold and output image data of each frame based on at least one channel; a dummy latch configured to store the dummy bits of the image data and the command data; a level shifter configured to receive the image data from the latch; a switch array configured to generate a data voltage according to the image data; as well as An output buffer is configured to output the data voltage.

10. The data driver according to claim 9, wherein: The dummy latch is disposed at an end of the dummy shift register.

11. The data driver according to claim 10, wherein: The dummy bits of the image data and the command data are provided at the beginning end of one transmission unit.

12. The data driver according to claim 9, wherein: The dummy latch is provided at a beginning end of the dummy shift register.

13. The data driver according to claim 12, wherein: The dummy bits of the image data and the command data are provided at the end of one transmission unit.

14. The data driver according to claim 9, wherein: When a predetermined number of dummy bits are stored, the dummy latch outputs a saturation signal to the timing controller.

15. The data driver according to claim 14, wherein: When the saturation signal is input to the timing controller, the dummy shift register generates a clock for latching the image data and the command data from which the dummy bits are removed.

16. A data driver comprising: a dummy shift register configured to generate a clock for latching image data and command data including a plurality of dummy bits; a latch configured to hold and output image data of each frame based on at least one channel; a dummy latch configured to store the dummy bits of the image data and the command data; a conversion unit configured to convert the image data into a data voltage; as well as An output buffer is configured to output the data voltage.

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