Display device

Abstract

The invention provides a display device which comprises a touch display panel, and the touch display panel comprises a gate drive circuit and a plurality of pixels. The gate drive circuit comprises a plurality of cascaded gate drive sub-circuits, and each gate drive sub-circuit is electrically connected with one row of pixels. One frame of picture period of the touch display panel comprises at least two display stages and at least one touch stage located between the two display stages. The gate drive circuit further comprises a first control signal line and a second control signal line, and the first control signal line provides a first control signal for the ith-level gate drive sub-circuit to reset the gate drive sub-circuit before the touch stage arrives. And the second control signal line provides a second control signal for the (i + 1) th-level gate driving sub-circuit after the touch control stage is ended so as to start the gate driving sub-circuit, so that the problems of electric leakage and cross grains caused by the difference between the gate driving signals in the touch control stage and the display stage are prevented.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] Existing touch display panels usually use in-cell touch technology, which includes long horizontal (Long-H) mode and long vertical (Long-V) mode. The long horizontal mode is widely used because it can support a higher touch burst rate. In the long horizontal mode, the cycle of a frame includes multiple display stages and multiple touch stages, and there is a touch stage between two display stages.

[0003] However, in the existing long horizontal mode, there is a significant difference between the gate driving signal in the touch stage and the gate driving signal in the display stage. Figure 1 As shown, the duration 101 of the potential holding phase of the node Q of the gate driving circuit of the relevant level in the touch stage is much longer than the duration 102 of the potential holding phase of the node Q of the gate driving circuit of the relevant level in the display stage. This difference will cause leakage of the node Q of the gate driving circuit of the relevant level corresponding to the touch stage, affecting the cascade transmission function of the gate driving circuit, causing the waveform of the gate driving signal output by the gate driving circuit to fail, thereby generating a black screen phenomenon, such as Figure 2 As shown; and, the thin film transistor device related to the node Q of the gate driving circuit corresponding to the touch stage and the thin film transistor device related to the node Q of the gate driving circuit corresponding to the display stage are subjected to voltage stress at different times, resulting in a horizontal stripe defect 301 in the display device after reliability verification, as shown in FIG. Figure 3 As shown, this horizontal stripe phenomenon seriously affects the display quality. Summary of the invention

[0004] The purpose of the present application is to provide a display device that can solve the technical problem of horizontal stripe defects in the prior art.

[0005] Embodiments of the present application provide a display device, including: a touch display panel, the touch display panel includes a gate driving circuit and a plurality of pixels, the gate driving circuit includes a plurality of cascaded gate driving sub - circuits, and one - level gate driving sub - circuit is electrically connected to one row of the pixels; wherein, the period of a frame of the picture displayed by the touch display panel includes at least two display phases and at least one touch phase, and one touch phase is located between two display phases; the gate driving circuit further includes a first control signal line and a second control signal line, the first control signal line is used to provide a first control signal to the i - th - level gate driving sub - circuit among the plurality of gate driving sub - circuits before the touch phase arrives, so as to reset the i - th - level gate driving sub - circuit, and the second control signal line is used to provide a second control signal to the (i + 1) - th - level gate driving sub - circuit among the plurality of gate driving sub - circuits after the touch phase ends, so as to turn on the (i + 1) - th - level gate driving sub - circuit, where i is a positive integer.

[0006] In the above - mentioned display device, the gate driving sub - circuit includes: a first transistor, the gate of the first transistor is electrically connected to the gate driving signal output terminal of the subsequent - level gate driving sub - circuit, the source of the first transistor is electrically connected to the low - level signal input terminal, and the drain of the first transistor is electrically connected to the node Q of the gate driving sub - circuit; a second transistor, the gate of the second transistor is electrically connected to the gate driving signal output terminal of the previous - level gate driving sub - circuit, the source of the second transistor is electrically connected to the high - level signal input terminal, and the drain of the second transistor is electrically connected to the node Q; a third transistor, the gate of the third transistor is electrically connected to the node Q, the source of the third transistor is electrically connected to the clock signal line, and the drain of the third transistor is electrically connected to the gate driving signal output terminal of the gate driving sub - circuit; wherein, the gate of the first transistor of the i - th - level gate driving sub - circuit is further electrically connected to the first control signal line, and the gate of the second transistor of the (i + 1) - th - level gate driving sub - circuit is further electrically connected to the second control signal line.

[0007] In the above - mentioned display device, the first control signal is used to pull down the potential of the node Q_i of the i - th - level gate driving sub - circuit before the touch phase arrives.

[0008] In the above - mentioned display device, the first control signal is first at a low level and then at a high level in the display phase before the touch phase, the rising edge of the first control signal is after the rising edge of the clock signal input to the i - th - level gate driving sub - circuit, and the falling edge of the first control signal is after the falling edge of the clock signal input to the i - th - level gate driving sub - circuit.

[0009] In the above display device, the second control signal is used to raise the potential of node Q_i+1 of the (i + 1)-th stage of the gate driving sub-circuit after the touch stage ends.

[0010] In the above display device, the second control signal is at a high level first and then at a low level during the display stage after the touch stage. The rising edge of the second control signal is before the rising edge of the clock signal input to the (i + 1)-th stage of the gate driving sub-circuit, and the falling edge of the second control signal is before the falling edge of the clock signal input to the (i + 1)-th stage of the gate driving sub-circuit.

[0011] In the above display device, the first control signal line is further configured to provide the first control signal to each of the gate driving sub-circuits from the (i - k)-th stage to the (i - 1)-th stage of the gate driving sub-circuits before the touch stage arrives, so as to reset each of the gate driving sub-circuits from the (i - k)-th stage to the (i - 1)-th stage of the gate driving sub-circuits. The second control signal line is further configured to provide the second control signal to each of the gate driving sub-circuits from the (i + 2)-th stage to the (i + j)-th stage of the gate driving sub-circuits after the touch stage ends, so as to turn on each of the gate driving sub-circuits from the (i + 2)-th stage to the (i + j)-th stage of the gate driving sub-circuits; where k and j are both positive integers.

[0012] In the above display device, the first control signal line is also electrically connected to the gates of the first transistors of each of the gate driving sub-circuits from the (i - k)-th stage to the (i - 1)-th stage of the gate driving sub-circuits; the second control signal line is also electrically connected to the gates of the second transistors of each of the gate driving sub-circuits from the (i + 2)-th stage to the (i + j)-th stage of the gate driving sub-circuits.

[0013] In the above display device, the duration of the high level of the first control signal transmitted by the first control signal line is equal to the duration of the high level of the second control signal transmitted by the second control signal line.

[0014] In the above display device, there is a gap region between the i-th stage of the gate driving sub-circuit and the (i + 1)-th stage of the gate driving sub-circuit. The first connection line connecting the i-th stage of the gate driving sub-circuit and the first control signal line and the second connection line connecting the (i + 1)-th stage of the gate driving sub-circuit and the second control signal line are located in the gap region.

[0015] The display device of the present application sets a first control signal line and a second control signal line in the gate driving circuit. Before the touch stage arrives, a first control signal is provided to the i-th stage gate driving sub-circuit through the first control signal line, and after the touch stage ends, a second control signal is provided to the (i + 1)-th stage gate driving sub-circuit through the second control signal line. Thus, the i-th stage gate driving sub-circuit is reset before the touch stage starts, and the (i + 1)-th stage gate driving sub-circuit is turned on after the touch stage ends. The technical solution of the present application can prevent the leakage problem caused by the overlong holding time of the potential of node Q during the touch stage, ensure the normal cascade transmission of the gate driving signal after the touch stage ends, and enable each stage of the gate driving sub-circuit to work normally according to the predetermined timing sequence. Since the leakage problem is effectively controlled, the waveform failure of the gate driving signal caused by leakage is avoided, thereby preventing the occurrence of the black screen phenomenon.

[0016] The above technical solution can make the voltage stress time of the thin film transistor devices related to node Q of the gate driving sub-circuit corresponding to the touch stage and the thin film transistor devices related to node Q of the gate driving sub-circuit corresponding to the display stage tend to be consistent, thus fundamentally avoiding the horizontal stripe defect caused by inconsistent stress time. Description of the Drawings

[0017] Figure 1 is a waveform diagram of node Q of the gate driving circuit in a traditional display device during the touch stage.

[0018] Figure 2 is a schematic diagram of the abnormal potential drop phenomenon of the gate driving signal in the gate driving circuit of a traditional display device.

[0019] Figure 3 is a schematic diagram of the horizontal stripe defect that appears in a traditional display device.

[0020] Figure 4 is a schematic diagram of the display device provided by the embodiment of the present application.

[0021] Figure 5 is a circuit diagram of the gate driving circuit in the display device provided by the embodiment of the present application.

[0022] Figure 6 is a layout diagram of the gate driving circuit in the display device provided by the embodiment of the present application.

[0023] Figure 7 is a waveform diagram of the gate driving circuit in the display device provided by the embodiment of the present application.

[0024] Figure 8It is a waveform diagram of the potentials of node Q and the gate signal output terminal of the gate driving sub-circuit in the gate driving circuit in the display device provided by the embodiment of the present application. Detailed implementation manners

[0025] The detailed implementation manners of the present application will be described in detail below with reference to the accompanying drawings.

[0026] Terms such as "first", "second" and similar words do not denote any order, quantity or importance, but are only used to distinguish different technical features. The term "a plurality of" and similar words mean two or more, unless otherwise clearly defined.

[0027] The embodiments of the present application can be combined with each other.

[0028] As Figure 4 shown, the display device provided by the embodiment of the present application includes a touch display panel TP, a timing controller TCON, a source driving circuit DD, and a power management chip (not shown in the figure, and the power management chip can be integrated with the timing controller TCON into the same chip). The touch display panel TP can be, for example, a liquid crystal display panel.

[0029] The touch display panel TP includes a display area and a non-display area. The display area is provided with m×n pixels PX arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange driving circuits and various signal lines. The touch display panel TP further includes a plurality of scan lines (GL1~GLn), a plurality of data lines (DL1~DLm), and a gate driving circuit GOA. The plurality of scan lines (GL1~GLn) extend along a first direction and are arranged along a second direction, the plurality of data lines (DL1~DLm) extend along the second direction and are arranged along the first direction, and the first direction is perpendicular to the second direction. The gate driving circuit GOA is disposed in the non-display area and is electrically connected to the plurality of scan lines (GL1~GLn). The source driving circuit DD is electrically connected to the plurality of data lines (DL1~DLm) through a flexible circuit board. The timing controller TCON is electrically connected to the gate driving circuit GOA and the source driving circuit DD respectively.

[0030] The touch display panel TP includes a thin film transistor array substrate, a counter substrate, and a liquid crystal layer disposed between the two substrates. The thin film transistor array substrate includes a glass substrate, a first metal layer disposed on the glass substrate, a gate insulating layer disposed on the first metal layer, a semiconductor layer disposed on the gate insulating layer, a second metal layer disposed on the semiconductor layer, a first passivation layer disposed on the second metal layer, a common electrode layer disposed on the first passivation layer, a second passivation layer disposed on the common electrode layer, and pixel electrodes disposed on the second passivation layer. The first metal layer includes scanning lines (GL1 to GLn), gate electrodes, etc. The second metal layer includes data lines (DL1 to DLm), source electrodes, drain electrodes, etc. The common electrode layer includes a plate-shaped common electrode, and the pixel electrodes are strip-shaped and arranged in parallel. The counter substrate includes a glass substrate and a black matrix disposed on the glass substrate. The touch display panel TP adopts the FFS (Fringe Field Switching) mode, and drives the rotation of liquid crystal molecules in the liquid crystal layer through the lateral electric field generated between the pixel electrodes and the common electrode.

[0031] Each pixel PX includes at least one thin film transistor and a pixel electrode. The gate of the thin film transistor is electrically connected to the corresponding scanning line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the corresponding pixel electrode. When the scanning line outputs a high-level gate driving signal, the thin film transistor is turned on, and the data signal on the data line is transmitted to the pixel electrode through the thin film transistor; when the scanning line outputs a low-level gate driving signal, the thin film transistor is turned off, and the pixel electrode maintains the voltage corresponding to the data signal.

[0032] The gate driving circuit GOA includes n cascaded gate driving sub-circuits, and each gate driving sub-circuit is electrically connected to a scanning line. The gate driving sub-circuit sequentially outputs gate driving signals under the control of the timing controller TCON to scan each row of pixels PX in the display area row by row. The source driving circuit DD generates and outputs data signals according to the image data under the control of the timing controller TCON. The timing controller TCON is used to receive and process externally input image data and timing signals, generate control signals, and transmit the image data to the source driving circuit DD. The power management chip is used to provide operating voltages for various parts of the display device, including providing a common voltage for the common electrode of the liquid crystal display panel, providing a gate driving voltage for the gate driving circuit GOA, providing a gamma voltage for the source driving circuit DD, etc.

[0033] Embodiments of the present application relate to a display device that adopts in-panel integrated touch technology to solve the technical problem of horizontal stripe phenomena in the long horizontal mode.

[0034] Embodiments of the present application provide a display device, such as Figure 5 and Figure 6As shown, the display device includes a touch display panel TP, and the touch display panel TP includes a gate driving circuit GOA and a plurality of pixels PX. The gate driving circuit GOA includes multiple cascaded gate driving sub - circuits, and one - stage gate driving sub - circuit is electrically connected to one row of pixels. As Figure 7 shown, the period of a frame of the picture displayed by the touch display panel TP includes at least two display phases and at least one touch phase, and one touch phase is located between two display phases.

[0035] As Figure 5 and Figure 6 shown, the gate driving circuit GOA further includes a first control signal line XCK1 and a second control signal line XCK2. The first control signal line XCK1 is used to provide a first control signal to the i - th stage gate driving sub - circuit GOA_i before the touch phase arrives, so as to reset the i - th stage gate driving sub - circuit GOA_i. The second control signal line XCK2 is used to provide a second control signal to the (i + 1)-th stage gate driving sub - circuit GOA_i+1 after the touch phase ends, so as to turn on the (i + 1)-th stage gate driving sub - circuit GOA_i+1. In this way, problems of leakage and horizontal stripes caused by different waveforms of the gate driving sub - circuits in the touch phase and the display phase can be prevented. Wherein, i is a positive integer.

[0036] The gate driving circuit GOA further includes a start signal line STV and p clock signal lines (for example, CK1, CK2, CK3, CK4, CK5, CK6, etc.), and the p clock signal lines are respectively electrically connected to different - stage gate driving sub - circuits, and p is a positive integer. The duration of the high level of the first control signal transmitted by the first control signal line XCK1 is equal to the duration of the high level of the second control signal transmitted by the second control signal line XCK2.

[0037] As Figure 6As shown, there is a gap region BA between the i-th stage gate driving sub-circuit GOA_i and the (i + 1)-th stage gate driving sub-circuit GOA_i+1. The width of the gap region BA in the arrangement direction of the multi-stage gate driving sub-circuits is greater than the width of any stage gate driving sub-circuit in this arrangement direction. The first connection line CL1 connecting the i-th stage gate driving sub-circuit GOA_i to the first control signal line XCK1 and the second connection line CL2 connecting the (i + 1)-th stage gate driving sub-circuit GOA_i+1 to the second control signal line XCK2 are located in this gap region BA. The first connection line CL1 is arranged on the side of the i-th stage gate driving sub-circuit GOA_i facing the (i + 1)-th stage gate driving sub-circuit GOA_i+1, and the second connection line CL2 is arranged on the side of the (i + 1)-th stage gate driving sub-circuit GOA_i+1 facing the i-th stage gate driving sub-circuit GOA_i. The length of the first connection line CL1 is less than the length of the second connection line CL2. By arranging the first connection line and the second connection line in a sufficiently wide gap region, interference between the connection lines is avoided, ensuring reliable transmission of the first control signal and the second control signal, which is conducive to achieving precise control of the gate driving sub-circuit.

[0038] As Figure 5 , Figure 6 and Figure 7 shown, in the embodiment of the present application, before the touch stage arrives, and after the rising edge of the gate driving signal output by the i-th stage gate driving sub-circuit GOA_i appears, and after the touch stage ends, and before the rising edge of the gate driving signal output by the (i + 1)-th stage gate driving sub-circuit GOA_i+1 appears, the first control signal line XCK1 is used to control the reset of the i-th stage gate driving sub-circuit GOA_i (pull down the potential of the node Q), and the second control signal line XCK2 is used to control the start of the (i + 1)-th stage gate driving sub-circuit GOA_i+1 (pull up the potential of the node Q). Specifically, the first control signal line XCK1 is used to provide a first control signal to the i-th stage gate driving sub-circuit GOA_i before the touch stage arrives to reset the i-th stage gate driving sub-circuit GOA_i (pull down the potential of the node Q). The second control signal line XCK2 is used to provide a second control signal to the (i + 1)-th stage gate driving sub-circuit GOA_i+1 after the touch stage ends to turn on the (i + 1)-th stage gate driving sub-circuit GOA_i+1 (pull up the potential of the node Q). In this way, problems such as leakage and horizontal stripes caused by different waveforms of the gate driving signals of the gate driving sub-circuits in the touch stage and the display stage can be prevented.

[0039] In terms of the working principle, before the touch stage arrives, that is, before the end of a display stage, the i-th stage in the multi-stage gate driving sub-circuit and the gate driving sub-circuits before the i-th stage gate driving sub-circuit (for example, GOA_i-1, GOA_i-2) have all output gate driving signals. When the touch stage arrives, it is the time when the i-th stage gate driving sub-circuit GOA_i ends outputting the gate driving signal. The first control signal line XCK1 provides a first control signal to the i-th stage gate driving sub-circuit GOA_i before the touch stage arrives (before the end of the display stage) to reset the i-th stage gate driving sub-circuit GOA_i.

[0040] After the touch stage ends, that is, at the beginning of the next display stage, the second control signal line XCK2 provides a second control signal to the (i + 1)-th stage gate driving sub-circuit GOA_i+1 to turn on the (i + 1)-th stage gate driving sub-circuit GOA_i+1. This makes the waveforms of the gate driving signals output by the i-th stage gate driving sub-circuit GOA_i and the (i + 1)-th stage gate driving sub-circuit GOA_i+1 consistent with the waveforms of the gate driving signals of other stage gate driving sub-circuits, thus ensuring the uniformity of the cascaded transmission of the gate driving signals and effectively preventing the generation of horizontal stripes. At the same time, since the leaking signals do not participate in the cascaded transmission, it also prevents display abnormalities caused by leakage.

[0041] It should be added that: as Figure 7 shown, the first control signal is first at a low level and then at a high level in the display stage before the touch stage. The rising edge of the first control signal is after the rising edge of the clock signal input to the i-th stage gate driving sub-circuit GOA_i, and the falling edge of the first control signal is after the falling edge of the clock signal input to the i-th stage gate driving sub-circuit GOA_i. This means that the first control signal is input to the i-th stage gate driving sub-circuit GOA_i after the i-th stage gate driving sub-circuit GOA_i outputs the gate driving signal. The second control signal is first at a high level and then at a low level in the display stage after the touch stage. The rising edge of the second control signal is before the rising edge of the clock signal input to the (i + 1)-th stage gate driving sub-circuit GOA_i+1, and the falling edge of the second control signal is before the falling edge of the clock signal input to the (i + 1)-th stage gate driving sub-circuit GOA_i+1. This means that after the second control signal is input to the (i + 1)-th stage gate driving sub-circuit GOA_i+1, the (i + 1)-th stage gate driving sub-circuit GOA_i+1 outputs the gate driving signal.

[0042] In the embodiments of the present application, the circuit structures of each stage gate driving sub-circuit are similar. Taking the i-th stage gate driving sub-circuit GOA_i as an example, as Figure 5As shown, the gate driving sub-circuit includes a first transistor T41_i, a second transistor T11_i, and a third transistor T21_i.

[0043] Specifically, the gate of the first transistor T41_i is electrically connected to the gate driving signal output terminal of the subsequent stage gate driving sub-circuit (for example, the gate signal output terminal G_i+3 of the (i + 3)-th stage gate driving sub-circuit), the source is electrically connected to the low-level signal input terminal VSS, and the drain is electrically connected to the node Q_i of this gate driving sub-circuit. The gate of the second transistor T11_i is electrically connected to the gate driving signal output terminal of the previous stage gate driving sub-circuit (for example, the gate signal output terminal G_i-3 of the (i - 3)-th stage gate driving sub-circuit), the source is electrically connected to the high-level signal input terminal VGH, and the drain is electrically connected to the node Q_i. The gate of the third transistor T21_i is electrically connected to the node Q_i, the source is electrically connected to the clock signal line, and the drain is electrically connected to the gate driving signal output terminal G_i of the i-th stage gate driving sub-circuit GOA_i.

[0044] The gate of the first transistor T41_i of the i-th stage gate driving sub-circuit GOA_i is further electrically connected to the first control signal line XCK1, and the gate of the second transistor T11_i+1 of the (i + 1)-th stage gate driving sub-circuit GOA_i+1 is further electrically connected to the second control signal line XCK2.

[0045] The first control signal is used to pull down the potential of the node Q of the i-th stage gate driving sub-circuit GOA_i before the touch stage arrives. Specifically, the first control signal is first at a low level and then at a high level during the display stage before the touch stage. The rising edge of the first control signal is after the rising edge of the clock signal input to the i-th stage gate driving sub-circuit GOA_i, and the falling edge of the first control signal is after the falling edge of the clock signal input to the i-th stage gate driving sub-circuit GOA_i.

[0046] The second control signal is used to pull up the potential of the node Q of the (i + 1)-th stage gate driving sub-circuit GOA_i+1 after the touch stage ends. Specifically, the second control signal is first at a high level and then at a low level during the display stage after the touch stage. The rising edge of the second control signal is before the rising edge of the clock signal input to the (i + 1)-th stage gate driving sub-circuit GOA_i+1, and the falling edge of the second control signal is before the falling edge of the clock signal input to the (i + 1)-th stage gate driving sub-circuit GOA_i+1.

[0047] As an improvement, the first control signal line XCK1 is further configured to provide a first control signal to each of the gate driving sub - circuits GOA_i - k to GOA_i - 1 from the (i - k)-th stage to the (i - 1)-th stage of the gate driving sub - circuits before the touch stage arrives, so as to reset each of the gate driving sub - circuits GOA_i - k to GOA_i - 1 from the (i - k)-th stage to the (i - 1)-th stage of the gate driving sub - circuits. The second control signal line XCK2 is further configured to provide a second control signal to each of the gate driving sub - circuits GOA_i + 1 to GOA_i + j from the (i + 2)-th stage to the (i + j)-th stage of the gate driving sub - circuits after the touch stage ends, so as to turn on each of the gate driving sub - circuits GOA_i + 2 to GOA_i + j from the (i + 2)-th stage to the (i + j)-th stage of the gate driving sub - circuits, where k and j are both positive integers. Specifically, k and j are greater than or equal to 1 and less than or equal to p. For example, p is equal to 6, k is equal to 4, and j is equal to 3.

[0048] As Figure 5 As shown, in the embodiments of the present application, each gate driving sub - circuit further includes the following devices: a fourth transistor TrQ_i, a fifth transistor T51_i, a sixth transistor T52_i, a seventh transistor T53_i, an eighth transistor T54_i, a ninth transistor T32_i, a tenth transistor T42_i, an eleventh transistor TrG_i, and a capacitor Cbt_i.

[0049] The gate of the fourth transistor TrQ_i is electrically connected to the reset signal input terminal RST, the source is electrically connected to the low - level signal input terminal VSS, and the drain is electrically connected to the node Q_i of the i - th stage gate driving sub - circuit GOA_i;

[0050] The gate of the fifth transistor T51_i is electrically connected to the high - level signal input terminal VGH, and the source is electrically connected to the high - level signal input terminal VGH;

[0051] The gate of the sixth transistor T52_i is electrically connected to the node Q_i of the i - th stage gate driving sub - circuit GOA_i, the source is electrically connected to the low - level signal input terminal VSS, and the drain is electrically connected to the drain of the fifth transistor T51_i;

[0052] The gate of the seventh transistor T53_i is electrically connected to the drain of the fifth transistor T51_i, and the source is electrically connected to the high - level signal input terminal VGH;

[0053] The gate of the eighth transistor T54_i is electrically connected to the node Q_i of the i - th stage gate driving sub - circuit GOA_i, the source is electrically connected to the low - level signal input terminal VSS, and the drain is electrically connected to the drain of the seventh transistor T53_i;

[0054] The gate of the ninth transistor T32_i is electrically connected to the drain of the seventh transistor T53_i, the source is electrically connected to the low-level signal input terminal VSS, and the drain is electrically connected to the gate signal output terminal G_i of the i-th stage gate driver circuit GOA_i;

[0055] The gate of the tenth transistor T42_i is electrically connected to the drain of the seventh transistor T53_i, the source is electrically connected to the low-level signal input terminal VSS, and the drain is electrically connected to the node Q of the i-th stage gate driver circuit GOA_i;

[0056] The gate of the eleventh transistor TrG_i is electrically connected to the reset signal input terminal RST, the source is electrically connected to the low-level signal input terminal VSS, and the drain is electrically connected to the gate signal output terminal G_i of the i-th stage gate driver circuit GOA_i;

[0057] The first plate of the capacitor Cbt_i is electrically connected to the node Q_i of the i-th stage gate driver circuit GOA_i, and the second plate is electrically connected to the gate signal output terminal G_i of the i-th stage gate driver circuit GOA_i.

[0058] In addition, the gates of the first transistors T41 in each of the gate driver circuits from the (i - k)-th stage gate driver circuit GOA_i-k to the (i - 1)-th stage gate driver circuit GOA_i-1 are also electrically connected to the first control signal line XCK1. The gates of the second transistors T11 in each of the gate driver circuits from the (i + 2)-th stage gate driver circuit GOA_i+2 to the (i + j)-th stage gate driver circuit GOA_i+j are also electrically connected to the second control signal line XCK2.

[0059] As Figure 8As shown, by comparing the potential curve Q1 of the node Q of the i-th stage gate driving sub-circuit GOA_i corresponding to the arrival of the touch control stage with the potential curve Q2 of the node Q of other stage gate driving sub-circuits corresponding to the display stage before the arrival of the touch control stage or the node Q of other stage gate driving sub-circuits corresponding to the display stage after the end of the touch control stage, it can be seen that the potential Q1_1 of the node Q of the i-th stage gate driving sub-circuit GOA_i corresponding to the arrival of the touch control stage is basically the same as the potential Q2_1 of the node Q of other stage gate driving sub-circuits corresponding to the display stage before the arrival of the touch control stage or the node Q of other stage gate driving sub-circuits corresponding to the display stage after the end of the touch control stage. By comparing the potential curve G1 of the gate driving signal output terminal of the i-th stage gate driving sub-circuit GOA_i corresponding to the arrival of the touch control stage with the potential curve G2 of the gate driving signal output terminal of other stage gate driving sub-circuits corresponding to the display stage before the arrival of the touch control stage or the gate driving signal output terminal of other stage gate driving sub-circuits corresponding to the display stage after the end of the touch control stage, it can be seen that the potential G1_1 of the gate driving signal output terminal of the i-th stage gate driving sub-circuit GOA_i corresponding to the arrival of the touch control stage is basically the same as the potential G2_1 of the gate driving signal output terminal of other stage gate driving sub-circuits corresponding to the display stage before the arrival of the touch control stage or the gate driving signal output terminal of other stage gate driving sub-circuits corresponding to the display stage after the end of the touch control stage. This indicates that by setting the first control signal line XCK1 and the second control signal line XCK2 in the gate driving circuit GOA, and resetting the i-th stage gate driving sub-circuit GOA_i and its previous k - 1 stage gate driving sub-circuits through the first control signal line XCK1 before the arrival of the touch control stage, and enabling the j stage gate driving sub-circuits after the i-th stage gate driving sub-circuit GOA_i through the second control signal line XCK2 after the end of the touch control stage, the technical solution of the present application can effectively solve the technical problems of leakage and horizontal stripe defects caused by the difference in the waveforms of the gate driving signals output by the (i - k + 1)-th stage gate driving sub-circuit GOA_i - k + 1 to the i-th stage gate driving sub-circuit GOA_i and the (i + 1)-th stage gate driving sub-circuit GOA_i + 1 to the (i + j)-th stage gate driving sub-circuit GOA_i + j and the waveforms of the gate driving signals of other gate driving sub-circuits in the prior art after passing through the touch control stage.

[0060] The display device according to the embodiment of the present application can be applied to the touch display panel TP of terminal devices such as notebook computers, tablet computers, and mobile phones. Through the technical solution of the present application, the influence of leakage on the cascade transmission of the gate driving signal (the gate driving signal also serves as a stage transmission signal) can be effectively prevented, thereby avoiding display abnormalities such as black screens and horizontal stripes and improving the display effect.

[0061] The display device of the present application sets a first control signal line XCK1 and a second control signal line XCK2 in the gate driving circuit GOA. Before the touch stage arrives, the first control signal line XCK1 provides a first control signal to the i-th stage gate driving sub-circuit GOA_i and its previous k - 1 stage gate driving sub-circuits. After the touch stage ends, the second control signal line XCK2 provides a second control signal to the j stage gate driving sub-circuits after the i-th stage gate driving sub-circuit GOA_i. Thus, before the touch stage starts, the i-th stage gate driving sub-circuit GOA_i and its previous k - 1 stage gate driving sub-circuits are reset, and after the touch stage ends, the j stage gate driving sub-circuits after the i-th stage gate driving sub-circuit GOA_i are turned on. This technical solution can prevent the leakage problem caused by the overlong holding time of the node Q potential during the touch stage, ensure the normal cascade transmission of the gate driving signal after the touch stage ends, and enable each stage of the gate driving sub-circuit to work normally according to the predetermined timing sequence. Since the leakage problem is effectively controlled, the waveform failure of the gate driving signal caused by leakage is avoided, thereby preventing the occurrence of the black screen phenomenon.

[0062] The above technical solution can make the voltage stress time of the thin film transistor devices related to the node Q of the gate driving sub-circuit corresponding to the touch stage and the thin film transistor devices related to the node Q of the gate driving sub-circuit corresponding to the display stage tend to be consistent, thus fundamentally avoiding the horizontal stripe defect caused by inconsistent stress time.

[0063] The embodiments of the present application have been introduced in detail above. The content of this specification should not be construed as a limitation on the protection scope of the present application.

Claims

1. A display device, characterized in that: include: A touch display panel, the touch display panel comprising a gate drive circuit and a plurality of pixels, the gate drive circuit comprising a plurality of cascaded gate drive sub-circuits, a gate drive sub-circuit at a stage being electrically connected to a row of pixels; Wherein, a period of one frame of picture displayed by the touch display panel includes at least two display phases and at least one touch phase, and one touch phase is located between two display phases; The gate drive circuit also includes a first control signal line and a second control signal line, the first control signal line is used to provide a first control signal to the i-th gate drive sub-circuit in the multiple stages of the gate drive sub-circuit before the touch stage arrives, so as to reset the i-th gate drive sub-circuit, and the second control signal line is used to provide a second control signal to the i+1-th gate drive sub-circuit in the multiple stages of the gate drive sub-circuit after the touch stage ends, so as to turn on the i+1-th gate drive sub-circuit, wherein i is a positive integer.

2. The display device according to claim 1, characterized in that The gate drive subcircuit comprises: a first transistor, wherein a gate of the first transistor is electrically connected to a gate drive signal output terminal of a subsequent gate drive subcircuit, a source of the first transistor is electrically connected to a low level signal input terminal, and a drain of the first transistor is electrically connected to a node Q of the gate drive subcircuit; a second transistor, wherein a gate of the second transistor is electrically connected to a gate drive signal output terminal of a previous gate drive subcircuit, a source of the second transistor is electrically connected to a high level signal input terminal, and a drain of the second transistor is electrically connected to the node Q; a third transistor, wherein a gate of the third transistor is electrically connected to the node Q, a source of the third transistor is electrically connected to a clock signal line, and a drain of the third transistor is electrically connected to a gate drive signal output terminal of the gate drive subcircuit; Among them, the gate of the first transistor of the i-th level gate driving sub-circuit is also electrically connected to the first control signal line, and the gate of the second transistor of the i+1-th level gate driving sub-circuit is also electrically connected to the second control signal line.

3. The display device according to claim 2, characterized in that: The first control signal is used to pull down the potential of the node Q_i of the i-th gate driving sub-circuit before the touch control stage arrives.

4. The display device according to claim 3, characterized in that: The first control signal is first at a low level and then at a high level in the display stage before the touch stage, the rising edge of the first control signal is located after the rising edge of the clock signal input to the i-th gate drive sub-circuit, and the falling edge of the first control signal is located after the falling edge of the clock signal input to the i-th gate drive sub-circuit.

5. The display device according to claim 2, characterized in that: The second control signal is used to pull up the potential of the node Q_i+1 of the i+1th gate driving sub-circuit after the touch control stage ends.

6. The display device according to claim 5, characterized in that: The second control signal is first at a high level and then at a low level in the display stage after the touch stage, the rising edge of the second control signal is located before the rising edge of the clock signal input to the i+1th level gate drive sub-circuit, and the falling edge of the second control signal is located before the falling edge of the clock signal input to the i+1th level gate drive sub-circuit.

7. The display device according to claim 1, characterized in that The first control signal line is further used to provide the first control signal to each of the gate driving sub-circuits of the ikth to i-1th levels before the touch stage arrives, so as to reset each of the gate driving sub-circuits of the ikth to i-1th levels. The second control signal line is further used to provide the second control signal to each of the gate driving sub-circuits of the i+2th to i+jth levels after the touch stage ends, so as to turn on each of the gate driving sub-circuits of the i+2th to i+jth levels. Wherein, k and j are both positive integers.

8. The display device according to claim 7, characterized in that: The first control signal line is also electrically connected to the gate of the first transistor of each gate driving sub-circuit from the ikth gate driving sub-circuit to the i-1th gate driving sub-circuit; The second control signal line is also electrically connected to the gate of the second transistor of each of the gate driving sub-circuits from the i+2th to the i+jth gate driving sub-circuits.

9. The display device according to claim 1, characterized in that: A duration of a high level of the first control signal transmitted by the first control signal line is equal to a duration of a high level of the second control signal transmitted by the second control signal line.

10. The display device according to claim 1, characterized in that There is a gap area between the i-th level gate driving sub-circuit and the i+1-th level gate driving sub-circuit, and the first connecting line connecting the i-th level gate driving sub-circuit and the first control signal line and the second connecting line connecting the i+1-th level gate driving sub-circuit and the second control signal line are located in the gap area.

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