A memory read-write consistency test method and system

Abstract

The present invention discloses a memory read-write consistency test method and system, which relates to the field of memory test technology. It includes: S1: performing crosstalk coupling modeling: constructing an inter-layer crosstalk coupling transfer function based on the quantum tunneling current curve and the three-dimensional parasitic parameter matrix; S2: constructing a three-dimensional failure probability model: obtaining a planar coupling error distribution map, and generating an inter-layer crosstalk coefficient matrix based on the inter-layer crosstalk coupling transfer function; S3: identifying electromagnetic coupling hotspot areas: determining the risk level of each area based on the three-dimensional failure probability, and setting test parameters based on the risk level, and performing read-write tests on the memory to be tested through the test parameters. The present invention realizes three-dimensional quantitative modeling of cross-layer interference, so that the detection range is expanded from the plane to the three-dimensional structure, solving the blind spots of the traditional method for inter-layer electromagnetic coupling.

Description

Technical Field

[0001] The present invention relates to the technical field of memory testing, and in particular to a memory read-write consistency testing method and system. Background Art

[0002] With the rapid development of information technology, memory technology has evolved from traditional mechanical hard disk drives (HDDs) to solid-state drives (SSDs), flash memory (such as NAND / NOR), and new non-volatile memories (such as MRAM and PRAM). These memories have continuously improved in speed, capacity, and energy consumption, becoming core components of modern electronic devices (such as smartphones, servers, and AI chips).

[0003] Memory consistency testing is a critical step in ensuring data integrity and system stability during read and write operations. Whether in a single-processor system or a multi-processor shared memory system (e.g., cache coherence issues), memory must maintain data consistency under various operating conditions (e.g., extreme temperatures, high loads), otherwise it will result in data corruption, system crashes, or security risks.

[0004] Chinese invention patent publication number CN116705131A discloses a memory read and write test method and test equipment, including: using the test equipment to drive a test vector pre-stored in the programmable device to cause the programmable device to execute a write mode in a memory chip under test to provide address and logic pattern data required for the write test, wherein the programmable device and the memory chip under test are respectively communicatively connected to an input end of a comparator, so that the comparator compares the output data of the memory chip under test with the data input by the programmable device in real time. If the data are consistent, the comparator outputs a logic high; if not, it outputs a logic low until the entire read test is completed; during the entire test operation, the test equipment samples, analyzes and judges the real-time output data of the comparator. If the real-time output data of the comparator are all high throughout the entire process, the test passes; otherwise, the test fails.

[0005] However, the process nodes of existing high-density memories are mostly 5nm and below, so the continued miniaturization of memory cell size will cause vertical coupling interference. Fixed-mode test solutions are not only unable to effectively characterize the dynamic impact of subthreshold leakage current on data retention characteristics, but also unable to cover the statistical distribution characteristics of memory cell electrical parameters caused by process fluctuations, making it difficult to accurately detect failed cells at the process edge. At the same time, traditional interference detection mechanisms are mostly based on two-dimensional plane processing and cannot cope with the read-write consistency degradation problem caused by cross-layer electromagnetic coupling in three-dimensional architectures such as 3D NAND / HBM in existing high-density memories. This leads to a serious mismatch between the test dimensions and the actual working scenarios of the device, which in turn creates a major blind spot in the reliability assessment of advanced memories during the mass production verification stage. Summary of the Invention

[0006] The object of the present invention is to provide a memory read-write consistency test method and system to solve the problems raised in the above background technology.

[0007] To achieve the above object, the present invention provides the following technical solution: a memory read-write consistency test method, comprising:

[0008] S1: Perform crosstalk coupling modeling: Construct a quantum tunneling current curve based on the transistor SPICE model and wafer test data, construct a three-dimensional parasitic parameter matrix based on the GDSII layout data of the memory array, and construct an inter-layer crosstalk coupling transfer function based on the quantum tunneling current curve and the three-dimensional parasitic parameter matrix;

[0009] S2: Constructing a three-dimensional failure probability model: Obtaining a planar coupling error distribution diagram based on the quantum tunneling current curve and the three-dimensional parasitic parameter matrix, and generating an interlayer crosstalk coefficient matrix based on the interlayer crosstalk coupling transfer function, and establishing a three-dimensional failure probability model based on the planar coupling error distribution diagram and the interlayer crosstalk coefficient matrix, including:

[0010] S2.1: Obtaining test results: Optimizing the quantum tunneling current curve and the three-dimensional parasitic parameter matrix using a reinforcement learning algorithm, and obtaining a test vector based on the interlayer crosstalk coupling transfer function;

[0011] S2.2: Obtaining a distribution map: Performing a read and write test on the memory device under test according to the test vector, and obtaining an inter-layer crosstalk coefficient based on the test results. Simultaneously, constructing a planar coupling error distribution map and an inter-layer crosstalk coefficient matrix using the test results and the inter-layer crosstalk coefficient.

[0012] S2.3: Determine three-dimensional failure hotspots: Perform spatial interpolation based on the planar coupling error distribution map and the interlayer crosstalk coefficient matrix to obtain a three-dimensional failure probability;

[0013] S3: Identify electromagnetic coupling hotspot areas: determine the risk level of each area based on the three-dimensional failure probability, set test parameters based on the risk level, and perform read and write tests on the memory to be tested using the test parameters.

[0014] Furthermore, the inter-layer crosstalk coupling transfer function is constructed, including:

[0015] S1.1: Obtaining a time-domain interference signal: Based on the transistor SPICE model and wafer test data, the threshold voltage and off-current of each transistor are obtained. The electric field strength and tunneling current density are obtained through FN tunneling effect simulation. At the same time, the time-domain interference signal is obtained based on the electric field strength and tunneling current density. Specifically,

[0016]

[0017] in: is the power spectral density of the interference source, is the time length of the signal, is the time domain waveform of the quantum tunneling current, is the base of natural logarithm, is the imaginary unit, is the frequency, is the time variable;

[0018] S1.2: Constructing a crosstalk transfer function: Based on the GDSII layout data of the memory array, determine the geometric parameters of the metal lines and vias in each layer of the memory array, obtain the scattering parameters and electric field / magnetic field distribution, and construct a three-dimensional parasitic parameter matrix. At the same time, based on the three-dimensional parasitic parameter matrix and the power spectral density of the interference source, determine the temperature-dependent crosstalk transfer function, specifically:

[0019]

[0020] in: is the temperature-dependent crosstalk transfer function, is the crosstalk power spectrum density at the receiving end, is the power spectral density of the interference source, is the base of natural logarithm, Temperature The attenuation coefficient, is the metal layer spacing;

[0021] S1.3: Temperature gradient calibration: Based on the temperature-dependent crosstalk transfer function, obtain the receiving end crosstalk power spectrum density at different temperatures and determine the magnitude of the attenuation coefficient in the crosstalk transfer function, specifically:

[0022]

[0023] in: Temperature The attenuation coefficient under is the attenuation coefficient at the reference temperature, is the temperature coefficient, is the current temperature, is the base temperature.

[0024] Furthermore, the electric field strength and tunneling current density are obtained, including:

[0025] WA1: Extracting electrical parameters: Use a semiconductor parameter analyzer to perform electrical testing on the transistors of the memory device under test, obtain the threshold voltage and off-current of each transistor, construct a statistical distribution histogram of the threshold voltage and off-current, and use linear extrapolation to obtain the Ids-Vgs curve and threshold voltage / off-current extraction diagram;

[0026] WA2: Generate current density curve: Use the set BSIM-CMG model to simulate the FN tunneling effect, obtain the tunneling current density and electric field strength, and construct a tunneling current density-electric field strength curve;

[0027] WA3: Statistical modeling: Based on the Ids-Vgs curve, threshold voltage / off current extraction diagram, and tunneling current density-electric field strength curve, a Monte Carlo method is used for simulation to obtain the distribution histogram of the threshold voltage and the statistical characteristics of the tunneling current density.

[0028] Furthermore, a three-dimensional parasitic parameter matrix is ​​constructed, including:

[0029] WB1: Extract parasitic parameters: Based on the GDSII layout data of the memory array in the memory under test, determine the geometric parameters of the metal lines and vias of each layer, and obtain the parasitic capacitance and parasitic inductance between adjacent layers. Specifically:

[0030]

[0031] in: is the parasitic capacitance, is the relative dielectric constant of the medium, is the dielectric constant of vacuum, is the effective overlapping area of ​​the metal plates, is the metal layer spacing, is the parasitic inductance, is the vacuum permeability, is the relative magnetic permeability of the conductor material, is the wire length, is the wire width;

[0032] WB2: Perform full-wave simulation: according to the parasitic capacitance and parasitic inductance, set the simulation initial value of the high-frequency structure simulator, and perform full-wave simulation to obtain scattering parameters and electric field / magnetic field distribution;

[0033] WB3: Generate 3D parasitic matrix: Construct a 3D parasitic matrix based on the geometric parameters, scattering parameters, and electric / magnetic field distribution of the metal lines and vias of each layer.

[0034] Furthermore, test vectors are obtained, including:

[0035] S2.1.1: Obtaining the Q value of the test vector: Normalize the quantum tunneling current curve and the three-dimensional parasitic parameter matrix to construct a state vector, use the state vector as input to a deep Q network model, and output the Q value of the test vector obtained from the state vector;

[0036] S2.1.2: Set the reward function: Obtain the total number of defective cells through 3D NAND testing. At the same time, determine the reward function based on the number of newly detected defects and the test time. Specifically, it is:

[0037]

[0038] in: For instant rewards, is the coverage weight coefficient, For test coverage, is the time penalty coefficient, Time-consuming for testing;

[0039] S2.1.3: Update the Q value of the test vector: Update the Q value of the test vector using the ε-greedy strategy algorithm and the reward function, specifically:

[0040]

[0041] in: is the Q value of the test vector after the current state is updated, is the Q value of the original test vector of the current state, is the learning rate, is the discount factor, For instant rewards, is the maximum Q value of the test vector for the next state.

[0042] Furthermore, the planar coupling error distribution map and inter-layer crosstalk coefficient matrix are constructed, including:

[0043] S2.2.1: Determine the inter-layer crosstalk coefficient matrix: Input the test vector into the row / column driver circuit of the memory to be tested, perform a read / write test, and obtain the error location and error frequency. At the same time, based on the error location, error frequency and crosstalk transfer function, determine the inter-layer crosstalk coefficient, specifically:

[0044]

[0045] in: is the inter-layer crosstalk coefficient, is the frequency-dependent geometric coupling weight, is the temperature-dependent crosstalk transfer function, is the frequency;

[0046] S2.2.2: Generate a distribution map: construct a planar coupling error distribution map based on the error position and error frequency, and combine the planar coupling error distribution map with the inter-layer crosstalk coefficient to obtain an inter-layer crosstalk coefficient matrix.

[0047] Furthermore, the three-dimensional failure probability is obtained, including:

[0048] S2.3.1: Row and column interpolation: Perform spatial interpolation based on the planar coupling error distribution map and the interlayer crosstalk coefficient matrix to obtain row and column direction interpolation, specifically:

[0049]

[0050] in: is the error probability after interpolation at the row coordinate x, For the line The error probability, is the row coordinate of the current interpolation point, is the adjacent left row coordinate with known error probability, is the adjacent right row coordinate with known error probability, For the line The error probability, is the error probability after interpolation at the column coordinate y, For columns The error probability, is the column coordinate of the current interpolation point, is the adjacent left column coordinate of the known error probability, For columns The error probability, is the adjacent right column coordinate of the known error probability;

[0051] S2.3.2: Bilinear interpolation: Perform bilinear interpolation based on the row and column interpolation to obtain the error probability after interpolation at the two-dimensional plane (x, y), specifically:

[0052]

[0053] in: is the error probability after interpolation on the two-dimensional plane (x, y), is the error probability after interpolation at the row coordinate x, is the error probability after interpolation at the column coordinate y;

[0054] S2.3.3: Determine the three-dimensional failure probability: Based on the interpolated error probability and the interlayer crosstalk coefficient matrix at the two-dimensional plane (x, y), determine the corresponding three-dimensional failure probability, specifically:

[0055]

[0056] in: is the failure probability of the memory cell at row x, column y, layer n, is the inter-layer crosstalk coefficient, is the error probability after interpolation on the two-dimensional plane (x, y), are the numbers of all other layers that may interfere with the current layer n. Numbers the vertical stacking layer where the storage unit is located.

[0057] Furthermore, the memory under test is subjected to read and write tests, including:

[0058] S3.1: Determine test parameters: Compare the three-dimensional failure probability with a preset probability threshold range, and based on the comparison results, classify the areas corresponding to the three-dimensional failure probability into risk levels. Based on the risk level classification results, adjust the test parameters for different risk areas, specifically:

[0059] When the risk area is a high-risk area, the number of test iterations is increased and the voltage margin is tightened; when the risk area is a medium-risk area, the number of tests is partially increased and the timing margin is adjusted; when the risk area is a low-risk area, the test parameters remain unchanged;

[0060] S3.2: GDSII layout mapping: Convert the coordinates in the three-dimensional failure probability into physical coordinates in the GDSII layout, specifically:

[0061]

[0062] in: is the horizontal coordinate in the physical coordinate system, is the vertical coordinate in the physical coordinate system, is the stacked coordinate in the physical coordinate system, is the row coordinate of the current interpolation point, is the column coordinate of the current interpolation point, Number the vertical stacking layer where the storage unit is located. is the physical distance between adjacent rows, is the physical distance between adjacent columns, is the physical distance between adjacent layers, is the starting offset of the X axis, is the starting offset of the Y axis;

[0063] S3.3: Determine hotspot areas: Compare the three-dimensional failure probability in the GDSII layout with a failure probability threshold, and determine the hotspot areas based on the comparison results, specifically:

[0064] When the three-dimensional failure probability is greater than the failure probability threshold, the area of ​​the three-dimensional failure probability in the GDSII layout is a hotspot area; otherwise, the area of ​​the three-dimensional failure probability in the GDSII layout is not a hotspot area;

[0065] S3.4: Determine the final test parameters of the hot spot area: Set the compensation voltage of the hot spot area using the temperature compensation coefficient, specifically:

[0066]

[0067] Specifically: is the compensation voltage, is the nominal voltage, is the temperature coefficient, is the nominal temperature, is the current temperature;

[0068] S3.5: Obtaining a test parameter set: performing a read / write test on the memory to be tested using the adjusted test parameters and the compensation voltage of the hot spot area to obtain a read / write test result.

[0069] Furthermore, the three-dimensional failure probability is compared with a preset probability threshold range, and based on the comparison result, the risk level of the area corresponding to the three-dimensional failure probability is divided into the following categories:

[0070] When the three-dimensional failure probability is greater than the upper limit threshold of the preset probability, the area corresponding to the three-dimensional failure probability is a high-risk area; when the three-dimensional failure probability is within the preset probability threshold range, the area corresponding to the three-dimensional failure probability is a medium-risk area; otherwise, the area corresponding to the three-dimensional failure probability is a low-risk area.

[0071] A memory read-write consistency test system uses any one of the above-mentioned memory read-write consistency test methods.

[0072] Compared with the prior art, the present invention has the following beneficial effects:

[0073] First, the present invention extracts metal layer spacing and via geometry parameters from the GDSII layout to construct a three-dimensional parasitic capacitance / inductance matrix, quantifying the strength of cross-layer electromagnetic coupling. Combined with the temperature-dependent attenuation coefficient, and by obtaining the attenuation characteristics of the crosstalk power spectrum density at different temperatures, this method covers the impact of metal layer spacing and temperature gradients on signal integrity in a 3D stack. This achieves three-dimensional quantitative modeling of cross-layer interference, expanding the detection range from planar to three-dimensional structures, and addressing the blind spots of traditional methods for interlayer electromagnetic coupling.

[0074] Second, the present invention extracts the statistical distribution of threshold voltage / off current through the Ids-Vgs curve and performs Monte Carlo simulation of quantum tunneling current density to generate a dynamic interference signal model under process fluctuations. Simultaneously, through a deep Q network and based on real-time test coverage and test time, it dynamically generates corresponding test vectors, thereby covering process edge failure units and reducing the risk of escape defects in mass production.

[0075] Thirdly, the present invention applies a compensation voltage to the hotspot area, thereby offsetting the threshold voltage shift caused by temperature drift and improving reliability in temperature gradient scenarios.

[0076] Fourthly, the present invention generates a corresponding three-dimensional risk heat map through bilinear interpolation and interlayer coupling superposition, and adjusts the number of test iterations and voltage margin according to the risk level, thereby achieving precise allocation of test resources, shortening the test time, and improving the test accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 Schematic diagram of the read-write consistency test method of the present invention;

[0078] Figure 2 is a planar coupling error distribution diagram in the present invention;

[0079] Figure 3 This is an analysis diagram of electromagnetic crosstalk between chip layers in the present invention;

[0080] Figure 4 Schematic diagram of Ids-Vgs curve and threshold voltage / off current extraction in the present invention;

[0081] Figure 5 is a statistical distribution diagram of the shutdown current in the present invention;

[0082] Figure 6 is a tunneling current density-electric field intensity curve diagram in the present invention;

[0083] Figure 7 This is a three-dimensional electric field distribution diagram in the present invention. DETAILED DESCRIPTION

[0084] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0085] The process nodes of existing high-density memories are mostly 5nm and below, so the continuous miniaturization of memory cell size will cause vertical coupling interference. The fixed-mode test scheme not only cannot effectively characterize the dynamic impact of subthreshold leakage current on data retention characteristics, but also cannot cover the statistical distribution characteristics of the electrical parameters of the memory cell caused by process fluctuations, making it difficult to accurately detect process edge failure units. At the same time, traditional interference detection mechanisms are mostly based on two-dimensional plane processing, which cannot cope with the read-write consistency degradation problem caused by cross-layer electromagnetic coupling in three-dimensional architectures such as 3D NAND / HBM in existing high-density memories, resulting in a serious mismatch between the test dimension and the actual working scenario of the device, which in turn makes the reliability assessment of advanced memories in the mass production verification stage have a major blind spot. The technical solution of this application constructs an inter-layer crosstalk transfer function through quantum tunneling effect modeling and three-dimensional parasitic parameter analysis, and combines reinforcement learning to dynamically optimize test vectors to generate a three-dimensional failure probability model of cross-layer electromagnetic coupling, and dynamically adjust test parameters based on risk levels. At the same time, through temperature gradient calibration, spatial interpolation and GDSII layout mapping, the electromagnetic coupling hotspot area is accurately located, which solves the blind spot of traditional two-dimensional testing on the interference between 3D architecture layers, improves the detection capability of edge failure units under process fluctuations, and ensures the data reliability of the memory under extreme conditions.

[0086] Example 1

[0087] refer to Figure 1 This embodiment provides a memory read-write consistency test method, which specifically includes the following steps:

[0088] Step S1: Perform crosstalk coupling modeling. Specifically, a quantum tunneling current curve is constructed based on the transistor SPICE model and wafer test data of the memory under test. Based on this quantum tunneling current curve, an interference source model is established. Simultaneously, a three-dimensional parasitic parameter matrix is ​​constructed using the GDSII layout data of the memory array in the memory under test. Based on this three-dimensional parasitic parameter matrix, an interlayer crosstalk coupling transfer function is constructed. The details are as follows:

[0089] Step S1.1: Obtain a time-domain interference signal. Specifically, based on the transistor SPICE model and wafer test data of the memory device under test, obtain the threshold voltage and off-state current corresponding to each transistor. Simultaneously, perform FN tunneling effect simulation using the configured BSIM-CMG model to obtain the corresponding electric field strength and tunneling current density. Furthermore, a Monte Carlo simulation is performed based on the threshold voltage, off-state current, electric field strength, and tunneling current density, obtaining a distribution histogram of the threshold voltage and statistical characteristics of the tunneling current density.

[0090] Specifically, according to the obtained distribution histogram of the threshold voltage and the statistical characteristics of the tunneling current density, the quantum tunneling current is converted into a time domain interference signal, specifically:

[0091]

[0092] in: is the power spectral density of the interference source, is the time length of the signal, is the time domain waveform of the quantum tunneling current, is the base of natural logarithm, is the imaginary unit, is the frequency, is the time variable.

[0093] Step S1.2: Construct a crosstalk transfer function. This involves determining the geometric parameters of the metal lines and vias corresponding to each layer based on the GDSII layout data of the memory array in the memory device under test. Simultaneously, based on the coupling structure between adjacent layers, the corresponding scattering parameters and electric / magnetic field distributions are obtained, and the corresponding three-dimensional parasitic parameter matrix is ​​constructed.

[0094] Specifically, based on the three-dimensional parasitic parameter matrix, an impedance network between nodes is constructed, and through circuit simulation, the corresponding receiving end crosstalk power spectrum density is obtained, which is specifically:

[0095]

[0096] in: is the crosstalk power spectrum density at the receiving end, is the frequency domain voltage of the victim node, is the time length of the signal, is the base of natural logarithm, is the imaginary unit, is the frequency, is the time variable, is the load impedance, is the background noise power spectral density.

[0097] Furthermore, based on the obtained receiving end crosstalk power spectrum density and the power spectrum density of the interference source obtained in step S1.1, a temperature-dependent crosstalk transfer function is determined, specifically:

[0098]

[0099] in: is the temperature-dependent crosstalk transfer function, is the crosstalk power spectrum density at the receiving end, is the power spectral density of the interference source, is the base of natural logarithm, Temperature The attenuation coefficient, is the metal layer spacing.

[0100] In the specific implementation process, when the temperature is 25°C and the frequency is 1 GHz, the corresponding power spectrum density of the interference source is 0.5 μW, the crosstalk power spectrum density of the receiving end is 0.1 μW, and the temperature-related attenuation coefficient is 2.5*10 4 At the same time, the metal layer spacing is 50nm, and the corresponding temperature-related crosstalk transfer function is 0.198.

[0101] Step S1.3: Temperature gradient calibration. That is, based on the temperature-dependent crosstalk transfer function obtained in step S1.2, under the premise of fixing the power spectrum density of the interference source, the crosstalk power spectrum density of the receiving end at different temperatures is obtained, thereby determining the crosstalk transfer function at different temperatures, and then determining the size of the attenuation coefficient in the crosstalk transfer function, specifically:

[0102]

[0103] in: Temperature The attenuation coefficient under is the attenuation coefficient at the reference temperature, is the temperature coefficient, is the current temperature, is the base temperature.

[0104] Furthermore, according to the set temperature and the attenuation coefficient of the corresponding temperature, a mapping relationship between the temperature and the attenuation coefficient is determined, thereby obtaining the crosstalk intensity at different temperatures.

[0105] Step S2: Construct a three-dimensional failure probability model. That is, optimize the time domain interference signal obtained in step S1.1 and the three-dimensional parasitic parameter matrix obtained in step S1.2 through a reinforcement learning algorithm to obtain the corresponding test vector. At the same time, based on the obtained test vector, obtain the corresponding plane coupling error distribution diagram, and based on the crosstalk transfer function obtained in step S1.3, generate the corresponding inter-layer crosstalk coefficient matrix. And based on the plane coupling error distribution diagram and the inter-layer crosstalk coefficient matrix, establish a three-dimensional failure probability model. The details are as follows:

[0106] Step S2.1: Obtain test results. That is, through the reinforcement learning algorithm, dynamically optimize the threshold voltage, off current, electric field strength, and tunneling current density obtained in step S1.1, and the crosstalk transfer function constructed in step S1.2 to obtain the corresponding test vector. The details are as follows:

[0107] Step S2.1.1: Obtain the Q value of the test vector. That is, the threshold voltage and shutdown current obtained in step S1.1 are normalized to obtain the corresponding normalized threshold voltage and normalized shutdown current. Simultaneously, the current operating temperature and power supply voltage fluctuation obtained in step S1.2 are normalized to obtain the corresponding normalized operating temperature and normalized power supply voltage fluctuation. Furthermore, a corresponding state vector is constructed based on the obtained normalized threshold voltage, normalized shutdown current, normalized operating temperature, and normalized power supply voltage fluctuation.

[0108] Furthermore, the constructed state vector is used as the input of the deep Q network model, and the Q value of the test vector corresponding to each state vector is obtained as the output.

[0109] Step S2.1.2: Set the reward function. This means obtaining the total number of defective cells through 3D NAND testing. Simultaneously, during the testing process in step S2.1, the number of newly detected defects and the test time are determined. Furthermore, based on the newly detected number of defects and the test time, a corresponding reward function is obtained, specifically:

[0110]

[0111] in: For instant rewards, is the coverage weight coefficient, For test coverage, is the time penalty coefficient, Testing takes time.

[0112] During the specific implementation process, when the current state vector is running, 5 new defects are detected, the total number of defects is 100, and it takes 2ms, then the corresponding immediate reward is 0.3.

[0113] Step S2.1.3: Update the Q-value of the test vector. This is done by using the ε-greedy strategy algorithm and the instant reward obtained in step S2.2 to update the Q-value of the test vector obtained in step S2.1. Specifically, the Q-value of the test vector in the current state is updated using the maximum Q-value of the next adjacent state vector and the set instant reward, as follows:

[0114]

[0115] in: is the Q value of the test vector after the current state is updated, is the Q value of the original test vector of the current state, is the learning rate, is the discount factor, For instant rewards, is the maximum Q value of the test vector for the next state.

[0116] Step S2.2: Obtain a distribution map. That is, based on the updated test vector obtained in step S2.1.3, perform read and write tests on the memory under test, and obtain the inter-layer crosstalk coefficient based on the test results. At the same time, based on the test results and the inter-layer crosstalk coefficient, construct a planar coupling error distribution map and an inter-layer crosstalk coefficient matrix. The details are as follows:

[0117] Step S2.2.1: Determine the inter-layer crosstalk coefficient matrix. This involves inputting the updated test vector obtained in step S2.1.3 into the row / column driver circuits of the memory under test and performing read and write operations. Simultaneously, sensors or external probes on the row / column driver circuits of the memory under test are used to obtain the corresponding error locations and error frequencies, i.e., the row / column addresses of the corresponding error cells and the number of errors occurring per unit time.

[0118] Furthermore, the obtained error position and error frequency are combined with the crosstalk transfer function constructed in step S1.2 to obtain the corresponding inter-layer crosstalk coefficient, which is specifically:

[0119]

[0120] in: is the inter-layer crosstalk coefficient, is the frequency-dependent geometric coupling weight, is the temperature-dependent crosstalk transfer function, is the frequency.

[0121] During the specific implementation, crosstalk analysis was performed on the first and second layers of the memory under test through 3D NAND. The input frequency points were 0.5 GHz, 1 GHz, 1.5 GHz, and 2 GHz, and the temperature was set to 85°C. The data table shown in Table 1 was obtained, specifically:

[0122] Table 1: Data table

[0123] Frequency / GHz <![CDATA[Geometric coupling weight / μm 2 > Crosstalk transfer function 0.5 10 0.15 1 15 0.2 1.5 12 0.18 2 8 0.1

[0124] According to the data in Table 1 above, the corresponding inter-layer crosstalk coefficient is 7.46.

[0125] Step S2.2.2: Generate a distribution map. This is done by using the row / column addresses of the error cells and the number of errors per unit time obtained in step S2.2.1 to construct a planar coupling error distribution map. Simultaneously, based on the inter-layer crosstalk coefficients obtained in step S2.2.1, the inter-layer crosstalk coefficients are added to the constructed planar coupling error distribution map to obtain the corresponding inter-layer crosstalk coefficient matrix.

[0126] refer to Figure 2 , Figure 2 is the plane coupling error distribution diagram in this embodiment, Figure 2 It can be seen that the errors are concentrated in the coordinate area (rows 4-7, columns 3-6), forming an obvious high-density error cluster. There are sporadic low-frequency errors in other areas, which are consistent with the characteristics of random defects. In addition, at least one error is detected in about 30%-50% of the areas.

[0127] refer to Figure 3 , Figure 3 This is the electromagnetic crosstalk analysis diagram between chip layers in this embodiment, Figure 3 It can be seen that the maximum crosstalk path appears between the polysilicon layer and the metal 1 layer, with a crosstalk coefficient of 7.16. At the same time, the crosstalk between adjacent metal layers is strong, such as between the metal 2 layer and the metal 3 layer, and between the metal 3 layer and the metal 4 layer. As the inter-layer spacing increases, the crosstalk intensity decreases.

[0128] Step S2.3: Determine the three-dimensional failure hotspot. That is, perform spatial interpolation based on the planar coupling error distribution map and interlayer crosstalk coefficient matrix obtained in step S2.2.2, and obtain the three-dimensional failure probability based on the interpolation results. The details are as follows:

[0129] Step S2.3.1: Row and column interpolation. That is, based on the planar coupling error distribution map and interlayer crosstalk coefficient matrix obtained in step S2.2.2, spatial interpolation is performed to obtain the corresponding row and column direction interpolation, specifically:

[0130]

[0131] in: is the error probability after interpolation at the row coordinate x, For the line The error probability, is the row coordinate of the current interpolation point, is the adjacent left row coordinate with known error probability, is the adjacent right row coordinate with known error probability, For the line The error probability, is the error probability after interpolation at the column coordinate y, For columns The error probability, is the column coordinate of the current interpolation point, is the adjacent left column coordinate of the known error probability, For the column The error probability, is the adjacent right column coordinate of the known error probability.

[0132] In the specific implementation process, a test point data table as shown in Table 2 below is set, specifically:

[0133] Table 2: Test point data table

[0134] Row coordinates Column coordinates Error probability 200 300 0.8 200 310 0.6 210 300 0.7 210 310 0.5

[0135] According to the data in the test point data table in Table 2 above, the error probabilities of the micro-test units in row 205 and column 305 are 0.75 and 0.7 respectively.

[0136] Step S2.3.2: Bilinear interpolation. That is, based on the interpolated error probability at the row coordinate x and the interpolated error probability at the column coordinate y obtained in step S2.3.1, bilinear interpolation is performed to obtain the interpolated error probability at the two-dimensional plane (x, y). Specifically,

[0137]

[0138] in: is the error probability after interpolation on the two-dimensional plane (x, y), is the error probability after interpolation at the row coordinate x, is the error probability after interpolation at the column coordinate y.

[0139] In a specific implementation, the error probabilities of the micro-test units in row 205 and column 305 are 0.75 and 0.7 respectively, and the interpolated error probability at the position (205, 305) is 0.725.

[0140] Step S2.3.3: Determine the three-dimensional failure probability. That is, based on the interpolated error probability at the two-dimensional plane (x, y) obtained in step S2.3.2 and the interlayer crosstalk coefficient matrix determined in step S2.2.1, determine the corresponding three-dimensional failure probability, specifically:

[0141]

[0142] in: is the failure probability of the memory cell at row x, column y, layer n, is the inter-layer crosstalk coefficient, is the error probability after interpolation on the two-dimensional plane (x, y), are the numbers of all other layers that may interfere with the current layer n. Numbers the vertical stacking layer where the storage unit is located.

[0143] Step S3: Identify electromagnetic coupling hotspots. This involves classifying the risk levels based on the three-dimensional failure probabilities obtained in step S2.3.3. Based on the risk level classification results, corresponding test parameters are set. Furthermore, read and write tests are performed on the memory under test based on the set test parameters. The details are as follows:

[0144] Step S3.1: Determine test parameters. Compare the three-dimensional failure probability obtained in step S2.3.3 with the preset probability threshold range, and based on the comparison results, perform risk classification on the areas corresponding to the three-dimensional failure probability, specifically:

[0145] When the three-dimensional failure probability obtained is greater than the upper limit threshold of the preset probability, the area corresponding to the three-dimensional failure probability is a high-risk area. When the three-dimensional failure probability obtained is within the preset probability threshold range, the area corresponding to the three-dimensional failure probability is a medium-risk area. Otherwise, the area corresponding to the three-dimensional failure probability is a low-risk area.

[0146] Furthermore, a three-dimensional heat map is generated based on the three-dimensional failure probability obtained in step S2.3.3, and in the three-dimensional heat map, different risk areas are marked with different colors according to the determined risk areas.

[0147] Furthermore, according to the different risk areas marked, the test parameters for different risk areas are adjusted, specifically:

[0148] If the risk area is high, increase the number of test iterations and tighten the voltage margin. If the risk area is medium, partially increase the number of tests and adjust the timing margin. If the risk area is low, keep the test parameters unchanged.

[0149] Step S3.2: GDSII layout mapping. This involves associating the three-dimensional failure probability obtained in step S2.3.3 with the coordinates in the GDSII layout. In other words, the coordinates corresponding to the three-dimensional failure probability are converted to physical coordinates in the GDSII layout. Specifically,

[0150]

[0151] in: is the horizontal coordinate in the physical coordinate system, is the vertical coordinate in the physical coordinate system, is the stacked coordinate in the physical coordinate system, is the row coordinate of the current interpolation point, is the column coordinate of the current interpolation point, Number the vertical stacking layer where the storage unit is located. is the physical distance between adjacent rows, is the physical distance between adjacent columns, is the physical distance between adjacent layers, is the starting offset of the X axis, The starting offset of the Y axis.

[0152] Step S3.3: Determine the hotspot area. That is, based on the set failure probability threshold, compare the failure probability threshold with the three-dimensional failure probability in the GDSII layout in step S3.2, and determine the hotspot area based on the comparison result. Specifically:

[0153] When the three-dimensional failure probability is greater than the failure probability threshold, the corresponding area of ​​the three-dimensional failure probability in the GDSII layout is a hot spot area; otherwise, it is not a hot spot area.

[0154] Step S3.4: Determine the final test parameters of the hotspot area. That is, according to the hotspot area determined in step S3.3, set the compensation voltage of the hotspot area by the temperature compensation coefficient, specifically:

[0155]

[0156] Specifically: is the compensation voltage, is the nominal voltage, is the temperature coefficient, is the nominal temperature, is the current temperature.

[0157] During the specific implementation, the current temperature of the hot spot area is 85°C, the nominal voltage is set to 25°C, the nominal voltage is set to 1.2V, and the temperature coefficient is set to -0.002 / °C, then the corresponding compensation voltage is 1.056V.

[0158] Step S3.5: Obtain a test parameter set. That is, according to the test parameters determined in step S3.1 and the final test parameters of the hotspot area obtained in step S3.4, set the test parameters, perform a read and write test on the memory to be tested, and obtain the corresponding test results.

[0159] This embodiment further provides a memory read-write consistency test system, which uses the above-mentioned memory read-write consistency test method.

[0160] Example 2

[0161] This embodiment provides a memory read / write consistency test method. Its specific implementation is the same as that of Example 1, except that, in step S1.1, a quantum tunneling current curve is constructed based on the transistor SPICE model of the memory to be tested and wafer test data. The present invention is described below with reference to the specific implementation of this embodiment.

[0162] In this embodiment, a quantum tunneling current curve is constructed as follows:

[0163] Step WA1: Extracting electrical parameters. This involves performing electrical testing on the transistors in the memory chip under test using a semiconductor parameter analyzer, and obtaining the threshold voltage and off-current corresponding to each transistor during the electrical testing process.

[0164] Furthermore, based on the gate voltage and drain current corresponding to each transistor, a statistical distribution histogram of the threshold voltage and the turn-off current is obtained. At the same time, the Ids-Vgs curve and the threshold voltage / turn-off current extraction schematic are obtained through linear extrapolation.

[0165] In the specific implementation process, the drain voltage is fixed at 0.1V, the gate voltage is scanned from -0.5V to 1.5V, and the step size is set to 0.01V. The drain current is measured for 1ds. Figure 4 and Figure 5 , Figure 4 The Ids-Vgs curve and threshold voltage / off current extraction diagram in this embodiment are shown in FIG. Figure 4 It can be seen that the solid line is the Ids-Vgs curve, and the position marked by the dot is the maximum slope point, where the gate voltage is 0.4V and the drain current is 1μA. At the same time, the dotted line is the threshold voltage extrapolation line, which is extrapolated from the maximum slope point to the drain current of 0, and the corresponding threshold voltage is 0.32V. Furthermore, the fitting curve of the threshold voltage conforms to the normal distribution, with a mean of 300mV and a standard deviation of 15mV. Figure 5 , Figure 5 is the statistical distribution diagram of the shutdown current in this embodiment, Figure 5 It can be seen that the fitting curve of the off-current conforms to the log-normal distribution, with a median value of 0.52 pA / μm and a 90% confidence interval of 0.3 pA / μm-1.2 pA / μm.

[0166] Step WA2: Generate a current density curve. This involves setting up the BSIM-CMG model and performing a FN tunneling simulation using the model. The corresponding electric field strength is obtained as the tunneling current density changes during the simulation. Based on the obtained electric field strength and tunneling current density, a tunneling current density-electric field strength curve is constructed.

[0167] In the specific implementation process, when setting up the BSIM-CMG model, the gate oxide thickness is set to 1.2nm, the dielectric constant is set to 3.9, and the gate voltage is scanned from 1V to 3V, with a step size of 0.2V. Figure 6 , Figure 6 is the tunneling current density-electric field strength curve in this embodiment, Figure 6 It can be seen that the tunneling current density increases exponentially with the electric field strength, so the tunneling current density is the dominant mechanism of leakage current.

[0168] Step WA3: Statistical modeling. This involves performing a Monte Carlo simulation based on the Ids-Vgs curve and threshold voltage / off-current extraction diagram obtained in Step WA1, and the tunneling current density-electric field strength curve obtained in Step WA2. The Monte Carlo method is then used to obtain a distribution histogram of the threshold voltage and statistical characteristics of the tunneling current density.

[0169] Example 3

[0170] This embodiment provides a memory read / write consistency test method. Its specific implementation is the same as that of Example 1, except that, in step S1.2, a three-dimensional parasitic parameter matrix is ​​constructed using the GDSII layout data of the memory array in the memory to be tested. The present invention is described below with reference to specific implementations of this embodiment.

[0171] In this embodiment, a three-dimensional parasitic parameter matrix is ​​constructed as follows:

[0172] Step WB1: Extract parasitic parameters. This involves determining the geometric parameters of the metal lines and vias corresponding to each layer, including length, width, and spacing, based on the GDSII layout data of the memory array in the memory under test. This includes the coupling structure between adjacent layers, including parasitic capacitance and parasitic inductance. Specifically,

[0173]

[0174] in: is the parasitic capacitance, is the relative dielectric constant of the medium, is the dielectric constant of vacuum, is the effective overlapping area of ​​the metal plates, is the metal layer spacing, is the parasitic inductance, is the vacuum permeability, is the relative magnetic permeability of the conductor material, is the wire length, is the wire width.

[0175] Step WB2: Perform full-wave simulation. That is, according to the parasitic capacitance and parasitic inductance obtained in step WB1, set the initial simulation value for the high-frequency structure simulator to perform full-wave simulation and obtain the corresponding scattering parameters and electric field / magnetic field distribution.

[0176] refer to Figure 7 , Figure 7 is the three-dimensional electric field distribution diagram in this embodiment, Figure 7 It can be seen that the electric field intensity transitions from low intensity (blue scattered points) to high intensity (red scattered points), and the concentrated area of ​​the electric field can be clearly identified.

[0177] Step WB3: Generate a 3D parasitic parameter matrix. This is done based on the spatial coordinates of the physical nodes, the geometric parameters of the metal lines and vias obtained in Step WB1, and the scattering parameters and electric / magnetic field distributions obtained in Step WB2. The 3D parasitic parameter matrix includes node numbers, node types, coordinates, and associated structures.

[0178] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is limited by the accompanying embodiments and their equivalents.

Claims

1. A memory read-write consistency test method, characterized in that: Includes: S1: Perform crosstalk coupling modeling: Construct a quantum tunneling current curve based on the transistor SPICE model and wafer test data, construct a three-dimensional parasitic parameter matrix based on the GDSII layout data of the memory array, and construct an inter-layer crosstalk coupling transfer function based on the quantum tunneling current curve and the three-dimensional parasitic parameter matrix; S2: Constructing a three-dimensional failure probability model: Obtaining a planar coupling error distribution diagram based on the quantum tunneling current curve and the three-dimensional parasitic parameter matrix, and generating an interlayer crosstalk coefficient matrix based on the interlayer crosstalk coupling transfer function, and establishing a three-dimensional failure probability model based on the planar coupling error distribution diagram and the interlayer crosstalk coefficient matrix, including: S2.1: Obtaining test results: Optimizing the quantum tunneling current curve and the three-dimensional parasitic parameter matrix using a reinforcement learning algorithm, and obtaining a test vector based on the interlayer crosstalk coupling transfer function; S2.2: Obtaining a distribution map: Performing a read and write test on the memory device under test according to the test vector, and obtaining an inter-layer crosstalk coefficient based on the test results. Simultaneously, constructing a planar coupling error distribution map and an inter-layer crosstalk coefficient matrix using the test results and the inter-layer crosstalk coefficient. S2.3: Determine three-dimensional failure hotspots: Perform spatial interpolation based on the planar coupling error distribution map and the interlayer crosstalk coefficient matrix to obtain a three-dimensional failure probability; S3: Identify electromagnetic coupling hotspot areas: determine the risk level of each area based on the three-dimensional failure probability, set test parameters based on the risk level, and perform read and write tests on the memory to be tested using the test parameters.

2. A memory read-write consistency test method according to claim 1, characterized in that: Construct the inter-layer crosstalk coupling transfer function, including: S1.1: Obtaining a time-domain interference signal: Based on the transistor SPICE model and wafer test data, the threshold voltage and off-current of each transistor are obtained. The electric field strength and tunneling current density are obtained through FN tunneling effect simulation. At the same time, the time-domain interference signal is obtained based on the electric field strength and tunneling current density. Specifically, ， in: is the power spectral density of the interference source, is the time length of the signal, is the time domain waveform of the quantum tunneling current, is the base of natural logarithm, is the imaginary unit, is the frequency, is the time variable; S1.2: Constructing a crosstalk transfer function: Based on the GDSII layout data of the memory array, determine the geometric parameters of the metal lines and vias in each layer of the memory array, obtain the scattering parameters and electric field / magnetic field distribution, and construct a three-dimensional parasitic parameter matrix. At the same time, based on the three-dimensional parasitic parameter matrix and the power spectral density of the interference source, determine the temperature-dependent crosstalk transfer function, specifically: ， in: is the temperature-dependent crosstalk transfer function, is the crosstalk power spectrum density at the receiving end, is the power spectral density of the interference source, is the base of natural logarithm, Temperature The attenuation coefficient, is the metal layer spacing; S1.3: Temperature gradient calibration: Based on the temperature-dependent crosstalk transfer function, obtain the receiving end crosstalk power spectrum density at different temperatures and determine the magnitude of the attenuation coefficient in the crosstalk transfer function, specifically: ， in: Temperature The attenuation coefficient under is the attenuation coefficient at the reference temperature, is the temperature coefficient, is the current temperature, is the base temperature.

3. A memory read-write consistency test method according to claim 2, characterized in that: Obtain electric field strength and tunneling current density, including: WA1: Extracting electrical parameters: Use a semiconductor parameter analyzer to perform electrical testing on the transistors of the memory device under test, obtain the threshold voltage and off-current of each transistor, construct a statistical distribution histogram of the threshold voltage and off-current, and use linear extrapolation to obtain the Ids-Vgs curve and threshold voltage / off-current extraction diagram; WA2: Generate current density curve: Use the set BSIM-CMG model to simulate the FN tunneling effect, obtain the tunneling current density and electric field strength, and construct a tunneling current density-electric field strength curve; WA3: Statistical modeling: Based on the Ids-Vgs curve, threshold voltage / off current extraction diagram, and tunneling current density-electric field strength curve, a Monte Carlo method is used for simulation to obtain the distribution histogram of the threshold voltage and the statistical characteristics of the tunneling current density.

4. A memory read-write consistency test method according to claim 2, characterized in that: Construct a three-dimensional parasitic parameter matrix, including: WB1: Extract parasitic parameters: Based on the GDSII layout data of the memory array in the memory under test, determine the geometric parameters of the metal lines and vias of each layer, and obtain the parasitic capacitance and parasitic inductance between adjacent layers. Specifically: ， in: is the parasitic capacitance, is the relative dielectric constant of the medium, is the dielectric constant of vacuum, is the effective overlapping area of ​​the metal plates, is the metal layer spacing, is the parasitic inductance, is the vacuum permeability, is the relative magnetic permeability of the conductor material, is the wire length, is the wire width; WB2: Perform full-wave simulation: according to the parasitic capacitance and parasitic inductance, set the simulation initial value of the high-frequency structure simulator, and perform full-wave simulation to obtain scattering parameters and electric field / magnetic field distribution; WB3: Generate 3D parasitic matrix: Construct a 3D parasitic matrix based on the geometric parameters, scattering parameters, and electric / magnetic field distribution of the metal lines and vias of each layer.

5. A memory read-write consistency test method according to claim 1, characterized in that: Get test vectors, including: S2.1.1: Obtaining the Q value of the test vector: Normalize the quantum tunneling current curve and the three-dimensional parasitic parameter matrix to construct a state vector, use the state vector as input to a deep Q network model, and output the Q value of the test vector obtained from the state vector; S2.1.2: Set Reward Function: Obtain the total number of defective cells through 3D NAND testing. Based on the number of newly detected defects and the test time, determine the reward function. Specifically, it is: ， in: For instant rewards, is the coverage weight coefficient, For test coverage, is the time penalty coefficient, Time-consuming for testing; S2.1.3: Update the Q value of the test vector: Update the Q value of the test vector using the ε-greedy strategy algorithm and the reward function, specifically: ， in: is the Q value of the test vector after the current state is updated, is the Q value of the original test vector of the current state, is the learning rate, is the discount factor, For instant rewards, is the maximum Q value of the test vector for the next state.

6. A memory read-write consistency test method according to claim 1, characterized in that: Construct a planar coupling error distribution map and inter-layer crosstalk coefficient matrix, including: S2.2.1: Determine the inter-layer crosstalk coefficient matrix: Input the test vector into the row / column driver circuit of the memory to be tested, perform a read / write test, and obtain the error location and error frequency. At the same time, based on the error location, error frequency and crosstalk transfer function, determine the inter-layer crosstalk coefficient, specifically: ， in: is the inter-layer crosstalk coefficient, is the frequency-dependent geometric coupling weight, is the temperature-dependent crosstalk transfer function, is the frequency; S2.2.2: Generate a distribution map: construct a planar coupling error distribution map based on the error position and error frequency, and combine the planar coupling error distribution map with the inter-layer crosstalk coefficient to obtain an inter-layer crosstalk coefficient matrix.

7. A memory read-write consistency test method according to claim 1, characterized in that: Obtain three-dimensional failure probability, including: S2.3.1: Row and column interpolation: Perform spatial interpolation based on the planar coupling error distribution map and the interlayer crosstalk coefficient matrix to obtain row and column direction interpolation, specifically: ， in: is the error probability after interpolation at the row coordinate x, For the line The error probability, is the row coordinate of the current interpolation point, is the adjacent left row coordinate with known error probability, is the adjacent right row coordinate with known error probability, For the line The error probability, is the error probability after interpolation at the column coordinate y, For columns The error probability, is the column coordinate of the current interpolation point, is the adjacent left column coordinate of the known error probability, For the column The error probability, is the adjacent right column coordinate of the known error probability; S2.3.2: Bilinear interpolation: Perform bilinear interpolation based on the row and column interpolation to obtain the error probability after interpolation at the two-dimensional plane (x, y), specifically: ， in: is the error probability after interpolation on the two-dimensional plane (x, y), is the error probability after interpolation at the row coordinate x, is the error probability after interpolation at the column coordinate y; S2.3.3: Determine the three-dimensional failure probability: Based on the interpolated error probability and the interlayer crosstalk coefficient matrix at the two-dimensional plane (x, y), determine the corresponding three-dimensional failure probability, specifically: ， in: is the failure probability of the memory cell at row x, column y, layer n, is the inter-layer crosstalk coefficient, is the error probability after interpolation on the two-dimensional plane (x, y), are the numbers of all other layers that may interfere with the current layer n. Numbers the vertical stacking layer where the storage unit is located.

8. A memory read-write consistency test method according to claim 1, characterized in that: Perform read and write tests on the memory under test, including: S3.1: Determine test parameters: Compare the three-dimensional failure probability with a preset probability threshold range, and based on the comparison results, classify the areas corresponding to the three-dimensional failure probability into risk levels. Based on the risk level classification results, adjust the test parameters for different risk areas, specifically: When the risk area is a high-risk area, the number of test iterations is increased and the voltage margin is tightened; when the risk area is a medium-risk area, the number of tests is partially increased and the timing margin is adjusted; when the risk area is a low-risk area, the test parameters remain unchanged; S3.2: GDSII layout mapping: Convert the coordinates in the three-dimensional failure probability into physical coordinates in the GDSII layout, specifically: ， in: is the horizontal coordinate in the physical coordinate system, is the vertical coordinate in the physical coordinate system, is the stacked coordinate in the physical coordinate system, is the row coordinate of the current interpolation point, is the column coordinate of the current interpolation point, Number the vertical stacking layer where the storage unit is located. is the physical distance between adjacent rows, is the physical distance between adjacent columns, is the physical distance between adjacent layers, is the starting offset of the X axis, is the starting offset of the Y axis; S3.3: Determine hotspot areas: Compare the three-dimensional failure probability in the GDSII layout with a failure probability threshold, and determine the hotspot areas based on the comparison results, specifically: When the three-dimensional failure probability is greater than the failure probability threshold, the area of ​​the three-dimensional failure probability in the GDSII layout is a hotspot area; otherwise, the area of ​​the three-dimensional failure probability in the GDSII layout is not a hotspot area; S3.4: Determine the final test parameters of the hot spot area: Set the compensation voltage of the hot spot area using the temperature compensation coefficient, specifically: ， Specifically: is the compensation voltage, is the nominal voltage, is the temperature coefficient, is the nominal temperature, is the current temperature; S3.5: Obtaining a test parameter set: performing a read / write test on the memory to be tested using the adjusted test parameters and the compensation voltage of the hot spot area to obtain a read / write test result.

9. A memory read-write consistency test method according to claim 8, characterized in that: The three-dimensional failure probability is compared with a preset probability threshold range, and based on the comparison result, the risk level of the area corresponding to the three-dimensional failure probability is divided into the following categories: When the three-dimensional failure probability is greater than the upper limit threshold of the preset probability, the area corresponding to the three-dimensional failure probability is a high-risk area; when the three-dimensional failure probability is within the preset probability threshold range, the area corresponding to the three-dimensional failure probability is a medium-risk area; On the contrary, the area corresponding to the three-dimensional failure probability is a low-risk area.

10. A memory read-write consistency test system, characterized in that: A memory read-write consistency testing method according to any one of claims 1 to 9 is used.

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