Memory device and testing method thereof

Abstract

A memory device and a testing method thereof are disclosed, the memory device may include: a memory circuit that generates a plurality of test data in a test mode; a plurality of comparator groups that generate a first comparison signal based on a portion of the plurality of test data and a portion of the plurality of reference data, and generate a second comparison signal based on the remaining test data and the remaining reference data; an error counter that generates first symbol information indicating a first number of errors occurring in a portion of the plurality of test data based on the first comparison signal, and generates second symbol information indicating a second number of errors occurring in the remaining test data based on the second comparison signal; and an error determiner that generates a pass / failure signal indicating whether the memory circuit is normal based on the first symbol information and the second symbol information.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0197276, filed on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a semiconductor design technology, and more particularly, to a memory device and a test method thereof. Background Art

[0004] When a defect occurs in a memory cell in a memory device, various techniques are used to repair the memory cell in which the defect has occurred (hereinafter referred to as a "defective cell"). Mainly, redundant repair techniques (where defective cells are replaced by normal memory cells) and error - correcting code (ECC) techniques (where the ECC function is used to correct data read from defective cells (i.e., error bits)) are used. Here, the ECC technique may include an on - chip ECC technique that performs the ECC function in the memory device and an off - chip ECC technique that performs the ECC function in a control device that externally controls the memory device. Summary of the Invention

[0005] Multiple embodiments of the present disclosure relate to a memory device having a test scheme optimized according to an error - correction ability level, and a test method of the memory device.

[0006] In addition, multiple embodiments of the present disclosure relate to a memory device having a test scheme optimized according to an error - correction ability level of an error - correcting code (ECC) function in a memory system employing an off - chip ECC function, and a test method of the memory device.

[0007] According to an embodiment of the present disclosure, a memory device may include: a memory circuit configured to generate a plurality of test data in a test mode; a plurality of comparator groups configured to generate a first comparison signal based on a part of the plurality of test data and a part of a plurality of reference data during a first read operation cycle, and generate a second comparison signal based on the remaining test data and the remaining reference data during a second read operation cycle; an error counter configured to generate first symbol information indicating a first error number occurring in a part of the plurality of test data based on the first comparison signal during the first read operation cycle, and generate second symbol information indicating a second error number occurring in the remaining test data based on the second comparison signal during the second read operation cycle; and an error determiner configured to generate a pass / fail signal based on the first symbol information and the second symbol information, the pass / fail signal indicating whether the memory circuit is normal.

[0008] According to an embodiment of the present disclosure, a memory device may include: a memory circuit configured to read N test data groups in a test mode, each test data group having a first burst length; and an error checking circuit configured to: divide the N test data groups into M target data groups, each target data group having a second burst length less than the first burst length; and generate a pass / fail signal indicating whether the memory circuit is normal based on the number of errors occurring in the M target data groups in the test mode, where N is a natural number greater than 1.

[0009] According to an embodiment of the present disclosure, a method for testing a memory device may include: setting expected data and reference quantity information; writing the expected data into a memory circuit; reading a plurality of test data from the memory circuit; checking a first number of errors occurring in a part of the plurality of test data during a first read operation cycle; checking a second number of errors occurring in the remaining test data during a second read operation cycle; summing the first number of errors and the second number of errors; and determining whether the memory circuit is normal based on the reference quantity information and the total number of errors occurring in the plurality of test data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram showing a configuration of a memory device according to an embodiment of the present disclosure.

[0011] Figure 2 is a block diagram showing an embodiment of the present disclosure Figure 1 a detailed configuration of the error checking circuit shown in.

[0012] Figure 3 is a block diagram showing an embodiment of the present disclosure Figure 2 a detailed configuration of the first comparator group shown in.

[0013] Figure 4 is a block diagram showing an embodiment of the present disclosure Figure 2 a detailed configuration of the error counter shown in.

[0014] Figure 5 is a block diagram showing an embodiment of the present disclosure Figure 2 a detailed configuration of the error determiner shown in.

[0015] Figure 6 is a block diagram showing an embodiment of the present disclosure Figure 5 a detailed configuration of the summing circuit shown in.

[0016] Figure 7 is a flowchart for describing a method for testing a memory device according to an embodiment of the present disclosure.

[0017] Figure 8 is a diagram for further describing a test method of a memory device as shown in accordance with an embodiment of the present disclosure. Figure 7 Detailed implementation manners

[0018] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings in order to describe the embodiments of the present disclosure in detail, so that those of ordinary skill in the art to which the present disclosure pertains can easily implement the technical spirit of the present disclosure.

[0019] Figure 1 is a block diagram showing a configuration of a memory device 100 according to an embodiment of the present disclosure.

[0020] Referring to Figure 1 , the memory device 100 may include a memory circuit 110 and an error checking circuit 120.

[0021] The memory circuit 110 may include N memory banks OCT0 to OCT7, where N is a natural number greater than 1. In the present embodiment, it is described by taking the memory circuit 110 including the first to eighth memory banks OCT0 to OCT7 (i.e., N = 8) as an example. Each of the first to eighth memory banks OCT0 to OCT7 may be a memory area. For example, the memory area may be a bank or a MAT (i.e., a cell matrix).

[0022] The first to eighth memory banks OCT0 to OCT7 may respectively read the first to eighth test data groups as the first to eighth read data groups GIO0<0:7> to GIO7<0:7> in a test mode. Each of the first to eighth test data groups may include a plurality of test data generated from the corresponding first to eighth memory banks OCT0 to OCT7. Each of the first to eighth test data groups may have a first burst length. For example, the first burst length may be K, where K is a natural number greater than 1, corresponding to the number of data bits continuously read through the same read path (e.g., bit lines and / or global input / output lines). In the present embodiment, it is described by taking the first burst length corresponding to the first to eighth data bits (i.e., K = 8) as an example.

[0023] In a normal mode, the first to eighth memory banks OCT0 to OCT7 may respectively read the first to eighth normal data groups as the first to eighth read data groups GIO0<0:7> to GIO7<0:7>.

[0024] ​In the test mode, the error checking circuit 120 may divide the first to eighth test data groups into M (where M is a natural number greater than N) target data groups based on the first to eighth read data groups GIO0<0:7> to GIO7<0:7>, and generate a pass / fail signal P / F indicating whether the memory circuit 110 is normal according to the number of errors occurring in the M target data groups. In this embodiment, taking the inclusion of the first to ninth target data groups as an example for illustration, i.e., M = 9. Each of the first to ninth target data groups may have a second burst length. For example, the second burst length may be P data bits, where P is a natural number less than K. Since the first to eighth test data groups are divided into the first to ninth target data groups, the second burst length may be less than the first burst length. In this embodiment, taking the second burst length corresponding to the first to seventh data bits as an example for illustration, i.e., P = 7. The first to ninth target data groups will be described in more detail below (see Figure 8 ).

[0025] For example, in the test mode, the error checking circuit 120 may generate a pass / fail signal P / F based on the first to eighth read data groups GIO0<0:7> to GIO7<0:7> and the first to eighth reference data groups Q0<0:7> to Q7<0:7>. More specifically, when the first to eighth reference data groups Q0<0:7> to Q7<0:7> are divided into the first to ninth comparison data groups corresponding to the first to ninth target data groups, the error checking circuit 120 may check the number of errors occurring in the first to ninth target data groups in units of groups based on the first to ninth target data groups and the first to ninth comparison data groups, and generate a pass / fail signal P / F based on the first symbol information and the second symbol information, where the first symbol information indicates the first number of errors occurring in the first to eighth target data groups among the first to ninth target data groups, and the second symbol information indicates the second number of errors occurring in the ninth target data group among the first to ninth target data groups.

[0026] In the normal mode, the error checking circuit 120 may generate a pass / fail signal P / F indicating whether the memory circuit 110 is normal according to the number of errors occurring in the first to eighth normal data groups based on the first to eighth read data groups GIO0<0:7> to GIO7<0:7>. For example, in the normal mode, the error checking circuit 120 may check the number of errors occurring in the first to eighth normal data groups by comparing the first to eighth normal data groups with the first to eighth reference data groups Q0<0:7> to Q7<0:7> respectively, and generate a pass / fail signal P / F corresponding to whether the memory circuit 110 is normal according to the number of errors occurring in the first to eighth normal data groups.

[0027] Figure 2is a block diagram showing the detailed configuration of the error checking circuit 120 according to an embodiment of the present disclosure. Figure 1 showing the detailed configuration of the error checking circuit 120 shown.

[0028] Referring Figure 2 , the error checking circuit 120 may include first to eighth comparator groups XOR_GP0 to XOR_GP7, an error counter 121, an error determiner 123, and a controller 125.

[0029] The first to eighth comparator groups XOR_GP0 to XOR_GP7 may be configured to correspond to the first to eighth memory groups OCT0 to OCT7, respectively. The first to eighth comparator groups XOR_GP0 to XOR_GP7 may generate first to eighth comparison signal groups X0<0:7> to X7<0:7> based on the first to eighth read data groups GIO0<0:7> to GIO7<0:7>, the first to eighth reference data groups Q0<0:7> to Q7<0:7>, and the first to eighth control signal groups EN0<0:7> to EN7<0:7>, respectively.

[0030] In the test mode, the first to eighth comparator groups XOR_GP0 to XOR_GP7 may generate first to eighth comparison signal groups X0<0:7> to X7<0:7> corresponding to the first to eighth target data groups in the first to ninth target data groups during a first read operation cycle, and then generate first to eighth comparison signal groups X0<0:7> to X7<0:7> corresponding to the ninth target data group in the first to ninth target data groups during a second read operation cycle. The second read operation cycle may be a cycle after the first read operation cycle. When a single read command is input, the first read operation cycle and the second read operation cycle may be continuously allocated. That is, the first read operation cycle and the second read operation cycle may be included in a single read operation cycle corresponding to a single read command.

[0031] In the normal mode, the first to eighth comparator groups XOR_GP0 to XOR_GP7 may commonly compare the first to eighth read data groups GIO0<0:7> to GIO7<0:7> with the first to eighth reference data groups Q0<0:7> to Q7<0:7> bit by bit and generate first to eighth comparison signal groups X0<0:7> to X7<0:7> corresponding to the first to eighth normal data groups.

[0032] In the test mode, the error counter 121 can generate first symbol information indicating the first error count occurring in the first to eighth target data groups as the first to third symbol signals 8S<0:2> based on the first to eighth comparison signal groups X0<0:7> to X7<0:7> during the first read operation cycle. In the test mode, the error counter 121 can generate second symbol information indicating the second error count occurring in the ninth target data group as the first to third symbol signals 8S<0:2> based on the first to eighth comparison signal groups X0<0:7> to X7<0:7> during the second read operation cycle.

[0033] In the normal mode, the error counter 121 can generate the first to third count signals 64B<0:2> corresponding to the error counts occurring in the first to eighth normal data groups based on the first to eighth comparison signal groups X0<0:7> to X7<0:7>.

[0034] According to this embodiment, the first to third count signals 64B<0:2> and the first to third symbol signals 8S<0:2> can be transmitted through different signal lines (e.g., the first to sixth signal lines) or shared signal lines (e.g., the first to third signal lines).

[0035] In the test mode, the error determiner 123 can generate a pass / fail signal P / F based on the first to third symbol signals 8S<0:2> according to the first error count and the second error count.

[0036] In the normal mode, the error determiner 123 can generate a pass / fail signal P / F based on the first to third count signals 64B<0:2> according to the error counts occurring in the first to eighth normal data groups.

[0037] When the test mode signal TM_7B1SYM is activated (i.e., in test mode), the controller 125 may generate first to eighth control signal groups EN0<0:7> to EN7<0:7>. In test mode, the first to eighth control signal groups EN0<0:7> to EN7<0:7> may be generated (i.e., activated and / or deactivated) in the same manner, and the following first control signal group EN0<0:7> is representatively described. In test mode, during a first read operation cycle, the first to seventh control signals EN0<0:6> corresponding to the first target data group among the control signals included in the first control signal group EN0<0:7> may be activated, and during the first read operation cycle, the eighth control signal EN0<7> corresponding to the ninth target data group among the control signals included in the first control signal group EN0<0:7> may be deactivated. In test mode, the first to seventh control signals EN0<0:6> corresponding to the first target data group among the control signals included in the first control signal group EN0<0:7> may be deactivated during a second read operation cycle, while the eighth control signal EN0<7> corresponding to the ninth target data group among the control signals included in the first control signal group EN0<0:7> may be activated during the second read operation cycle.

[0038] In normal mode, when the test mode signal TM_7B1SYM is deactivated, the controller 125 may activate all the control signals included in the first to eighth control signal groups EN0<0:7> to EN7<0:7>.

[0039] Figure 3 is a block diagram showing the detailed configuration of the first comparator group XOR_GP0 as shown in Figure 2 the embodiment according to the present disclosure.

[0040] Refer to Figure 3 , the first comparator group XOR_GP0 may include first to eighth comparators XOR00 to XOR07. For example, each of the first to eighth comparators XOR00 to XOR07 may include an exclusive OR (XOR) gate.

[0041] When the first to seventh control signals EN0<0:6> are activated during a first read operation cycle, the first to seventh comparators XOR00 to XOR06 may compare the first to seventh target data GIO0<0:6> among the first to eighth target data included in the first read data group GIO0<0:7> with the first to seventh reference data Q0<0:6> among the first to eighth reference data included in the first reference data group Q0<0:7>, and generate first to seventh comparison signals X0<0:6> corresponding to the comparison results.

[0042] In the test mode, when the first to seventh control signals EN0<0:6> are deactivated during the second read operation cycle, the first to seventh comparators XOR00 to XOR06 can generate the first to seventh comparison signals X0<0:6> corresponding to "pass", regardless of the first to seventh target data GIO0<0:6> and the first to seventh reference data Q0<0:6>.

[0043] In the test mode, when the eighth control signal EN0<7> is deactivated during the first read operation cycle, the eighth comparator XOR07 can generate the eighth comparison signal X0<7> corresponding to "pass", regardless of the eighth target data GIO0<7> included in the first read data group GIO0<0:7> and the eighth reference data Q0<7> included in the first reference data group Q0<0:7>.

[0044] In the test mode, when the eighth control signal EN0<7> is activated during the second read operation cycle, the eighth comparator XOR07 can compare the eighth target data GIO0<7> included in the first read data group GIO0<0:7> with the eighth reference data Q0<7> included in the first reference data group Q0<0:7>, and generate the eighth comparison signal X0<7> corresponding to the comparison result.

[0045] When the first to eighth control signals EN0<0:7> are activated in the normal mode, the first to eighth comparators XOR00 to XOR07 can compare the first to eighth normal data included in the first read data group GIO0<0:7> with the first to eighth reference data included in the first reference data group Q0<0:7>, and generate the first to eighth comparison signals X0<0:7> corresponding to the comparison results.

[0046] Since each of the second to eighth comparator groups XOR_GP1 to XOR_GP7 can be designed in the same manner as the first comparator group XOR_GP0, its description is omitted.

[0047] Figure 4 is a block diagram showing the detailed configuration of the error counter 121 according to an embodiment of the present disclosure Figure 2 shown in

[0048] Reference Figure 4 , the error counter 121 may include first to fifth stages STG0 to STG4.

[0049] In the test mode, the first to fifth levels of STG0 to STG4 can determine, in groups, whether an error has occurred in the first to seventh test data groups during the first read operation cycle, and accumulate the determination results in sequence. Therefore, the first to fifth levels of STG0 to STG4 can generate first symbol information indicating the first error quantity as the first to third symbol signals 8S<0:2>.

[0050] In the test mode, the first to fifth levels of STG0 to STG4 can determine, in bit units, whether an error has occurred in the eighth test data group during the second read operation cycle, and accumulate the determination results in sequence. Therefore, the first to fifth levels of STG0 to STG4 can generate second symbol information indicating the second error quantity as the first to third symbol signals 8S<0:2>.

[0051] In the normal mode, the first to fifth levels of STG0 to STG4 can determine the number of errors occurring in the first to eighth normal data groups in bit units, and accumulate the determination results in sequence. Therefore, the first to fifth levels of STG0 to STG4 can generate the first to third count signals 64B<0:2> corresponding to the number of errors.

[0052] The first level STG0 can include the first to sixteenth adders ADD00 to ADD015. For example, each of the first to sixteenth adders ADD00 to ADD015 can include a 2-bit adder.

[0053] In the test mode, the first and second adders ADD00 and ADD01 can generate a first accumulated signal group 4B0<0:2> and 4B1<0:2> corresponding to the number of errors occurring in the first target data group based on the first comparison signal group X0<0:7> during the first read operation cycle. In the test mode, the first and second adders ADD00 and ADD01 can generate a first accumulated signal group 4B0<0:2> and 4B1<0:2> corresponding to the number of errors occurring in the first target data included in the ninth target data group based on the first comparison signal group X0<0:7> during the second read operation cycle. In the normal mode, the first and second adders ADD00 and ADD01 can generate a first accumulated signal group 4B0<0:2> and 4B1<0:2> corresponding to the number of errors occurring in the first normal data group based on the first comparison signal group X0<0:7>.

[0054] Since each of the third to sixteenth adders ADD02 to ADD015 can be designed in the same way as the first adder ADD00 or the second adder ADD01, their detailed descriptions are omitted.

[0055] The second-stage STG1 may include first to eighth adders ADD10 to ADD17. For example, each of the first to eighth adders ADD10 to ADD17 may include a 2-bit adder.

[0056] In the test mode, the first adder ADD10 may generate a first set of accumulated signals 1S0<0> based on the first set of accumulated signals 4B0<0:2> and 4B1<0:2> during the first read operation cycle. For example, when the number of errors occurring in the first target data set is at least 1, the first adder ADD10 may activate the first set of accumulated signals 1S0<0>. In the test mode, the first adder ADD10 may generate a first set of accumulated signals 1S0<0> based on the first set of accumulated signals 4B0<0:2> and 4B1<0:2> during the second read operation cycle. For example, when an error occurs in the first target data included in the ninth target data set, the first adder ADD10 may activate the first set of accumulated signals 1S0<0>. In the normal mode, the first adder ADD10 may generate a first set of count signals 8B0<0:2> based on the first set of accumulated signals 4B0<0:2> and 4B1<0:2>. For example, the first adder ADD10 may generate a first set of count signals 8B0<0:2> corresponding to the number of errors occurring in the first normal data set.

[0057] According to an embodiment of the present disclosure, the first adder ADD10 may include a normal-only circuit for generating the first set of count signals 8B0<0:2> and a test-only circuit for generating the first set of accumulated signals 1S0<0>. According to another embodiment of the present disclosure, the normal-only circuit and the test-only circuit may be designed to have a structure in which a part of the normal-only circuit and a part of the test-only circuit are shared.

[0058] According to an embodiment of the present disclosure, the first set of count signals 8B0<0:2> and the first set of accumulated signals 1S0<0> may be transmitted through different signal lines, such as the first to fourth signal lines, or through partially shared signal lines, such as the first to third signal lines.

[0059] Since each of the second to eighth adders ADD11 to ADD17 may be designed in the same manner as the first adder ADD10, their detailed descriptions are omitted. However, in the test mode, the eighth adder ADD17 may generate an eighth set of accumulated signals 1S7<0> based on the eighth set of accumulated signals 4B14<0:2> and 4B15<0:2> during the second read operation cycle, and transmit the eighth set of accumulated signals 1S7<0> to an external controller (not shown) (see Figure 8 in (C)). The controller may determine whether an error has occurred in other target data (i.e., the remaining target data) based on the eighth set of accumulated signals 1S7<0>.

[0060] The third - stage STG2 may include first to fourth adders ADD20 to ADD23. For example, each of the first to fourth adders ADD20 to ADD23 may include a 2 - bit adder.

[0061] In the test mode, the first adder ADD20 may generate accumulation information as the first and second sets of accumulation signals 2S0<0:1> based on the first set of accumulation signals 1S0<0> and the second set of accumulation signals 1S1<0> during the first read operation cycle. The accumulation information corresponds to the result of accumulating the number of errors occurring in the first target data set and the number of errors occurring in the second target data set. In the test mode, the first adder ADD20 may generate accumulation information corresponding to the number of errors occurring in the first target data and the second target data included in the ninth target data set as the first set of accumulation signals 2S0<0:1> based on the first set of accumulation signals 1S0<0> and the second set of accumulation signals 1S1<0> during the second read operation cycle. In the normal mode, the first adder ADD20 may generate accumulation information corresponding to the result of accumulating the number of errors occurring in the first normal data set and the number of errors occurring in the second normal data set as the first set of count signals 16B0<0:2> based on the first set of count signals 8B0<0:2> and the second set of count signals 8B1<0:2>.

[0062] According to an embodiment of the present disclosure, the second adder ADD20 may include a normal - only circuit for generating the first set of count signals 16B0<0:2> and a test - only circuit for generating the first set of accumulation signals 2S0<0:1>. According to another embodiment of the present disclosure, the normal - only circuit and the test - only circuit may be designed to have a structure in which a part of the normal - only circuit and a part of the test - only circuit are shared.

[0063] According to an embodiment of the present disclosure, the first set of count signals 16B0<0:2> and the first set of accumulation signals 2S0<0:1> may be transmitted through different signal lines (e.g., the first to fifth signal lines) or partially shared signal lines (e.g., the first to third signal lines).

[0064] Since each of the second to third adders ADD21 to ADD23 may be designed in the same way as the first adder ADD20, their detailed descriptions are omitted.

[0065] The fourth - stage STG3 may include a first adder ADD30 and a second adder ADD31. For example, each of the first and second adders ADD30 and ADD31 may include a 2 - bit adder.

[0066] In the test mode, the first adder ADD30 can generate, based on the first set of accumulation signals 2S0<0:1> and the second set of accumulation signals 2S1<0:1> during the first read operation cycle, accumulation information corresponding to the result of accumulating the number of errors occurring in the first target data group, the number of errors occurring in the second target data group, the number of errors occurring in the third target data group, and the number of errors occurring in the fourth target data group as the first set of accumulation signals 4S0<0:2>. In the test mode, the first adder ADD30 can generate, based on the first set of accumulation signals 2S0<0:1> and the second set of accumulation signals 2S1<0:1> during the second read operation cycle, accumulation information corresponding to the result of accumulating the number of errors occurring in the first target data, the second target data, the third target data, and the fourth target data included in the ninth target data group as the first set of accumulation signals 4S0<0:2>. In the normal mode, the first adder ADD30 can generate, based on the first set of count signals 16B0<0:2> and the second set of count signals 16B1<0:2>, accumulation information corresponding to the result of accumulating the number of errors occurring in the first normal data group, the number of errors occurring in the second normal data group, the number of errors occurring in the third normal data group, and the number of errors occurring in the fourth normal data group as the first set of count signals 32B0<0:2>.

[0067] According to an embodiment of the present disclosure, the first adder ADD30 can include a normal-only circuit for generating the first set of count signals 32B0<0:2> and a test-only circuit for generating the first set of accumulation signals 4S0<0:2>. According to another embodiment of the present disclosure, the normal-only circuit and the test-only circuit can be designed to have a structure in which a part of the normal-only circuit and a part of the test-only circuit are shared.

[0068] According to an embodiment of the present disclosure, the first set of count signals 32B0<0:2> and the first set of accumulation signals 4S0<0:2> can be transmitted through different signal lines (e.g., the first to sixth signal lines) or partially shared signal lines (e.g., the first to third signal lines).

[0069] Since the second adder ADD31 can be designed in the same manner as the first adder ADD30, its detailed description is omitted.

[0070] The fifth stage STG4 can include a first adder ADD40. For example, the first adder ADD40 can include a 2-bit adder.

[0071] In the test mode, the first adder ADD40 can generate, based on the first set of accumulation signals 4S0<0:2> and the second set of accumulation signals 4S1<0:2> during the first read operation cycle, accumulation information corresponding to the result of accumulating the number of errors occurring in the first target data group, the number of errors occurring in the second target data group, the number of errors occurring in the third target data group, the number of errors occurring in the fourth target data group, the number of errors occurring in the fifth target data group, the number of errors occurring in the sixth target data group, the number of errors occurring in the seventh target data group, and the number of errors occurring in the eighth target data group (i.e., the first error number) as the first to third symbol signals 8S<0:2>. In the test mode, the first adder ADD40 can generate, based on the first set of accumulation signals 4S0<0:2> and the second set of accumulation signals 4S1<0:2> during the second read operation cycle, accumulation information corresponding to the result of accumulating the number of errors occurring in the first target data, the second target data, the third target data, the fourth target data, the fifth target data, the sixth target data, the seventh target data, and the eighth target data included in the ninth target data group as the first to third symbol signals 8S<0:2>. In the normal mode, the first adder ADD40 can generate, based on the first set of count signals 32B0<0:2> and the second set of count signals 32B1<0:2>, accumulation information corresponding to the result of accumulating the number of errors occurring in the first normal data group, the number of errors occurring in the second normal data group, the number of errors occurring in the third normal data group, the number of errors occurring in the fourth normal data group, the number of errors occurring in the fifth normal data group, the number of errors occurring in the sixth normal data group, the number of errors occurring in the seventh normal data group, and the number of errors occurring in the eighth normal data group as the first to third sets of count signals 64B<0:2>.

[0072] According to an embodiment of the present disclosure, the first adder ADD40 may include a normal-only circuit for generating the first set of count signals 64B<0:2> and a test-only circuit for generating the first to third symbol signals 8S<0:2>. According to another embodiment of the present disclosure, the normal-only circuit and the test-only circuit may be designed to have a structure in which a part of the normal-only circuit and a part of the test-only circuit are shared.

[0073] According to an embodiment of the present disclosure, the first set of count signals 64B<0:2> and the first to third symbol signals 8S<0:2> may be transmitted through different signal lines (e.g., the first to sixth signal lines) or partially shared signal lines (e.g., the first to third signal lines).

[0074] Figure 5 is a block diagram showing the detailed configuration of the error determiner 123 shown in Figure 2 an embodiment according to the present disclosure.

[0075] Reference Figure 5 The error determiner 123 may include a latch circuit 123_1, a bypass circuit 123_3, a summing circuit 123_5, and a pass / fail check circuit 123_7.

[0076] The latch circuit 123_1 may latch the first to third symbol signals 8S<0:2> corresponding to the first symbol information as first data RD1<0:2> according to a first strobe signal 1stSTBP triggered at least during a first read operation cycle.

[0077] The bypass circuit 123_3 may bypass the first to third symbol signals 8S<0:2> corresponding to the second symbol information as second data RD2<0:2> according to a second strobe signal 2ndSTBP triggered at least during a second read operation cycle.

[0078] The summing circuit 123_5 may sum the first data RD1<0:2> and the second data RD2<0:2> and generate result data M<0:2>.

[0079] The pass / fail check circuit 123_7 may generate a pass / fail signal P / F based on the result data M<0:2> and reference quantity information WIV_SYM. For example, when the total number of errors corresponding to the result data M<0:2> (i.e., the sum of the first error quantity and the second error quantity) is less than the reference quantity corresponding to the reference quantity information WIV_SYM, the pass / fail check circuit 123_7 may generate a pass / fail signal P / F corresponding to "pass". On the other hand, when the total number of errors corresponding to the result data M<0:2> (i.e., the sum of the first error quantity and the second error quantity) is greater than the reference quantity corresponding to the reference quantity information WIV_SYM, the pass / fail check circuit 123_7 may generate a pass / fail signal P / F corresponding to "fail". The reference quantity may be set according to the error correction capability level of the error correction code function of the controller.

[0080] Figure 6 is a block diagram showing the detailed configuration of the summing circuit 123_5 shown in Figure 5 an embodiment according to the present disclosure.

[0081] Reference Figure 6 The summing circuit 123_5 may include an adder ADD50, an overflow detector OVFL, a first selector U0, and a second selector U1.

[0082] Reference Figure 6, the adder ADD50 can add the partial RD1<0:1> of the first data RD1<0:2> and the partial RD2<0:1> of the second data RD2<0:2>, and generate the partial 8S_RD1<0:1> of the third data 8S_RD1<0:2> and the overflow signal CC.

[0083] The overflow detector OVFL can generate the remaining data 8S_RD1<2> of the third data 8S_RD1<0:2> based on another data RD1<2> of the first data RD1<0:2>, the remaining data RD2<2> of the second data RD2<0:2>, and the overflow signal CC. For example, when the overflow signal CC is activated, the remaining data 8S_RD1<2> of the third data 8S_RD1<0:2> can be unconditionally activated. When the number of errors corresponding to the partial 8S_RD1<0:1> of the third data 8S_RD1<0:2> is greater than the reference number, the overflow signal CC can be activated.

[0084] The first selector U0 can generate the partial M<0:1> of the result data M<0:2> according to the test mode signal TM_7B1SYM from the partial 8S_RD1<0:1> of the third data 8S_RD1<0:2> or the first and second normal count signals 64B<0:1>. For example, in the test mode, the first selector U0 can output the partial 8S_RD1<0:1> of the third data 8S_RD1<0:2> as the partial M<0:1> of the result data M<0:2>. In the normal mode, the first selector U0 can output the first and second normal count signals 64B<0:1> as the partial M<0:1> of the result data M<0:2>.

[0085] The second selector U1 can generate the remaining data M<2> of the result data M<0:2> according to the test mode signal TM_7B1SYM from the remaining data 8S_RD1<2> of the third data 8S_RD1<0:2> or the third normal count signal 64B<2>. For example, in the test mode, the second selector U1 can output the remaining data 8S_RD1<2> of the third data 8S_RD1<0:2> as the remaining data M<2> of the result data M<0:2>. In the normal mode, the second selector U1 can output the third normal count signal 64B<2> as the remaining data M<2> of the result data M<0:2>.

[0086] Hereinafter, refer to Figure 7 and Figure 8 Describe the operation of the memory device 100 having the above configuration according to an embodiment of the present disclosure.

[0087] Figure 7It is a flowchart for describing a test method of a memory device 100 according to an embodiment of the present disclosure.

[0088] Referring to Figure 7 , the memory device 100 may set expected data and reference quantity information WIV_SYM in operation S100. The expected data may be data corresponding to a low logic level (i.e., 0) or data corresponding to a high logic level (i.e., 1).

[0089] The memory device 100 may write the same data (i.e., the expected data) to all of the first to eighth memory banks OCT0 to OCT7 included in the memory circuit 110 in operation S102.

[0090] In operation S104, the memory device 100 may read a plurality of test data corresponding to the expected data from the memory circuit 110.

[0091] In operation S106, the memory device 100 may check the number of first errors occurring in a part of the plurality of test data during the first read operation cycle. For example, when the first to eighth memory banks OCT0 to OCT7 are divided into first to ninth target data groups, the memory device 100 may generate first symbol information indicating the number of first errors occurring in the first to eighth target data groups among the first to ninth target data groups.

[0092] In operation S108, the memory device 100 may check the number of second errors occurring in the remaining data among the plurality of test data during the second read operation cycle. When the first to eighth memory banks OCT0 to OCT7 are divided into first to ninth target data groups, the memory device 100 may generate second symbol information indicating the number of second errors occurring in the ninth target data group among the first to ninth target data groups.

[0093] The memory device 100 may sum the number of first errors and the number of second errors in operation S109, and determine whether the memory circuit 110 is normal in operation S110 according to the reference quantity information WIV_SYM and the total number of errors occurring in the plurality of test data (i.e., the number of first errors + the number of second errors).

[0094] When the overflow signal CC is activated in at least one of operation S106 for checking the number of first errors, operation S108 for checking the number of second errors, and the operation of adding the number of first errors and the number of second errors, operation S110 for determining whether the memory circuit 110 is normal may determine that the memory circuit 110 is defective regardless of the total number of errors occurring in the test data.

[0095] Figure 8is a diagram for further describing a test method of the memory device 100 shown in Figure 7 the following.

[0096] Referring to Figure 8 , a part of multiple test data may include a part of data bits that are successively read through the same read path ( Figure 8 the shaded part in (A) of Figure 8 ). The part of the data bits (

[0097] the shaded part in (A) of Figure 8 ) may correspond to the first to eighth target data groups. The number of first errors occurring in the first to eighth target data groups may be checked during the first read operation cycle.

[0098] Other bits of the multiple test data ( Figure 8 the shaded part in (B) of

[0099] ) may correspond to the ninth target data group. The number of second errors occurring in the ninth target data group may be checked during the second read operation cycle.

[0100] According to an embodiment of the present disclosure, there is an advantage that it is possible to check whether a memory circuit is normal through an optimized test scheme based on the number of errors occurring in multiple target data groups divided according to an error correction capability level.

[0101] According to an embodiment of the present disclosure, by having an optimized test scheme according to an error correction capability level, it is possible to contribute to improving the yield of a memory device.

[0102] Although the present disclosure has been illustrated and described with respect to specific embodiments, the disclosed embodiments are for description only and are not intended to be limiting. In addition, it is noted that the embodiments of the present disclosure can be implemented in various ways by replacement, change, and modification, and these replacements, changes, and modifications all fall within the scope of the appended claims, and those skilled in the art will recognize this based on the present disclosure. In addition, the embodiments can be combined to form additional embodiments.

Claims

1. A memory device, comprising: a memory circuit that generates a plurality of test data in a test mode; a plurality of comparator groups, which: generate a first comparison signal based on a portion of the plurality of test data and a portion of the plurality of reference data during a first read operation cycle; and generate a second comparison signal based on remaining test data and remaining reference data during a second read operation cycle; an error counter that: generates first sign information based on the first comparison signal during the first read operation cycle, the first sign information indicating a first error number occurring in the portion of the plurality of test data; and generates second sign information based on the second comparison signal during the second read operation cycle, the second sign information indicating a second error number occurring in the remaining test data; and An error determiner generates a pass / fail signal based on the first symbol information and the second symbol information, the pass / fail signal indicating whether the memory circuit is normal.

2. The memory device according to claim 1, wherein: Each of the plurality of comparator groups comprises: P comparators, which: compare P bits of K bits included in a first burst length of corresponding test data among the plurality of test data with P bits of K bits included in the first burst length of corresponding reference data among the plurality of reference data, and generate a corresponding first comparison signal among the first comparison signals corresponding to the comparison result, wherein P is a natural number less than K, and K is a natural number greater than 3; and (KP) comparators, which compare (KP) bits of the K bits included in the first burst length of the corresponding test data in the multiple test data with (KP) bits of the K bits included in the first burst length of the corresponding reference data in the multiple reference data, and generate at least one corresponding second comparison signal in the second comparison signal corresponding to the comparison result.

3. The memory device according to claim 1, in, The error counter comprises a plurality of stages, wherein the plurality of stages: generate the first symbol information indicating the first error number by determining whether an error occurs in the portion of the plurality of test data in units of groups during the first read operation cycle and sequentially accumulating the determination results, and The plurality of stages generate the second symbol information indicating the second error quantity by determining whether an error occurs in the remaining test data in units of bits during the second read operation cycle and sequentially accumulating the determination results.

4. The memory device according to claim 1, wherein: The error determiner comprises: a latch circuit that latches the first sign information as first data based on a first selection signal triggered during at least the first read operation cycle; a bypass circuit that bypasses the second sign information as second data based on a second strobe signal triggered during at least the second read operation cycle; a summing circuit that sums the first data and the second data and generates result data; and A pass / fail check circuit generates the pass / fail signal based on the result data.

5. The memory device according to claim 4, wherein: The summing circuit comprises: an adder that adds a portion of the first data and a portion of the second data and generates a portion of third data and an overflow signal; an overflow detector, which: generates remaining third data based on the remaining first data, the remaining second data and the overflow signal; a first selector that: generates, as a part of the result data, a part of the third data indicating the number of errors occurring in the memory circuit in a normal mode or a part of normal information based on a test mode signal corresponding to the test mode; and A second selector generates the remaining third data or the remaining normal information as remaining result data based on the test mode signal.

6. The memory device according to claim 1, in, The memory circuit reads a plurality of normal data in a normal mode, and Wherein, in the normal mode, the error checking circuit checks the number of errors occurring in the normal data in units of bits based on the multiple normal data and multiple normal reference data, and generates the pass / fail signal corresponding to whether the memory circuit is normal according to the number of errors occurring in the normal data.

7. A memory device comprising: a memory circuit that reads N test data groups in a test mode, each of the test data groups having a first burst length; as well as An error checking circuit, which: divides the N test data groups into M target data groups, each of the target data groups having a second burst length that is smaller than the first burst length; and generates a pass / fail signal indicating whether the memory circuit is normal according to the number of errors occurring in the M target data groups under the test mode, wherein N is a natural number greater than 1.

8. The memory device according to claim 7, wherein: The error checking circuit checks the number of errors occurring in the M target data groups based on the M target data groups and the M reference data groups, and generates the pass / fail signal based on first symbol information and second symbol information, wherein the first symbol information indicates the number of first errors occurring in a first group of the M target data groups, and the second symbol information indicates the number of second errors occurring in at least one second group of the M target data groups.

9. The memory device according to claim 7, wherein: The error checking circuit comprises: N comparator groups, which: generate a first comparison signal group corresponding to a first group of the M target data groups during a first read operation cycle based on the N test data groups and the N reference data groups, and generate a second comparison signal group corresponding to at least one second group of the M target data groups during a second read operation cycle; an error counter that: generates first sign information indicating the number of first errors occurring in the first group based on the first comparison signal group during the first read operation cycle; and generates second sign information indicating the number of second errors occurring in the second group based on the second comparison signal group during the second read operation cycle; and An error determiner generates the pass / fail signal based on the first sign information and the second sign information.

10. The memory device according to claim 9, wherein: Each of the N comparator groups comprises: P comparators, which: compare P bits of the K bits included in the first burst length of the corresponding test data group in the N test data groups with P bits of the K bits included in the first burst length of the corresponding reference data group in the N reference data groups, and generate corresponding first comparison signals in the first comparison signal group corresponding to the comparison results, wherein P is a natural number less than K, and K is a natural number greater than 3; and (KP) comparators, which: compare the (KP) bits among the K bits included in the first burst length of the corresponding test data group among the N test data groups with the (KP) bits among the K bits included in the first burst length of the corresponding reference data group among the N reference data groups, and generate at least one corresponding second comparison signal in the second comparison signal group corresponding to the comparison result.

11. The memory device according to claim 9, in, The error counter comprises a plurality of stages, wherein the plurality of stages: generate the first symbol information indicating the first error quantity by determining whether an error occurs in the first group in units of groups during the first read operation cycle and sequentially accumulating the determination results, and The plurality of stages generate the second symbol information indicating the second error quantity by determining whether an error occurs in the second group in units of bits during the second read operation cycle and sequentially accumulating the determination results.

12. The memory device according to claim 9, wherein: The error determiner comprises: a latch circuit that latches the first sign information as first data based on a first selection signal triggered during at least the first read operation cycle; a bypass circuit that bypasses the second sign information as second data based on a second strobe signal triggered during at least the second read operation cycle; a summing circuit that sums the first data and the second data and generates result data; and A pass / fail check circuit generates the pass / fail signal based on the result data.

13. The memory device according to claim 12, wherein: The summing circuit comprises: an adder that adds a portion of the first data and a portion of the second data and generates a portion of third data and an overflow signal; an overflow detector that generates remaining third data based on the remaining first data, the remaining second data, and the overflow signal; a first selector that: generates, as a part of the result data, a part of the third data indicating the number of errors occurring in the memory circuit in a normal mode or a part of normal information based on a test mode signal corresponding to the test mode; and A second selector generates the remaining third data or the remaining normal information as remaining result data based on the test mode signal.

14. The memory device according to claim 7, in, The memory circuit reads normal data in a normal mode, and Wherein, in the normal mode, the error checking circuit checks the number of errors occurring in the normal data in units of bits based on the normal data and the second reference data, and generates the pass / fail signal corresponding to whether the memory circuit is normal according to the number of errors occurring in the normal data.

15. A method for testing a memory device, the method comprising: Set expected data and reference quantity information; writing the expected data into a memory circuit; reading a plurality of test data from the memory circuit; checking a first number of errors occurring in a portion of the plurality of test data during a first read operation cycle; checking a second number of errors occurring in the remaining test data during a second read operation cycle; summing the first number of errors and the second number of errors; as well as Whether the memory circuit is normal is determined based on the reference quantity information and a total number of errors occurring in the plurality of test data.

16. The testing method according to claim 15, wherein: When an overflow signal is activated in at least one of the steps of checking the first error number, checking the second error number, and summing the first error number and the second error number, the step of determining whether the memory circuit is normal determines that the memory circuit is defective regardless of the total number of errors occurring in the test data.

17. The testing method according to claim 15, wherein: The portion of the plurality of test data includes a portion of data bits that are read continuously through the same read path, and the remaining test data includes other data bits.

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