Memory chip and semiconductor test system

Abstract

The application relates to a storage chip and a semiconductor test system. The storage chip comprises a clock selector, a configuration selector, an on-chip clock source and a storage module; wherein: the clock selector is used for determining a working clock signal of the storage chip from an external input clock signal and an on-chip clock signal generated by the on-chip clock source based on a received signal; the configuration selector is used for setting the on-chip clock source and / or the storage module based on a received signal; the on-chip clock source is used for generating at least one on-chip clock signal based on the setting of the configuration selector; and the storage module is used for writing data and / or reading data based on a received signal and a working clock signal. The storage chip can improve compatibility and flexibility.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a memory chip and a semiconductor testing system. Background Technology

[0002] Memory chips are integrated circuits used to store programs and data, and can include SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), Read-Only Memory (ROM), flash memory, etc. As the application areas of memory chips expand, users and manufacturers are placing increasingly higher demands on their performance. However, testing the read and write performance of memory chips is cumbersome. Due to the extremely high speed of SRAM and similar components, precise timing control is required during testing to ensure correct data reading and writing. This involves issues such as control address, data bus, and the timing of read / write signals. Furthermore, under different testing scenarios and requirements, memory chips may be limited by the testing equipment, such as affecting high-frequency testing. Traditional technologies for memory chips struggle to meet the demands of diverse testing scenarios, exhibiting issues of accuracy, compatibility, and flexibility. Summary of the Invention

[0003] Therefore, it is necessary to provide a memory chip and semiconductor testing system that can meet the needs of different testing scenarios and improve accuracy, compatibility and flexibility in response to the above-mentioned technical problems.

[0004] In a first aspect, this application provides a memory chip, which includes a clock selector, a configuration selector, an on-chip clock source, and a memory module; wherein:

[0005] The clock selector is used to determine the operating clock signal of the memory chip based on the received signal, from the external input clock signal and the on-chip clock signal generated by the on-chip clock source.

[0006] The configuration selector is used to configure the on-chip clock source and / or the storage module based on the received signal;

[0007] The on-chip clock source is used to generate at least one on-chip clock signal based on the settings of the configuration selector;

[0008] The storage module is used to write and / or read data based on the received signals and the operating clock signal.

[0009] In one embodiment, the received signals include data signals, address signals, and control signals;

[0010] The memory chip also includes data pads, address pads, and control pads, which are used as external interfaces to transmit data signals, address signals, and control signals respectively.

[0011] In one embodiment, the control signal includes an input clock signal and a clock selection signal;

[0012] When the clock selection signal is an external clock, the clock selector is used to receive the input clock signal and use the input clock signal as the working clock signal of the memory chip.

[0013] In one embodiment, the control signal further includes a clock output signal;

[0014] When the clock selection signal is to use an internal clock, the clock selector is used to receive the on-chip clock signal generated by the on-chip clock source and use the on-chip clock signal as the working clock signal of the memory chip;

[0015] The working clock signal is also used as the clock output signal to be output to an external device.

[0016] In one embodiment, the control signal further includes a configuration selection signal and a configuration input signal;

[0017] When the configuration selection signal is set to input configuration, the configuration selector configures the on-chip clock source and / or memory module based on the configuration input signal.

[0018] In one embodiment, the control signal further includes a configuration protocol signal;

[0019] The storage chip also includes a configuration register for storing preset configuration information;

[0020] When the configuration selection signal is to use internal configuration, the configuration register is used to receive the configuration protocol signal and transmit the configuration information to the configuration selector; the configuration selector is used to configure the on-chip clock source and / or memory module based on the configuration information.

[0021] In one embodiment, the storage module includes a time-series balancing module and multiple repositories, the time-series balancing module being connected to each of the multiple repositories;

[0022] The timing balancing module is used to receive the working clock signal, and transmit the working clock signal to the storage repository after performing delay compensation based on the delay parameters.

[0023] The configuration selector further includes a delay configuration module, which is used to configure the delay parameters of the timing balance module based on the received signal.

[0024] In one embodiment, the repository includes multiple repository units;

[0025] The timing balancing module includes a delay main module and at least one delay adjustment module. The delay adjustment module is connected to the output terminal of the delay main module, wherein:

[0026] The delay module is used to delay the input working clock signal for a first time and then output a first signal.

[0027] The delay adjustment module is used to receive the corresponding delay parameters according to the delay requirements, and after delaying the first signal for a second time, output the second signal to the multiple storage units.

[0028] The Chebyshev distance or Euclidean distance between the delay adjustment module and the multiple storage unit units is equal.

[0029] In one embodiment, the on-chip clock source includes a clock adjuster and multiple on-chip clock generators, with different on-chip clock generators generating clock signals of different frequencies;

[0030] Based on the configuration selector, a target clock generator is determined from the plurality of on-chip clock generators, and the clock signal generated by the target clock generator is output to the clock adjuster.

[0031] The clock adjuster fine-tunes the clock signal generated by the on-chip clock generator based on the control signal to obtain the fine-tuned clock signal corresponding to the control signal, which is then used as the final clock signal.

[0032] Secondly, this application provides a semiconductor testing system, including testing equipment and a memory chip as described in the first aspect above.

[0033] The aforementioned memory chip and semiconductor testing system, through a clock selector, determines the operating clock signal of the memory chip based on the received signal, choosing between an external input clock signal and an on-chip clock signal generated by the on-chip clock source; a configuration selector configures the on-chip clock source and / or the memory module based on the received signal; the on-chip clock source generates at least one on-chip clock signal based on the configuration selector's settings; the memory module writes and / or reads data based on the received signal and the operating clock signal. The memory chip can flexibly switch between external clock signals and on-chip clock signals, achieving dynamic configuration and multi-mode compatibility. This allows the memory chip to adapt to various testing scenarios, achieving precise timing control under different testing conditions, thereby improving accuracy, compatibility, and flexibility. Attached Figure Description

[0034] Figure 1 This is a block diagram of the memory chip in one embodiment;

[0035] Figure 2 This is a block diagram of the memory chip in another embodiment;

[0036] Figure 3 This is a diagram of the test environment for the memory chip in one embodiment;

[0037] Figure 4 This is a schematic diagram of the structure of a clock adjuster provided in an embodiment of this application;

[0038] Figure 5 This is a circuit diagram of a current source component provided in an embodiment of this application;

[0039] Figure 6 This is a schematic diagram of a ring oscillator provided in an embodiment of this application;

[0040] Figure 7 This is a schematic diagram of the circuit structure of multiple on-chip clock generators provided in the embodiments of this application;

[0041] Figure 8 This is a schematic diagram of the overall structure of an on-chip clock signal generation circuit provided in an embodiment of this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0043] Example 1

[0044] like Figure 1 As shown, a memory chip is provided, comprising a clock selector 1, a configuration selector 2, an on-chip clock source 3, and a memory module 4; wherein:

[0045] The clock selector 1 is used to determine the operating clock signal of the memory chip based on the received signal, from the external input clock signal and the on-chip clock signal generated by the on-chip clock source 3.

[0046] The configuration selector 2 is used to configure the on-chip clock source 3 and / or the storage module 4 based on the received signal;

[0047] The on-chip clock source 3 is used to generate at least one on-chip clock signal based on the settings of the configuration selector 2;

[0048] The storage module 4 is used to write and / or read data based on the received signals and the working clock signal.

[0049] The clock selector 1 can determine the clock signal for read / write operations of the memory chip based on the received signal. It can dynamically select the operating clock signal from at least two clock signal sources based on the input signal, thus providing multi-mode compatibility. The received signal can be a clock signal from outside the memory chip or a clock signal from other modules inside the memory chip.

[0050] For example, clock selector 1 may include logic circuitry and signal ports. The signal ports are used to receive signals, and the logic circuitry is used to determine the result based on the received signals. Further, clock selector 1 may be one or more components, including multiplexers, analog switches, or digital logic gates. For example, when clock selector 1 receives a signal, it determines the required clock signal source based on the signal and uses the selected clock signal source as the operating clock signal for the memory chip according to the input port of the selected clock.

[0051] Configuration selector 2 is a circuit component capable of setting or adjusting the on-chip clock source 3 and storage module 4 based on received signals. For example, configuration selector 2 may include one or more components such as registers, decoders, and control logic circuits. For example, configuration selector 2 can convert received signals into specific setting instructions. Further, the configuration selector 2's settings for the on-chip clock source 3 may include setting its enable state, frequency, phase, etc., and the settings for the storage module 4 may include setting its enable state, delay parameters, read speed, write speed, power consumption mode, etc.

[0052] For example, configuration selector 2 can receive configuration-related signals and parse their contents, then send the parsing results to on-chip clock source 3 or storage module 4. This enables the storage chip to adjust its operating mode according to actual needs, improving flexibility and energy efficiency.

[0053] The on-chip clock source 3 can be a clock signal generation module integrated inside the chip to provide a stable clock signal. For example, the on-chip clock source 3 can include an oscillator, such as an RC oscillator, an LC oscillator, a crystal oscillator, etc., so that a basic clock signal can be generated by the oscillator.

[0054] Furthermore, the on-chip clock source 3 may also include a frequency divider for generating clock signals of different frequencies based on the base clock signal. The on-chip clock source 3 can provide a clock signal independent of an external clock source, enhancing the robustness and autonomy of the system, while supporting multiple frequency clock signal outputs to meet the needs of different application scenarios. For example, the frequency divider can be configured to divide or multiply the base clock signal to output an on-chip clock signal, thereby reducing dependence on external clock signals and improving system reliability.

[0055] Storage module 4 can be a module within a storage chip used to store data and programs. Storage module 4 may include a storage cell array, such as DRAM storage cells, SRAM storage cells, flash memory storage cells, etc., and controls the writing and reading of data from the storage cells. For example, storage module 4 can adjust the read / write process according to the operating clock signal and the settings of configuration selector 2. Furthermore, storage module 4 may also include an address decoder and a data input / output buffer, wherein the address decoder is used to locate the target storage cell, and the data input / output buffer is used to implement data transmission.

[0056] This embodiment provides a memory chip that uses a clock selector 1 to determine the operating clock signal of the memory chip based on a received signal, from an external input clock signal and an on-chip clock signal generated by an on-chip clock source 3; a configuration selector 2 to configure the on-chip clock source 3 and / or the memory module 4 based on the received signal; the on-chip clock source 3 generates at least one on-chip clock signal based on the configuration selector 2; and the memory module 4 writes and / or reads data based on the received signal and the operating clock signal. The memory chip can flexibly switch between external clock signals and on-chip clock signals, achieving dynamic configuration and multi-mode compatibility, enabling the memory chip to adapt to various application scenarios, thereby improving compatibility and flexibility.

[0057] In one embodiment, the received signals include data signals, address signals, and control signals; the memory chip further includes data pads, address pads, and control pads, used as external interfaces to transmit data signals, address signals, and control signals respectively.

[0058] The external interfaces of the memory chip are configured in three groups: a data path, i.e., the data signals for writing / reading, which are transmitted via data pads; an address path, i.e., the address for writing / reading data, which is transmitted via address pads; and a control path, i.e., the control signals required for writing / reading operations, which are transmitted via control pads. In different application scenarios, data signals, address signals, and / or control signals can be selectively generated partially on the chip and partially input through these external interfaces. This application does not limit the requirement that all data signals, address signals, and control signals be input through external interfaces. For example, clock signals in the control signals and address signals can also be implemented using on-chip signal generation modules; this application does not impose specific limitations.

[0059] This embodiment provides a memory chip that provides an efficient data transmission channel through data pads, enabling data interaction between the memory chip and external devices; provides precise address positioning through address pads, enabling effective management of large-scale storage space; and allows the memory chip to adjust its operating mode according to external instructions through flexible control of the control pads, thereby improving the adaptability and flexibility of the memory chip.

[0060] In one embodiment, the control signal includes an input clock signal and a clock selection signal;

[0061] When the clock selection signal is an external clock, the clock selector is used to receive the input clock signal and use the input clock signal as the working clock signal of the memory chip.

[0062] The input clock signal can be a periodic clock signal provided by an external device, used to drive the write and read operations of the memory chip. For example, the input clock signal can be transmitted to a clock selector via control pads. The frequency and phase of the input clock signal can be determined and generated by the external device. The input clock signal provides an externally reliable clock source for the memory chip to control the read and write operations of the memory cells within the chip.

[0063] For example, an external device generates an input clock signal and transmits it to a clock selector via a control pad. When the clock selection signal is set to use an external clock, the clock selector uses the input clock signal as the operating clock signal for the memory chip.

[0064] A clock selection signal can be a control signal used to instruct a clock selector to select either an external input clock signal or an on-chip clock signal as the operating clock signal for the memory chip. For example, this signal can be transmitted to the clock selector via control pads. For example, when selecting one of two clock signals as the operating clock signal, the clock selection signal can be in the form of logic levels distinguished by high and low levels. For example, when selecting one of two or more clock signals as the operating clock signal, the clock selection signal can also be in the form of an encoded signal to achieve the selection distinction.

[0065] This embodiment provides a memory chip that dynamically adjusts the selection of the working clock signal according to the indication of the clock selection signal through a clock selector. This enables the clock signal selection function, thereby enhancing the flexibility and robustness of the memory chip's operation and improving its adaptability and flexibility.

[0066] In one embodiment, the control signal further includes a clock output signal;

[0067] When the clock selection signal is to use an internal clock, the clock selector is used to receive the on-chip clock signal generated by the on-chip clock source and use the on-chip clock signal as the working clock signal of the memory chip;

[0068] The working clock signal is also used as the clock output signal to be output to an external device.

[0069] The clock selection signal can be a control signal used to instruct the clock selector to select an external input clock signal or an on-chip clock signal as the operating clock signal for the memory chip. The specific form of the clock selection signal will not be elaborated upon in this embodiment.

[0070] When the clock selection signal uses the internal clock signal, the on-chip clock signal is generated by the on-chip clock source. The frequency and phase of the on-chip clock signal can be determined and generated according to the configuration selector settings. The on-chip clock signal, as the clock source signal generated internally by the memory chip, is provided as a clock output signal to external test equipment, ensuring that the output and capture signals of the external test equipment are synchronized with the operating clock signal of the memory chip. For example, since SRAM circuits are synchronous clock circuits, the start of read and write operations is triggered by a specific clock edge; therefore, the actions of external test equipment need to be driven and triggered by the same clock.

[0071] This embodiment provides a memory chip that uses an on-chip clock source to generate a clock signal for internal read and write operations and can output a clock signal for use as an external device. This ensures a certain degree of testing flexibility while improving clock quality, thereby significantly enhancing the system's integration and autonomy, optimizing resource utilization, and being compatible with various application scenarios that require master-slave clock synchronization, thus improving the adaptability and flexibility of the memory chip.

[0072] In one embodiment, the control signal further includes a configuration selection signal and a configuration input signal;

[0073] When the configuration selection signal is set to input configuration, the configuration selector configures the on-chip clock source and / or memory module based on the configuration input signal.

[0074] The configuration selection signal can be used to instruct the configuration selector to configure using externally input or internally stored configuration parameters. The configuration selection signal can be generated by an external device and transmitted to the configuration selector via control pads.

[0075] For example, after an external device generates a configuration selection signal, the signal is transmitted to the configuration selector via control pads. The configuration selector parses the configuration selection signal to determine whether the external input configuration signal should be used for parameter configuration. If the configuration selection signal indicates that input configuration should be used, the configuration selector can configure the on-chip clock source and / or memory module based on the configuration input signal.

[0076] Configuration input signals may include configuration parameters provided by external devices to indicate settings for the on-chip clock source and / or memory modules. For example, configuration input signals may include configuration parameters such as the frequency, phase, and delay of a clock signal.

[0077] By receiving configuration input signals from external devices, the configuration selector determines whether to use the configuration input signal based on the configuration selection signal and applies the configuration parameters to the actual operation. When the configuration selection signal indicates that external input configuration is used, the configuration selector parses the configuration input signal and may send the parsing result to the on-chip clock source and / or memory module. These modules adjust their operating states according to the received configuration parameters, which can better improve the test frequency and better reflect the chip performance.

[0078] A configuration selector can receive configuration selection signals and / or configuration input signals, and determine through internal logic whether external input configuration should be used. For example, a configuration selector may include a decoding module and an output module, used for parsing signals and generating configuration instructions, respectively.

[0079] This embodiment provides a memory chip that allows the memory chip to select whether to use externally input configuration parameters according to actual needs through a configuration selection signal, thereby improving the flexibility of the memory chip; the memory chip can dynamically adjust the working state of the on-chip clock source and / or memory module according to the needs of external devices, thereby enhancing the adaptability of the memory chip, thus achieving the effect of improving the adaptability and flexibility of the memory chip.

[0080] In one embodiment, the control signal further includes a configuration protocol signal;

[0081] The storage chip also includes a configuration register for storing preset configuration information;

[0082] When the configuration selection signal is to use internal configuration, the configuration register is used to receive the configuration protocol signal and transmit the configuration information to the configuration selector; the configuration selector is used to configure the on-chip clock source and / or memory module based on the configuration information.

[0083] The configuration protocol signal can be a control signal used to instruct the configuration register inside the memory chip to transmit preset configuration information to the configuration selector. For example, the configuration protocol signal can be generated by an external device and transmitted to the configuration register.

[0084] A configuration register can be a storage unit used to store configuration information. Furthermore, the configuration information can be obtained by storing configuration protocol signals. For example, a configuration register can be composed of flip-flops and latches.

[0085] When the configuration selection signal indicates that internal configuration is used, the configuration register can receive the configuration protocol signal, store the configuration information in the configuration protocol signal, and transmit the configuration information to the configuration selector. The configuration selector configures the on-chip clock source and / or memory module according to the configuration information.

[0086] This embodiment provides a memory chip that, through a configuration protocol signal, can adjust the output of a configuration register, providing flexible internal configuration switching capabilities. This allows the memory chip to dynamically adjust its operating mode according to preset configuration information. The configuration register stores configuration information and can operate autonomously without external input, reducing dependence on external devices and thus improving the adaptability and flexibility of the memory chip.

[0087] In one embodiment, the storage module includes a time-series balancing module and multiple repositories, the time-series balancing module being connected to each of the multiple repositories;

[0088] The timing balancing module is used to receive the working clock signal, and transmit the working clock signal to the storage repository after performing delay compensation based on the delay parameters.

[0089] The configuration selector further includes a delay configuration module, which is used to configure the delay parameters of the timing balance module based on the received signal.

[0090] The timing balancing module is a component used to compensate for the delay of the operating clock signal to ensure timing consistency among multiple repositories. The timing balancing module receives the operating clock signal from the clock selector and adjusts the input operating clock signal according to the delay parameters set by the configuration selector, thereby outputting a delay-compensated clock signal.

[0091] For example, the timing balancing module may receive the working clock signal from the clock selector, and perform delay compensation on the working clock signal through the delay unit according to the currently set delay parameters, and transmit the delay-compensated working clock signal to multiple repositories.

[0092] The configuration selector further includes a delay configuration module, which configures the delay parameters of the timing balancing module based on the received signal. Further, the configuration selector configures a selection signal and, based on the configuration input signal or configuration information provided by the configuration register, parses the delay parameter value to obtain the value and sends it to the timing balancing module to adjust its delay compensation. For example, the delay configuration module may include registers and a decoder, where the register stores the delay parameters, and the decoder may be a binary decoder, a multiplexer, etc., whose function is to parse the delay parameters in the configuration information.

[0093] This embodiment provides a memory chip that uses a delay configuration module to parse configuration information and send delay parameters. A timing balancing module compensates for the delay of the working clock signal based on the delay parameters. This ensures that multiple memory repositories operate in the same clock domain, thereby reducing data errors or performance degradation caused by clock skew. This achieves the technical effects of improving timing consistency and enhancing chip flexibility.

[0094] In one embodiment, the repository includes multiple repository units;

[0095] The timing balancing module includes a delay main module and at least one delay adjustment module. The delay adjustment module is connected to the output terminal of the delay main module, wherein:

[0096] The delay module is used to delay the input working clock signal for a first time and then output a first signal.

[0097] The delay adjustment module is used to receive the corresponding delay parameters according to the delay requirements, and after delaying the first signal for a second time, output the second signal to the multiple storage units.

[0098] The Chebyshev distance or Euclidean distance between the delay adjustment module and the multiple storage unit units is equal.

[0099] The delay module can be a component used to perform preliminary delay compensation on the input working clock signal, thereby making the delay of the clock signal to each repository the same, providing a unified time reference for the delay adjustment module. The delay adjustment module is used to solve the delay problem between different repository units within the same repository; generally, one delay adjustment module is set up in each repository, and the Chebyshev distance or Euclidean distance from the delay adjustment module to each repository unit in the repository is equal.

[0100] This embodiment provides a memory chip that provides basic delay compensation through a delay main module to ensure that subsequent modules are adjusted based on a unified time base, and a delay adjustment module performs further delay compensation to optimize the timing consistency of multiple storage units. By optimizing the structural design and physical layout of the timing balancing module, the delay problem in the clock signal transmission process can be solved, thereby improving the timing consistency and reliability between different storage units, optimizing resource utilization efficiency, and achieving the technical effects of improving timing consistency and enhancing chip flexibility.

[0101] In one embodiment, the on-chip clock source includes a clock adjuster and multiple on-chip clock generators, with different on-chip clock generators generating clock signals of different frequencies;

[0102] Based on the configuration selector, a target clock generator is determined from the plurality of on-chip clock generators, and the clock signal generated by the target clock generator is output to the clock adjuster.

[0103] The clock adjuster fine-tunes the clock signal generated by the on-chip clock generator based on the control signal to obtain the fine-tuned clock signal corresponding to the control signal, which is then used as the final clock signal.

[0104] The on-chip clock source includes multiple on-chip clock generators, which can generate clock signals of different frequencies or frequency ranges to provide the memory chip with clock signals of various frequencies to meet the needs of different scenarios. For example, the on-chip clock generator may include an oscillator and a frequency divider. The oscillator generates a base clock signal, and the frequency divider divides or multiplies the base clock signal according to the settings of the configuration selector, and outputs the clock signal to the clock adjuster.

[0105] A clock adjuster is used to fine-tune the clock signal generated by the on-chip clock generator, thereby improving the accuracy and stability of the clock signal. For example, the clock adjuster may include a digital time-locked loop (DLL), an analog time-locked loop (ADLL), a programmable delay unit, etc.

[0106] This embodiment provides a memory chip with a built-in on-chip clock source. It can generate multiple frequency clock signals through multiple on-chip clock generators for selection, and fine-tune the selected clock signal through a clock adjuster. This improves the accuracy and stability of the clock signal, thereby achieving the technical effects of improving timing consistency and enhancing chip stability.

[0107] To more clearly illustrate the technical solution of this application, this embodiment also provides a detailed embodiment in a specific application scenario.

[0108] In one embodiment, such as Figure 2 As shown, a memory chip is provided, which is applied to, for example Figure 3 The test environment shown includes an SRAM memory cell and three sets of external interfaces: a data path for transmitting data to be written / read, an address path for transmitting addresses for data to be written / read, and a control path. The control path transmits at least one of the following signals: a read / write control signal to control whether the current operation is a write or read operation, and at least one clock signal. Additionally, the control path may also transmit: (1) a configuration protocol signal for configuring the chip's internal configuration registers; (2) a configuration selection signal and a configuration input signal; and (3) a clock selection signal, a clock input signal, and a clock output signal.

[0109] In this embodiment, the memory chip is an SRAM chip controlled by a clock signal. The clock signal can be generated internally by the SRAM chip, and the SRAM chip will output the internally generated clock signal to the outside of the chip; the clock signal can also be input from the outside.

[0110] This embodiment's memory chip includes multiple banks, each bank comprising at least one bank cell array, and each bank cell comprising at least one storage sub-cell. Multiple storage sub-cells within the same bank cell array constitute a storage sub-cell array. Each storage sub-cell in the array can share the same control logic circuit to achieve data storage. Since the banks are relatively large and may be distributed across various corners of the chip, and each bank cell requires data, address, delay selection, and a system clock, this embodiment uses a timing balancing module to address the clock signal delay issue in order to ensure that the delays of these signals reaching each bank cell are as consistent as possible.

[0111] The memory chip also includes a clock selector, which selects one of a clock input and an on-chip clock as the operating clock signal based on a clock selection signal. When the clock selection signal is an external clock, the clock selector receives the input clock signal and uses it as the operating clock signal for the memory chip. When the clock selection signal is an internal clock, the clock selector receives the on-chip clock signal generated by the on-chip clock source and uses it as the operating clock signal for the memory chip; the operating clock signal is also used as the clock output signal to external test equipment.

[0112] The memory chip also includes a configuration selector and a configuration register, the latter storing preset configuration information. When the configuration selection signal is for input configuration, the configuration selector configures the on-chip clock source and / or memory module based on the configuration input signal. When the configuration selection signal is for internal configuration, the configuration register receives the configuration protocol signal and transmits the configuration information to the configuration selector; the configuration selector then configures the on-chip clock source and / or memory module based on the configuration information.

[0113] Depending on the clock selection signal and configuration selection signal in the control path, the memory chip in this embodiment can implement at least four operating modes:

[0114] Working Mode 1:

[0115] The clock selection signal selects the clock input as the operating clock signal for the memory chip, and the configuration selection signal selects the input configuration. The configuration selector configures the on-chip clock source and / or memory module based on the configuration input signal.

[0116] In this mode, since the configuration selection signal selects to use the input configuration, the configuration information output by the configuration register is ignored. In this mode, the configuration protocol and the working content of the configuration register are not referenced.

[0117] Similarly, since the on-chip clock will be ignored when the clock selection signal uses the clock input signal, the operation of the on-chip clock source will be either disabled or ignored.

[0118] The signals input to the "timing balance module" include: data signals and address signals; operating clock signals, which are the system clock output by the clock input signal via the clock selector; and configuration input signals, which are the delay selection signals output by the clock source and delay configuration input via the configuration selector.

[0119] This operating mode is the basic operating mode, in which test signals, control signals and clock signals are directly driven by external test equipment. It offers high testing flexibility and the memory chip is not limited by the test equipment. However, it cannot run high-frequency tests, and the test speed and chip area are significantly reduced.

[0120] Working Mode 2:

[0121] The clock selection signal uses the clock input signal as the system's operating clock signal, while the configuration selection signal uses the internal configuration.

[0122] In this mode, since the on-chip clock will be ignored when the clock selection signal uses the clock input signal, the on-chip clock source will either be disabled or ignored.

[0123] Since the configuration selection signal uses internal configuration, namely the clock source and delay configuration internal signals, the corresponding configuration parameters are transmitted to the configuration register through the configuration protocol signal. The configuration selector configures the on-chip clock source and / or memory module based on the configuration parameters.

[0124] The signals input to the timing balancing module include: data signals and address signals; operating clock signals, which are system signals output from the clock input signal via the clock selector; and delay selection signals output from the configuration protocol signal via the configuration register and configuration selector.

[0125] In this operating mode, the clock and test signals are provided by external test equipment, while the control signals are provided by the memory chip itself. This ensures test flexibility while providing more control bits and reducing the number of configuration input I / O ports, but at the cost of test preparation time.

[0126] Working Mode 3:

[0127] The clock selection signal uses the on-chip clock as the system's operating clock signal, i.e., the on-chip clock signal is used as the system's operating clock signal. The configuration selection signal uses input configuration, and the configuration selector configures the on-chip clock source and / or memory module based on the configuration input signal.

[0128] In this mode, since the configuration selection signal uses input configuration, the configuration information output by the configuration register is ignored. The configuration protocol and the contents of the configuration register are not referenced in this mode. Because the clock selection signal uses the on-chip clock signal, multiple on-chip clock generators generate multiple clock sources. The clock source selection signal output by the configuration selector determines which on-chip clock generator's clock signal will be output to the on-chip clock, i.e., used as the on-chip clock signal.

[0129] The signals input to the timing balancing module include: data signals and address signals; operating clock signals, i.e., the system clock output by the on-chip clock signal via the clock selector; and configuration input signals, i.e., the delay selection signal output by the clock source and delay configuration input via the configuration selector.

[0130] In this operating mode, the clock signal is generated internally by the memory chip, and the external test equipment provides test and control signals. This can ensure a certain degree of test flexibility and improve the quality of the clock signal. However, the external test equipment has high requirements for clock synchronization with the internal clock of the memory chip and for the real-time performance of the external test equipment.

[0131] Working Mode 4:

[0132] The clock selection signal selects the on-chip clock as the system's operating clock signal, while the configuration selection signal selects the internal configuration.

[0133] In this mode, since the configuration selection signal uses the internal configuration (i.e., the internal clock source and delay configuration signals), the corresponding configuration parameters must be transmitted to the configuration register via the configuration protocol signal. The configuration selector then configures the on-chip clock source and / or memory module based on these parameters. Because the clock selection signal uses the on-chip clock signal, multiple on-chip clock generators generate multiple clock sources. The clock source selection signal output by the configuration selector determines which on-chip clock generator's clock signal will be output to the on-chip clock, i.e., used as the on-chip clock signal.

[0134] The signals input to the timing balancing module include: data signals and address signals; the operating clock signal, which is the system clock output by the on-chip clock signal through the clock selector; and the delay selection signal output by the configuration protocol signal through the configuration register and the configuration selector.

[0135] In this operating mode, the test signal, control signal, and clock signal are all generated internally by the memory chip, which can greatly improve the test frequency and better reflect the chip's read and write performance. However, it sacrifices test flexibility and requires additional design to complete the test and transmit the test results.

[0136] The memory chip design in this embodiment can perfectly support at least four of the above-mentioned working modes, match the read and write test requirements of different scenarios, support high-frequency testing, achieve precise timing control, and can be widely used in read and write tests of different memory chips.

[0137] Furthermore, the on-chip clock source also includes a data-controlled oscillator (DCO). A DCO is an oscillator based on digital signal processing technology. Its working principle is to adjust the oscillator frequency by controlling the frequency of a digital signal. The DCO, as an on-chip clock generation circuit, can provide different frequency ranges. In this embodiment, the clock signal is generated internally using a DCO to ensure that the frequency of the on-chip generated clock signal matches the chip's corresponding operating frequency.

[0138] The on-chip clock source includes multiple on-chip clock generators and clock adjusters. Different on-chip clock generators generate clock signals of different frequencies. The clock signal generated by the target clock generator is output to the clock adjuster. The clock adjuster fine-tunes the clock signal generated by the target on-chip clock generator based on control signals to obtain the fine-tuned clock signal corresponding to the control signals, which serves as the final clock signal. Figure 8The diagram shown is a schematic representation of the overall structure of an on-chip clock signal generation circuit according to this embodiment. Figure 7 As shown, digital control performs path selection, and the frequency is coarsely adjusted by the effective number of stages in the ring oscillator circuit, thereby generating multiple frequencies, resulting in a wide adjustable frequency range. The single-stage delay of the ring oscillator in the clock adjuster is controlled based on the control current signal, so as to finely adjust the clock signal using the ring oscillator and obtain the oscillation frequency of the finely adjusted clock signal.

[0139] Specifically, the generation of the clock signal from the on-chip clock source may include the following steps:

[0140] Step S201: Determine the target on-chip clock generator from multiple on-chip clock generators based on the chip's operating frequency.

[0141] The frequency of the clock signal generated by the on-chip clock generator is within a preset frequency range; the operating frequency of the chip is within a preset frequency range, that is, this preset frequency range is based on the operating frequency of the chip, and the operating frequency of the chip will be within this preset frequency range.

[0142] An on-chip clock source can include multiple on-chip clock generators and clock adjusters. Different on-chip clock generators generate clock signals of different frequencies, enabling the memory chip to operate at different frequencies.

[0143] Typically, a preset frequency range can be determined based on the operating frequency required for the memory chip to operate. Specifically, the operating frequency of the memory chip must fall within the preset frequency range. Furthermore, the on-chip clock generator whose clock signal frequency falls within the preset frequency range is identified as the target on-chip clock generator. This ensures that the frequency of the clock signal generated by the target on-chip clock generator is within the same frequency range as the operating frequency of the memory chip, thus achieving coarse adjustment of the clock signal on the memory chip.

[0144] Step S202: Input multiple control signals into the clock adjuster to fine-tune the clock signal and obtain the oscillation frequency of the fine-tuned clock signal corresponding to each control signal.

[0145] The clock adjuster includes adjusting single-stage delays based on control signals.

[0146] Furthermore, multiple control signals are input into the clock adjuster. The single-stage delay of the clock adjuster corresponding to each control signal is different. Thus, by adjusting the single-stage delay of the clock adjuster through multiple control signals, the clock signal output by the on-chip clock generator is adjusted, and the oscillation frequency of the clock signal corresponding to each control signal is obtained.

[0147] Step S203: Determine the target control signal based on the operating frequency of the memory chip and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal.

[0148] Furthermore, the control signal corresponding to the clock signal oscillation frequency that is consistent with the operating frequency of the memory chip or within a preset error range is determined as the target control signal.

[0149] Step S204: Based on the target on-chip clock generator and the target control signal, control the generation of the final clock signal.

[0150] Furthermore, a target on-chip clock generator is determined from multiple on-chip clock generators, and the target control signal is input into the clock adjuster. The clock adjuster is then used to fine-tune the clock signal generated by the target on-chip clock generator to obtain the final clock signal, so that the oscillation frequency of the final clock signal can be consistent with the chip's operating frequency or within a preset error range.

[0151] In the above implementation process, based on the operating frequency of the memory chip, a target on-chip clock generator is determined from multiple on-chip clock generators. This ensures that the frequency of the clock signal generated by the target on-chip clock generator is within the same frequency range as the operating frequency of the memory chip, achieving coarse adjustment of the clock signal. Furthermore, multiple control signals are input into the clock adjuster, thereby adjusting the single-stage delay of the clock adjuster through each control signal, thus adjusting the clock signal output by the target on-chip clock generator. By determining the target control signal based on the operating frequency of the memory chip and the oscillation frequency of the finely adjusted clock signal corresponding to each control signal, fine adjustment of the clock signal is achieved, ensuring that the frequency of the final output clock signal is consistent with the operating frequency of the chip or within a preset error range.

[0152] Furthermore, the control signals are digital signals, such as... Figure 4 As shown, the clock adjuster includes a digitally controlled current source, a ring oscillator, and a feedback loop. A digital signal is input to the digitally controlled current source, which outputs a control current signal. This control current signal can control the output frequency of the ring oscillator by controlling a single-stage delay. Inputting multiple control signals into the clock adjuster to fine-tune the clock signal and obtain the fine-tuned clock signal oscillation frequency corresponding to each control signal can include the following steps:

[0153] Step 1: The current source component in the clock regulator converts the digital signal into a control current signal.

[0154] Step 2: Based on the control current signal, control the single-stage delay of the ring oscillator in the clock adjuster to fine-tune the clock signal and obtain the oscillation frequency of the fine-tuned clock signal.

[0155] For example, the control signal can be a digital signal, and the frequency formula of the ring oscillator is:

[0156]

[0157] Among them, f osc Let denot n represent the frequency of the ring oscillator, n represent the number of stages in the ring oscillator, and τ represent the single-stage delay of the ring oscillator. Therefore, the frequency of the ring oscillator can be adjusted by controlling its number of stages and single-stage delay.

[0158] Specifically, after multiple digital signals are input into the clock regulator, the current source component in the clock regulator converts the digital signals into control current signals. Further, the single-stage delay of the ring oscillator in the clock regulator is controlled by the control current signal. By adjusting the single-stage delay of the ring oscillator, the clock signal is fine-tuned, and the oscillation frequency of the fine-tuned clock signal corresponding to each digital signal is obtained.

[0159] In the above implementation process, the digital signal is converted into a control current signal by the current source component in the clock regulator, and the single-stage delay of the ring oscillator in the clock regulator is controlled by the control current signal, thereby realizing the fine adjustment of the clock signal by the ring oscillator.

[0160] Furthermore, based on the chip's operating frequency and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal, the target control signal is determined, including: among the oscillation frequencies of the fine-tuned clock signals corresponding to multiple control signals, the control signal corresponding to the clock signal that is consistent with the operating frequency or within a preset error range is determined as the target control signal.

[0161] Specifically, when determining the target control signal, the control signal corresponding to the clock signal that is consistent with the operating frequency or within the preset error range among the oscillation frequencies of the finely tuned clock signals corresponding to multiple control signals is determined as the target control signal. This ensures that the frequency of the clock signal generated by the target on-chip clock generator is consistent with the chip's operating frequency or within the preset error range, thus ensuring that the clock signal frequency of the on-chip generator in the chip is within the corresponding chip's operating frequency range.

[0162] Furthermore, the single-stage delay of the ring oscillator in the clock adjuster based on the control current signal, in order to fine-tune the clock signal using the ring oscillator and obtain the oscillation frequency of the fine-tuned clock signal, may include the following steps:

[0163] Step 1: Reduce the oscillation frequency to obtain the reduced oscillation frequency.

[0164] Step 2: Deduplicate the oscillation frequency after frequency reduction to obtain the deduplicated oscillation frequency.

[0165] Step 3: Convert the deduplicated oscillation frequency into a feedback current signal through the feedback loop in the clock adjuster.

[0166] Step 4: Based on the control current signal and the feedback current signal, control the single-stage delay of the ring oscillator in the clock adjuster to fine-tune the clock signal using the ring oscillator and obtain the oscillation frequency of the fine-tuned clock signal.

[0167] To achieve a relatively linear oscillator using a digitally controlled current source, the DCO function can be improved through negative feedback techniques. The feedback loop is formed by sampling the output and mixing it with the input. Because the frequency of the oscillator output is too high, there is no time to directly sample through capacitor charging and discharging.

[0168] Specifically, the output frequency of the ring oscillator can be reduced using a frequency divider circuit to obtain the reduced oscillation frequency. This reduced oscillation frequency is then deduplicated using a non-overlapping pulse generation circuit to obtain the final oscillation frequency. Furthermore, the deduplicated oscillation frequency is converted into a feedback current signal through a feedback loop in a clock regulator.

[0169] Furthermore, the control current signal and the feedback current signal are combined, and the combined signal controls the single-stage delay of the ring oscillator in the clock adjuster, so as to use the ring oscillator to fine-tune the clock signal and obtain the oscillation frequency of the fine-tuned clock signal.

[0170] The target control signal is determined based on the chip's operating frequency and the oscillation frequency of the clock signal corresponding to each control signal. This also includes ensuring that the stability of the oscillation frequency of the fine-tuned clock signal is higher than a preset value.

[0171] Furthermore, after fine-tuning the clock signal of the ring oscillator, the stability of the oscillation frequency of the fine-tuned clock signal is higher than the preset value. Specifically, this preset value can be determined according to the chip's operating frequency, application scenario requirements, etc.

[0172] In the above implementation process, the frequency of the ring oscillator output is reduced by a frequency divider circuit. Instead of an overlapping pulse generation circuit, the frequency of the reduced oscillation frequency is deduplicated. The deduplicated oscillation frequency is then converted into a feedback current signal through the feedback loop in the clock regulator. The control current signal and the feedback current signal are then combined, and the combined signal controls the single-stage delay of the ring oscillator in the clock regulator, thus realizing the loop regulation of the clock regulator.

[0173] Furthermore, the current source component is also used to generate various proportional currents via digital signal control.

[0174] The current source assembly includes a current source, a matching transistor, and a digitally controlled transistor. The first terminal of the matching transistor is connected to the current source, the second terminal of the matching transistor is connected to the digitally controlled transistor, and the third terminal of the matching transistor is connected to a ring oscillator. The matching transistor is used to stabilize the current output by the current source and input the stabilized current into the ring oscillator through the third terminal of the matching transistor. The first terminal of the digitally controlled transistor is connected to a first digital signal, and the second terminal of the digitally controlled transistor is connected to the second terminal of the matching transistor. The digitally controlled transistor is used to control the magnitude of the current output by the matching transistor based on the first digital signal.

[0175] Specifically, the current source component generates various proportional currents through digital signal control. Figure 5 This is a circuit diagram of a current source component provided in an embodiment of this application, such as... Figure 5 The current source assembly shown in the large blue dashed box includes a current source, a matching transistor (black solid box), and a digitally controlled transistor (yellow dashed box). The matching transistor in the black solid box replicates the current from the stable current source in binary mode via a current mirror. The digitally controlled transistor in the yellow dashed box consists of digitally controlled parallel binary weighted transistors. By using digital codes to turn the transistors on / off, the current through Ms1 is determined by the input digital code. The output node is connected to a single, permanently conducting transistor (Ms2), and the digitally controlled transistor is isolated from this node, which helps reduce the impact of voltage level variations in the digital control signal on the current value. The size of the digitally controlled transistor increases in binary mode. This section uses eight digital signals C0, C1, ..., C8 as controllable signal inputs, corresponding to 512 input levels from 00000000 to 11111111, providing 512 different current values.

[0176] In the above implementation process, a current source component consisting of a current source, a matching transistor, and a digitally controlled transistor is used to generate different proportional currents by a digitally controlled current source.

[0177] Furthermore, the ring oscillator in the clock regulator includes multiple differential units, each of which includes a latch and two inverters for driving current into the latch. The latch includes two cross-coupled inverters.

[0178] For example, Figure 6 This is a schematic diagram of a ring oscillator provided in an embodiment of this application, as shown below. Figure 6 The oscillator shown is a ring structure (a), consisting of four differential units. Figure 6(c) in the diagram represents the current source component. Each differential unit (b) includes a cross-coupled structure comprising two cross-coupled inverters (solid black boxes) used as latches and two inverters (dashed green boxes) responsible for driving current into the latches. To change the latching speed and thus the delay of each unit, we varied the current intensity (cs1 / cs2) driving the inverter. To improve the oscillator's jitter performance, an inverter is used in each output node to adjust the swing level. The oscillator produces eight distinct phases at the output.

[0179] In the above implementation, a ring oscillator structure consisting of four differential units, including latches and two inverters for driving current into the latches, and the latches including two cross-coupled inverters, enables the ring oscillator to output multiple different phases.

[0180] In one embodiment, the plurality of on-chip clock generators include a ring oscillator circuit and a multiplexer. Determining a target on-chip clock generator from the plurality of on-chip clock generators based on the chip's operating frequency may include the following steps:

[0181] Step 1: The ring oscillator circuit adjusts the effective number of stages in the oscillation path through a multiplexer to generate clock signals of different frequencies;

[0182] Step 2: Input the selection signal into the multiplexer to determine the effective number of stages of the ring oscillator circuit, thereby determining the target on-chip clock generator; the frequency of the clock signal generated by the target on-chip clock generator is within the preset frequency range; the operating frequency of the chip is within the preset frequency range.

[0183] Specifically, Figure 7This is a schematic diagram of the circuit structure of multiple on-chip clock generators (including a ring oscillator circuit and a multiplexer) provided in the embodiments of this application. It includes a ring oscillator circuit composed of a NAND gate, K delay units, and a 16-to-1 multiplexer, where K is an even number greater than 0. The NAND gate includes two input terminals and one output terminal, one of which, EN, is used to connect an external start control signal to control the switching of the circuit. The delay units are connected in series, with the input terminal of the first delay unit connected to the output terminal of the NAND gate, and the output terminal of the last delay unit connected to one input of the 16-to-1 multiplexer. Each delay unit consists of an odd number of inverters. The 16-to-1 multiplexer includes 16 inputs (dividing the K delay units into 16 equal segments), four digital control selection signals S1 / S2 / S3 / S4, and one output. The output terminal of the 16-to-1 multiplexer is connected to the other input terminal of the NAND gate, forming a ring oscillator structure. Four digital signals S0 / S2 / S3 / S4 are used as controllable signal inputs, corresponding to 16 input levels from 0000 to 1111, with 0000 corresponding to the highest effective level and the lowest oscillation frequency output. Coarse frequency adjustment is achieved by selecting a 16-to-1 multiplexer to control the path selection and adjusting the effective level in the oscillation path.

[0184] When determining the target on-chip clock generator, the ring oscillator circuit adjusts the effective number of stages in the oscillation path through a multiplexer to generate clock signals of different frequencies.

[0185] Furthermore, the selection signal is input to the multiplexer to determine the effective number of stages of the ring oscillator circuit. When the frequency of the clock signal generated by a certain on-chip clock generator is within the preset frequency range, and the operating frequency of the chip is within the preset frequency range, the on-chip clock generator is determined as the target on-chip clock generator.

[0186] In the above implementation process, the 16-to-1 multiplexer is controlled by the selection signal to select the path, and the effective number of stages in the oscillation path is adjusted to determine the target on-chip clock generator, thereby achieving coarse frequency adjustment. This ensures that the frequency of the clock signal generated by the target on-chip clock generator is within the preset frequency range, and the operating frequency of the chip is within the preset frequency range.

[0187] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0188] Based on the same inventive concept, this application also provides a semiconductor testing system, including testing equipment and the aforementioned memory chip, which can be used to test the read and write performance of the memory chip. In the one or more semiconductor testing system embodiments provided below, the specific limitations on the memory chip can be found in the above-described limitations on the memory chip, and will not be repeated here.

[0189] In one embodiment, a semiconductor testing system is provided, including a testing device and a memory chip as described in any of the above embodiments. Further, the testing device may include a processor, a memory chip, a communication interface, a display screen, and an input device connected via a system bus, and interacts with the memory chip via control paths, address paths, and data paths. The processor of the testing device provides computing and control capabilities. The communication interface of the testing device is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. The display screen of the testing device can be a liquid crystal display (LCD) or an e-ink display. The input device of the testing device can be a touch layer covering the display screen, or buttons, a trackball, or a touchpad mounted on the casing of the testing device, or an external keyboard, touchpad, or mouse, etc.

[0190] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0191] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A memory chip, characterized by, The storage chip comprises a clock selector, a configuration selector, an on-chip clock source and a storage module; the on-chip clock source comprises a clock adjuster and a plurality of on-chip clock generators, and different on-chip clock generators generate clock signals of different frequencies based on data control oscillators; The clock signal generation of the on-chip clock source comprises: based on the configuration selector, determining, as a target on-chip clock generator, an on-chip clock generator of which the frequency of the clock signal in the on-chip clock generator is within a preset frequency range among the plurality of on-chip clock generators, and outputting the clock signal generated by the target on-chip clock generator to the clock adjuster; the clock adjuster comprises a digital control current source, a ring oscillator and a feedback loop; wherein a digital signal is input into the digital control current source to output a control current signal; based on the control current signal and a feedback current signal, the single-stage delay of the ring oscillator in the clock adjuster is controlled to fine-tune the clock signal by the ring oscillator, and the oscillation frequency of the fine-tuned clock signal is obtained; the oscillation frequency stability of the fine-tuned clock signal is higher than a preset value; the feedback current signal is obtained by converting the de-duplicated oscillation frequency through the feedback loop; wherein the frequency output by the ring oscillator is reduced through a frequency division circuit to obtain a reduced oscillation frequency, and the reduced oscillation frequency is de-duplicated through a non-overlapping pulse generation circuit to obtain a de-duplicated oscillation frequency; The clock selector is configured to determine the working clock signal of the storage chip from the external input clock signal and the on-chip clock signal generated by the on-chip clock source based on the received signal; The configuration selector is configured to set the on-chip clock source and / or the storage module based on the received signal; The on-chip clock source is configured to generate at least one on-chip clock signal based on the setting of the configuration selector; The storage module is configured to write and / or read data based on the received signal and the working clock signal.

2. The memory chip of claim 1, wherein, The received signal comprises a data signal, an address signal and a control signal; The storage chip further comprises a data pad, an address pad and a control pad for transmitting the data signal, the address signal and the control signal as external interfaces, respectively.

3. The memory chip of claim 2, wherein, The control signal comprises an input clock signal and a clock selection signal; When the clock selection signal is to use an external clock, the clock selector is configured to receive the input clock signal and use the input clock signal as the working clock signal of the storage chip.

4. The memory chip of claim 3, wherein, The control signal further comprises a clock output signal; When the clock selection signal is to use an internal clock, the clock selector is configured to receive the on-chip clock signal generated by the on-chip clock source and use the on-chip clock signal as the working clock signal of the storage chip; The working clock signal is further configured to be output to an external device as the clock output signal.

5. The memory chip of claim 2, wherein, The control signal further comprises a configuration selection signal and a configuration input signal; When the configuration selection signal is to use an input configuration, the configuration selector is configured to configure the on-chip clock source and / or the storage module based on the configuration input signal.

6. The memory chip of claim 5, wherein, The control signal further comprises a configuration protocol signal; The storage chip further comprises a configuration register configured to store preset configuration information; When the configuration selection signal is the internal configuration, the configuration register is configured to receive the configuration protocol signal and transmit the configuration information to the configuration selector; and the configuration selector is configured to configure the on-chip clock source and / or the storage module based on the configuration information.

7. The memory chip of claim 1, wherein, The storage module comprises a timing balance module and a plurality of storage banks, and the timing balance module is connected to the plurality of storage banks respectively; The timing balance module is configured to receive a working clock signal, and transmit the working clock signal to the storage banks after delay compensation based on a delay parameter. The configuration selector further comprises a delay configuration module configured to configure the delay parameter of the timing balance module based on a received signal.

8. The memory chip of claim 7, wherein, The storage bank comprises a plurality of storage units. The timing balance module comprises a delay main module and at least one delay adjustment module, and the delay adjustment module is connected to an output end of the delay main module. The delay main module is configured to output a first signal after delaying an input working clock signal for a first time. The delay adjustment module is configured to receive a corresponding delay parameter according to a delay requirement, delay the first signal for a second time, and output a second signal to the plurality of storage units. The Chebyshev distance or Euclidean distance between the delay adjustment module and the plurality of storage units is equal.

9. The memory chip of claim 1, wherein, The clock adjuster fine tunes the clock signal generated by the target on-chip clock generator based on a control signal to obtain a fine-tuned clock signal corresponding to the control signal as a final clock signal.

10. A semiconductor test system, characterized by, The test device and the storage chip as claimed in any one of claims 1 to 9 are provided.

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