Multilayer capacitor

Abstract

The present disclosure provides a multilayer capacitor. The multilayer capacitor according to the present disclosure includes a dielectric layer including an aluminum nitride (AlN)-based compound including AlN, a doped AlN compound, or a combination thereof, in which AlN is doped with Ni, Co, Mn, Cr, V, Zn, Re, Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, La, or a combination thereof, and a crystal orientation of the aluminum nitride-based compound is a c-axis crystal orientation.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0196170, filed with the Korean Intellectual Property Office on December 29, 2023, and Korean Patent Application No. 10-2024-0098902, filed with the Korean Intellectual Property Office on July 25, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a multilayer capacitor. Background Art

[0003] Recently, with the rapid development of the multifunctionalization and miniaturization of electronic devices, the miniaturization and performance improvement of electronic components have also been developing at an extremely fast pace. In addition, the demand for high reliability of electronic devices for automobiles, network devices, etc., and electronic components for industry has also increased significantly.

[0004] To meet such market demands, the competition in the technical development of passive components such as inductors, capacitors, or resistors has been accelerating. In particular, it requires great efforts to occupy the market by developing various multilayer ceramic capacitor (MLCC) products, the applications and uses of which have been continuously increasing as passive components.

[0005] In addition, multilayer capacitors are manufactured by stacking dielectric layers and internal electrodes and are used in various electronic devices such as mobile phones, laptop computers, and liquid crystal display televisions (LCD TVs).

[0006] With recent technological advancements, multilayer capacitors are required to have improved performance such as higher capacitance, increased capacitance density, and increased withstand voltage.

[0007] Recently, thin film capacitors different from existing multilayer ceramic capacitor (MLCC) types have been developed. In the case of thin film capacitors, high capacitance can be achieved by maximizing the area of the capacitor and minimizing the thickness of the dielectric layer.

[0008] To implement thin film capacitors, it is necessary to develop dielectric materials and electrode materials that can improve capacitance characteristics and withstand voltage characteristics. Summary of the Invention

[0009] One aspect of the present disclosure provides a multilayer capacitor that can improve withstand voltage characteristics and achieve high capacitance.

[0010] However, the problems to be solved by the embodiments are not limited to the above problems and can be extended in various ways within the scope of the technical idea included in the embodiments.

[0011] The multi-layer capacitor according to an embodiment includes: a dielectric layer including an aluminum nitride (AlN)-based compound, wherein the aluminum nitride-based compound includes AlN, a doped AlN compound, or a combination thereof, and in the doped AlN compound, AlN is doped with Ni, Co, Mn, Cr, V, Zn, Re, Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, La, or a combination thereof, the dielectric layer includes dielectric grains, and the crystal orientation of the dielectric grains is a c-axis crystal orientation.

[0012] In the doped AlN compound, AlN may be doped with Sc, Er, Y, La, or a combination thereof.

[0013] The content (at%) of the element doped in the doped AlN compound may be greater than or equal to about 1 at% and less than about 30 at%.

[0014] The aluminum nitride-based compound included in the dielectric layer may have a hexagonal close-packed (HCP) crystal structure and may have a (0002) crystal plane.

[0015] The average thickness of the dielectric layer may be in the range of about 20 nm to about 400 nm.

[0016] The multi-layer capacitor may include: a substrate; a base layer located on the substrate; a capacitor body disposed on the base layer and including alternately arranged inner electrodes and dielectric layers; and outer electrodes disposed on the base layer and outside the capacitor body.

[0017] The inner electrodes include a first inner electrode and a second inner electrode, the first inner electrode and the second inner electrode include a conductive metal containing Mo, W, Ru, Ti, Pt, Al, or a combination thereof, and the conductive metals included in the first inner electrode and the second inner electrode may be different.

[0018] The inner electrodes may include a conductive metal having a body-centered cubic (BCC) crystal structure and a (110) crystal plane, a conductive metal having a hexagonal close-packed (HCP) crystal structure and a (0002) crystal plane, a conductive metal having a face-centered cubic (FCC) crystal structure and a (111) crystal plane, or a combination thereof.

[0019] The multi-layer capacitor may further include an inner electrode stack located between the base layer and the dielectric layer.

[0020] The average thickness of the inner electrodes may be in the range of about 20 nm to about 400 nm.

[0021] The multi-layer capacitor may further include a seed layer located between the base layer and the capacitor body.

[0022] A multilayer capacitor according to another embodiment includes: a substrate; a base layer located on the substrate; a capacitor body disposed on the base layer and including alternately arranged inner electrodes and dielectric layers; and an outer electrode disposed on the base layer and outside the capacitor body, wherein the dielectric layer includes an aluminum nitride (AlN)-based compound, the aluminum nitride-based compound includes AlN, a doped AlN compound, or a combination thereof, in the doped AlN compound, AlN is doped with Ni, Co, Mn, Cr, V, Zn, Re, Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, La, or a combination thereof, the dielectric layer includes a plurality of dielectric grains, and the crystal orientation of the dielectric grains is a c-axis crystal orientation, the inner electrodes include a first inner electrode and a second inner electrode, the first inner electrode and the second inner electrode include a conductive metal including Mo, W, Ru, Ti, Pt, Al, or a combination thereof, and the conductive metals included in the first inner electrode and the second inner electrode are different.

[0023] The multilayer capacitor according to the embodiment has the advantages of improving the withstand voltage characteristics and achieving a high capacitance.

[0024] However, the various beneficial advantages and effects of the present disclosure are not limited to the above description and can be more easily understood during the process of explaining the specific embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 4 is a cross-sectional view schematically showing a multilayer capacitor 100 according to an embodiment.

[0026] Figure 5 is a schematic view schematically showing the crystal structure and crystal plane of the inner electrode material according to an embodiment.

[0027] Figure 6 is a graph showing the results of measuring the dielectric constant of an AlScN compound according to the Sc content (at%).

[0028] Figure 7 is an XRD analysis graph of the dielectric layer included in the multilayer capacitor according to Example 2-1 and Example 2-2.

[0029] Figure 8 is a schematic view schematically showing a multilayer capacitor manufactured by a method for manufacturing a multilayer capacitor according to an embodiment.

[0030] Figure 9 is a schematic view schematically showing a multilayer capacitor manufactured by a method for manufacturing a multilayer capacitor according to another embodiment. DETAILED DESCRIPTION

[0031] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. The drawings and the description are considered to be illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements. In addition, the drawings are provided to assist in easily understanding the exemplary embodiments disclosed in this specification, and the technical spirit disclosed in this specification is not limited by the drawings, and it will be understood that the present disclosure includes all variations, equivalents, and alternatives included in the spirit and technical scope of the present disclosure.

[0032] Terms including ordinal numbers (such as "first" and "second") are used to describe various components, but these components are not limited by the terms. These terms are only used to distinguish one component from another component.

[0033] When a component is referred to as being "connected" or "coupled" to another component, it will be understood that the component can be directly connected or coupled to the other component, or there may be other components in between. In contrast, when a component is referred to as being "directly connected" or "directly coupled" to another component, it will be understood that there are no other components in between.

[0034] In this application, it will be understood that the terms "comprising" and "having" are intended to indicate the presence of the features, numbers, steps, operations, components, assemblies, or combinations thereof described in the specification, and do not exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, assemblies, or combinations thereof. Therefore, unless explicitly described to the contrary, the word "comprising" and variations such as "including" or "having" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0035] Throughout the specification, the "stacking direction" refers to the direction in which components are stacked sequentially, and can also be the "thickness direction" perpendicular to the wide surface (main surface) of the sheet-like component. In the drawings, the "stacking direction" corresponds to the T-axis direction. In addition, the "lateral direction" refers to the direction extending parallel to the wide surface (main surface) from the edge of the sheet-like component, which can be the "length direction" and corresponds to the L-axis direction in the drawings. The direction perpendicular to the T-axis direction and the L-axis direction in the drawings can be defined as the W-axis direction (width direction).

[0036] Throughout the specification, in the multilayer capacitor 100, two surfaces that face each other in the thickness direction (T-axis direction) may be defined as the first surface and the second surface, two surfaces that are bonded to the first surface and the second surface and face each other in the length direction (L-axis direction) may be defined as the third surface and the fourth surface, and two surfaces that are bonded to the first surface and the second surface, bonded to the third surface and the fourth surface, and face each other in the width direction (W-axis direction) may be defined as the fifth surface and the sixth surface.

[0037] As an example, the first surface, which is the lower surface, may be the mounting surface. In addition, the first surface to the sixth surface may be flat. However, the present exemplary embodiment is not limited thereto. For example, the first surface to the sixth surface may be curved surfaces having a convex central portion, and the boundary (i.e., the edge) of each surface may be rounded.

[0038] The shape and size of the multilayer capacitor 100 and the number of stacked dielectric layers 130 are not limited to those of the multilayer capacitor shown in the drawings of the present embodiment and the number of stacked dielectric layers.

[0039] In addition, the multilayer capacitor 100 may include an active region and a covering region.

[0040] The active region is a portion that contributes to the formation of the capacitance of the multilayer capacitor 100. As an example, the active region may be a region where the first internal electrode 141 and the second internal electrode 142 stacked along the thickness direction (T-axis direction) overlap.

[0041] The covering region is an edge portion in the thickness direction and may be located on the upper surface and the lower surface of the active region in the thickness direction (T-axis direction), respectively. In addition, the multilayer capacitor 100 may further include side covering regions. The side covering regions are edge portions in the width direction and may be located on the two opposite side surfaces of the active region in the width direction (W-axis direction), respectively. In addition, the side covering regions are also provided at the ends of the first internal electrode 141 and the second internal electrode 142 that are not connected to the external electrodes 161 and 162 in the length direction (L-axis direction).

[0042] For example, the covering region may be a single dielectric layer 130 or two or more dielectric layers 130 stacked on the upper surface and the lower surface of the active region, respectively. For example, the covering region may include insulating materials such as silicon dioxide (SiO2), silicon nitride (SiN, Si3N4), aluminum nitride (AlN), or aluminum oxide (Al2O3).

[0043] The covering region and the side covering regions are used to prevent damage to the first internal electrode 141 and the second internal electrode 142 due to physical stress or chemical stress.

[0044] Hereinafter, various embodiments and variations will be described in detail with reference to the accompanying drawings.

[0045] Figures 1 to 4 is a cross-sectional view schematically showing a multilayer capacitor 100 according to an embodiment.

[0046] Referring to Figures 1 to 4 , the multilayer capacitor 100 according to an embodiment includes: a substrate 110; a base layer 120 located on the substrate 110; a capacitor body disposed on the base layer 120 and including alternately arranged inner electrodes 141 and 142 and dielectric layers 130; and outer electrodes 161 and 162 disposed on the base layer 120 and outside the capacitor body.

[0047] Referring to Figure 2 and Figure 3 , the multilayer capacitor 100 may further include an inner electrode stack 143 disposed between the base layer 120 and the dielectric layer 130.

[0048] Referring to Figure 4 , the multilayer capacitor 100 may further include a seed layer 170 located between the base layer 120 and the capacitor body.

[0049] The substrate 110 may include a silicon substrate and may include, for example, a silicon wafer (Si wafer) type substrate or a silicon-on-insulator (SOI) type substrate.

[0050] The base layer 120 serves as a buffer layer to prevent the substrate 110 from being etched when the electrode-dielectric layer to be described later is etched by a dry etching process after depositing the dielectric layer 130 and the inner electrodes 141 and 142. The base layer 120 may include silicon dioxide (SiO2), silicon nitride (SiN, Si3N4), aluminum nitride (AlN), aluminum oxide (Al2O3), or a combination thereof.

[0051] dielectric layer The multilayer capacitor 100 according to an embodiment includes a dielectric layer 130. The dielectric layer 130 includes an aluminum nitride (AlN)-based compound. The aluminum nitride-based compound includes AlN, an AlN compound (or "doped AlN compound"), or a combination thereof. In the AlN compound, AlN is doped with Ni, Co, Mn, Cr, V, Zn, Re, Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, La, or a combination thereof (i.e., one of Ni, Co, Mn, Cr, V, Zn, Re, Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, and La, or a combination thereof). The dielectric layer includes a plurality of dielectric grains, and the crystal orientation of the dielectric grains is a c-axis crystal orientation.

[0052] As an example, the AlN-based compound included in the dielectric layer 130 may have a hexagonal close-packed (HCP) crystal structure and a (0002) crystal plane perpendicular to the c-axis.

[0053] As an example, an aluminum nitride (AlN)-based compound may include AlN, an AlN compound doped with Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, La, or a combination thereof, or a combination of them.

[0054] As a specific example, an aluminum nitride (AlN)-based compound may include AlN, an AlN compound doped with Sc, Er, Y, La, or a combination thereof, or a combination of them.

[0055] The aluminum nitride (AlN)-based compound may include an AlN compound in which the Al sites are doped with other elements to achieve a high-capacitance dielectric.

[0056] As an example, other elements doped into AlN replace the Al sites of AlN to increase the dielectric constant of the doped compound, thereby achieving a high-capacitance dielectric.

[0057] For example, when the atomic size of the atoms doped into AlN is larger than the atomic size of Al atoms, distortion of the unit lattice occurs in the doped compound, and the net polarity increases compared to AlN, thereby increasing the dielectric constant.

[0058] As an example, AlN may be doped with elements having an atomic radius larger than the atomic radius of Al atoms. As an example, AlN may be doped with elements having an atomic radius larger than about 1.43 Å. As a specific example, AlN may be doped with elements having an atomic radius larger than about 1.60 Å.

[0059] In an embodiment, the content (atomic %, at%) of the doped elements in the doped AlN compound may be greater than or equal to about 1 at%, greater than or equal to about 5 at%, or greater than or equal to about 10 at%, and less than about 30 at%, less than or equal to about 25 at%, or less than or equal to about 20 at%.

[0060] If the content of the doped elements in the doped AlN compound is less than about 1 at%, it may be difficult to achieve a high-capacitance dielectric by doping, and if the content of the doped elements in the doped AlN compound is greater than or equal to about 30 at%, a brittle crystal phase is produced, making it difficult to manufacture the dielectric for sputtering, and there may be a large amount of abnormal grain growth in the dielectric layer 130.

[0061] As an example, the dielectric layer 130 includes a plurality of dielectric grains, and the dielectric grains may include the aforementioned aluminum nitride-based compound.

[0062] In an embodiment, the crystal orientation of the dielectric grains is a c-axis crystal orientation.

[0063] To deposit a dielectric layer 130 including an aluminum nitride-based compound on a substrate 110 in a semi-epitaxial manner, the crystal orientation of dielectric grains in the dielectric layer 130 can be aligned with the c-axis crystal orientation.

[0064] When the crystal orientation of the aluminum nitride-based compound is aligned with the c-axis crystal orientation, the defect sites in the dielectric layer 130 are reduced, and the withstand voltage characteristics can be improved.

[0065] As an example, the crystal orientation of the dielectric layer 130 can be confirmed by high-resolution X-ray diffraction (XRD) or high-resolution transmission electron microscopy (HR-TEM) analysis.

[0066] As an example, after performing high-resolution XRD rocking curve analysis on the dielectric layer 130, the full width at half maximum (FWHM) and the intensity of the main peak can be measured in the XRD curve.

[0067] For example, the higher the c-axis crystal orientation of the aluminum nitride-based compound included in the dielectric layer 130, the smaller the FWHM value can be.

[0068] For example, the higher the c-axis crystal orientation of the aluminum nitride-based compound included in the dielectric layer 130, the smaller the FWHM / intensity value (the value normalized by FWHM to intensity) can be.

[0069] For example, the average thickness of the dielectric layer 130 can be greater than or equal to about 20 nm, greater than or equal to about 50 nm, greater than or equal to about 100 nm, or greater than or equal to about 200 nm, and can be less than or equal to about 400 nm or less than or equal to about 300 nm.

[0070] If the average thickness of the dielectric layer 130 is less than about 20 nm, a short circuit may occur between the inner electrodes, and if the average thickness of the dielectric layer 130 is greater than about 400 nm, it may be difficult to achieve a thin film capacitor with high capacitance.

[0071] The following is a method for measuring the average thickness of the dielectric layer 130.

[0072] First, the multilayer capacitor 100 is placed in an epoxy resin mixture and cured, and the sides in the L-axis direction and the T-axis direction of the multilayer capacitor 100 are polished to the 1 / 2 point in the W-axis direction, and then placed in a vacuum atmosphere chamber to prepare a cross-sectional sample (hereinafter referred to as the "cross-sectional sample") cut along the L-axis direction and the T-axis direction from the center in the W-axis direction of the multilayer capacitor 100.

[0073] An SEM image or a TEM image is obtained by observing the cross-sectional sample with a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0074] The average thickness of the dielectric layer 130 can be the arithmetic mean of the thicknesses at 10 points spaced apart from a reference point at a predetermined interval in the SEM image or TEM image of the cross-sectional sample, when the center point of the dielectric layer 130 in the length direction (L-axis direction) or width direction (W-axis direction) is used as the reference point.

[0075] The interval between two adjacent points among the 10 points can be adjusted according to the scale of the SEM image. In this case, all 10 points should be located within the dielectric layer 130, and when not all 10 points are located within the dielectric layer 130, the position of the reference point can be changed or the interval between two adjacent points among the 10 points can be adjusted.

[0076] inner electrode The inner electrodes include a first inner electrode 141 and a second inner electrode 142. The first inner electrode 141 and the second inner electrode 142 are electrodes with different polarities, and are alternately arranged to face each other along the T-axis direction with the dielectric layer 130 therebetween, and one end of the first inner electrode 141 and one end of the second inner electrode 142 can be respectively exposed to the third surface and the fourth surface of the multilayer capacitor 100.

[0077] The first inner electrode 141 and the second inner electrode 142 can be electrically insulated from each other by the dielectric layer 130 provided therebetween.

[0078] The ends of the first inner electrode 141 and the second inner electrode 142 that are alternately exposed to the third surface and the fourth surface of the multilayer capacitor 100 can be respectively connected to the first outer electrode 161 and the second outer electrode 162.

[0079] In an embodiment, the inner electrodes 141 and 142 can include an electrode material that can minimize the lattice mismatch rate (%) with the unit cell of the aluminum nitride (AlN)-based compound included in the dielectric layer 130.

[0080] The AlN-based compound included in the dielectric layer 130 has a hexagonal close-packed (HCP) crystal structure, has a (0002) crystal plane perpendicular to the c-axis, and can grow on the inner electrodes 141 and 142.

[0081] Here, for the inner electrodes 141 and 142, a material that can minimize the lattice mismatch rate with the unit cell of the AlN-based compound having a hexagonal close-packed (HCP) crystal structure and a (0002) crystal plane can be used. When such a material is used as the inner electrode material, the crystal orientation of the dielectric layer 130 can be improved, and the leakage current of the capacitor can be reduced.

[0082] Figure 5 is a schematic diagram schematically showing the crystal structure and crystal plane of the inner electrode material according to an embodiment.

[0083] Referring to Figure 5 (a) to Figure 5 (c) of, with respect to an AlN-based dielectric material having an HCP (0002) crystal structure, when the inner electrode material has a body-centered cubic (BCC) crystal structure, it can be confirmed that when it has a (110) crystal plane, a preferred crystal orientation is formed.

[0084] In addition, when the inner electrode material has a hexagonal close-packed (HCP) crystal structure, it can be confirmed that when it has a (0002) crystal plane, a preferred crystal orientation is formed.

[0085] In addition, when the inner electrode material has a face-centered cubic (FCC) crystal structure, it can be confirmed that when it has a (111) crystal plane, a preferred crystal orientation can be formed.

[0086] When a preferred crystal orientation is formed, the lattice mismatch rate with the dielectric layer material can be within 20%, enabling the dielectric layer 130 to grow in a semi-epitaxial manner.

[0087] In an embodiment, the first inner electrode 141 and the second inner electrode 142 may include a conductive metal, and the conductive metal may include Mo, W, Ru, Ti, Pt, Al, or a combination thereof. For example, the types of conductive metals included in the first inner electrode 141 and the second inner electrode 142 may be different.

[0088] For example, the first inner electrode 141 and the second inner electrode 142 may include a conductive metal having a BCC crystal structure and a (110) crystal plane, a conductive metal having an HCP crystal structure and a (0002) crystal plane, a conductive metal having an FCC crystal structure and a (111) crystal plane, or a combination thereof.

[0089] As a specific example, the conductive metal having a BCC crystal structure and a (110) crystal plane may include Mo or W.

[0090] As a specific example, the conductive metal having an HCP crystal structure and a (0002) crystal plane may include Ru or Ti.

[0091] As a specific example, the conductive metal having an FCC crystal structure and a (111) crystal plane may include Pt or Al.

[0092] Referring to Figure 2 and Figure 3 , the multilayer capacitor 100 may further include an inner electrode stack 143 located between the base layer 120 and the dielectric layer 130.

[0093] As an example, the inner electrode stack 143 may be an inner electrode located at the bottom of the capacitor body.

[0094] The inner electrode stack 143 may be disposed at the bottom of the capacitor body and between the base layer 120 and the dielectric layer 130.

[0095] The inner electrode stack 143 may be a stack in which the first inner electrode 141 and the second inner electrode 142 are in direct contact. At this time, the types of conductive metals included in the first inner electrode 141 and the second inner electrode 142 may be different.

[0096] The inner electrode stack 143 has the following structure: Electrodes containing two different materials are alternately stacked such that one inner electrode disposed at the bottom of the inner electrode stack 143 can improve the crystal orientation of another inner electrode on the top of the inner electrode stack 143, and if the dielectric layer 130 is disposed on the top of this inner electrode stack, the crystal orientation of the dielectric layer 130 can be further improved.

[0097] For example, the inner electrodes 141 and 142 constituting the inner electrode stack 143 may include Mo, W, Ru, Ti, Pt, Al, or a combination thereof, but the first inner electrode 141 and the second inner electrode 142 may include different types of conductive metals.

[0098] Specifically, the inner electrode stack 143 may include, for example, a Mo (bottom) / Ti (top) stack or a Ti (bottom) / Mo (top) stack. The inner electrodes and the inner electrode stack according to the embodiment include non-magnetic electrode materials instead of magnetic Ni electrodes, and thus have the advantages of reducing the magnetic flux density and decreasing the equivalent series inductance (ESL) of the capacitor. For example, the average thickness of the inner electrodes 141 and 142 may be greater than or equal to about 20 nm, greater than or equal to about 50 nm, greater than or equal to about 100 nm, or greater than or equal to about 150 nm, and less than or equal to about 400 nm or less than or equal to about 300 nm.

[0099] For example, the average thickness of the inner electrode stack 143 may be greater than or equal to about 50 nm, greater than or equal to about 100 nm, or greater than or equal to about 150 nm, and less than or equal to about 500 nm, less than or equal to about 400 nm, or less than or equal to about 300 nm.

[0100] The average thickness of the inner electrodes 141 and 142 or the inner electrode stack 143 can be measured by the following method.

[0101] The average thickness of the inner electrodes 141 and 142 or the inner electrode stack 143 may be the arithmetic mean of the thicknesses at 10 points spaced apart from the reference point at a predetermined interval in the SEM image or TEM image of the cross-sectional sample when the center points of the inner electrodes 141 and 142 or the inner electrode stack 143 in the length direction (L-axis direction) or the width direction (W-axis direction) are used as the reference points.

[0102] The interval between two adjacent ones of the 10 points can be adjusted according to the scale of the SEM image. In this case, all 10 points should be located within the inner electrodes 141 and 142 or the inner electrode stack 143, and when not all 10 points are located within the inner electrodes 141 and 142 or the inner electrode stack 143, the position of the reference point can be changed or the interval between two adjacent ones of the 10 points can be adjusted.

[0103] seed layer Referring to Figure 4 , the multilayer capacitor 100 according to the embodiment may further include a seed layer 170 located between the base layer 120 and the capacitor body.

[0104] The multilayer capacitor 100 according to another embodiment may further include a seed layer 170 located between the base layer 120 and the inner electrode stack 143.

[0105] The seed layer 170 may be provided at the bottom of the inner electrodes 141 and 142 or the inner electrode stack 143 and serve as a seed for forming the inner electrodes.

[0106] If the seed layer 170 is further included, the crystal orientation of the inner electrodes 141 and 142 provided on the seed layer 170 can be improved, and if the dielectric layer 130 is provided on the inner electrodes 141 and 142, the crystal orientation of the dielectric layer 130 can be further improved.

[0107] For example, the seed layer 170 may include the same compound as the aforementioned dielectric layer 130, and specifically, an aluminum nitride (AlN)-based compound serving as a dielectric, where the aluminum nitride (AlN)-based compound may include AlN, an AlN compound doped with Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, La, Ni, Co, Mn, Cr, V, Zn, Re, or a combination thereof, or a combination of them.

[0108] The average thickness of the seed layer 170 may be greater than or equal to about 10 nm, greater than or equal to about 20 nm, or greater than or equal to about 40 nm, and less than or equal to about 100 nm, less than or equal to about 80 nm, or less than or equal to about 60 nm.

[0109] The method for measuring the average thickness of the seed layer 170 may be the same as the method for measuring the average thickness of the dielectric layer 130 or the inner electrodes 141 and 142 or the inner electrode stack 143.

[0110] outer electrode The first and second external electrodes 161 and 162 are supplied with voltages having different polarities and are electrically connected to exposed portions of the first and second internal electrodes 141 and 142 , respectively.

[0111] According to the above configuration, if a predetermined voltage is applied to the first and second external electrodes 161 and 162, charges are accumulated between the first and second internal electrodes 141 and 142 facing each other. Here, the multilayer capacitor 100 may have a capacitance proportional to an area in which the first and second internal electrodes 141 and 142 overlap each other in the T-axis direction in the active region.

[0112] For example, the first external electrode 161 and the second external electrode 162 may further include: a sintered metal layer; a conductive resin layer disposed to cover the sintered metal layer; and a plating layer disposed to cover the conductive resin layer, respectively.

[0113] The sintered metal layer may include conductive metal and glass.

[0114] As an example, the sintered metal layer may include at least one of copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof as a conductive metal, for example, the conductive metal including copper (Cu) may mean that the conductive metal includes a copper (Cu) element or a copper (Cu) alloy. When the conductive metal includes copper, a metal other than copper may be included in an amount of about 5 mol parts or less based on 100 mol parts of copper.

[0115] As an example, the sintered metal layer may include a composition including an oxide as glass, and may include, for example, one or more selected from silicon oxide, boron oxide, aluminum oxide, transition metal oxide, alkali metal oxide, and alkaline earth metal oxide. The transition metal may be selected from zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni), the alkali metal may be selected from lithium (Li), sodium (Na), and potassium (K), and the alkaline earth metal may be one or more selected from magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0116] Alternatively, the conductive resin layer is formed on the sintered metal layer, for example, may be formed to completely cover the sintered metal layer. In addition, the first and second external electrodes 161 and 162 may not include the sintered metal layer.

[0117] The conductive resin layer can extend to the first and second surfaces and / or the fifth and sixth surfaces of the multilayer capacitor 100, and the length of the region (i.e., the belt portion) where the conductive resin layer extends to the first and second surfaces and / or the fifth and sixth surfaces of the multilayer capacitor 100 can be longer than the length of the region (i.e., the belt portion) where the sintered metal layer extends to the first and second surfaces and / or the fifth and sixth surfaces of the multilayer capacitor 100. In other words, the conductive resin layer can be formed on the sintered metal layer and can be formed to completely cover the sintered metal layer.

[0118] The conductive resin layer includes a resin and a conductive metal.

[0119] There is no particular limitation on the resin included in the conductive resin layer as long as it has adhesiveness and impact absorbency and can be mixed with the conductive metal powder to form a paste, and it can include, for example, phenolic resin, acrylic resin, silicone resin, epoxy resin, or polyimide resin.

[0120] The conductive metal included in the conductive resin layer is used to electrically connect the first internal electrode 141 and the second internal electrode 142 or the sintered metal layer to the plating layer described below.

[0121] The conductive metal included in the conductive resin layer can have a spherical shape, a flake shape, or a combination thereof. In other words, the conductive metal can be formed only in a flake shape, or can be formed only in a spherical shape, or can be in the form of a mixture of a flake shape and a spherical shape.

[0122] Here, the spherical shape can include a shape that is not completely spherical, and can include, for example, a shape in which the ratio of the length of the major axis to the length of the minor axis (major axis / minor axis) is less than or equal to about 1.45. The flake shape refers to a flat and elongated shape and is not particularly limited, but for example, the ratio of the length of the major axis to the length of the minor axis (major axis / minor axis) can be greater than or equal to about 1.95.

[0123] The first external electrode 161 and the second external electrode 162 can also include a plating layer provided outside the conductive resin layer.

[0124] The plating layer can include nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), or lead (Pb) that can be included individually, or their alloys. As an example, each plating layer can be a nickel (Ni) plating layer or a tin (Sn) plating layer, or can be in the form of a nickel (Ni) plating layer and a tin (Sn) plating layer stacked in sequence, or can be in the form of a tin (Sn) plating layer, a (Ni) plating layer, and a tin (Sn) plating layer stacked in sequence. Optionally, each plating layer can include multiple nickel (Ni) plating layers and / or multiple tin (Sn) plating layers.

[0125] The coating layer can improve the mountability to a substrate, structural reliability, external durability, heat resistance, and equivalent series resistance (ESR) of the multilayer capacitor 100.

[0126] Method for manufacturing a multilayer capacitor A method of manufacturing a multilayer capacitor according to an embodiment includes: (1) depositing a base layer on a substrate; (2) depositing an electrode-dielectric layer stack in which a first internal electrode, a dielectric layer, and a second internal electrode are alternately deposited on the base layer; (3) grooving the electrode-dielectric layer stack through a dry slope etching process; (4) wet-etching the second internal electrode and also wet-etching the first internal electrode; (5) depositing a side covering region in a cavity formed by wet-etching; (6) filling an insulating material at the top of the electrode-dielectric layer stack to form a covering region to manufacture a capacitor stack; and (7) forming an external electrode at the outside of the capacitor stack.

[0127] For example, after depositing the base layer on the substrate and before depositing the electrode-dielectric layer stack, a seed layer may also be deposited.

[0128] Figure 8 is a schematic diagram schematically showing a multilayer capacitor manufactured by a method for manufacturing a multilayer capacitor according to an embodiment. Figure 9 is a schematic diagram schematically showing a multilayer capacitor manufactured by a method for manufacturing a multilayer capacitor according to another embodiment.

[0129] Hereinafter, reference will be made to Figure 8 and Figure 9 to describe each manufacturing method.

[0130] First, when depositing the base layer on the substrate, a sputtering process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an evaporation process, or the like may be used.

[0131] The sputtering process may include a magnetron sputtering (e.g., radio frequency (RF) magnetron sputtering) process, a laser sputtering process, a direct current (DC) sputtering process, or the like.

[0132] Subsequently, the deposition of the electrode-dielectric layer stack is shown, in which the first internal electrode, the dielectric layer, and the second internal electrode are alternately deposited on the base layer.

[0133] For example, the electrode-dielectric layer stack may be formed by sequentially depositing the first internal electrode, the dielectric layer, the second internal electrode, and the dielectric layer on the base layer multiple times. For example, the internal electrode may be directly disposed on the base layer. For example, the dielectric layer may be disposed at the top of the electrode-dielectric layer stack.

[0134] The method of depositing the inner electrode and the dielectric layer may be the same as the method of depositing the base layer, and is mainly carried out by a sputtering process.

[0135] The step of grooving the electrode-dielectric layer stack by a dry slope etching process may etch away the electrode-dielectric layer stack except for the substrate. Here, the base layer may serve to protect the substrate from the dry slope etching.

[0136] Referring to Figure 9 , when observed in a cross-section obtained by cutting a multilayer capacitor along the L-axis direction and the T-axis direction at the center in the W-axis direction, the electrode-dielectric layer stack grooved by the dry slope etching process may have a trapezoidal shape that widens from top to bottom. For example, the trapezoidal-shaped electrode-dielectric layer stack may have a lower inclination angle of less than or equal to about 80° (e.g., less than or equal to about 70°, less than or equal to about 60°, less than or equal to about 50°, or less than or equal to about 45°). If the trapezoidal-shaped electrode-dielectric layer stack is included, the capacitor body can be easily connected to the outer electrode.

[0137] The steps of wet etching the second inner electrode and wet etching the first inner electrode may form a cavity by wet etching the sides of the inner electrode. Subsequently, the cavity is filled with an insulating material to form a side coverage area.

[0138] For example, when wet etching the first inner electrode, the second inner electrode cannot be etched, and when wet etching the second inner electrode, the first inner electrode cannot be etched. Therefore, the types of conductive metals included in the first inner electrode and the second inner electrode may be different from each other.

[0139] Therefore, the multilayer capacitor according to the embodiment has the advantages of being able to selectively etch the inner electrode, having high conductivity of the inner electrode material, and relatively low cost.

[0140] The step of depositing the side coverage area in the cavity formed by wet etching may include the step of filling the cavity with an insulating material.

[0141] The method of filling the cavity with an insulating material may include, for example, an atomic layer deposition (ALD) process.

[0142] The insulating material may include silicon dioxide (SiO2), silicon nitride (SiN, Si3N4), aluminum nitride (AlN), aluminum oxide (Al2O3), or a combination thereof.

[0143] Existing multilayer capacitors have the disadvantage of increasing the current path due to the thick coverage area. However, in the case of the thin film capacitor according to the present disclosure, the insulating material is deposited as a thin film on the effective area to form the side coverage area, so the current path can be reduced. Therefore, the ESL can be reduced by reducing the thickness of the side coverage area and reducing the current path.

[0144] Subsequently, the step of forming a cover region by filling an insulating material at the top of the electrode-dielectric layer stack to form a capacitor stack may include the step of filling an insulating material in a part of the top of the electrode-dielectric layer stack.

[0145] The step of filling an insulating material in a part of the top of the electrode-dielectric layer stack may be performed by using a lift-off process.

[0146] The insulating material may include silicon dioxide (SiO2), silicon nitride (SiN, Si3N4), aluminum nitride (AlN), aluminum oxide (Al2O3), or a combination thereof.

[0147] The step of forming an external electrode at the outside of the capacitor stack may include the step of depositing a conductive metal on the outside of the capacitor stack.

[0148] Refer to Figure 8 and Figure 9 , the deposited external electrode may be connected to the side of the upper cover region and formed along the outside of the capacitor body on the top of the base layer.

[0149] The type of the conductive metal may be the same as that described above for the external electrode.

[0150] The method of depositing a conductive metal at the outside of the capacitor stack may include a sputtering (e.g., RF magnetron sputtering) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an evaporation process, etc.

[0151] The sputtering process may include magnetron sputtering (e.g., RF magnetron sputtering), laser sputtering, direct current (DC) sputtering, etc.

[0152] Hereinafter, specific examples of the present disclosure will be presented. However, the following examples are only intended to specifically illustrate or describe the present disclosure and should not be construed as limiting the scope of the present disclosure.

[0153] (Reference Example) Reference Example 1: Evaluation of elements dopable into AlN Table 1 shows whether each doping element can replace the Al site of AlN and the atomic radius of the doping element.

[0154] (Table 1)

[0155] If the doping element can replace the Al site of AlN, it is marked as O, and if the doping element cannot replace the Al site of AlN, it is marked as X.

[0156] Referring to Table 1, Ni, Co, Mn, Cr, V, Zn, Re, Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, and La can substitute for the Al sites in AlN. Among these elements, the atomic radii of Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, and La are greater than that of Al (1.43 Å). And among these elements with atomic radii greater than that of Al (1.43 Å), the doping elements with atomic radii greater than 1.60 Å are Sc, Er, Y, and La.

[0157] Reference Example 2: Evaluation of dielectric constant according to the content of doped elements The dielectric constant of the AlScN compound prepared by doping AlN with Sc element was measured according to the Sc content (at%), and the results are shown in Table 2 and Figure 6 are shown below.

[0158] (Table 2)

[0159] Referring to Table 2 and Figure 6 , as the content of doped Sc increases, the AlN-based compound has a higher dielectric constant.

[0160] Reference Example 3: Evaluation of inner electrode material Table 3 shows the crystal characteristics of the inner electrode materials that can be used with the AlN dielectric having an HCP crystal structure and a (0002) crystal plane, as well as the lattice mismatch rate (%) between the inner electrode materials and the AlN dielectric.

[0161] (Table 3)

[0162] If a preferred crystal orientation is formed, it is marked as O.

[0163] Referring to Table 3, if Mo and W with a BCC crystal structure ((110) crystal plane), Ru and Ti with an HCP crystal structure ((0002) crystal plane), or Pt and Al with an FCC crystal structure ((111) crystal plane) are used as the inner electrode materials, the inner electrode materials and the AlN dielectric exhibit a very low lattice mismatch rate of less than or equal to 20%.

[0164] (Example) Example 1-1 A base layer including SiO2 was deposited on a silicon wafer by sputtering. On the base layer, a seed layer including AlN was deposited by sputtering to a thickness of 50 nm.

[0165] On the seed layer, Mo (200 nm, second inner electrode) / AlN (400 nm, dielectric layer) / Ti (200 nm, first inner electrode) are deposited in sequence multiple times by sputtering, but AlN is deposited as the last layer to form an electrode-dielectric layer stack.

[0166] Subsequently, the electrode-dielectric layer stack is grooved by a dry ramp etching process.

[0167] Then, Mo and Ti are wet-etched in sequence, and Al2O3 is filled in the cavity formed by the wet etching by ALD process. In addition, SiN is filled at the top of the electrode-dielectric layer stack by a lift-off process.

[0168] Subsequently, Cu is deposited on the outside of the electrode-dielectric layer stack by sputtering to form an outer electrode, thereby manufacturing a multilayer capacitor according to Example 1-1.

[0169] Example 1-2 A multilayer capacitor according to Example 1-2 is manufactured in the same manner as Example 1-1, except that Mo (200 nm) / Ti (50 nm) as an inner electrode stack is deposited instead of the second inner electrode directly formed on the seed layer.

[0170] Example 1-3 A multilayer capacitor according to Example 1-3 is manufactured in the same manner as Example 1-1, except that no seed layer is introduced onto the base layer and Ti (50 nm) / Mo (200 nm) as an inner electrode stack is deposited instead of the second inner electrode directly formed on the seed layer.

[0171] Example 1-4 A multilayer capacitor according to Example 1-4 is manufactured in the same manner as Example 1-3, except that a seed layer (50 nm) including AlN is further directly deposited on the base layer and directly under the inner electrode stack.

[0172] (Evaluation Example) Evaluation Example 1: Analysis according to the crystal orientation of the inner electrode The FWHM of each dielectric layer of the multilayer capacitors according to Example 1-1, Example 1-2, Example 1-3, and Example 1-4 is measured, and the results are shown in Table 4.

[0173] (Table 4)

[0174] Referring to Table 4, Examples 1-2 and 1-4 of the internal electrode stack exhibit a lower full width at half maximum (FWHM) of the dielectric layer than Example 1-1 with a single internal electrode, and thus exhibit a relatively better c-axis crystal orientation.

[0175] Alternatively, Example 1-4 including a seed layer exhibits a lower FWHM of the dielectric layer than Example 1-3 without a seed layer, and thus exhibits a relatively better c-axis crystal orientation.

[0176] In addition, Table 5 and Figure 7 show the FWHM of each dielectric layer of the multilayer capacitors of Example 2-1 (without a seed layer) and Example 2-2 (with a seed layer). The only difference between Example 2-1 and Example 2-2 is the presence or absence of an AlN seed layer.

[0177] (Table 5)

[0178] Referring to Table 5 and Figure 7 , the multilayer capacitor including an AlN seed layer according to Example 2-2 exhibits a lower FWHM of the dielectric layer than the multilayer capacitor without an AlN seed layer according to Example 2-1, and thus exhibits a relatively better c-axis crystal orientation.

[0179] Although the present disclosure has been described in connection with presently considered practical exemplary embodiments, it should be understood that the present disclosure is not limited to the disclosed exemplary embodiments. On the contrary, it is intended to cover various modifications and equivalent schemes included within the spirit and scope of the appended claims.

[0180] <Symbol Explanation> 100: Multilayer capacitor 110: Substrate 120: Base layer 130: Dielectric layer 141, 142: First internal electrode and second internal electrode 143: Internal electrode stack 161, 162: First external electrode and second external electrode 170: Seed layer.

Claims

1. A multilayer capacitor comprising: A dielectric layer comprising an aluminum nitride-based compound, The aluminum nitride-based compound includes AlN, a doped AlN compound, or a combination thereof, wherein the doped AlN compound is doped with Ni, Co, Mn, Cr, V, Zn, Re, Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, La, or a combination thereof, The dielectric layer includes dielectric grains, and The crystal orientation of the dielectric grains is a c-axis crystal orientation.

2. The multilayer capacitor according to claim 1, wherein In the doped AlN compound, AlN is doped with Sc, Er, Y, La or a combination thereof.

3. The multilayer capacitor according to claim 1, wherein The content of the doped element in the doped AlN compound is greater than or equal to 1 at % and less than 30 at %.

4. The multilayer capacitor according to claim 1, wherein The aluminum nitride-based compound included in the dielectric layer has an HCP crystal structure and has a (0002) crystal plane.

5. The multilayer capacitor according to claim 1, wherein The average thickness of the dielectric layer is in the range of 20 nm to 400 nm.

6. The multilayer capacitor of claim 1, further comprising: substrate; A base layer, located on the substrate; a capacitor body disposed on the substrate and comprising inner electrodes and dielectric layers arranged alternately; as well as The external electrode is disposed on the base layer and outside the capacitor body.

7. The multilayer capacitor according to claim 6, wherein The inner electrode comprises a first inner electrode and a second inner electrode, The first internal electrode and the second internal electrode include a conductive metal including Mo, W, Ru, Ti, Pt, Al, or a combination thereof, and Conductive metals included in the first and second internal electrodes are different.

8. The multilayer capacitor according to claim 6, wherein The inner electrode includes a conductive metal having a BCC crystal structure and a (110) crystal plane, a conductive metal having a HCP crystal structure and a (0002) crystal plane, a conductive metal having a FCC crystal structure and a (111) crystal plane, or a combination thereof.

9. The multilayer capacitor according to claim 6, wherein The multilayer capacitor also includes an inner electrode stack between the base layer and the dielectric layer.

10. The multilayer capacitor according to claim 6, wherein The inner electrode has an average thickness in a range of 20 nm to 400 nm.

11. The multilayer capacitor of claim 6, further comprising a seed layer between the base layer and the capacitor body.

12. A multilayer capacitor comprising: substrate; A base layer, located on the substrate; a capacitor body disposed on the substrate and comprising inner electrodes and dielectric layers arranged alternately; as well as an external electrode disposed on the substrate and outside the capacitor body, The dielectric layer includes an aluminum nitride-based compound, the aluminum nitride-based compound includes AlN, a doped AlN compound, or a combination thereof, wherein the doped AlN compound is doped with Ni, Co, Mn, Cr, V, Zn, Re, Ta, Nb, Ti, Zr, Mg, Sc, Er, Y, La, or a combination thereof, The dielectric layer includes a plurality of dielectric grains, and the crystal orientation of the dielectric grains is a c-axis crystal orientation. The inner electrode comprises a first inner electrode and a second inner electrode, The first internal electrode and the second internal electrode include a conductive metal including Mo, W, Ru, Ti, Pt, Al, or a combination thereof, and Conductive metals included in the first and second internal electrodes are different.

13. The multilayer capacitor according to claim 12, wherein In the doped AlN compound, AlN is doped with Sc, Er, Y, La or a combination thereof.

14. The multilayer capacitor according to claim 12, wherein: The content of the doped element in the doped AlN compound is greater than or equal to 1 at % and less than 30 at %.

15. The multilayer capacitor according to claim 12, wherein The aluminum nitride-based compound included in the dielectric layer has an HCP crystal structure and has a (0002) crystal plane.

16. The multilayer capacitor according to claim 12, wherein The average thickness of the dielectric layer is in the range of 20 nm to 400 nm.

17. The multilayer capacitor according to claim 12, wherein: The inner electrode includes a conductive metal having a BCC crystal structure and a (110) crystal plane, a conductive metal having a HCP crystal structure and a (0002) crystal plane, a conductive metal having a FCC crystal structure and a (111) crystal plane, or a combination thereof.

18. The multilayer capacitor according to claim 12, wherein The multilayer capacitor also includes an inner electrode stack between the base layer and the dielectric layer.

19. The multilayer capacitor according to claim 12, wherein: The inner electrode has an average thickness in a range of 20 nm to 400 nm.

20. The multilayer capacitor of claim 12, further comprising a seed layer between the base layer and the capacitor body.

21. The multilayer capacitor according to claim 20, wherein The average thickness of the seed layer is in the range of 10 nm to 100 nm.

22. The multilayer capacitor of claim 18, wherein: The inner electrode stack has an average thickness in a range of 50 nm to 500 nm.

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