Preparation method of connection structure for transmitting signals and connection structure

Abstract

The invention provides a preparation method of a connection structure for transmitting signals and the connection structure. The preparation method of the connection structure for transmitting the signal comprises the following steps: sequentially forming a plurality of layers of stacked structures on a first surface and a second surface of a carrier plate to form an intermediate structure; wherein each layer of stacked structure sequentially comprises a metal layer, a first dielectric material layer, a wire layer and a second dielectric material layer in a direction far away from the carrier plate; wherein the wire layer is provided with wires which are arranged at intervals; the distance between every two adjacent wires on the wire layer is smaller than 100 micrometers. Vertically cutting the middle structure to obtain a base structure; and for the basic structure, stripping the multi-layer stacked structures formed on the first surface and the second surface from the carrier plate to obtain the connection structure formed by the multi-layer stacked structures. According to the preparation method of the connection structure for transmitting the signal and the connection structure provided by the invention, the bandwidth is improved, and meanwhile, the interference can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of chip packaging, and particularly to a preparation method and a connection structure for a connection structure for transmitting signals. Background Art

[0002] With the continuous development of modern electronic devices and the increasing demand for multi-functionalization, higher requirements are put forward for aspects such as the performance, connection density, and power consumption of chips. In order to meet these requirements, existing chip technologies need to achieve vertical conduction in order to connect multiple chips, provide signal transmission, and power supply.

[0003] Currently, through-silicon via technology is mainly used to achieve vertical conduction of chips. When using through-silicon vias to achieve vertical conduction, the spacing between the through-silicon vias formed by the etching process is relatively large, resulting in a small density of through-silicon vias per unit area, which is not conducive to improving the overall transmission bandwidth. Summary of the Invention

[0004] In view of this, the present application provides a preparation method and a connection structure for a connection structure for transmitting signals, so as to improve the transmission bandwidth.

[0005] Specifically, the present application is implemented through the following technical solutions:

[0006] The first aspect of the present application provides a preparation method for a connection structure for transmitting signals, and the method includes:

[0007] Form a multi-layer stacked structure on the first surface and the second surface of the carrier board in sequence to form an intermediate structure; wherein, in the direction away from the carrier board, each layer of the stacked structure sequentially includes a metal layer, a first dielectric material layer, a wire layer, and a second dielectric material layer; the wire layer has wires arranged at intervals; the distance between two adjacent wires on the wire layer is less than 100 micrometers;

[0008] Vertically cut the intermediate structure to obtain a plurality of basic structures;

[0009] For each of the basic structures, peel off the multi-layer stacked structure formed on the first surface and the second surface from the carrier board to obtain a connection structure composed of the multi-layer stacked structure.

[0010] Optionally, the forming of the multi-layer stacked structure on the first surface and the second surface of the carrier board in sequence includes:

[0011] Take the first surface and the second surface of the carrier board as the base surfaces, and form a metal layer on the base surfaces;

[0012] Form a first dielectric material layer on the metal layer;

[0013] A wire layer is formed on the first dielectric material layer; wherein, wires are arranged at intervals on the wire layer;

[0014] A second dielectric material layer is formed on the wire layer to form a stacked structure;

[0015] Taking the second dielectric material layer as a base, the step of forming a metal layer on the base surface is performed again until a multi-layer stacked structure is formed on the first surface and the second surface.

[0016] Optionally, the distance between two adjacent wires on the wire layer is less than 10 microns.

[0017] Optionally, the metal layer is made of any one of the following materials: copper and aluminum.

[0018] The second aspect of the present application provides a connection structure for transmitting signals, and the connection structure is prepared by using any one of the methods provided in the first aspect of the present application; the connection structure includes a multi-layer stacked structure; each layer of the stacked structure sequentially includes a metal layer, a first dielectric material layer, a wire layer, and a second dielectric material layer; wherein, the wire layer has wires arranged at intervals; the distance between two adjacent wires on the wire layer is less than 100 microns.

[0019] Optionally, the distance between two adjacent wires on the wire layer is less than 10 microns.

[0020] Optionally, the metal layer is made of any one of the following materials: copper and aluminum.

[0021] The third aspect of the present application provides a chip packaging structure, characterized in that the chip packaging structure includes a chip and at least one of the connection structures; wherein, the chip transmits signals through the connection structure.

[0022] The present application provides a method for preparing a connection structure for transmitting signals, wherein a multilayer stacking structure is sequentially formed on a first surface and a second surface of a carrier to form an intermediate structure; wherein, in a direction away from the carrier, each layer of the stacking structure sequentially includes a metal layer, a first dielectric material layer, a wire layer, and a second dielectric material layer; the wire layer has wires arranged at intervals; the spacing between two adjacent wires on the wire layer is less than 100 microns, and further, the intermediate structure is vertically cut to obtain a plurality of basic structures, and then, for each of the basic structures, the multilayer stacking structures formed on the first surface and the second surface are peeled off from the carrier to obtain a connection structure composed of the multilayer stacking structures. In this way, in the process of forming the intermediate structure, a stacked structure consisting of a metal layer, a first dielectric material layer, a wire layer, and a second dielectric material layer is sequentially formed on the first surface and the second surface of the carrier. When preparing the wire layer, since the wire is formed based on lateral etching and electroplating, the spacing between the wires can be much smaller than the existing vertical etching and electroplating, and the length of the wire can also be much larger than the length of the wire formed by the prior art (since this method is not limited by the aspect ratio, the length of the formed wire is longer). In this way, the density of the wire is greater, the channels for transmitting signals are more, and the bandwidth is higher. In addition, in each layer of the stacked structure, by setting a metal layer, each layer of the stacked structure can be isolated by the metal layer, and the wires between layers are isolated by the metal layer, so that the interference between signal lines is minimized, and while improving the bandwidth, the interference between the wires between layers and the interference between adjacent wires in the same layer can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A flow chart of Embodiment 1 of a method for preparing a connection structure for transmitting signals provided in the present application;

[0024] Figure 2 A cross-sectional view of an intermediate structure shown in an exemplary embodiment of the present application;

[0025] Figure 3 This is a schematic diagram showing a metal layer formation implementation according to an exemplary embodiment of the present application;

[0026] Figure 4 A schematic diagram showing a first dielectric material layer according to an exemplary embodiment of the present application;

[0027] Figure 5 This is a schematic diagram showing a method for forming a conductive line layer according to an exemplary embodiment of the present application;

[0028] Figure 6 A schematic diagram showing a second dielectric material layer formed according to an exemplary embodiment of the present application;

[0029] Figure 7Planar view of the intermediate structure shown in an exemplary embodiment of the present application;

[0030] Figure 8 Cross-sectional view of the connection structure shown in an exemplary embodiment of the present application;

[0031] Figure 9 Stereogram of the connection structure shown in an exemplary embodiment of the present application;

[0032] Figure 10 Schematic diagram of the chip packaging structure shown in an exemplary embodiment of the present application;

[0033] Figure 11 Schematic diagram of connecting the connection structure to the substrate shown in an exemplary embodiment of the present application;

[0034] Figure 12 Schematic diagram of the implementation principle of connecting the chip to the substrate shown in an exemplary embodiment of the present application;

[0035] Figure 13 Schematic diagram of the chip packaging structure of another exemplary embodiment provided by the present application;

[0036] Figure 14 Schematic diagram of connecting the connection structure to the carrier shown in an exemplary embodiment of the present application;

[0037] Figure 15 Schematic diagram of the implementation principle of connecting the chip to the carrier shown in an exemplary embodiment of the present application;

[0038] Figure 16 Schematic diagram of the first intermediate chip frame shown in an exemplary embodiment of the present application;

[0039] Figure 17 Schematic diagram of preparing the first redistribution wire layer shown in an exemplary embodiment of the present application;

[0040] Figure 18 Schematic diagram of the second intermediate chip frame shown in an exemplary embodiment of the present application;

[0041] Figure 19 Schematic diagram of preparing the second redistribution wire layer shown in an exemplary embodiment of the present application;

[0042] Figure 20 Schematic diagram of flipping the chip onto the second redistribution wire layer shown in an exemplary embodiment of the present application;

[0043] Figure 21 Schematic diagram of the second chip frame shown in an exemplary embodiment of the present application. Description of the drawings:

[0045] 100: Intermediate structure;

[0046] 200: First chip frame structure;

[0047] 300: Second chip frame structure;

[0048] 301: First redistribution wire layer;

[0049] 302: Third connection structure;

[0050] 303: Fourth connection structure;

[0051] 304: Third chip;

[0052] 305: Second redistribution wire layer;

[0053] 306: Fourth chip;

[0054] 1: Carrier board;

[0055] 2: Multilayer stacked structure on the first surface of the carrier board;

[0056] 3: Multilayer stacked structure on the second surface of the carrier board;

[0057] 4: Stacked structure;

[0058] 41: Metal layer;

[0059] 42: First dielectric material layer;

[0060] 43: Wire layer;

[0061] 431: Wire;

[0062] 44: Second dielectric material layer;

[0063] 5: First heat sink cover;

[0064] 6: Substrate;

[0065] 7: First connection structure;

[0066] 8: Second connection structure;

[0067] 9: First chip;

[0068] 10: Second chip;

[0069] 11: Second heat sink cover. Detailed implementation mode

[0070] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0071] The terms used in the present application are for the purpose of describing particular embodiments only and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0072] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0073] The present application provides a preparation method and a connection structure for a connection structure for transmitting signals, so as to improve the transmission bandwidth.

[0074] The present application provides a method for preparing a connection structure for transmitting signals, wherein a multilayer stacking structure is sequentially formed on a first surface and a second surface of a carrier to form an intermediate structure; wherein, in a direction away from the carrier, each layer of the stacking structure sequentially includes a metal layer, a first dielectric material layer, a wire layer, and a second dielectric material layer; the wire layer has wires arranged at intervals; the spacing between two adjacent wires on the wire layer is less than 100 microns, and further, the intermediate structure is vertically cut to obtain a plurality of basic structures, and then, for each of the basic structures, the multilayer stacking structures formed on the first surface and the second surface are peeled off from the carrier to obtain a connection structure composed of the multilayer stacking structures. In this way, in the process of forming the intermediate structure, a stacked structure consisting of a metal layer, a first dielectric material layer, a wire layer, and a second dielectric material layer is sequentially formed on the first surface and the second surface of the carrier. When preparing the wire layer, since the wire is formed based on lateral etching and electroplating, the spacing between the wires can be much smaller than the existing vertical etching and electroplating, and the length of the wire can also be much larger than the length of the wire formed by the prior art (since this method is not limited by the aspect ratio, the length of the formed wire is longer). In this way, the density of the wire is greater, the channels for transmitting signals are more, and the bandwidth is higher. In addition, in each layer of the stacked structure, by setting a metal layer, each layer of the stacked structure can be isolated by the metal layer, and the wires between layers are isolated by the metal layer, so that the interference between signal lines is minimized, and while improving the bandwidth, the interference between the wires between layers and the interference between adjacent wires in the same layer can be avoided.

[0075] Figure 1 This is a flow chart of Embodiment 1 of the method for preparing a connection structure for transmitting signals provided in this application. Figure 1 The method for preparing the connection structure for transmitting signals provided in this embodiment may include:

[0076] S101. Form a multi-layer stacking structure on the first surface and the second surface of the carrier in sequence to form an intermediate structure; wherein, in the direction away from the carrier, each layer of the stacking structure includes a metal layer, a first dielectric material layer, a wire layer, and a second dielectric material layer in sequence; the wire layer has wires arranged at intervals; and the spacing between two adjacent wires on the wire layer is less than 100 microns.

[0077] Figure 2 This is a cross-sectional view of an intermediate structure shown in an exemplary embodiment of the present application. Figure 2 The intermediate structure 100 includes a carrier board 1 , a multi-layer stacking structure 2 formed on a first surface of the carrier board 1 , and a multi-layer stacking structure 3 formed on a second surface of the carrier board 1 .

[0078] Specifically, the carrier board 1 can be a peelable carrier board, which can be a flat carrier board to form a stacked structure 4 thereon. In addition, the shape of the carrier board 1 is set according to actual needs and is not limited in this embodiment. For example, in one possible implementation, the carrier board 1 can be a cuboid. For another example, in another possible implementation, the carrier board 1 can be a cube.

[0079] The size of the carrier board 1 is set according to actual needs and is not limited in this embodiment. For example, the size of the carrier board 1 can be determined according to the usage scenario of the connection structure.

[0080] Optionally, in one possible implementation, the carrier board 1 can be made of any of the following materials: FR4 (flame-retardant type-4 woven glass-reinforced epoxy) glass, ceramics, etc.

[0081] It should be noted that the multi-layer stacked structure 2 formed on the first surface of the carrier board 1 and the multi-layer stacked structure 3 formed on the second surface of the carrier board 1 can be symmetric or asymmetric and are not limited in this embodiment.

[0082] Furthermore, the number of stacked structures 4 included in the multi-layer stacked structure is set according to actual needs and is not limited in this embodiment. For example, in Figure 2 the example shown, the number of stacked structures 4 included in the multi-layer stacked structure is 4 layers.

[0083] Please continue to refer to Figure 2 , in the direction away from the carrier board 1, each layer of the stacked structure 4 sequentially includes a metal layer 41, a first dielectric material layer 42, a wire layer 42, and a second dielectric material layer 44.

[0084] Optionally, in one possible implementation, the metal layer 41 is made of any of the following materials: copper.

[0085] Furthermore, the thickness of the metal layer 41 is less than 30 microns. For example, in one embodiment, the thickness of the metal layer can be 5 to 25 microns.

[0086] It should be noted that by providing the metal layer 41, each layer of the stacked structure can be isolated by the metal layer 41, and the wires between layers are isolated by the metal layer 41, minimizing the interference between signal lines. While increasing the bandwidth, interference between inter-layer wires and interference between adjacent wires on the same layer can be avoided.

[0087] Further, the function of the first dielectric material layer 42 is to isolate the wire layer 43, prevent current leakage and interference, and it can provide insulation performance to ensure that the electrical signal will not be interfered or radiated by electromagnetic waves. It can be formed by selecting a dielectric material. For example, the material of the first dielectric material layer 42 can be glass fiber-reinforced epoxy resin (FCR-4), Ajinomoto build-up film (ABF), or polytetrafluoroethylene (PTFE), etc.

[0088] The thickness of the first dielectric material layer 42 is set according to actual needs and is not limited in this embodiment.

[0089] Further, the wire layer 43 has wires 431 arranged at intervals, and the wires 431 are spaced apart by a dielectric material. It should be noted that in this embodiment, the distance between two adjacent wires 431 on the wire layer 43 is less than 100 microns.

[0090] The thickness of the wire layer 43 is set according to actual needs and is not limited in this embodiment.

[0091] Similar to the first dielectric material layer 42, the function of the second dielectric material layer 44 is to isolate the wire layer, prevent current leakage and interference, and it can provide insulation performance to ensure that the electrical signal will not be interfered or radiated by electromagnetic waves. It can be formed by selecting a dielectric material. For example, the material of the second dielectric material layer 44 can be glass fiber-reinforced epoxy resin (FR-4), Ajinomoto build-up film (ABF), or polytetrafluoroethylene (PTFE), etc., and is not limited in this embodiment.

[0092] It should be noted that the material used for the second dielectric material layer 44 can be the same as or different from the material used for the first dielectric material layer 42, and is not limited in this embodiment.

[0093] In addition, the thickness of the second dielectric material layer 44 is set according to actual needs and is not limited in this embodiment.

[0094] Optionally, in a possible implementation manner, the process of sequentially forming a multi-layer stacked structure on the first surface and the second surface of the carrier board 1 may include:

[0095] (1) Taking the first surface and the second surface of the carrier board as the base surfaces, a metal layer is formed on the base surfaces.

[0096] Figure 3 This is the schematic diagram of the implementation of forming a metal layer shown in an exemplary embodiment of the present application. Please refer to Figure 3 , in a possible implementation manner, the metal layer 41 can be formed on the first surface and the second surface of the carrier board 1 by a deposition technique.

[0097] For example, in one embodiment, the metal layer 41 can be formed by electroplating technology. For another example, the metal layer 41 can be formed by physical deposition method.

[0098] Specifically, when forming the metal layer 41, relevant parameters can be controlled to achieve the purpose of controlling the thickness of the metal layer 41.

[0099] It should be noted that the metal layer 41 isolates each stacked structure layer and isolates the wires between layers, so that noise is consumed in the metal layer 41. While increasing the bandwidth, it can avoid interference between interlayer wires and interference between adjacent wires on the same layer.

[0100] (2) Form a first dielectric material layer on the metal layer.

[0101] Figure 4 The implementation schematic diagram of forming the first dielectric material layer shown in an exemplary embodiment of this application is as follows. Please refer to Figure 4 , and the first dielectric material layer 42 can be formed by electroplating or physical deposition methods.

[0102] (3) Form a wire layer on the first dielectric material layer; wherein, the wire layer has wires arranged at intervals.

[0103] Figure 5 The implementation schematic diagram of forming the wire layer shown in an exemplary embodiment of this application is as follows. Refer to Figure 5 , first, through lateral etching and electroplating preparation, grooves-like patterns arranged at intervals for forming the wires 431 are etched on the first dielectric material layer 42, and then a metal material is filled in the patterns to form the wires 431 on the patterns.

[0104] It should be noted that the distance between two adjacent wires 431 is less than 100 microns to increase the transmission bandwidth. Specifically, the specific value of the distance between two adjacent wires 431 is set according to actual needs and is not limited in this embodiment. For example, the distance between two adjacent wires 431 can be set according to the bandwidth requirement. When a larger bandwidth is needed, the distance between two adjacent wires 431 can be set smaller. For example, in one embodiment, the distance between two adjacent wires 431 can be 50 microns.

[0105] Preferably, the distance between two adjacent wires 431 on the wire layer 4 is less than 10 microns. Specifically, when the distance between two adjacent wires 431 is set to be less than 10 microns, the bandwidth can be better improved, that is, the smaller the distance, the greater the distribution density of the wires 431, the more the number of signal transmission channels, and the higher the bandwidth.

[0106] Further, the size of the wire 431 is also set according to actual needs and is not limited in this embodiment. In the method provided in this embodiment, since the wire layer is formed by lateral etching, the size of the wire can be made very small, and on the basis of the very small wire size, there is no problem of virtual breakage (in the prior art, when forming a wire by vertical drilling, in order to avoid the problem of virtual breakage, the via hole size is generally relatively large. In other words, when forming a wire by vertical drilling, if the size of the via hole is small, it is difficult to inject metal into it to form a wire).

[0107] (4) Form a second dielectric material layer on the wire layer to form a stacked structure.

[0108] Figure 6 The schematic diagram of forming the second dielectric material layer shown in an exemplary embodiment of the present application. Please refer to Figure 6 and a second dielectric material layer 44 can be formed on the wire layer by electroplating or physical deposition to form a stacked structure 4.

[0109] (5) Taking the second dielectric material layer as a basis, perform the step of forming a metal layer on the basis surface again until a multi-layer stacked structure is formed on the first surface and the second surface.

[0110] Specifically, please continue to refer to Figure 2 and the second dielectric material layer 44 can continue to be used as a basis to perform the step of forming a metal layer 41 on the basis surface again until a multi-layer stacked structure is formed on the first surface and the second surface.

[0111] S102. Vertically cut the intermediate structure to obtain a plurality of basic structures.

[0112] Figure 7 The plan view of the intermediate structure shown in an exemplary embodiment of the present application. Please refer to Figure 7 , after the intermediate structure 100 is formed, according to actual needs, along the pre-cut line ( Figure 7 the dotted line shown), the intermediate structure 100 is vertically cut to obtain a plurality of basic structures.

[0113] In other words, the intermediate structure can be vertically cut according to the size required in actuality to obtain the basic structure with the required size. The morphology and layer structure of the basic structure are the same as those of the intermediate structure, only the size is different from that of the intermediate structure.

[0114] S103. For each of the basic structures, peel off the multi-layer stacked structure formed on the first surface and the second surface from the carrier plate to obtain a connection structure composed of the multi-layer stacked structure.

[0115] Figure 8A cross-sectional view of the connection structure shown in an exemplary embodiment of the present application. Please refer to Figure 8 , the connection structure is composed of a multi-layer stacked structure.

[0116] Refer to Figure 2 . For each basic structure, after peeling off the multi-layer stacked structure formed on the first surface and the multi-layer stacked structure formed on the second surface from the carrier plate, two connection structures will be formed.

[0117] It should be noted that in practical applications, the peeled connection structure needs to be vertically rotated by 90 degrees for application in actual scenarios. Figure 9 A perspective view of the connection structure shown in an exemplary embodiment of the present application (the perspective view after being vertically rotated by 90°). Please refer to Figure 9 . After peeling off the multi-layer stacked structure from the carrier plate 1, a connection structure composed of the multi-layer stacked structure is obtained. Further, after vertically rotating this connection structure by 90°, the connection structure shown in Figure 9 can be obtained, and subsequently, this connection structure can be used to transmit signals.

[0118] The preparation method of the connection structure for transmitting signals provided in this embodiment forms an intermediate structure by sequentially forming a multi-layer stacked structure on the first surface and the second surface of the carrier plate; wherein, in the direction away from the carrier plate, each layer of the stacked structure sequentially includes a metal layer, a first dielectric material layer, a wire layer, and a second dielectric material layer; the wire layer has wires arranged at intervals; the distance between two adjacent wires on the wire layer is less than 100 microns. Further, the intermediate structure is vertically cut to obtain a plurality of basic structures. Immediately afterwards, for each basic structure, the multi-layer stacked structure formed on the first surface and the second surface is peeled off from the carrier plate to obtain a connection structure composed of the multi-layer stacked structure. In this way, during the process of forming the intermediate structure, a stacked structure composed of a metal layer, a first dielectric material layer, a wire layer, and a second dielectric material layer is sequentially formed on the first surface and the second surface of the carrier plate. When preparing the wire layer, since the wires are formed based on lateral etching and electroplating, the distance between the wires can be made much smaller than that of the existing vertical etching and electroplating, and the length of the wires can also be much longer than that of the wires formed by the prior art (since this method is not limited by the aspect ratio, the length of the wires formed is longer). In this way, the density of the wires is greater, the number of signal transmission channels is more, and the bandwidth is higher. In addition, in each layer of the stacked structure, by setting the metal layer, each layer of the stacked structure can be isolated by the metal layer, and the wires between layers are isolated by the metal layer, so that the interference between signal lines is minimized. While increasing the bandwidth, the interference between wires between layers and the interference between adjacent wires on the same layer can be avoided.

[0119] Corresponding to the foregoing method for preparing a connection structure for transmitting signals, the present application also provides a connection structure for transmitting signals. The connection structure provided by the present application will be introduced below:

[0120] Please refer to both Figure 2 and Figure 8 . The connection structure provided by the present application includes a multi-layer stacked structure; each layer of the stacked structure sequentially includes a metal layer 41, a first dielectric material layer 42, a wire layer 43, and a second dielectric material layer 44; wherein, the wire layer 43 has wires 431 arranged at intervals; the distance between two adjacent wires 431 on the wire layer 43 is less than 100 microns.

[0121] For the connection structure provided by the present application, since the wires are formed by lateral etching, the distance between the wires can be made smaller, the density can be made larger, there are more signal transmission channels, and the bandwidth is also higher. In addition, in each layer of the stacked structure, by providing a metal layer, each layer of the stacked structure can be isolated by the metal layer, and the wires between layers can be isolated by the metal layer, so that the interference between the signal lines is minimized. While increasing the bandwidth, interference between wires between layers and interference between adjacent wires on the same layer can be avoided.

[0122] Optionally, the distance between two adjacent wires 431 on the wire layer 43 is less than 10 microns.

[0123] Optionally, the metal layer 41 is made of any one of the following materials: copper and aluminum.

[0124] The present application also provides a chip packaging structure, which includes a chip and at least one of the connection structures; wherein, the chip transmits signals through the connection structure.

[0125] Two specific embodiments are given below to illustrate the chip packaging structure provided by the present application.

[0126] Embodiment 1

[0127] Figure 10 is a schematic diagram of a chip packaging structure shown in an exemplary embodiment of the present application. Please refer to Figure 10 . The chip packaging structure provided in this embodiment includes a first chip frame structure 200 and a first heat sink cover 5; wherein,

[0128] The first chip frame structure 200 includes a substrate 6, a first connection structure 7, a second connection structure 8, a first chip 9, and a second chip 10;

[0129] The first connection structure 7 and the second connection structure 8 are arranged on both sides of the substrate 6 to enclose a groove on the substrate 6;

[0130] The first chip 9 is disposed on the substrate 6, and the first chip 9 is received in the groove;

[0131] The second chip 10 is respectively connected to the first connection structure 7 and the second connection structure 8;

[0132] The first heat dissipation cover 5 covers the second chip 10 and is connected to the substrate 6 to cover a portion of the first chip frame structure 200 located above the substrate 6.

[0133] For the chip packaging structure provided in this embodiment, by using the above connection structure to connect the substrate and the second chip, the transmission bandwidth can be increased, and interference can also be avoided.

[0134] Specifically, the chip packaging structure is prepared by the following method:

[0135] (1) Prepare the substrate 6.

[0136] (2) Prepare the first connection structure 7 and the second connection structure 8.

[0137] (3) Connect the first connection structure 7 and the second connection structure 8 to both sides of the substrate 6 to enclose a groove on the substrate 6.

[0138] Figure 11 It is a schematic diagram of the connection structure shown in an exemplary embodiment of the present application connected to the substrate. Please refer to Figure 11 , after connecting the first connection structure 7 and the second connection structure 8 to both sides of the substrate 6, the first connection structure 7 and the second connection structure 8 enclose a groove on the substrate 6. (4) Connect the first chip 9 to the substrate 6, and the first chip 9 is disposed in the groove enclosed on the substrate 6.

[0139] (5) Connect the second chip 10 to the first connection structure 7 and the second connection structure 8.

[0140] Figure 12 It is a schematic diagram of the implementation principle of connecting the chip to the substrate shown in an exemplary embodiment of the present application. Refer to Figure 12 , the first chip 9 is received in the groove, and the second chip 10 covers the first connection structure 7 and the second connection structure 8.

[0141] (6) Cover the heat dissipation cover 5 on the second chip 10, and connect both sides of the heat dissipation cover 5 to the substrate 6 to cover a portion of the first chip frame structure 200 located above the substrate 6.

[0142] Please continue to refer to Figure 10 , the heat dissipation cover covers the second chip 10 to achieve the purpose of heat dissipation.

[0143] Embodiment 2

[0144] Figure 13 This is a schematic diagram of a chip packaging structure provided by another exemplary embodiment of the present application. Please refer to Figure 13 , the chip packaging structure provided in this embodiment includes a second chip frame structure 300 and a second heat sink cover 11; wherein,

[0145] The second chip frame structure 300 includes a first redistribution wire layer 301, a third connection structure 302, a fourth connection structure 303, a third chip 304, a second redistribution wire layer 305, and a fourth chip 306; wherein,

[0146] The third connection structure 302 and the fourth connection structure 303 are disposed on both sides of the first redistribution wire layer 301 to form a groove on the first redistribution wire layer 301;

[0147] The third chip 304 is disposed on the first redistribution wire layer 301, and the third chip 304 is received in the groove so that the third chip 304, the third connection structure 302, and the fourth connection structure 303 form a plane;

[0148] The second redistribution wire layer 305 is disposed on the plane;

[0149] The fourth chip 306 is disposed above the second redistribution wire layer 305;

[0150] The second heat sink cover 11 covers the fourth chip 306 and is connected to the second redistribution wire layer 305 to cover the portion of the second chip frame structure 300 above the second redistribution wire layer 305.

[0151] The chip packaging structure provided in this embodiment uses the above-prepared connection structure for connection, which can improve the transmission bandwidth and avoid interference.

[0152] Specifically, the preparation method of the chip packaging structure may include:

[0153] (1) Prepare a carrier plate 1;

[0154] (2) Prepare a third connection structure 302 and a fourth connection structure 303;

[0155] For the specific preparation method, refer to the previous description and will not be elaborated here.

[0156] (3) Connect the third connection structure 302 and the fourth connection structure 303 to both sides of the carrier plate 1 to enclose a groove on the carrier plate 1.

[0157] Figure 14 Schematic diagram of a connection structure connected to a carrier board shown in an exemplary embodiment of the present application. Please refer to Figure 14 , after connecting the third connection structure 302 and the fourth connection structure 303 to both sides of the carrier board 1, a groove will be formed around the carrier board 1.

[0158] (4) Connect the third chip 304 to the groove formed around the carrier board 1.

[0159] Figure 15 Schematic diagram of the implementation principle of connecting a chip to a carrier board shown in an exemplary embodiment of the present application. Please refer to Figure 15 , the third chip 304, the third connection structure 302 and the fourth connection structure 303 have the same height.

[0160] (5) Encapsulate the intermediate chip frame so that the third chip 304, the third connection structure 302 and the fourth connection structure 303 form a plane to obtain a first intermediate chip frame.

[0161] Figure 16 Schematic diagram of the first intermediate chip frame shown in an exemplary embodiment of the present application. Please refer to Figure 16 , after encapsulation, the third chip 304, the third connection structure 302 and the fourth connection structure 303 form a plane.

[0162] (6) Prepare a first redistribution wire layer 301 on the above plane.

[0163] Figure 17 Schematic diagram of preparing the first redistribution wire layer shown in an exemplary embodiment of the present application.

[0164] (7) Remove the carrier board 1 to obtain a second intermediate chip frame.

[0165] Figure 18 Schematic diagram of the second intermediate chip frame shown in an exemplary embodiment of the present application.

[0166] (8) Prepare a second redistribution wire layer 305 on the side of the second intermediate chip frame away from the first redistribution wire layer 301.

[0167] Figure 19 Schematic diagram of preparing the second redistribution wire layer shown in an exemplary embodiment of the present application.

[0168] (9) Flip-chip the fourth chip 306 onto the second redistribution wire layer 305.

[0169] Figure 20 Schematic diagram of flip-chipping a chip onto the second redistribution wire layer shown in an exemplary embodiment of the present application.

[0170] (10) Fill the area of the fourth chip 306 opposite to the second redistribution wire layer 305 to obtain the second chip frame 300.

[0171] Figure 21 Schematic diagram of the second chip frame shown in an exemplary embodiment of the present application.

[0172] (11) Cover the second heat sink cover 11 on the fourth chip 306; the second heat sink cover 11 is connected to the second redistribution wire layer 305 to cover the part of the second chip frame structure 300 located above the second redistribution wire layer 305.

[0173] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of protection of the present application.

Claims

1. A preparation method of a connection structure for transmitting signals, characterized in that, The method includes: Successively forming a multi-layer stacked structure on the first surface and the second surface of a carrier board to form an intermediate structure; wherein, in the direction away from the carrier board, each layer of the stacked structure sequentially includes a metal layer, a first dielectric material layer, a wire layer, and a second dielectric material layer; the wire layer has wires arranged at intervals; the distance between two adjacent wires on the wire layer is less than 100 microns; Vertically cutting the intermediate structure to obtain a plurality of basic structures; For each of the basic structures, peeling the multi-layer stacked structure formed on the first surface and the second surface from the carrier board to obtain a connection structure composed of the multi-layer stacked structure.

2. The method according to claim 1, characterized in that, The successively forming a multi-layer stacked structure on the first surface and the second surface of the carrier board includes: Taking the first surface and the second surface of the carrier board as basic surfaces, and forming a metal layer on the basic surfaces; Forming a first dielectric material layer on the metal layer; Forming a wire layer on the first dielectric material layer; wherein, the wire layer has wires arranged at intervals; Forming a second dielectric material layer on the wire layer to form a layer of stacked structure; Taking the second dielectric material layer as the basis, and performing the step of forming a metal layer on the basic surface again until a multi-layer stacked structure is formed on the first surface and the second surface.

3. The method according to claim 1 or 2, characterized in that, The distance between two adjacent wires on the wire layer is less than 10 microns.

4. The method according to claim 1 or 2, characterized in that, The metal layer is made of any one of the following materials: copper and aluminum.

5. The method according to claim 1 or 2, characterized in that, The thickness of the metal layer is less than 30 microns.

6. The method according to claim 1 or 2, characterized in that, The size of the wire is from 1 micron to 50 microns.

7. A connection structure for transmitting signals, characterized in that, The connection structure is prepared by using the method according to any one of claims 1-6; the connection structure includes a multi-layer stacked structure; each layer of the stacked structure sequentially includes a metal layer, a first dielectric material layer, a wire layer, and a second dielectric material layer; wherein, the wire layer has wires arranged at intervals; the distance between two adjacent wires on the wire layer is less than 100 microns.

8. The connection structure according to claim 7, wherein The distance between two adjacent wires on the wire layer is less than 10 microns.

9. The connection structure according to claim 7, wherein The metal layer is made of any one of the following materials: copper and aluminum.

10. A chip packaging structure, characterized in that, The chip packaging structure includes a chip and at least one of the connection structures; wherein, the chip transmits signals through the connection structure.

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