Heat dissipation type semiconductor packaging structure and preparation method thereof

Abstract

The invention provides a heat dissipation type semiconductor packaging structure and a preparation method thereof. When a third rewiring layer is prepared, virtual metal wiring with good thermal conductivity is formed on the back surface of a first chip so as to form a heat conduction rail in contact with the first chip; and a P-type semiconductor element and an N-type semiconductor element which are electrically connected with the third rewiring layer are bonded on the third rewiring layer to form a PN heat dissipation loop which is in contact with the heat conduction rail, so that a heat dissipation type semiconductor packaging structure with good heat conductivity can be prepared. The first chip is thinned while the chip bonding film with poor thermal conductivity is removed, so that the requirements of consumers on light, thin, short and small products can be met; furthermore, the heat conduction rail can further comprise a capacitor and / or an inductor which are / is formed while the third rewiring layer is prepared, so that heat dissipation is achieved while the functions of the capacitor and the inductor are achieved, the cost is reduced, and the packaging size is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a heat-dissipating semiconductor packaging structure and a preparation method thereof. Background Art

[0002] The rapid development of electronic products is the main driving force for the evolution of current packaging technologies. Miniaturization, high density, high frequency, high speed, high reliability, and low cost are the mainstream development directions of advanced packaging. Among them, System In a Package (SIP) is one of the most important and potential technologies to meet such high-density system integration.

[0003] SIP packaging refers to integrating multiple functional chips, such as processor, memory and other functional chips, into a packaging structure according to factors such as application scenarios and the number of layers of the packaging substrate, so as to achieve complete functions through one packaging structure.

[0004] Currently, the SIP packaging structure is highly centralized, and the heat generated during the operation of the chips will cause irreversible damage to the chips themselves. Therefore, it is necessary to consider the heat dissipation problem of the packaging structure.

[0005] Such as Figure 1 , in the traditional heat-dissipating packaging structure, usually a heat sink 10 is mounted on the back of the chip 20 to conduct heat through the heat sink 10, so as to effectively avoid damage to the chip 20 caused by high temperature. The products of this structure can be applied to large-size terminal products. However, this heat dissipation method will greatly increase the size of the packaging structure, which is not conducive to the miniaturization of IC (Integrated Circuit) chips, that is, it is not conducive to the preparation of microelectronic devices and cannot be applied to miniaturized consumer terminals such as mobile phones.

[0006] Therefore, it is necessary to provide a heat-dissipating semiconductor packaging structure and a preparation method thereof. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a heat-dissipating semiconductor packaging structure and a preparation method thereof, which are used to solve the problem that it is difficult to prepare a miniaturized heat-dissipating packaging structure in the prior art.

[0008] To achieve the above purpose and other related purposes, the present invention provides a preparation method of a heat-dissipating semiconductor packaging structure, including the following steps:

[0009] Provide a first support substrate;

[0010] Form metal pillars on the first support substrate, and the first end of the metal pillars is in contact with the first support substrate;

[0011] A chip composite structure is formed on the first support substrate. The chip composite structure includes a first chip and a first redistribution layer. Among them, the back surface of the first chip contacts the first support substrate through a chip adhesive film, and the first redistribution layer is located on the front surface of the first chip and is electrically connected to the chip pads.

[0012] A first encapsulation layer is formed. The first encapsulation layer includes an opposite first surface and a second surface. The first encapsulation layer covers the metal posts and the chip composite structure, and the second surface of the first encapsulation layer exposes the second ends of the metal posts and the first redistribution layer.

[0013] A second redistribution layer is formed on the second surface of the first encapsulation layer. The second redistribution layer is electrically connected to both the metal posts and the first redistribution layer.

[0014] A second support substrate is provided and bonded to the second redistribution layer.

[0015] The first support substrate is removed to expose the first ends of the metal posts and the chip adhesive film.

[0016] Grinding is performed to remove the chip adhesive film.

[0017] A third redistribution layer is formed on the first surface of the first encapsulation layer. The third redistribution layer is electrically connected to the metal posts, and the third redistribution layer further includes virtual metal wirings located on the back surface of the first chip and in contact with the back surface of the first chip. The virtual metal wirings form a heat conduction track of the first chip.

[0018] A second chip, a P-type semiconductor element, and an N-type semiconductor element are formed on the third redistribution layer. The second chip is electrically connected to the third redistribution layer.

[0019] The P-type semiconductor element and the N-type semiconductor element are connected by wire bonding. The P-type semiconductor element, the N-type semiconductor element, and the third redistribution layer are electrically connected to form a PN heat dissipation loop, and the cold end of the PN heat dissipation loop is in contact with the heat conduction track.

[0020] A second encapsulation layer is formed. The second encapsulation layer covers the second chip, the PN heat dissipation loop, and the third redistribution layer.

[0021] The second support substrate is removed to expose the second redistribution layer.

[0022] Metal bumps are formed on the second redistribution layer. The metal bumps are electrically connected to the second redistribution layer.

[0023] Optionally, after grinding to remove the chip bonding film, grinding is further performed to thin the first chip.

[0024] Optionally, the thickness of the first chip after grinding is 80 μm or less.

[0025] Optionally, the dummy metal wiring is prepared synchronously with the metal wiring in the third redistribution layer.

[0026] Optionally, the projection of the dummy metal wiring along the vertical direction covers the heat source area of the first chip.

[0027] Optionally, the dummy metal wiring includes one or a combination of a capacitor and an inductor.

[0028] The present invention also provides a heat dissipation type semiconductor package structure, which includes:

[0029] A metal post, the metal post includes opposite first and second ends;

[0030] A chip composite structure, the chip composite structure includes a first chip and a first redistribution layer, the first redistribution layer is located on the front surface of the first chip and is electrically connected to the chip pads;

[0031] A first encapsulation layer, the first encapsulation layer includes opposite first and second surfaces, the first encapsulation layer covers the metal post and the chip composite structure, and the second surface of the first encapsulation layer exposes the second end of the metal post and the first redistribution layer;

[0032] A second redistribution layer, the second redistribution layer is located on the second surface of the first encapsulation layer, the second redistribution layer is electrically connected to both the metal post and the first redistribution layer;

[0033] A third redistribution layer, the third redistribution layer is located on the first surface of the first encapsulation layer, the third redistribution layer is electrically connected to the first end of the metal post, and the third redistribution layer further includes a dummy metal wiring located on the back surface of the first chip and in contact with the back surface of the first chip, and a heat conduction track of the first chip is formed through the dummy metal wiring;

[0034] A second chip, the second chip is located on the third redistribution layer, and the second chip is electrically connected to the third redistribution layer;

[0035] P-type semiconductor element and N-type semiconductor element, the P-type semiconductor element and the N-type semiconductor element are located on the third redistribution layer, the P-type semiconductor element and the N-type semiconductor element are interconnected by wire bonding, the P-type semiconductor element, the N-type semiconductor element and the third redistribution layer are electrically connected to form a PN heat dissipation loop, and the cold end of the PN heat dissipation loop is in contact with the heat conduction rail;

[0036] Second encapsulation layer, the second encapsulation layer covers the second chip, the PN heat dissipation loop and the third redistribution layer;

[0037] Metal bumps, the metal bumps are located on the second redistribution layer and are electrically connected to the second redistribution layer.

[0038] Optionally, the thickness of the first chip is 80 μm or less.

[0039] Optionally, the virtual metal wiring has the same material as the metal wiring in the third redistribution layer; the virtual metal wiring includes one or a combination of a capacitor and an inductor.

[0040] Optionally, the vertical projection of the virtual metal wiring covers the heat source area of the first chip.

[0041] As described above, the heat dissipation type semiconductor package structure and its manufacturing method of the present invention form a virtual metal wiring with good thermal conductivity on the back of the first chip while manufacturing the third redistribution layer to form a heat conduction rail in contact with the first chip, and bond a P-type semiconductor element and an N-type semiconductor element electrically connected to the third redistribution layer on the third redistribution layer to form a PN heat dissipation loop in contact with the heat conduction rail, so as to manufacture a heat dissipation type semiconductor package structure with good thermal conductivity; while removing the chip adhesive film with poor thermal conductivity, the first chip is thinned, which can meet the needs of consumers for thin, light, short and small products; further, the heat conduction rail can also include a capacitor and / or an inductor formed while manufacturing the third redistribution layer, so as to realize heat dissipation while realizing the functions of the capacitor and the inductor, reduce costs and reduce the package size. Description of the Drawings

[0042] Figure 1 Shows a schematic structural diagram of a heat dissipation package in the prior art.

[0043] Figures 2 to 8 Shows a schematic structural diagram of each step in the preparation of the semiconductor package structure in the comparative example of the present invention.

[0044] Figure 9 Shows a process flow diagram for manufacturing a heat dissipation type semiconductor package structure in an embodiment of the present invention.

[0045] Figures 10 to 21 It shows the structural schematic diagrams of each step in the preparation of the heat-dissipating semiconductor package structure in the embodiments of the present invention.

[0046] Figure 22 It shows the working principle diagram of the PN heat-dissipating circuit in the embodiments of the present invention.

[0047] Description of the reference numerals in the drawings

[0048] 10 Heat sink

[0049] 20 Chip

[0050] 110 First support substrate

[0051] 111 First separation layer

[0052] 120 Second support substrate

[0053] 121 Second separation layer

[0054] 122 Substrate adhesive film

[0055] 201 First metal seed layer

[0056] 202 Second metal seed layer

[0057] 311 First metal wiring

[0058] 312 First dielectric layer

[0059] 321 Second metal wiring

[0060] 322 Second dielectric layer

[0061] 331 Third metal wiring

[0062] 332 Third dielectric layer

[0063] 333 Virtual metal wiring

[0064] 400 Metal pillar

[0065] 500 Chip adhesive film

[0066] 610 First chip

[0067] 611 First chip pad

[0068] 620 Second chip

[0069] 621 Second chip pad

[0070] 710 First encapsulation layer

[0071] 720 Second encapsulation layer

[0072] 810 First metal bump

[0073] 820 Second metal bump

[0074] 910 P-type semiconductor element

[0075] 920 N-type semiconductor element

[0076] 930 Metal wire

[0077] A Heat conducting rail

[0078] Steps S1 to S14 Detailed implementation mode

[0079] The following uses specific specific examples to illustrate the implementation mode of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0080] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions of length, width and depth should be included.

[0081] For the convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation, in addition to the directions depicted in the drawings. Embodiments where the first and second features are formed in direct contact may be included, and embodiments where additional features are formed between the first and second features may also be included, such that the first and second features may not be in direct contact. Additionally, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0082] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0083] Comparative example

[0084] Refer toFigures 2 to 8 , a heat dissipation type semiconductor package structure and a preparation method thereof are provided, and the preparation steps may include:

[0085] First, as Figure 2 , a first support substrate 110 is provided. For the convenience of separation, it is preferred that the surface of the first support substrate 110 has a first separation layer 111.

[0086] Next, as Figure 3 and Figure 4 , a first redistribution layer is formed on the first support substrate 110.

[0087] Among them, as Figure 3 , a metal seed layer, such as a Ti / Cu metal seed layer, can be first formed on the first support substrate 110. That is, the first metal seed layer 201 can be a Ti layer, and the second metal seed layer 202 can be a Cu layer. Then, as Figure 4 , the first redistribution layer including the first metal wiring 311 and the first dielectric layer 312 is formed on the metal seed layer by electroplating.

[0088] Next, as Figure 4 , a metal post 400 and a chip composite structure are formed on the first redistribution layer. The first end of the metal post 400 is electrically connected to the first metal wiring 311. The chip composite structure includes a first chip 610 and a second redistribution layer. Among them, the back surface of the first chip 610 is bonded to the first redistribution layer through a chip adhesive film 500, and the second redistribution layer is located on the front surface of the first chip 610 and includes a second metal wiring 321 and a second dielectric layer 322 that are electrically connected to the first chip pad 611.

[0089] Next, as Figure 5 , a first encapsulation layer 710 is formed. The first encapsulation layer 710 includes an opposite first surface and a second surface. The first encapsulation layer 710 covers the metal post 400 and the chip composite structure, and the second surface of the first encapsulation layer 710 exposes the second end of the metal post 400 and the second metal wiring 321 in the second redistribution layer.

[0090] Next, as Figure 6 , a third redistribution layer is formed on the second surface of the first encapsulation layer 710. The third redistribution layer includes a third metal wiring 331 and a third dielectric layer 332 that are electrically connected to the second end of the metal post 400.

[0091] Next, as Figure 6 , a second support substrate 120 is provided and the second support substrate 120 is bonded to the third redistribution layer.

[0092] Among them, for the convenience of separation, it is preferred that the surface of the second support substrate 120 has a second separation layer 121, and for the convenience of the combination of the second support substrate 120 and the third redistribution layer, a substrate adhesive film 122 is provided on the surface of the second separation layer 121.

[0093] Next, as Figure 7 , the first support substrate 110 is removed to expose the first metal wiring 311 in the first redistribution layer, and a second chip 620 is formed on the first redistribution layer. The second chip 620 can be electrically connected to the first redistribution layer through the first metal bumps 810 electrically connected to the second chip pads 621.

[0094] Then, as Figure 7 , a second encapsulation layer 720 is formed, and the second encapsulation layer 720 covers the second chip 620 and the first redistribution layer.

[0095] Next, as Figure 8 , the second support substrate 120 is removed to expose the third redistribution layer.

[0096] After that, as Figure 8 , second metal bumps 820 are formed on the third redistribution layer, and the second metal bumps 820 are electrically connected to the third redistribution layer.

[0097] In the heat-dissipating semiconductor package structure formed in this comparative example, since the back surface of the first chip 610 has the chip adhesive film 500, the heat-dissipating performance of the heat-dissipating semiconductor package structure is poor; and since the first chip 610 is attached to the first redistribution layer through the chip adhesive film 500, in the chip mounting process, the thickness of the first chip 610 needs to be more than 10 μm to avoid the risk of chip breakage, and during the preparation of the heat-dissipating semiconductor package structure, the first chip 610 cannot be thinned either. Therefore, the size of this heat-dissipating semiconductor package structure is also difficult to meet the requirements of miniaturized products.

[0098] Embodiment

[0099] Referring to Figure 9 , this embodiment provides a method for preparing a heat-dissipating semiconductor package structure, wherein Figures 10 to 20 schematically shows the structural diagrams presented in each step when preparing the heat-dissipating semiconductor package structure. The preparation of the heat-dissipating semiconductor package structure will be introduced below with reference to the accompanying drawings of the specification.

[0100] First, referring to Figure 9 and Figure 10 , step S1 is executed to provide a first support substrate 110.

[0101] Specifically, the first support substrate 110 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., to provide support for subsequent processes through the first support substrate 110. The size of the first support substrate 110 is not limited here, and preferably it is wafer-level.

[0102] Wherein, to facilitate the subsequent removal of the first support substrate 110, in this embodiment, preferably a first separation layer 111 is formed on the surface of the first support substrate 110. The first separation layer 111 includes but is not limited to a tape and a polymer layer. For example, the first separation layer 111 can be a photothermal conversion layer formed by a photothermal conversion (LTHC) coating material, so that subsequently, such as light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the first support substrate 110, improving the convenience of the separation operation.

[0103] Next, refer to Figure 9 、 Figure 11 and Figure 12 and perform step S2 to form a metal pillar 400 on the first support substrate 110. The first end of the metal pillar 400 is in contact with the first support substrate 110.

[0104] Specifically, refer to Figure 11 and Figure 12 In this embodiment, the metal pillar 400 is formed by electroplating. Thus, a metal seed layer is formed on the surface of the first separation layer 111 by physical vapor deposition (PVD). Among them, the metal seed layer may include a first metal seed layer 201 and a second metal seed layer 202 located above the first metal seed layer 201. In this embodiment, the first metal seed layer 201 is a Ti layer, and the second metal seed layer 202 is a Cu layer. However, the types of the metal seed layer are not limited thereto. For example, the metal seed layer can also be a Ti / Ag layer, a Ni / Ti layer, etc., and no excessive limitation is made here. After forming the metal seed layer, a photoresist can be used for lithography and electroplating to form the metal pillar 400, and then the photoresist is removed.

[0105] Next, refer to Figure 9 and Figure 12 and perform step S3 to form a chip composite structure on the first support substrate 110. The chip composite structure includes a first chip 610 and a first redistribution layer. Among them, the back surface of the first chip 610 is bonded to the first support substrate 110 through a chip adhesive film 500, and the first redistribution layer is located on the front surface of the first chip 610 and is electrically connected to the chip pads.

[0106] Specifically, the chip composite structure is combined with the chip adhesive film 500 to be attached to the metal seed layer. The first redistribution layer in the chip composite structure includes a first metal wiring 311 and a first dielectric layer 312. The first metal wiring 311 is electrically connected to a first chip pad 611 on the front of the first chip 610. The first dielectric layer 312 can be formed of polymers such as polybenzoxazole (PBO) and polyimide, or formed of inorganic dielectric materials such as silicon nitride and silicon oxide; the first metal wiring 311 can include, for example, aluminum, copper, tungsten, or their alloys, etc. There is no excessive limitation on the specific structure and material selection of the first redistribution layer here.

[0107] Among them, for the convenience of removing and thinning the first chip 610 by subsequent grinding processes, the chip adhesive film 500 is preferably a bonding film material with a relatively hard material, and the specific type can be selected according to needs.

[0108] Next, refer to Figure 9 and Figure 13 , perform step S4 to form a first encapsulation layer 710. The first encapsulation layer 710 includes an opposite first surface and a second surface. The first encapsulation layer 710 covers the metal posts 400 and the chip composite structure, and the second surface of the first encapsulation layer 710 exposes the second end of the metal posts 400 and the first redistribution layer.

[0109] Specifically, the method of forming the first encapsulation layer 710 can include, but is not limited to, compression molding, transfer molding, and spin coating. The material of the first encapsulation layer 710 can include, but is not limited to, epoxy resin and polyamide. There is no excessive limitation on the material and preparation method of the first encapsulation layer 710 here.

[0110] Among them, when forming the first encapsulation layer 710, it may include a grinding step to expose the second end of the metal posts 400 and the first metal wiring 311. The first redistribution layer can protect the first chip 610 from being damaged by grinding.

[0111] Next, refer to Figure 9 and Figure 14 , perform step S5 to form a second redistribution layer on the second surface of the first encapsulation layer 710. The second redistribution layer is electrically connected to both the metal posts 400 and the first redistribution layer.

[0112] Specifically, the second redistribution layer includes a second metal wiring 321 and a second dielectric layer 322. The second metal wiring 321 is electrically connected to the second end of the metal post 400 and is also electrically connected to the first metal wiring 311. The second dielectric layer 322 can be formed of polymers such as polybenzoxazole (PBO) and polyimide, or inorganic dielectric materials such as silicon nitride and silicon oxide. The second metal wiring 321 can include materials such as aluminum, copper, tungsten, or their alloys. There is no excessive limitation on the specific structure and material selection of the second redistribution layer here.

[0113] Next, refer to Figure 9 and Figure 14 , and perform step S6 to provide a second support substrate 120 and bond the second support substrate 120 to the second redistribution layer.

[0114] Specifically, the second support substrate 120 can include a glass substrate, a metal substrate, a semiconductor substrate, etc., to provide support for subsequent processes through the second support substrate 120. There is no limitation on the size of the second support substrate 120 here.

[0115] Among them, for the convenience of removing the second support substrate 120 subsequently, in this embodiment, preferably, a second separation layer 121 is formed on the surface of the second support substrate 120. The second separation layer 121 includes but is not limited to tapes and polymer layers. For example, the second separation layer 121 can be selected as a photothermal conversion layer formed of a photothermal conversion (LTHC) coating material, so that subsequently, methods such as light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the second support substrate 120, improving the convenience of the separation operation.

[0116] Furthermore, preferably, a substrate adhesive film 122 is formed on the surface of the second separation layer 121 to achieve good bonding between the second separation layer 121 and the second redistribution layer through the substrate adhesive film 122. Among them, the substrate adhesive film 122 can include materials such as PBO, polyimide, benzocyclobutene (BCB), or other applicable polymers. After separating the second support substrate 120 subsequently, the substrate adhesive film 122 can be removed using a cleaning solution.

[0117] Next, refer to Figure 9 , Figure 15 and Figure 16 , and perform step S7 to remove the first support substrate 110, exposing the first end of the metal post 400 and the chip adhesive film 500.

[0118] Specifically, as Figure 15After removing the first support substrate 110, the metal seed layer is removed to expose the chip bonding film 500.

[0119] Next, referring to Figure 9 and Figure 17 Step S8 is performed to grind and remove the chip bonding film 500.

[0120] Specifically, when grinding, the chip bonding film 500 with poor thermal conductivity can be removed to facilitate the heat dissipation of the first chip 610. Then, grinding can be continued to thin the metal posts 400 and the first chip 610, thereby reducing the package size. Among them, the grinding method can be, for example, chemical mechanical polishing (CMP), etc., and no excessive limitation is made here.

[0121] As an example, the thickness of the first chip 610 after grinding can be 80 μm or less, such as 80 μm, 60 μm, 50 μm, etc., to meet the needs of consumers for thin, light, short, and small products.

[0122] Next, referring to Figure 9 and Figure 18 Step S9 is performed to grind and form a third redistribution layer on the first surface of the first encapsulation layer 710. The third redistribution layer is electrically connected to the metal posts 400, and the third redistribution layer further includes a dummy metal wiring 333 located on the back surface of the first chip 610 and in contact with the back surface of the first chip 610. The heat conduction rail A of the first chip 610 is formed through the dummy metal wiring 333.

[0123] Specifically, the third redistribution layer includes a third dielectric layer 332, a third metal wiring 331, and the dummy metal wiring 333. The third dielectric layer 332 can be formed of a polymer such as polybenzoxazole (PBO), polyimide, etc., or an inorganic dielectric material such as silicon nitride, silicon oxide, etc.; the third metal wiring 331 is electrically connected to the first end of the metal post 400, and the third metal wiring 331 can include, for example, aluminum, copper, tungsten, or their alloys.

[0124] Among them, it is preferred that the dummy metal wiring 333 is prepared synchronously with the third metal wiring 331 in the third redistribution layer, so that the heat conduction rail A in contact with the back surface of the first chip 610 can be formed on the back surface of the first chip 610 without increasing the process steps, facilitating the heat dissipation of the first chip 610. Of course, the dummy metal wiring 333 can also be prepared separately, and no excessive limitation is made here.

[0125] Preferably, the vertical projection of the virtual metal wiring 333 covers the heat source area of the first chip 610, so as to achieve good heat dissipation for the heat source area of the first chip 610.

[0126] No excessive restrictions are imposed here on the specific structures and material selections of the third dielectric layer 332, the third metal wiring 331, and the virtual metal wiring 333 in the third rewiring layer.

[0127] Next, refer to Figure 9 and Figure 19 , perform step S10 to form a second chip 620, a P-type semiconductor element 910, and an N-type semiconductor element 920 on the third rewiring layer. The second chip 620 is electrically connected to the third rewiring layer.

[0128] Among them, the second chip pad 621 of the second chip 620 can be electrically connected to the third metal wiring 331 through a first metal bump 810 such as a solder ball bump, but it is not limited thereto.

[0129] No limitation is imposed here on the bonding sequence of the second chip 620, the P-type semiconductor element 910, and the N-type semiconductor element 920.

[0130] Next, refer to Figure 9 and Figure 19 , perform step S11 to connect the P-type semiconductor element 910 and the N-type semiconductor element 920 by wire bonding. The P-type semiconductor element 910, the N-type semiconductor element 920, and the third rewiring layer are electrically connected to form a PN heat dissipation circuit, and the cold end of the PN heat dissipation circuit is in contact with the heat conduction rail A.

[0131] Specifically, as Figure 22 illustrates the working principle of the PN heat dissipation circuit. Among them, the power supply provides the energy required for the electron flow. After the power is turned on, the electrons start from the negative electrode (-), pass through the P-type semiconductor element and absorb heat, and then release the heat at the N-type semiconductor element. Thus, for each NP module passed through, heat is transferred from one side to the other side to cause a temperature difference to form a cold and a hot end. Therefore, when the cold end is in contact with the heat source, heat dissipation for the heat source can be achieved.

[0132] In this embodiment, the P-type semiconductor element 910 and the N-type semiconductor element 920 bonded to the third redistribution layer are electrically connected to the third metal wiring 331 in the third redistribution layer, and the P-type semiconductor element 910 and the N-type semiconductor element 920 can be interconnected by a metal wire 930 after wire bonding. Thus, a PN heat dissipation loop is formed between the P-type semiconductor element 910, the N-type semiconductor element 920 and the third redistribution layer. Since the PN heat dissipation loop is interconnected with the heat conduction rail A, after the cold end of the PN heat dissipation loop is contacted with the heat conduction rail A, the heat conduction rail A can be effectively cooled to further improve the heat dissipation effect. Next, referring to Figure 9 and Figure 20 , step S12 is performed to form a second encapsulation layer 720. The second encapsulation layer 720 covers the second chip 620, the PN heat dissipation loop and the third redistribution layer to protect the second chip 620, the PN heat dissipation loop and the third redistribution layer through the second encapsulation layer 720.

[0133] Specifically, the method for forming the second encapsulation layer 720 may include but is not limited to compression molding, transfer molding and spin coating. The material of the second encapsulation layer 720 may include but is not limited to epoxy resin and polyamide. The material and preparation method of the second encapsulation layer 720 are not overly limited here.

[0134] Next, referring to Figure 9 and Figure 21 , step S13 is performed to remove the second support substrate 120 to expose the second redistribution layer.

[0135] Next, referring to Figure 9 and Figure 21 , step S14 is performed to form second metal bumps 820 on the second redistribution layer. The second metal bumps 820 are electrically connected to the second metal wiring 321 in the second redistribution layer.

[0136] Among them, the second metal bumps 820 may include, for example, solder ball bumps, C4 metal bumps, copper pillar bumps, etc. The specific types and materials of the metal bumps are not overly limited here.

[0137] Referring to Figure 21 , the present invention also provides a heat dissipation type semiconductor package structure. The heat dissipation type semiconductor package structure includes:

[0138] A metal column 400, the metal column 400 includes opposite first and second ends;

[0139] Chip composite structure, the chip composite structure includes a first chip 610 and a first redistribution layer, the first redistribution layer is located on the front of the first chip 610 and is electrically connected to the chip pad;

[0140] A first encapsulation layer 710, the first encapsulation layer 710 includes an opposite first surface and a second surface, the first encapsulation layer 710 covers the metal posts 400 and the chip composite structure, and the second surface of the first encapsulation layer 710 exposes the second ends of the metal posts 400 and the first redistribution layer;

[0141] A second redistribution layer, the second redistribution layer is located on the second surface of the first encapsulation layer 710, the second redistribution layer is electrically connected to both the metal posts 400 and the first redistribution layer;

[0142] A third redistribution layer, the third redistribution layer is located on the first surface of the first encapsulation layer 710, the third redistribution layer is electrically connected to the first ends of the metal posts 400, and the third redistribution layer further includes a virtual metal wiring 333 located on the back of the first chip 610 and in contact with the back of the first chip 610, and a heat conduction rail A of the first chip 610 is formed through the virtual metal wiring 333;

[0143] A second chip 620, the second chip 620 is located on the third redistribution layer, and the second chip 620 is electrically connected to the third redistribution layer;

[0144] A P-type semiconductor element 910 and an N-type semiconductor element 920, the P-type semiconductor element 910 and the N-type semiconductor element 920 are located on the third redistribution layer, the P-type semiconductor element 910 and the N-type semiconductor element 920 are interconnected by wire bonding, the P-type semiconductor element 910, the N-type semiconductor element 920 and the third redistribution layer are electrically connected to form a PN heat dissipation loop, and the cold end of the PN heat dissipation loop is in contact with the heat conduction rail A;

[0145] A second encapsulation layer 720, the second encapsulation layer 720 covers the second chip 620, the PN heat dissipation loop and the third redistribution layer;

[0146] Metal bumps, the metal bumps are located on the second redistribution layer and are electrically connected to the second redistribution layer.

[0147] Specifically, the preparation method of the heat-dissipating semiconductor package structure can be prepared by the above steps, but is not limited thereto. In this embodiment, the above preparation process is directly used to prepare the heat-dissipating semiconductor package structure. Therefore, for the preparation, materials, and specific structure of the heat-dissipating semiconductor package structure, reference can be made to the above steps, which will not be elaborated here.

[0148] As an example, the thickness of the first chip 610 can be 80 μm or less, such as 80 μm, 60 μm, 50 μm, etc., to meet the needs of consumers for thin, light, short, and small products.

[0149] As an example, the virtual metal wiring 333 has the same material as the metal wiring in the third redistribution layer, so that the virtual metal wiring 333 and the metal wiring in the third redistribution layer can be prepared synchronously to reduce the complexity of process control.

[0150] As an example, the virtual metal wiring 333 can include one or a combination of a capacitor and an inductor, so as to achieve good heat dissipation while realizing the functions of the capacitor and the inductor.

[0151] As an example, the projection of the virtual metal wiring 333 along the vertical direction covers the heat source area of the first chip 610 to achieve good heat dissipation for the heat source area of the first chip 610.

[0152] In summary, for the heat-dissipating semiconductor package structure and its preparation method of the present invention, a virtual metal wiring with good thermal conductivity is formed on the back of the first chip while preparing the third redistribution layer to form a heat conduction rail in contact with the first chip, and a P-type semiconductor element and an N-type semiconductor element electrically connected to the third redistribution layer are bonded on the third redistribution layer to form a PN heat dissipation loop in contact with the heat conduction rail, so that a heat-dissipating semiconductor package structure with good thermal conductivity can be prepared; while removing the chip adhesive film with poor thermal conductivity, the first chip is thinned, which can meet the needs of consumers for thin, light, short, and small products; further, the heat conduction rail can also include a capacitor and / or an inductor formed while preparing the third redistribution layer, so as to achieve heat dissipation while realizing the functions of the capacitor and the inductor, reduce costs, and reduce the package size.

[0153] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A preparation method of a heat-dissipating semiconductor package structure, characterized in that, It includes the following steps: Provide a first support substrate; Form metal pillars on the first support substrate, with the first end of the metal pillars in contact with the first support substrate; Form a chip composite structure on the first support substrate, the chip composite structure including a first chip and a first redistribution layer. Wherein, the back surface of the first chip is bonded to the first support substrate through a chip adhesive film, and the first redistribution layer is located on the front surface of the first chip and is electrically connected to chip pads; Form a first encapsulation layer, the first encapsulation layer including an opposite first surface and a second surface. The first encapsulation layer covers the metal pillars and the chip composite structure, and the second surface of the first encapsulation layer exposes the second end of the metal pillars and the first redistribution layer; Form a second redistribution layer on the second surface of the first encapsulation layer, the second redistribution layer being electrically connected to both the metal pillars and the first redistribution layer; Provide a second support substrate and bond the second support substrate to the second redistribution layer; Remove the first support substrate to expose the first end of the metal pillars and the chip adhesive film; Perform grinding to remove the chip adhesive film; Form a third redistribution layer on the first surface of the first encapsulation layer, the third redistribution layer being electrically connected to the metal pillars. And the third redistribution layer further includes virtual metal wirings located on the back surface of the first chip and in contact with the back surface of the first chip. The virtual metal wirings constitute a heat conduction track of the first chip; Form a second chip, a P-type semiconductor element and an N-type semiconductor element on the third redistribution layer, the second chip being electrically connected to the third redistribution layer; Connect the P-type semiconductor element and the N-type semiconductor element by wire bonding. The P-type semiconductor element, the N-type semiconductor element and the third redistribution layer are electrically connected to form a PN heat dissipation loop, and the cold end of the PN heat dissipation loop is in contact with the heat conduction track; Form a second encapsulation layer, the second encapsulation layer covering the second chip, the PN heat dissipation loop and the third redistribution layer; Remove the second support substrate to expose the second redistribution layer; Form metal bumps on the second redistribution layer, the metal bumps being electrically connected to the second redistribution layer.

2. The manufacturing method of the heat-dissipating semiconductor package structure according to claim 1, wherein: After grinding to remove the chip adhesive film, it further includes continuing to grind to thin the first chip.

3. The manufacturing method of the heat dissipation type semiconductor package structure according to claim 2, characterized in that: The thickness of the ground first chip is 80 μm or less.

4. The manufacturing method of the heat dissipation type semiconductor package structure according to claim 1, characterized in that: The virtual metal wirings are prepared synchronously with the metal wirings in the third redistribution layer.

5. The manufacturing method of the heat dissipation type semiconductor package structure according to claim 1, wherein: The vertical projection of the virtual metal wirings covers the heat source area of the first chip.

6. The manufacturing method of the heat dissipation type semiconductor package structure according to claim 1, characterized in that: The virtual metal wirings include one or a combination of a capacitor and an inductor.

7. A heat-dissipating semiconductor package structure, characterized in that, The heat dissipation type semiconductor package structure includes: Metal pillars, the metal pillars including opposite first and second ends; A chip composite structure, the chip composite structure including a first chip and a first redistribution layer, the first redistribution layer being located on the front surface of the first chip and being electrically connected to chip pads; The first encapsulation layer, the first encapsulation layer includes opposite first and second surfaces, the first encapsulation layer encapsulates the metal pillar and the chip composite structure, and the second surface of the first encapsulation layer exposes the second end of the metal pillar and the first redistribution layer; A second redistribution layer, the second redistribution layer is located on the second surface of the first encapsulation layer, and the second redistribution layer is electrically connected to both the metal pillar and the first redistribution layer; A third redistribution layer, the third redistribution layer is located on the first surface of the first encapsulation layer, the third redistribution layer is electrically connected to the first end of the metal pillar, and the third redistribution layer further includes a virtual metal wiring located on the back surface of the first chip and in contact with the back surface of the first chip, and a heat conduction track of the first chip is formed through the virtual metal wiring; A second chip, the second chip is located on the third redistribution layer, and the second chip is electrically connected to the third redistribution layer; A P-type semiconductor element and an N-type semiconductor element, the P-type semiconductor element and the N-type semiconductor element are located on the third redistribution layer, the P-type semiconductor element and the N-type semiconductor element are interconnected by wire bonding, the P-type semiconductor element, the N-type semiconductor element and the third redistribution layer are electrically connected to form a PN heat dissipation circuit, and the cold end of the PN heat dissipation circuit is in contact with the heat conduction track; A second encapsulation layer, the second encapsulation layer encapsulates the second chip, the PN heat dissipation circuit and the third redistribution layer; Metal bumps, the metal bumps are located on the second redistribution layer and are electrically connected to the second redistribution layer.

8. The heat dissipating semiconductor package structure according to claim 7, wherein: The thickness of the first chip is 80 μm or less.

9. The heat dissipating semiconductor package structure according to claim 7, wherein: The virtual metal wiring has the same material as the metal wiring in the third redistribution layer; the virtual metal wiring includes one or a combination of a capacitor and an inductor.

10. The heat-dissipating semiconductor package structure according to claim 7, wherein: The projection of the virtual metal wiring along the vertical direction covers the heat source area of the first chip.

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