Heat dissipation type semiconductor packaging structure and preparation method thereof

Abstract

The invention provides a heat dissipation type semiconductor packaging structure and a preparation method thereof, and the method comprises the steps: forming a virtual metal wire with good thermal conductivity on the back surface of a first chip while preparing a third rewiring layer, so as to form a heat conduction rail which is in contact with the first chip, and forming a metal heat dissipation part which is in contact with the heat conduction rail; therefore, the heat dissipation type semiconductor packaging structure with good thermal conductivity is prepared. The first chip is thinned while the chip bonding film with poor thermal conductivity is removed, so that the requirements of consumers on light, thin, short and small products can be met; furthermore, the heat conduction rail can further comprise a capacitor and / or an inductor which are / is formed while the third rewiring layer is prepared, so that heat dissipation is achieved while the functions of the capacitor and the inductor are achieved, the cost is reduced, and the packaging size is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a heat-dissipating semiconductor packaging structure and a preparation method thereof. Background Art

[0002] The rapid development of electronic products is the main driving force for the evolution of current packaging technologies. Miniaturization, high density, high frequency, high speed, high reliability, and low cost are the mainstream development directions of advanced packaging. Among them, System In a Package (SIP) is one of the most important and promising technologies to meet such high-density system integration.

[0003] SIP packaging refers to integrating multiple functional chips, such as processor, memory and other functional chips, into a packaging structure according to factors such as application scenarios and the number of layers of the packaging substrate, so as to achieve complete functions through one packaging structure.

[0004] Currently, the SIP packaging structure is highly centralized, and the heat generated during the operation of the chips will cause irreversible damage to the chips themselves. Therefore, the heat dissipation problem of the packaging structure needs to be considered.

[0005] For example Figure 1 , in the traditional heat dissipation packaging structure, usually a heat sink 10 is mounted on the back of the chip 20 to conduct the heat through the heat sink 10, so as to effectively avoid the damage of high temperature to the chip 20. The products of this structure can be applied to large-size terminal products. However, this heat dissipation method will greatly increase the size of the packaging structure, which is not conducive to the miniaturization of IC (Integrated Circuit) chips, that is, it is not conducive to the preparation of microelectronic devices and cannot be applied to miniaturized consumer terminals such as mobile phones.

[0006] Therefore, it is necessary to provide a heat-dissipating semiconductor packaging structure and a preparation method thereof. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a heat-dissipating semiconductor packaging structure and a preparation method thereof, which are used to solve the problem that it is difficult to prepare a miniaturized heat dissipation packaging structure in the prior art.

[0008] To achieve the above purpose and other related purposes, the present invention provides a preparation method of a heat-dissipating semiconductor packaging structure, including the following steps:

[0009] Provide a first support substrate;

[0010] Form metal pillars on the first support substrate, and the first end of the metal pillars is in contact with the first support substrate;

[0011] forming a chip composite structure on the first supporting substrate, the chip composite structure comprising a first chip and a first rewiring layer, wherein the back side of the first chip is in contact with the first supporting substrate by bonding a chip adhesive film, and the first rewiring layer is located on the front side of the first chip and is electrically connected to the chip pad;

[0012] forming a first packaging layer, wherein the first packaging layer comprises a first surface and a second surface opposite to each other, the first packaging layer covers the metal pillar and the chip composite structure, and the second surface of the first packaging layer exposes the second end of the metal pillar and the first rewiring layer;

[0013] forming a second rewiring layer on the second surface of the first packaging layer, wherein the second rewiring layer is electrically connected to the metal pillar and the first rewiring layer;

[0014] Providing a second supporting substrate, and bonding the second supporting substrate to the second rewiring layer;

[0015] removing the first supporting substrate to expose the first end of the metal column and the chip bonding film;

[0016] Grinding to remove the chip adhesive film;

[0017] forming a third rewiring layer on the first surface of the first packaging layer, the third rewiring layer being electrically connected to the metal pillar, and the third rewiring layer further comprising a dummy metal wiring located on and in contact with the back surface of the first chip, and forming a heat conduction track of the first chip through the dummy metal wiring;

[0018] forming a second chip and a metal heat sink on the third redistribution layer, wherein the second chip is electrically connected to the third redistribution layer, and the metal heat sink is in contact with the heat conducting rail;

[0019] forming a second packaging layer, wherein the second packaging layer covers the second chip, the metal heat sink and the third rewiring layer;

[0020] removing the second supporting substrate to expose the second rewiring layer;

[0021] A metal bump is formed on the second rewiring layer, wherein the metal bump is electrically connected to the second rewiring layer.

[0022] Optionally, after removing the chip adhesive film by grinding, the method further includes continuing to grind to thin the first chip.

[0023] Optionally, the thickness of the first chip after grinding is less than 80 μm.

[0024] Optionally, the virtual metal wiring is prepared synchronously with the metal wiring in the third redistribution layer.

[0025] Optionally, the projections of the metal heat sink and the virtual metal wiring in the vertical direction cover the heat source area of the first chip.

[0026] Optionally, the virtual metal wiring includes one or a combination of a capacitor and an inductor; the metal heat sink includes a plate-shaped metal heat sink or a block-shaped metal heat sink.

[0027] The present invention also provides a heat-dissipating semiconductor package structure, which includes:

[0028] A metal post, the metal post including opposite first and second ends;

[0029] A chip composite structure, the chip composite structure including a first chip and a first redistribution layer, the first redistribution layer being located on the front surface of the first chip and electrically connected to the chip pads;

[0030] A first encapsulation layer, the first encapsulation layer including opposite first and second surfaces, the first encapsulation layer covering the metal post and the chip composite structure, and the second surface of the first encapsulation layer exposing the second end of the metal post and the first redistribution layer;

[0031] A second redistribution layer, the second redistribution layer being located on the second surface of the first encapsulation layer, the second redistribution layer being electrically connected to both the metal post and the first redistribution layer;

[0032] A third redistribution layer, the third redistribution layer being located on the first surface of the first encapsulation layer, the third redistribution layer being electrically connected to the first end of the metal post, and the third redistribution layer further including a virtual metal wiring located on the back surface of the first chip and in contact with the back surface of the first chip, and the virtual metal wiring forms a heat conduction track of the first chip;

[0033] A second chip, the second chip being located on the third redistribution layer, the second chip being electrically connected to the third redistribution layer;

[0034] A metal heat sink, the metal heat sink being located on the third redistribution layer, the metal heat sink being in contact with the heat conduction track;

[0035] A second encapsulation layer, the second encapsulation layer covering the second chip and the third redistribution layer;

[0036] Metal bumps, the metal bumps being located on the second redistribution layer and electrically connected to the second redistribution layer.

[0037] Optionally, the thickness of the first chip is 80 μm or less.

[0038] Optionally, the dummy metal wiring has the same material as the metal wiring in the third redistribution layer; the dummy metal wiring includes one or a combination of a capacitor and an inductor; the metal heat sink includes a plate-shaped metal heat sink or a block-shaped metal heat sink.

[0039] Optionally, the vertical projection of the metal heat sink and the dummy metal wiring covers the heat source area of the first chip.

[0040] As described above, for the heat dissipation type semiconductor package structure and its manufacturing method of the present invention, while manufacturing the third redistribution layer, a dummy metal wiring with good thermal conductivity is formed on the back surface of the first chip to form a heat conduction rail in contact with the first chip, and a metal heat sink in contact with the heat conduction rail is formed to manufacture a heat dissipation type semiconductor package structure with good thermal conductivity; while removing the chip adhesive film with poor thermal conductivity, the first chip is thinned, which can meet the needs of consumers for thin, light, short, and small products; further, the heat conduction rail may further include a capacitor and / or an inductor formed while manufacturing the third redistribution layer, so as to achieve heat dissipation while realizing the functions of the capacitor and the inductor, reduce costs, and reduce the package size. Description of the Drawings

[0041] Figure 1 Shows a schematic structural diagram of a heat dissipation package in the prior art.

[0042] Figures 2 to 8 Shows a schematic structural diagram of each step in the manufacturing of the semiconductor package structure in the comparative example of the present invention.

[0043] Figure 9 Shows a process flow diagram of manufacturing a heat dissipation type semiconductor package structure in an embodiment of the present invention.

[0044] Figures 10 to 20 Shows a schematic structural diagram of each step in the manufacturing of a heat dissipation type semiconductor package structure in an embodiment of the present invention.

[0045] Figures 21 to 23 Shows Figure 20 a top view structural diagram of

[0046] Description of the Reference Numerals

[0047] 10 Heat sink

[0048] 20 Chip

[0049] 110 First support substrate

[0050] 111 First separation layer

[0051] 120 Second support substrate

[0052] 121 Second separation layer

[0053] 122 Substrate adhesive film

[0054] 201 First metal seed layer

[0055] 202 Second metal seed layer

[0056] 311 First metal wiring

[0057] 312 First dielectric layer

[0058] 321 Second metal wiring

[0059] 322 Second dielectric layer

[0060] 331 Third metal wiring

[0061] 332 Third dielectric layer

[0062] 333 Virtual metal wiring

[0063] 400 Metal column

[0064] 500 Chip adhesive film

[0065] 610 First chip

[0066] 611 First chip pad

[0067] 620 Second chip

[0068] 621 Second chip pad

[0069] 710 First encapsulation layer

[0070] 720 Second encapsulation layer

[0071] 810 First metal bump

[0072] 820 Second metal bump

[0073] 830 Thermal conductive adhesive layer

[0074] 900 Metal heat sink

[0075] A Thermal conduction rail

[0076] Steps S1 to S13 Detailed implementation manners

[0077] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0078] When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure will be enlarged locally out of the general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0079] For convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" etc. may be used here to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation besides the directions depicted in the drawings. Embodiments may include those where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0080] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout pattern may also be more complex.

[0081] Comparative example

[0082] Refer to Figures 2 to 8 , a heat dissipation type semiconductor package structure and a preparation method thereof are provided, and the preparation steps may include:

[0083] First, as Figure 2 , a first support substrate 110 is provided. For ease of separation, preferably, the surface of the first support substrate 110 has a first separation layer 111.

[0084] Next, as Figure 3 and Figure 4 , a first redistribution layer is formed on the first support substrate 110.

[0085] Among them, as Figure 3A metal seed layer, such as a Ti / Cu metal seed layer, may be first formed on the first support substrate 110. That is, the first metal seed layer 201 may be a Ti layer, and the second metal seed layer 202 may be a Cu layer. Then, as Figure 4 , the first rewiring layer including the first metal wiring 311 and the first dielectric layer 312 is formed on the metal seed layer by electroplating.

[0086] Next, as Figure 4 , a metal pillar 400 and a chip composite structure are formed on the first rewiring layer. The first end of the metal pillar 400 is electrically connected to the first metal wiring 311. The chip composite structure includes a first chip 610 and a second rewiring layer. Among them, the back surface of the first chip 610 contacts the first rewiring layer through a chip adhesive film 500. The second rewiring layer is located on the front surface of the first chip 610 and includes a second metal wiring 321 and a second dielectric layer 322 that are electrically connected to the first chip pad 611.

[0087] Next, as Figure 5 , a first encapsulation layer 710 is formed. The first encapsulation layer 710 includes an opposite first surface and a second surface. The first encapsulation layer 710 covers the metal pillar 400 and the chip composite structure, and the second surface of the first encapsulation layer 710 exposes the second end of the metal pillar 400 and the second metal wiring 321 in the second rewiring layer.

[0088] Next, as Figure 6 , a third rewiring layer is formed on the second surface of the first encapsulation layer 710. The third rewiring layer includes a third metal wiring 331 and a third dielectric layer 332 that are electrically connected to the second end of the metal pillar 400.

[0089] Next, as Figure 6 , a second support substrate 120 is provided and bonded to the third rewiring layer.

[0090] Among them, for the convenience of separation, it is preferred that the surface of the second support substrate 120 has a second separation layer 121. And for the convenience of the bonding between the second support substrate 120 and the third rewiring layer, a substrate adhesive film 122 is provided on the surface of the second separation layer 121.

[0091] Next, as Figure 7 , the first support substrate 110 is removed to expose the first metal wiring 311 in the first rewiring layer. A second chip 620 is formed on the first rewiring layer. The second chip 620 can be electrically connected to the first rewiring layer through a first metal bump 810 that is electrically connected to the second chip pad 621.

[0092] Then, as shown in Figure 7 , a second encapsulation layer 720 is formed, and the second encapsulation layer 720 covers the second chip 620 and the first redistribution layer.

[0093] Next, as shown in Figure 8 , the second support substrate 120 is removed to expose the third redistribution layer.

[0094] After that, as shown in Figure 8 , second metal bumps 820 are formed on the third redistribution layer, and the second metal bumps 820 are electrically connected to the third redistribution layer.

[0095] In the heat-dissipating semiconductor package structure formed in this comparative example, since the back surface of the first chip 610 has the chip adhesive film 500, the heat-dissipating performance of the heat-dissipating semiconductor package structure is poor; and since the first chip 610 is attached to the first redistribution layer through the chip adhesive film 500, in the chip mounting process, the thickness of the first chip 610 needs to be more than 10 μm to avoid the risk of chip breakage, and during the process of manufacturing the heat-dissipating semiconductor package structure, the first chip 610 cannot be thinned either. Therefore, the size of this heat-dissipating semiconductor package structure is also difficult to meet the requirements of miniaturized products.

[0096] Embodiment

[0097] Referring to Figure 9 , this embodiment provides a method for manufacturing a heat-dissipating semiconductor package structure, wherein Figures 10 to 20 schematically shows the structural diagrams presented in each step when manufacturing the heat-dissipating semiconductor package structure. The manufacturing of the heat-dissipating semiconductor package structure will be introduced below with reference to the accompanying drawings of the specification.

[0098] First, referring to Figure 9 and Figure 10 , step S1 is performed to provide a first support substrate 110.

[0099] Specifically, the first support substrate 110 may include, for example, a glass substrate, a metal substrate, a semiconductor substrate, etc., to provide support for subsequent processes through the first support substrate 110. The size of the first support substrate 110 is not limited here, and preferably it is wafer-level.

[0100] Among them, for the convenience of removing the first support substrate 110 subsequently, in this embodiment, preferably, a first separation layer 111 is formed on the surface of the first support substrate 110. The first separation layer 111 includes, but is not limited to, tape and polymer layers. For example, the first separation layer 111 can be a photothermal conversion layer formed by a light-to-heat conversion (LTHC) coating material, so that subsequently, light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the first support substrate 110, improving the convenience of the separation operation.

[0101] Next, refer to Figure 9 , Figure 11 and Figure 12 , and perform step S2 to form metal pillars 400 on the first support substrate 110. The first end of the metal pillar 400 is in contact with the first support substrate 110.

[0102] Specifically, refer to Figure 11 and Figure 12 , in this embodiment, the electroplating method is used to form the metal pillars 400. Thus, a metal seed layer is formed on the surface of the first separation layer 111 by a physical vapor deposition method (PVD). Among them, the metal seed layer can include a first metal seed layer 201 and a second metal seed layer 202 located above the first metal seed layer 201. In this embodiment, the first metal seed layer 201 is a Ti layer, and the second metal seed layer 202 is a Cu layer. However, the types of the metal seed layer are not limited thereto. For example, the metal seed layer can also be a Ti / Ag layer, a Ni / Ti layer, etc., and no excessive limitation is made here. After forming the metal seed layer, a photoresist can be used to form the metal pillars 400 after photolithography and electroplating, and then the photoresist is removed.

[0103] Next, refer to Figure 9 and Figure 12 , and perform step S3 to form a chip composite structure on the first support substrate 110. The chip composite structure includes a first chip 610 and a first redistribution layer. Among them, the back surface of the first chip 610 is bonded to the first support substrate 110 in contact with the chip adhesive film 500, and the first redistribution layer is located on the front surface of the first chip 610 and is electrically connected to the chip pads.

[0104] Specifically, the chip composite structure is combined with the chip adhesive film 500 to be attached to the metal seed layer. The first redistribution layer in the chip composite structure includes a first metal wiring 311 and a first dielectric layer 312. The first metal wiring 311 is electrically connected to a first chip pad 611 on the front side of the first chip 610. The first dielectric layer 312 can be formed of polymers such as polybenzoxazole (PBO) and polyimide, or formed of inorganic dielectric materials such as silicon nitride and silicon oxide. The first metal wiring 311 can include, for example, aluminum, copper, tungsten, or their alloys. There is no excessive limitation on the specific structure and material selection of the first redistribution layer here.

[0105] Among them, for facilitating the subsequent removal and thinning of the first chip 610 by a grinding process, the chip adhesive film 500 is preferably a bonding film material with a relatively hard material, and the specific type can be selected according to needs.

[0106] Next, refer to Figure 9 and Figure 13 , perform step S4 to form a first encapsulation layer 710. The first encapsulation layer 710 includes an opposite first surface and a second surface. The first encapsulation layer 710 covers the metal posts 400 and the chip composite structure, and the second surface of the first encapsulation layer 710 exposes the second ends of the metal posts 400 and the first redistribution layer.

[0107] Specifically, the method for forming the first encapsulation layer 710 can include but is not limited to compression molding, transfer molding, and spin coating. The material of the first encapsulation layer 710 can include but is not limited to epoxy resin and polyamide. There is no excessive limitation on the material and preparation method of the first encapsulation layer 710 here.

[0108] Among them, when forming the first encapsulation layer 710, it can include a grinding step to expose the second ends of the metal posts 400 and the first metal wiring 311. The first redistribution layer can protect the first chip 610 to avoid damaging the first chip 610 due to grinding.

[0109] Next, refer to Figure 9 and Figure 14 , perform step S5 to form a second redistribution layer on the second surface of the first encapsulation layer 710. The second redistribution layer is electrically connected to both the metal posts 400 and the first redistribution layer.

[0110] Specifically, the second rewiring layer includes a second metal wiring 321 and a second dielectric layer 322. The second metal wiring 321 is electrically connected to the second end of the metal pillar 400, and the second metal wiring 321 is electrically connected to the first metal wiring 311. The second dielectric layer 322 can be formed of polymers such as polybenzoxazole (PBO) and polyimide, or inorganic dielectric materials such as silicon nitride and silicon oxide; the second metal wiring 321 can include, for example, aluminum, copper, tungsten, or their alloys, etc. There is no excessive limitation on the specific structure and material selection of the second rewiring layer here.

[0111] Next, refer to Figure 9 and Figure 14 , perform step S6, provide a second support substrate 120, and bond the second support substrate 120 to the second rewiring layer.

[0112] Specifically, the second support substrate 120 can include, for example, a glass substrate, a metal substrate, a semiconductor substrate, etc., to provide support for subsequent processes through the second support substrate 120. There is no limitation on the size of the second support substrate 120 here.

[0113] Among them, for the convenience of removing the second support substrate 120 subsequently, in this embodiment, preferably, a second separation layer 121 is formed on the surface of the second support substrate 120. The second separation layer 121 includes but is not limited to tape and polymer layers. For example, the second separation layer 121 can be selected as a photothermal conversion layer formed of a photothermal conversion (LTHC) coating material, so that subsequently, such as light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the second support substrate 120, improving the convenience of the separation operation.

[0114] Furthermore, preferably, a substrate adhesion film 122 is formed on the surface of the second separation layer 121 to achieve good bonding between the second separation layer 121 and the second rewiring layer through the substrate adhesion film 122. Among them, the substrate adhesion film 122 can include, for example, PBO, polyimide, benzocyclobutene (BCB), or other applicable polymers. After separating the second support substrate 120 subsequently, the substrate adhesion film 122 can be removed by a cleaning solution.

[0115] Next, refer to Figure 9 , Figure 15 and Figure 16 , perform step S7, remove the first support substrate 110, and expose the first end of the metal pillar 400 and the chip adhesion film 500.

[0116] Specifically, as Figure 15, after removing the first support substrate 110, the metal seed layer is removed to expose the chip bonding film 500.

[0117] Next, referring to Figure 9 and Figure 17 , step S8 is performed to grind and remove the chip bonding film 500.

[0118] Specifically, when grinding, the chip bonding film 500 with poor thermal conductivity can be removed to facilitate the heat dissipation of the first chip 610. Then, grinding can be continued to thin the metal pillar 400 and the first chip 610, thereby reducing the package size. Among them, the grinding method can be, for example, chemical mechanical polishing (CMP), etc., and no excessive limitation is made here.

[0119] As an example, the thickness of the first chip 610 after grinding can be 80 μm or less, such as 80 μm, 60 μm, 50 μm, etc., to meet the needs of consumers for thin, light, short, and small products.

[0120] Next, referring to Figure 9 and Figure 18 , step S9 is performed to grind and form a third redistribution layer on the first surface of the first encapsulation layer 710. The third redistribution layer is electrically connected to the metal pillar 400, and the third redistribution layer further includes a dummy metal wiring 333 located on the back surface of the first chip 610 and in contact with the back surface of the first chip 610. The dummy metal wiring 333 constitutes the heat conduction track A of the first chip 610.

[0121] Specifically, the third redistribution layer includes a third dielectric layer 332, a third metal wiring 331, and the dummy metal wiring 333. The third dielectric layer 332 can be formed of polymers such as polybenzoxazole (PBO), polyimide, etc., or formed of inorganic dielectric materials such as silicon nitride, silicon oxide, etc.; the third metal wiring 331 is electrically connected to the first end of the metal pillar 400, and the third metal wiring 331 can include, for example, aluminum, copper, tungsten, or their alloys, etc.

[0122] Among them, it is preferred that the dummy metal wiring 333 is prepared synchronously with the third metal wiring 331 in the third redistribution layer. Thus, without increasing the process steps, the heat conduction track A in contact with the back surface of the first chip 610 can be formed on the back surface of the first chip 610 to facilitate the heat dissipation of the first chip 610. Of course, the dummy metal wiring 333 can also be prepared separately, and no excessive limitation is made here.

[0123] Preferably, the vertical projection of the virtual metal wiring 333 covers the heat source area of the first chip 610, so as to achieve good heat dissipation for the heat source area of the first chip 610.

[0124] No excessive restrictions are imposed here on the specific structures and material selections of the third dielectric layer 332, the third metal wiring 331, and the virtual metal wiring 333 in the third rewiring layer.

[0125] Next, referring to Figure 9 and Figure 19 , perform step S10 to form a second chip 620 and a metal heat sink 900 on the third rewiring layer. The second chip 620 is electrically connected to the third rewiring layer, and the metal heat sink 900 is in contact with the heat conduction rail A.

[0126] Among them, the second chip pad 621 of the second chip 620 can be electrically connected to the third metal wiring 331 through a first metal bump 810 such as a solder ball bump, but is not limited thereto. The metal heat sink 900 can be attached to the third rewiring layer through a thermal adhesive layer 830 such as an indium sheet, thermal paste, or a Cu / Sn adhesive layer formed by the Bump process, etc., so as to achieve heat transfer between the metal heat sink 900 and the heat conduction rail A while attaching the metal heat sink 900. The attachment sequence of the second chip 620 and the metal heat sink 900 is not limited here.

[0127] Preferably, the vertical projections of the virtual metal wiring 333 and the metal heat sink 900 cover the heat source area of the first chip 610, so as to achieve good heat dissipation for the heat source area of the first chip 610.

[0128] Next, referring to Figure 9 and Figure 19 , perform step S11 to form a second encapsulation layer 720. The second encapsulation layer 720 covers the second chip 620, the metal heat sink 900, and the third rewiring layer, so as to protect the second chip 620 and the third rewiring layer through the second encapsulation layer 720.

[0129] Specifically, the method for forming the second encapsulation layer 720 may include but is not limited to compression molding, transfer molding, and spin coating. The material of the second encapsulation layer 720 may include but is not limited to epoxy resin and polyamide. No excessive restrictions are imposed here on the material and preparation method of the second encapsulation layer 720.

[0130] Next, referring to Figure 9 and Figure 20, perform step S12 to remove the second support substrate 120, exposing the second redistribution layer.

[0131] Next, refer to Figure 9 and Figure 20 , perform step S13 to form second metal bumps 820 on the second redistribution layer, and the second metal bumps 820 are electrically connected to the second metal wirings 321 in the second redistribution layer.

[0132] Among them, the second metal bumps 820 may include solder ball bumps, C4 metal bumps, copper pillar bumps, etc., and the specific types and materials of the metal bumps are not overly restricted here.

[0133] Refer to Figures 21 to 23 , the formed metal heat sink 900 may include a plate-shaped metal heat sink or a block-shaped metal heat sink, and the morphology formed by the metal heat sink 900 may be one or a combination of a ring shape, a plate shape, and a block shape, which can be specifically set according to needs. Refer to Figure 20 , the present invention also provides a heat dissipation type semiconductor package structure, and the heat dissipation type semiconductor package structure includes:

[0134] A metal pillar 400, the metal pillar 400 includes opposite first and second ends;

[0135] A chip composite structure, the chip composite structure includes a first chip 610 and a first redistribution layer, and the first redistribution layer is located on the front surface of the first chip 610 and is electrically connected to the chip pads;

[0136] A first encapsulation layer 710, the first encapsulation layer 710 includes opposite first and second surfaces, the first encapsulation layer 710 covers the metal pillar 400 and the chip composite structure, and the second surface of the first encapsulation layer 710 exposes the second end of the metal pillar 400 and the first redistribution layer;

[0137] A second redistribution layer, the second redistribution layer is located on the second surface of the first encapsulation layer 710, and the second redistribution layer is electrically connected to both the metal pillar 400 and the first redistribution layer;

[0138] A third redistribution layer, the third redistribution layer is located on the first surface of the first encapsulation layer 710, the third redistribution layer is electrically connected to the first end of the metal pillar 400, and the third redistribution layer further includes a virtual metal wiring 333 located on the back surface of the first chip 610 and in contact with the back surface of the first chip 610, and the virtual metal wiring 333 constitutes a heat conduction rail A of the first chip 610;

[0139] A second chip 620, which is located on the third redistribution layer and is electrically connected to the third redistribution layer;

[0140] A metal heat sink 900, which is located on the third redistribution layer and is in contact with the heat conduction rail A;

[0141] A second encapsulation layer 720, which encapsulates the second chip 620 and the third redistribution layer;

[0142] Metal bumps, which are located on the second redistribution layer and are electrically connected to the second redistribution layer.

[0143] Wherein, the metal heat sink 900 can be attached to the third redistribution layer through a thermal conductive adhesive layer 830, such as an indium sheet, a thermal conductive adhesive, a Cu / Sn adhesive layer formed by using the Bump process, etc., so as to realize the heat transfer between the metal heat sink 900 and the heat conduction rail A while attaching the metal heat sink 900.

[0144] Specifically, the preparation method of the heat dissipation type semiconductor package structure can adopt the above steps for preparation, but is not limited thereto. In this embodiment, the above preparation process is directly adopted to prepare the heat dissipation type semiconductor package structure. Therefore, regarding the preparation, materials and specific structure of the heat dissipation type semiconductor package structure, etc., reference can be made to the above steps, which will not be elaborated here.

[0145] As an example, the thickness of the first chip 610 can be 80 μm or less, such as 80 μm, 60 μm, 50 μm, etc., to meet the needs of consumers for thin, light, short and small products.

[0146] As an example, the virtual metal wiring 333 and the metal wiring in the third redistribution layer have the same material, so that the virtual metal wiring 333 and the metal wiring in the third redistribution layer can be prepared synchronously to reduce the complexity of process control.

[0147] As an example, the virtual metal wiring 333 can include one or a combination of a capacitor and an inductor, so as to realize good heat dissipation while realizing the functions of the capacitor and the inductor.

[0148] As an example, the projections of the virtual metal wiring 333 and the metal heat sink 900 along the vertical direction cover the heat source area of the first chip 610, so as to realize good heat dissipation for the heat source area of the first chip 610.

[0149] In summary, for the heat-dissipating semiconductor package structure and its manufacturing method of the present invention, a virtual metal wiring with good thermal conductivity is formed on the back surface of the first chip while preparing the third redistribution layer to form a heat conduction rail in contact with the first chip, and a metal heat sink in contact with the heat conduction rail is formed to manufacture a heat-dissipating semiconductor package structure with good thermal conductivity; while removing the chip bonding film with poor thermal conductivity, the first chip is thinned, which can meet the consumer demand for thin, light, short, and small products; further, the heat conduction rail may further include a capacitor and / or an inductor formed while preparing the third redistribution layer, so as to achieve heat dissipation while realizing the functions of the capacitor and the inductor, reduce costs, and reduce the package size.

[0150] The above embodiments merely illustrate the principles and effects of the present invention, rather than limiting the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a heat-dissipating semiconductor packaging structure, characterized in that, Including the following steps: Providing a first support substrate; Forming metal pillars on the first support substrate, with the first ends of the metal pillars in contact with the first support substrate; Forming a chip composite structure on the first support substrate, the chip composite structure including a first chip and a first redistribution layer. Wherein, the back surface of the first chip is bonded to the first support substrate through a chip adhesive film, and the first redistribution layer is located on the front surface of the first chip and is electrically connected to chip pads; Forming a first encapsulation layer, the first encapsulation layer including an opposite first surface and a second surface, the first encapsulation layer covering the metal pillars and the chip composite structure, and the second surface of the first encapsulation layer exposing the second ends of the metal pillars and the first redistribution layer; Forming a second redistribution layer on the second surface of the first encapsulation layer, the second redistribution layer being electrically connected to both the metal pillars and the first redistribution layer; Providing a second support substrate and bonding the second support substrate to the second redistribution layer; Removing the first support substrate to expose the first ends of the metal pillars and the chip adhesive film; Performing grinding to remove the chip adhesive film; Forming a third redistribution layer on the first surface of the first encapsulation layer, the third redistribution layer being electrically connected to the metal pillars, and the third redistribution layer further including virtual metal wirings located on and in contact with the back surface of the first chip, and a heat conduction track of the first chip is formed through the virtual metal wirings; Forming a second chip and a metal heat sink on the third redistribution layer, the second chip being electrically connected to the third redistribution layer, and the metal heat sink being in contact with the heat conduction track; Forming a second encapsulation layer, the second encapsulation layer covering the second chip, the metal heat sink and the third redistribution layer; Removing the second support substrate to expose the second redistribution layer; Forming metal bumps on the second redistribution layer, the metal bumps being electrically connected to the second redistribution layer.

2. The manufacturing method of the heat-dissipating semiconductor package structure according to claim 1, wherein: After performing grinding to remove the chip adhesive film, it further includes continuing to perform grinding to thin the first chip.

3. The manufacturing method of the heat-dissipating semiconductor package structure according to claim 2, characterized in that: The thickness of the ground first chip is 80 μm or less.

4. The manufacturing method of the heat dissipation type semiconductor package structure according to claim 1, characterized in that: The virtual metal wirings are prepared synchronously with the metal wirings in the third redistribution layer.

5. The preparation method of the heat dissipation type semiconductor package structure according to claim 1, wherein: The vertical projections of the metal heat sink and the virtual metal wirings cover the heat source area of the first chip.

6. The manufacturing method of the heat dissipation type semiconductor package structure according to claim 1, characterized in that: The virtual metal wirings include one or a combination of capacitors and inductors; the metal heat sink includes a plate-shaped metal heat sink or a block-shaped metal heat sink.

7. A heat-dissipating semiconductor package structure, characterized in that, The heat dissipation type semiconductor package structure includes: Metal pillars, the metal pillars including opposite first ends and second ends; A chip composite structure, the chip composite structure including a first chip and a first redistribution layer, the first redistribution layer being located on the front surface of the first chip and being electrically connected to chip pads; A first encapsulation layer, the first encapsulation layer including an opposite first surface and a second surface, the first encapsulation layer covering the metal pillars and the chip composite structure, and the second surface of the first encapsulation layer exposing the second ends of the metal pillars and the The first redistribution layer; The second redistribution layer, which is located on the second surface of the first encapsulation layer, and the second redistribution layer is electrically connected to both the metal posts and the first redistribution layer; The third redistribution layer, which is located on the first surface of the first encapsulation layer, and the third redistribution layer is electrically connected to the first end of the metal posts, and the third redistribution layer further includes virtual metal wirings located on the back surface of the first chip and in contact with the back surface of the first chip, and the heat conduction rails of the first chip are formed through the virtual metal wirings; The second chip, which is located on the third redistribution layer, and the second chip is electrically connected to the third redistribution layer; The metal heat sink, which is located on the third redistribution layer, and the metal heat sink is in contact with the heat conduction rails; The second encapsulation layer, which covers the second chip and the third redistribution layer; The metal bumps, which are located on the second redistribution layer and electrically connected to the second redistribution layer.

8. The heat dissipating semiconductor package structure according to claim 7, wherein: The thickness of the first chip is 80 μm or less.

9. The heat-dissipating semiconductor package structure according to claim 7, wherein: The virtual metal wirings and the metal wirings in the third redistribution layer have the same material; the virtual metal wirings include one or a combination of a capacitor and an inductor; the metal heat sink includes a plate-shaped metal heat sink or a block-shaped metal heat sink.

10. The heat dissipating semiconductor package structure according to claim 7, wherein: The projections of the metal heat sink and the virtual metal wirings in the vertical direction cover the heat source area of the first chip.

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