Three-dimensional memory and electronic equipment

Abstract

The embodiment of the invention provides a three-dimensional memory and electronic equipment, the three-dimensional memory comprises a first chip and a second chip which are arranged along a third direction, the first chip comprises a memory array area and a non-memory array area, and the second chip comprises a control device area; the projection of the control device area in the third direction covers the non-storage array area; the non-storage array area of the first chip comprises a plurality of vertical capacitor structures, each vertical capacitor structure is formed between the first wiring layer and the second wiring layer of the first chip, and the first wiring layer, the storage unit array in the storage array area and the second wiring layer are sequentially arranged in the third direction.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and in particular, to a three-dimensional memory and an electronic device. Background Art

[0002] A single wafer structure refers to integrating all devices in a memory onto a single chip. In a single wafer structure, a comb structure is often made of metal wiring to prepare a Metal-Oxide-Metal (MOM) capacitor structure, which results in a large amount of memory area being required for the capacitor structure region, causing waste of the memory area. Summary of the Invention

[0003] Embodiments of the present disclosure provide a three-dimensional memory and an electronic device.

[0004] In a first aspect, embodiments of the present disclosure provide a three-dimensional memory. The three-dimensional memory includes a first chip and a second chip arranged along a third direction. The first chip includes a memory array region and a non-memory array region, and the second chip includes a control device region; a projection of the control device region along the third direction covers the non-memory array region;

[0005] The non-memory array region of the first chip includes a plurality of vertical capacitor structures. Each vertical capacitor structure is formed between a first wiring layer and a second wiring layer of the first chip, and the first wiring layer, a memory cell array in the memory array region, and the second wiring layer are arranged in sequence along the third direction.

[0006] In some embodiments, the vertical capacitor structure includes a plurality of first metal structures, a plurality of second metal structures, and a dielectric material, and the dielectric material fills between the plurality of first metal structures and the plurality of second metal structures;

[0007] The plurality of first metal structures are all located on the first wiring layer of the first chip. Each first metal structure extends along a first direction, and the plurality of first metal structures are arranged in parallel along a second direction; the plurality of second metal structures are all located on the second wiring layer of the first chip. Each second metal structure extends along the second direction, and the plurality of second metal structures are arranged in parallel along the first direction;

[0008] Each second metal structure is electrically connected to at least two first metal structures. The first metal structures electrically connected by adjacent second metal structures are arranged in a staggered manner along the second direction, and adjacent second metal structures are not electrically connected to the same first metal structure;

[0009] Wherein, the first direction and the second direction intersect.

[0010] In some embodiments, the first metal structures are numbered along the second direction, and the second metal structures are numbered along the first direction;

[0011] For each second metal structure with an odd number, it is electrically connected to all the first metal structures with odd numbers through a plurality of first contact structures one by one, so as to form one electrode of the vertical capacitor structure;

[0012] For each second metal structure with an even number, it is electrically connected to all the first metal structures with even numbers through a plurality of second contact structures one by one, so as to form the other electrode of the vertical capacitor structure.

[0013] In some embodiments, along the first direction, the first contact structures and the second contact structures are alternately distributed in sequence;

[0014] Along the second direction, the first contact structures and the second contact structures are alternately distributed in sequence.

[0015] In some embodiments, the first chip includes a plurality of first bonding structure groups, and each vertical capacitor structure is coupled to one of the first bonding structure groups;

[0016] The first bonding structure group includes a first bonding structure and a second bonding structure. All the first contact structures in the vertical capacitor structure are coupled to the first bonding structure, and all the second contact structures in the vertical capacitor structure are coupled to the second bonding structure;

[0017] The second chip includes a plurality of second bonding structure groups, and each first bonding structure group is coupled to one of the second bonding structure groups;

[0018] The second bonding structure group includes a third bonding structure and a fourth bonding structure, and the third bonding structure is bonded to the first bonding structure, and the fourth bonding structure is bonded to the second bonding structure.

[0019] In some embodiments, for some of the first bonding structure groups, they are coupled to output driving devices in the second chip, and the third bonding structure is used to transmit a power signal, and the fourth bonding structure is used to transmit a ground signal.

[0020] In some embodiments, the first chip further includes a plurality of comb-shaped capacitor structures, and the vertical capacitor structures and the comb-shaped capacitor structures are arranged in sequence along the third direction;

[0021] Each of the comb-shaped capacitor structures includes a first comb-shaped electrode and a second comb-shaped electrode, and the comb teeth portions of the first comb-shaped electrode and the comb teeth portions of the second comb-shaped electrode are alternately arranged in parallel.

[0022] In some embodiments, the first comb-shaped electrode includes a first comb-shaped sub-electrode, a second comb-shaped sub-electrode, and a third comb-shaped sub-electrode; the second comb-shaped electrode includes a fourth comb-shaped sub-electrode, a fifth comb-shaped sub-electrode, and a sixth comb-shaped sub-electrode;

[0023] Wherein, the first comb-shaped sub-electrode and the fourth comb-shaped sub-electrode are both formed on the second wiring layer, and the comb teeth portions of the first comb-shaped sub-electrode and the comb teeth portions of the fourth comb-shaped sub-electrode are alternately arranged in parallel; the second comb-shaped sub-electrode and the fifth comb-shaped sub-electrode are both formed on the third wiring layer, and the comb teeth portions of the second comb-shaped sub-electrode and the comb teeth portions of the fifth comb-shaped sub-electrode are alternately arranged in parallel; the third comb-shaped sub-electrode and the sixth comb-shaped sub-electrode are both formed on the fourth wiring layer, and the comb teeth portions of the third comb-shaped sub-electrode and the comb teeth portions of the sixth comb-shaped sub-electrode are alternately arranged in parallel;

[0024] The second wiring layer, the third wiring layer, and the fourth wiring layer are sequentially arranged along the third direction.

[0025] In some embodiments, the distance between the first wiring layer and the second wiring layer along the third direction is greater than the distance between the second wiring layer and the third wiring layer along the third direction;

[0026] Moreover, the distance between the first wiring layer and the second wiring layer along the third direction is greater than the distance between the third wiring layer and the fourth wiring layer along the third direction.

[0027] In some embodiments, the first contact structure and the second contact structure are long contact holes.

[0028] In a second aspect, an embodiment of the present disclosure provides an electronic device, and the electronic device includes the three-dimensional memory according to any one of the first aspect.

[0029] Embodiments of the present disclosure provide a three-dimensional memory and a memory. The three-dimensional memory includes a first chip and a second chip arranged along a third direction. The first chip includes a storage array region and a non-storage array region, and the second chip includes a control device region. The projection of the control device region along the third direction covers the non-storage array region. The non-storage array region of the first chip includes a plurality of vertical capacitor structures, each vertical capacitor structure is formed between a first wiring layer and a second wiring layer of the first chip, and the first wiring layer, the memory cell array in the storage array region, and the second wiring layer are arranged in sequence along the third direction. In this way, by fabricating a plurality of vertical capacitor structures in the non-storage array region of the first chip, the total capacitance value can be increased and the area can be saved. Description of the Drawings

[0030] Figure 1 Schematic diagram of the composition structure of a chip structure Figure 1 ;

[0031] Figure 2 Schematic diagram of the composition structure of a chip structure Figure 2 ;

[0032] Figure 3 Schematic diagram of the composition structure of a capacitor structure Figure 1 ;

[0033] Figure 4 Schematic diagram of the composition structure of a capacitor structure Figure 2 ;

[0034] Figure 5 Schematic diagram of the composition structure of a three-dimensional memory provided by an embodiment of the present disclosure Figure 1 ;

[0035] Figure 6 Schematic three-dimensional structure diagram of a vertical capacitor structure provided by an embodiment of the present disclosure;

[0036] Figure 7 Schematic diagram of the composition structure of a vertical capacitor structure provided by an embodiment of the present disclosure Figure 1 ;

[0037] Figure 8 Schematic diagram of the composition structure of a vertical capacitor structure provided by an embodiment of the present disclosure Figure 2 ;

[0038] Figure 9 Schematic diagram of the composition structure of a three-dimensional memory provided by an embodiment of the present disclosure Figure 2 ;

[0039] Figure 10 Schematic three-dimensional structure diagram of a comb-shaped capacitor structure provided by an embodiment of the present disclosure;

[0040] Figure 11Schematic diagram of the composition structure of a 3D memory provided by an embodiment of the present disclosure Figure 3 ;

[0041] Figure 12 Schematic diagram of the composition structure of an electronic device provided by an embodiment of the present disclosure. Detailed implementation manners

[0042] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the relevant application, rather than limiting the present disclosure. In addition, it should be noted that for the convenience of description, only the parts related to the relevant application are shown in the drawings.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0044] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0045] It should be noted that the terms "first / second / third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0046] See Figure 1 , which shows a schematic diagram of the composition structure of a chip structure Figure 1 . As Figure 1 shown, the chip structure is specifically a single-chip structure 10. The single-chip structure 10 includes a memory array (Cell Array) area 111 and a peripheral circuit area (Peripheral Area) 112, and the memory array area 111 is distributed on both sides of the peripheral circuit area 112. In the single-chip structure 10, the memory array area 111 includes not only memory cells (Memory Cell, Cell), but also devices such as sense amplifiers (Sense Amplifier, SA), sub-word line drivers (Sub Wordline Driver, SWD), and input / output amplifier drivers (IOSADRV).

[0047] Furthermore, the devices integrated on one chip can be separately fabricated on two chips. SeeFigure 2 , which shows a schematic composition structure of a chip structure Figure 2 . As Figure 2 shown, the chip structure is specifically a Wafer on Wafer (WoW) structure 20. The WoW structure 20 includes two chips, one of which is a cell array wafer, which can also be called an AG1 chip 21, and the other is a logic wafer, which can also be called an AG2 chip 22. The AG1 chip 21 and the AG2 chip 22 can be connected together through a bonding technology.

[0048] It should be noted that the AG1 chip 21 includes a storage array area 211 and an intermediate area 212. The storage array area 211 is distributed on both sides of the intermediate area 212. The storage array area 211 only includes storage cells, and there are no devices in the intermediate area 212, which is a blank area and is a complementary metal oxide semiconductor free zone (CMOS Free Zone). The intermediate area 212 can also be called a non-storage array area (CMOS Free Zone). Since the intermediate area 212 is empty, devices such as capacitor structures and resistor structures can be fabricated in the intermediate area 212, and no specific limitations are imposed on this.

[0049] It should also be noted that the AG2 chip 22 includes a redistribution area 221 and a peripheral circuit area 222. The redistribution area 221 is located on both sides of the peripheral circuit area 222. The storage array area 211 of the AG1 chip 21 only includes storage cells, and other devices such as SA, SWD, and IOSA DRV included in the storage array area 111 of the single-chip structure 10 are placed in the redistribution area 221 of the AG2 chip 22; the composition structures of the peripheral circuit area 222 of the AG2 chip 22 and the peripheral circuit area 112 of the single-chip structure 10 are the same.

[0050] It should also be noted that after changing the single-chip structure 10 to the WoW structure 20, the original storage array area in the AG1 chip 21 (i.e., the storage array area 111 of the single-chip structure 10) now only includes storage cells, and the metal wirings at the positions where devices such as SA and SWD were made in the original single-chip structure 10 need to be re-routed and connected to the devices such as SA and SWD on the AG2 chip 22; and in the original storage array area of the AG2 chip 22, now only includes devices such as SA and SWD and no storage cells, so the corresponding metal wirings also need to be re-routed. These metal wirings that need to be re-routed in the AG1 chip 21 and the AG2 chip 22 are called the redistribution area 221.

[0051] See Figure 3 , which shows a schematic composition structure of a capacitive structure Figure 1 . As Figure 3 shown, the capacitive structure 30 is specifically a MOM capacitive structure, which includes a first comb-shaped electrode 31 and a second comb-shaped electrode 32, and the comb teeth portions of the first comb-shaped electrode 31 and the second comb-shaped electrode 32 are alternately arranged in parallel. Among them, the first comb-shaped electrode 31 includes a first comb-shaped sub-electrode 311, a second comb-shaped sub-electrode 312, and a third comb-shaped sub-electrode 313, and the second comb-shaped electrode 32 includes a fourth comb-shaped sub-electrode 321, a fifth comb-shaped sub-electrode 322, and a sixth comb-shaped sub-electrode 323; the first comb-shaped sub-electrode 311 and the fourth comb-shaped sub-electrode 321 are formed on the M1 layer, the second comb-shaped sub-electrode 312 and the fifth comb-shaped sub-electrode 322 are formed on the M2 layer, and the third comb-shaped sub-electrode 313 and the sixth comb-shaped sub-electrode 323 are formed on the M3 layer.

[0052] It should be noted that the capacitive structure 30 is located in the chip of the single-chip structure. In addition, Figure 3 the hollow part in

[0053] is also filled with materials. Figure 4 See further Figure 2 , which shows a schematic composition structure of a capacitive structure Figure 4 , specifically a top view of the capacitive structure 30. As Figure 4 shown, exemplarily, 5 comb teeth portions of the first comb-shaped electrode 31 and 5 comb teeth portions of the second comb-shaped electrode 32 are alternately arranged in parallel.

[0054] In summary, the metal wirings in the metal wiring layers M1, M2, and M3 are made into a comb-shaped structure to prepare the MOM capacitive structure, but a large area is required to make the capacitive structure region, resulting in waste of area.

[0055] Based on this, the embodiments of the present disclosure provide a three-dimensional memory, which includes a first chip and a second chip arranged along a third direction. The first chip includes a storage array area and a non-storage array area, and the second chip includes a control device area; the projection of the control device area along the third direction covers the non-storage array area; the non-storage array area of the first chip includes a plurality of vertical capacitive structures, and each vertical capacitive structure is formed between the first wiring layer and the second wiring layer of the first chip, and the first wiring layer, the memory cell array in the storage array area, and the second wiring layer are arranged in sequence along the third direction. In this way, by preparing the capacitive structure in the single-chip structure in the WoW structure and preparing a plurality of vertical capacitive structures in the non-storage array area of the first chip in the WoW structure, the total capacitance value can be increased, and based on the increased total capacitance value, the area can be saved compared with only preparing the MOM capacitive structure.

[0056] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0057] In one embodiment of the present disclosure, referring to Figure 5 , which shows a schematic composition structure of a three-dimensional memory provided by an embodiment of the present disclosure Figure 1 . As Figure 5 shown, the three-dimensional memory 40 may include a first chip 41 and a second chip 42 arranged along a third direction. The first chip 41 includes a memory array region 411 and a non-memory array region 412, and the second chip 42 includes a control device region 421; the projection of the control device region 421 along the third direction covers the non-memory array region 412;

[0058] The non-memory array region 412 of the first chip 41 includes a plurality of vertical capacitor structures 50. Each vertical capacitor structure 50 is formed between a first wiring layer and a second wiring layer of the first chip 41, and the first wiring layer, the memory cell array in the memory array region 411, and the second wiring layer are arranged in sequence along the third direction.

[0059] In the embodiment of the present disclosure, the three-dimensional memory 40 relates to the field of semiconductor integrated circuits, particularly to the layout design of integrated chips. Specifically, long contact holes are used to form vertical capacitor structures, which can be applied to circuits that require passive high-frequency capacitors, but no specific limitation is made thereto. Additionally, the three-dimensional memory 40 may be a dynamic random access memory (DRAM), but no specific limitation is made thereto.

[0060] Here, the first wiring layer is denoted as M0, and the second wiring layer is denoted as M1.

[0061] It should be noted that a semiconductor chip may include a top surface on the front side and a bottom surface on the back side opposite to the front side; in the case of ignoring the flatness of the top surface and the bottom surface, the direction intersecting (e.g., perpendicular) with the top surface and the bottom surface of the semiconductor chip is defined as the third direction.

[0062] It should also be noted that the first chip 41 may also be referred to as a memory array chip, and the second chip 42 may also be referred to as a logic chip. The first chip 41 and the second chip 42 form a WoW structure. The non-memory array region 412 in the original first chip 41 was empty, so a plurality of vertical capacitor structures 50 can be fabricated in the non-memory array region 412 of the first chip 41. Additionally, the non-memory array region 412 is located in the middle region of the first chip 41, and the memory array region 411 is located on both sides of the non-memory array region 412.

[0063] It should also be noted that, as Figure 5As shown, the second chip 42 may further include a storage array region 422, which is located on both sides of the control device region 421.

[0064] It should also be noted that the control device region 421 may also be referred to as a peripheral circuit region. The control device region 421 includes output driver devices around the data pads (DQ Pads), and no specific limitations are imposed thereon. In addition, the projection of the control device region 421 along the third direction covers the non-storage array region 412. That is to say, the projection of the vertical capacitor structure 50 along the third direction is located within the projection of the control device region 421 along the third direction, and its projection will not exceed the non-storage array region 412 and will not extend to the storage array region 411.

[0065] Here, the storage array region 411 includes a storage cell array, and the storage cell array includes a plurality of storage cells arranged in rows and columns.

[0066] As Figure 5 shown, a plurality of vertical capacitor structures 50 are fabricated in the non-storage array region 412 of the first chip 41. Each vertical capacitor structure 50 is formed between the M0 layer and the M1 layer of the first chip 41, thereby increasing the capacitance value.

[0067] Regarding the vertical capacitor structure 50, in some embodiments, refer to Figure 6 , which shows a schematic three-dimensional structure diagram of a vertical capacitor structure provided by an embodiment of the present disclosure. As Figure 6 shown, the vertical capacitor structure 50 may include a plurality of first metal structures 51, a plurality of second metal structures 52, and a dielectric material, and the dielectric material is filled between the plurality of first metal structures 51 and the plurality of second metal structures 52;

[0068] The plurality of first metal structures 51 are all located on the first wiring layer of the first chip 41. Each first metal structure 51 extends along the first direction, and the plurality of first metal structures 51 are arranged in parallel along the second direction; the plurality of second metal structures 52 are all located on the second wiring layer of the first chip 41. Each second metal structure 52 extends along the second direction, and the plurality of second metal structures 52 are arranged in parallel along the first direction;

[0069] Each second metal structure 52 is electrically connected to at least two first metal structures 51. The first metal structures 51 electrically connected by adjacent second metal structures 52 are arranged in a staggered manner along the second direction, and adjacent second metal structures 52 are not electrically connected to the same first metal structure 51;

[0070] Among them, the first direction and the second direction intersect.

[0071] Exemplarily, Figure 6Only 4 first metal structures 51 and 4 of the plurality of second metal structures 52 are shown.

[0072] It should be noted that a first direction and a second direction are defined on the top surface of the semiconductor chip. That is to say, a third direction is perpendicular to the plane where the first direction and the second direction are located. In addition, the first direction and the second direction intersect. The first direction and the second direction may be perpendicular to each other or intersect at other angles, and no specific limitation is made thereto. Exemplarily, taking the first direction and the second direction being perpendicular to each other as an example, the specific implementation of the embodiments of the present disclosure will be described in detail.

[0073] It should also be noted that the hollow portions in the vertical capacitor structure 50 are all filled with a dielectric material. Exemplarily, the dielectric material may be alumina, or silicon dioxide, or other materials, and no specific limitation is made thereto.

[0074] Furthermore, in some embodiments, as Figure 6 shown, the vertical capacitor structure 50 may further include a plurality of first contact structures 53 and a plurality of second contact structures 54. The first metal structures 51 are numbered along the second direction, and the second metal structures 52 are numbered along the first direction;

[0075] For each second metal structure 52 with an odd number, it is electrically connected to all the first metal structures 51 with odd numbers one by one through a plurality of first contact structures 53 to form one electrode of the vertical capacitor structure 50;

[0076] For each second metal structure 52 with an even number, it is electrically connected to all the first metal structures 51 with even numbers one by one through a plurality of second contact structures 54 to form the other electrode of the vertical capacitor structure 50.

[0077] Exemplarily, Figure 6 only 4 first contact structures 53 and 4 of the plurality of second contact structures 54 are shown, and only 1 first contact structure and 1 second contact structure are labeled, and the remaining first contact structures and second contact structures are not labeled.

[0078] In addition, as Figure 6As shown, the first metal structures 51 are numbered 51-1, 51-2, 51-3, and 51-4 along the second direction. Among them, the first metal structure 51-1 and the first metal structure 51-3 represent the first metal structures 51 with odd numbers, and the first metal structure 51-2 and the first metal structure 51-4 represent the first metal structures 51 with even numbers. Similarly, the second metal structures 52 are numbered 52-1, 52-2, 52-3, and 52-4 along the first direction. Among them, the second metal structure 52-1 and the second metal structure 52-3 represent the second metal structures 52 with odd numbers, and the second metal structure 52-2 and the second metal structure 52-4 represent the second metal structures 52 with even numbers.

[0079] It should be noted that the second metal structure 52-1 is electrically connected to the first metal structure 51-1 and the first metal structure 51-3 through two first contact structures 53, and the second metal structure 52-3 is also electrically connected to the first metal structure 51-1 and the first metal structure 51-3 through another two first contact structures 53. The projections of these four first contact structures 53 in the third direction are located at different positions. The second metal structure 52-2 is electrically connected to the first metal structure 51-2 and the first metal structure 51-4 through two second contact structures 54, and the second metal structure 52-4 is also electrically connected to the first metal structure 51-2 and the first metal structure 51-4 through another two second contact structures 54. The projections of these four second contact structures 54 in the third direction are located at different positions.

[0080] It should also be noted that the second metal structure 52-1 is electrically connected to the first metal structure 51-1 and the first metal structure 51-3, the second metal structure 52-2 is electrically connected to the first metal structure 51-2 and the first metal structure 51-4, and the first metal structures 51-1, 51-2, 51-3, and 51-4 to which the second metal structure 52-1 and the second metal structure 52-2 are electrically connected are arranged alternately along the second direction.

[0081] See Figure 7 which shows a schematic composition structure of a vertical capacitance structure provided by an embodiment of the present disclosure Figure 1 specifically Figure 6 is a schematic vertical cross-sectional view along the first direction of the three-dimensional structure of the vertical capacitance structure 50 shown. Exemplarily, Figure 7 shows the second metal structure 52-2 to the second metal structure 52-5, as well as the first metal structure 51-1 and the first metal structure 51-2.

[0082] As Figure 7As shown, the first metal structures 51-2 electrically connected to the second metal structure 52-2 and the first metal structures 51-1 electrically connected to the second metal structure 52-3 are arranged alternately along the second direction, and the adjacent second metal structures 52-1 and 52-2 are not electrically connected to the same first metal structure.

[0083] Further, in some embodiments, referring to Figure 8 , which shows a schematic composition structure of a vertical capacitor structure provided by an embodiment of the present disclosure Figure 2 , specifically Figure 6 is a top view schematic diagram of the three-dimensional structure of the vertical capacitor structure 50 shown. As Figure 8 shown, along the first direction, the first contact structures 53 and the second contact structures 54 ( Figure 8 only one label 53 and 54 are marked in

[0084] Exemplarily, Figure 8 shows 6 first metal structures 51 (specifically 51-1 to 51-6), 4 second metal structures 52 (specifically 52-1 to 52-4), 6 first contact structures 53 and 6 second contact structures 54. Each second metal structure 52 with an odd number is electrically connected to 3 first metal structures 51 with odd numbers through 3 first contact structures 53 one by one, and each second metal structure 52 with an even number is electrically connected to 3 first metal structures 51 with even numbers through 3 second contact structures 54 one by one.

[0085] In some embodiments, referring to Figure 9 , which shows a schematic composition structure of a three-dimensional memory provided by an embodiment of the present disclosure Figure 2 . As Figure 9 shown, the first chip 41 may include a plurality of first bonding structure groups 61, and each vertical capacitor structure 50 is coupled to one first bonding structure group 61;

[0086] The first bonding structure group 61 includes a first bonding structure 611 and a second bonding structure 612. All the first contact structures 53 in the vertical capacitor structure 50 are coupled to the first bonding structure 611, and all the second contact structures 54 in the vertical capacitor structure 50 are coupled to the second bonding structure 612 ( Figure 9 only one label 53 and 54 are marked in

[0087] The second chip 42 includes a plurality of second bonding structure groups 62, and each first bonding structure group 61 is coupled to one second bonding structure group 62;

[0088] The second bonding structure group 62 includes a third bonding structure 621 and a fourth bonding structure 622, and the third bonding structure 621 is bonded to the first bonding structure 611, and the fourth bonding structure 622 is bonded to the second bonding structure 612.

[0089] Specifically, as Figure 9 shown, all the first contact structures 53 in the vertical capacitor structure 50 are first coupled to the second wiring layer M1, then sequentially coupled to the third wiring layer M2 and the fourth wiring layer M3 through the M1 layer, and then coupled to the first bonding structure 611 through the M3 layer; all the second contact structures 54 in the vertical capacitor structure 50 are first coupled to the M1 layer, then sequentially coupled to the M2 layer and the M3 layer through the M1 layer, and then coupled to the second bonding structure 612 through the M3 layer.

[0090] It should be noted that the first bonding structure 611 can be bonded to the third bonding structure 621 through a hybrid bonding structure (Hybrid Bonding PAD), or can be bonded to the third bonding structure 621 through other bonding technologies, such as conductive bumps, etc., and no specific limitation is made thereto. Similarly, the second bonding structure 612 can be bonded to the fourth bonding structure 622 through a hybrid bonding structure, or can be bonded to the fourth bonding structure 622 through other bonding technologies, and no specific limitation is made thereto either.

[0091] It should also be noted that, as Figure 9 shown, the memory array region in the first chip 41 can also be bonded to the memory array region in the second chip 42 through the M1 layer, the M2 layer, the M3 layer and the hybrid bonding structure. Here, the memory array region in the first chip 41 only includes memory cells, and the memory array region in the second chip 42 includes devices such as a row decoder (X-Decoder, XDEC), a bit line sense amplifier (Bit Line Sense Amplifier, BLSA), SWD, etc., but does not include memory cells. Specifically, the memory cells in the memory array region in the first chip 41 are bonded to the BLSA or X-DEC devices in the memory array region in the second chip 42. In addition, Figure 9 only the specific connection relationship between the memory array regions in the first chip 41 and the second chip 42 on one side is shown, and the memory array regions on the other side are not shown. Please refer to Figure 9 for understanding.

[0092] It should also be noted that in the memory array region, a bit line (Bit Line, BL) or a word line (Word Line, WL) can be connected out through a contact structure (Contact).

[0093] In some embodiments, as Figure 9As shown, for a part of the first bonding structure group 61, it is coupled to an output driving device in the second chip 42, and the third bonding structure 621 is used to transmit a power signal, and the fourth bonding structure 622 is used to transmit a ground signal.

[0094] Here, VDDQ represents a power signal (also referred to as a "power terminal") for providing a high-level signal; VSSQ represents a ground signal (also referred to as a "ground terminal") for providing a low-level signal.

[0095] It should be noted that the output driving device is located around the data pads in the peripheral circuit region.

[0096] It should also be noted that all odd-numbered first metal structures 51 are electrically connected to all odd-numbered second metal structures 52 one-to-one through the first contact structure 53, forming one plate (also referred to as an electrode) of the vertical capacitor structure 50, and are connected to VDDQ through the first bonding structure 611 and the third bonding structure 621. All even-numbered first metal structures 51 are electrically connected to all even-numbered second metal structures 52 one-to-one through the second contact structure 54, forming the other plate of the vertical capacitor structure 50, and are connected to VSSQ through the second bonding structure 612 and the fourth bonding structure 622.

[0097] In some embodiments, referring to Figure 10 , which shows a three-dimensional structural schematic diagram of a comb-shaped capacitor structure provided by an embodiment of the present disclosure. As Figure 10 shown, the first chip 41 may further include a plurality of comb-shaped capacitor structures 70, and the vertical capacitor structure 50 and the comb-shaped capacitor structures 70 are arranged in sequence along the third direction;

[0098] Each comb-shaped capacitor structure 70 includes a first comb-shaped electrode 71 and a second comb-shaped electrode 72, and the comb teeth portions of the first comb-shaped electrode 71 and the comb teeth portions of the second comb-shaped electrode 72 are alternately arranged in parallel.

[0099] It should be noted that the comb-shaped capacitor structure 70 may be located in the non-memory array region 412 of the first chip 41 or may be located in the memory array region 411 of the first chip 41, and no specific limitation is made thereto, but the comb-shaped capacitor structure 70 is located above the vertical capacitor structure 50 along the third direction.

[0100] Exemplarily, in some embodiments, as Figure 10 shown, the first comb-shaped electrode 71 includes a first comb-shaped sub-electrode 711, a second comb-shaped sub-electrode 712, and a third comb-shaped sub-electrode 713; the second comb-shaped electrode 72 includes a fourth comb-shaped sub-electrode 721, a fifth comb-shaped sub-electrode 722, and a sixth comb-shaped sub-electrode 723;

[0101] Among them, the first comb-shaped sub-electrode 711 and the fourth comb-shaped sub-electrode 721 are both formed on the second wiring layer, and the comb teeth portions of the first comb-shaped sub-electrode 711 and the fourth comb-shaped sub-electrode 721 are alternately arranged in parallel; the second comb-shaped sub-electrode 712 and the fifth comb-shaped sub-electrode 722 are both formed on the third wiring layer, and the comb teeth portions of the second comb-shaped sub-electrode 712 and the fifth comb-shaped sub-electrode 722 are alternately arranged in parallel; the third comb-shaped sub-electrode 713 and the sixth comb-shaped sub-electrode 723 are both formed on the fourth wiring layer, and the comb teeth portions of the third comb-shaped sub-electrode 713 and the sixth comb-shaped sub-electrode 723 are alternately arranged in parallel;

[0102] The second wiring layer, the third wiring layer, and the fourth wiring layer are arranged in sequence along the third direction.

[0103] Here, the third wiring layer is denoted as M2, and the fourth wiring layer is denoted as M3.

[0104] It should be noted that the hollow portions in the comb-shaped capacitor structure 70 are all filled with a dielectric material. Exemplarily, the dielectric material can be alumina, or silicon dioxide, or other materials, and no specific limitation is made thereto.

[0105] It should also be noted that as Figure 10 shown, the comb-shaped sub-electrodes on one side of each wiring layer pointed by the arrow in the second direction constitute one electrode plate of the comb-shaped capacitor structure 70, and the comb-shaped sub-electrodes on the other side of each wiring layer opposite to the arrow in the second direction constitute the other electrode plate of the comb-shaped capacitor structure 70. Specifically, the first comb-shaped sub-electrode 711, the second comb-shaped sub-electrode 712, and the third comb-shaped sub-electrode 713 together constitute one electrode of the comb-shaped capacitor structure 70, and the fourth comb-shaped sub-electrode 721, the fifth comb-shaped sub-electrode 722, and the sixth comb-shaped sub-electrode 723 together constitute the other electrode of the comb-shaped capacitor structure 70.

[0106] In some embodiments, the distance between the first wiring layer and the second wiring layer along the third direction is greater than the distance between the second wiring layer and the third wiring layer along the third direction;

[0107] and, the distance between the first wiring layer and the second wiring layer along the third direction is greater than the distance between the third wiring layer and the fourth wiring layer along the third direction.

[0108] That is to say, the vertical distance between the M0 layer and the M1 layer is larger than the vertical distance between the M1 layer and the M2 layer, and the vertical distance between the M2 layer and the M3 layer. Also, because the capacitance value of the vertical capacitor structure 50 is proportional to the facing area of the electrode plates, forming the vertical capacitor structure 50 between the M0 layer and the M1 layer can increase the capacitance value.

[0109] In some embodiments, the first contact structure 53 and the second contact structure 54 are long contact holes.

[0110] Understandably, the vertical spacing between the M0 layer and the M1 layer is large, and the lengths of the first contact structure 53 and the second contact structure 54 connecting the first metal structure 51 located in the M0 layer and the second metal structure 52 located in the M1 layer are long, with a high aspect ratio, which are long contact holes.

[0111] In summary, the embodiments of the present disclosure provide a semiconductor chip, including a first chip 41 integrating a storage unit and a second chip 42 integrating a logic circuit. The structures on the first chip 41 and the second chip 42 together form a vertical capacitor (i.e., the vertical capacitance structure 50), and this capacitor can be applied to output driving devices around data pads including but not limited to the peripheral circuit region. The upper and lower plates of this vertical capacitor are respectively connected to VDDQ and VSSQ on the second chip 42 through wiring metal and a hybrid bonding structure. Specifically, the second metal structure 52 in the M1 layer is formed on the upper layer of the memory cell array in the memory array region 411, and the first metal structure 51 in the M0 layer is formed on the lower layer of the memory cell array; the second metal structure 52 and the first metal structure 51 are connected through the first contact structure 53 and the second contact structure 54; each odd-numbered second metal structure 52 is electrically connected to all odd-numbered first metal structures 51 one by one to form one plate of the vertical capacitance structure 50, and each even-numbered second metal structure 52 is electrically connected to all even-numbered first metal structures 51 one by one to form the other plate of the vertical capacitance structure 50, thereby increasing the total capacitance value and saving area.

[0112] Based on the three-dimensional memory 40 in the foregoing embodiments, refer to Figure 11 , which shows the schematic composition structure of a three-dimensional memory provided by the embodiments of the present disclosure Figure 3 . As shown in (a) in Figure 11 , it is the wiring schematic diagram of the M0 layer and the M1 layer; as shown in (b) in Figure 11 , it is the wiring schematic diagram of the M2 layer and the M3 layer.

[0113] It should be noted that a long contact hole (CT) is used to prepare the vertical capacitance structure 50 between the M0 layer and the M1 layer, and a comb-shaped capacitance structure 70 is prepared between the M1 layer and the M3 layer.

[0114] It should also be noted that Figure 1 the double arrow (1) indicates a width (Width) of 0.3 micrometers (μm), the double arrow (2) indicates a spacing (Space) of 0.22 μm, and the corresponding widths and spacings in the M1 layer, M2 layer, and M3 layer are the same.

[0115] Table 1 shows the total capacitance values of different items. As shown in Table 1, the size of the total capacitance is 100μm × 100μm, and the capacitance value of the vertical capacitance structure 50 prepared through the M0 layer, the long contact hole, and the M1 layer is 3.48 picofarads (pF); the total capacitance value of the total capacitance structure composed of the comb-shaped capacitance structure 70 and the vertical capacitance structure 50 prepared through the M1 layer to the M3 layer is 5.03 pF.

[0116] Table 1

[0117]

[0118] In summary, a vertical capacitance structure is prepared between the M0 layer and the M1 layer, and a MOM capacitance structure is prepared between the M1 layer and the M3 layer. Through experiments, it can be obtained that using the vertical capacitance structure can increase the total capacitance value of a certain area to 5.03 pF, thereby increasing the total capacitance value and saving area compared with only preparing the MOM capacitance structure.

[0119] In another embodiment of the present disclosure, refer to Figure 12 , which shows a schematic diagram of the composition structure of an electronic device provided by an embodiment of the present disclosure. As Figure 12 shown, the electronic device 80 includes the three-dimensional memory 40 described in any one of the foregoing embodiments.

[0120] In the embodiment of the present disclosure, for the electronic device 80, since it includes the three-dimensional memory 40 described in the foregoing embodiment, the total capacitance value can be increased and the area can be saved.

[0121] For the details not disclosed in the embodiments of the present disclosure, reference may be made to the description of the foregoing embodiments for understanding.

[0122] The above is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0123] It should be noted that in the present disclosure, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0124] The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments.

[0125] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0126] The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0127] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0128] As mentioned above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A three-dimensional memory, characterized in that, The three-dimensional memory includes a first chip and a second chip arranged along a third direction. The first chip includes a memory array region and a non-memory array region, and the second chip includes a control device region; a projection of the control device region along the third direction covers the non-memory array region; The non-memory array region of the first chip includes a plurality of vertical capacitor structures. Each vertical capacitor structure is formed between a first wiring layer and a second wiring layer of the first chip, and the first wiring layer, a memory cell array in the memory array region, and the second wiring layer are arranged in sequence along the third direction.

2. The three-dimensional memory according to claim 1, wherein The vertical capacitor structure includes a plurality of first metal structures, a plurality of second metal structures, and a dielectric material, and the dielectric material is filled between the plurality of first metal structures and the plurality of second metal structures; The plurality of first metal structures are all located on the first wiring layer of the first chip. Each first metal structure extends along a first direction, and the plurality of first metal structures are arranged in parallel along a second direction; the plurality of second metal structures are all located on the second wiring layer of the first chip. Each second metal structure extends along the second direction, and the plurality of second metal structures are arranged in parallel along the first direction; Each second metal structure is electrically connected to at least two first metal structures, and the first metal structures electrically connected by adjacent second metal structures are arranged alternately along the second direction, and adjacent second metal structures are not electrically connected to the same first metal structure; Wherein, the first direction and the second direction intersect.

3. The three-dimensional memory according to claim 2, wherein The first metal structures are numbered along the second direction, and the second metal structures are numbered along the first direction; For each second metal structure with an odd number, it is electrically connected to all first metal structures with odd numbers through a plurality of first contact structures one by one to form one electrode of the vertical capacitor structure; For each second metal structure with an even number, it is electrically connected to all first metal structures with even numbers through a plurality of second contact structures one by one to form the other electrode of the vertical capacitor structure.

4. The three-dimensional memory according to claim 3, wherein Along the first direction, the first contact structures and the second contact structures are alternately distributed in sequence; Along the second direction, the first contact structures and the second contact structures are alternately distributed in sequence.

5. The three-dimensional memory according to claim 3, characterized in that, The first chip includes a plurality of first bonding structure groups, and each vertical capacitor structure is coupled to one first bonding structure group; The first bonding structure group includes a first bonding structure and a second bonding structure. All the first contact structures in the vertical capacitor structure are coupled to the first bonding structure, and all the second contact structures in the vertical capacitor structure are coupled to the second bonding structure; The second chip includes a plurality of second bonding structure groups, and each of the first bonding structure groups is coupled to one of the second bonding structure groups; Each of the second bonding structure groups includes a third bonding structure and a fourth bonding structure, and the third bonding structure is bonded to the first bonding structure, and the fourth bonding structure is bonded to the second bonding structure.

6. The three-dimensional memory according to claim 5, wherein For some of the first bonding structure groups, they are coupled to output driving devices in the second chip, and the third bonding structure is used to transmit a power signal, and the fourth bonding structure is used to transmit a ground signal.

7. The three-dimensional memory according to claim 1, characterized in that, The first chip further includes a plurality of comb-shaped capacitor structures, and the vertical capacitor structures and the comb-shaped capacitor structures are arranged in sequence along the third direction; Each of the comb-shaped capacitor structures includes a first comb-shaped electrode and a second comb-shaped electrode, and the comb teeth portions of the first comb-shaped electrode and the comb teeth portions of the second comb-shaped electrode are alternately arranged in parallel.

8. The three-dimensional memory according to claim 7, wherein The first comb-shaped electrode includes a first comb-shaped sub-electrode, a second comb-shaped sub-electrode, and a third comb-shaped sub-electrode; the second comb-shaped electrode includes a fourth comb-shaped sub-electrode, a fifth comb-shaped sub-electrode, and a sixth comb-shaped sub-electrode; Wherein, the first comb-shaped sub-electrode and the fourth comb-shaped sub-electrode are both formed on the second wiring layer, and the comb teeth portions of the first comb-shaped sub-electrode and the fourth comb-shaped sub-electrode are alternately arranged in parallel; the second comb-shaped sub-electrode and the fifth comb-shaped sub-electrode are both formed on the third wiring layer, and the comb teeth portions of the second comb-shaped sub-electrode and the fifth comb-shaped sub-electrode are alternately arranged in parallel; the third comb-shaped sub-electrode and the sixth comb-shaped sub-electrode are both formed on the fourth wiring layer, and the comb teeth portions of the third comb-shaped sub-electrode and the sixth comb-shaped sub-electrode are alternately arranged in parallel; The second wiring layer, the third wiring layer, and the fourth wiring layer are arranged in sequence along the third direction.

9. The three-dimensional memory according to claim 8, wherein The distance between the first wiring layer and the second wiring layer along the third direction is greater than the distance between the second wiring layer and the third wiring layer along the third direction; And, the distance between the first wiring layer and the second wiring layer along the third direction is greater than the distance between the third wiring layer and the fourth wiring layer along the third direction.

10. The three-dimensional memory according to claim 3, characterized in that The first contact structure and the second contact structure are long contact holes.

11. An electronic device, characterized in that, The electronic device includes the three-dimensional memory according to any one of claims 1-10.

Images