Chip circuit anti-interference structure and chip
By alternately setting connection areas and trench isolation structures on the chip, the capacitance coupling and interference problems between different places are solved, lower capacitance value and less voltage variation interference are achieved, and the performance of the analog circuit is improved.
Patent Information
- Application Number
- CN202311866613.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-01
AI Technical Summary
In the prior art, interference between different places in the chip, especially noise generated by digital circuits, is harmful to the small signal index of the analog circuit, and traditional chip manufacturing processes lead to different coupling on the substrate, resulting in interference.
The connection region and a trench isolation structure with a stable potential are alternately arranged on the chip to form a multi-layer capacitance structure, so that each layer of capacitance structure is connected in series, thereby reducing capacitance coupling between different places, and reducing interference caused by voltage changes through the stable potential of the trench isolation structure.
Effectively reduce capacitive coupling between different grounds, reduce interference between voltage changes and ground, and improve the small signal index of the analog circuit.
Smart Images
Figure CN120237130A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to an anti-interference structure for a chip circuit and a chip. Background Art
[0002] With the development of semiconductor technology, the form of products is becoming more and more complex. For a system with both digital circuits and analog circuits, the interference between different grounds in the chip will affect the normal operation of the circuit. In particular, the noise generated by the digital circuit will affect the analog circuit and deteriorate the small-signal index of the analog circuit.
[0003] Although it is possible to ensure a high resistance between different grounds through circuit design, the traditional chip manufacturing process will cause coupling between different grounds on the chip substrate, resulting in interference. As Figure 1 shown, in the prior art, an isolation structure penetrating the substrate is provided on the substrate of the chip to isolate different grounds from each other, thereby reducing the coupling between different grounds. Summary of the Invention
[0004] To solve the above technical problems, the present invention provides an anti-interference structure for a chip circuit and a chip, which can better reduce the interference between different grounds.
[0005] In a first aspect, the present invention provides an anti-interference structure for a chip circuit, including: a multi-layer capacitor structure, including an alternating ground region and at least one trench isolation structure having a stable potential.
[0006] Preferably, one or more of the ground regions are provided between the two ground regions to reduce the capacitance value of the multi-layer capacitor structure.
[0007] Further, at least one of the trench isolation structures forms a series capacitor group with the adjacent ground region.
[0008] Preferably, the several trench isolation structures have the same or different stable potentials.
[0009] Still further, the trench isolation structure is connected to a power supply through a corresponding switch to charge and discharge the capacitor group.
[0010] Even further, the switches are closed simultaneously or at different times.
[0011] Preferably, some of the trench isolation structures are floating.
[0012] Still further, the trench isolation structure includes an isolation layer for storing charges and a conductive layer connected to the power supply, which are arranged from outside to inside.
[0013] Preferably, the grounding region and the trench isolation structure are disposed on at least one side of the isolated circuit to isolate noise and / or light and / or heat and / or stress from the peripheral circuit region.
[0014] Further, the grounding region and the trench isolation structure are concentrically disposed between the isolated circuit and the peripheral circuit region.
[0015] Preferably, both the grounding region and the trench isolation structure are internally disposed in a first conductivity type substrate, and the grounding region has a second conductivity type.
[0016] On the other hand, the present invention also provides a chip having the chip circuit anti-interference structure described in any one of the above.
[0017] Compared with the prior art, the present invention has the following beneficial effects:
[0018] In the present invention, by alternately disposing a grounding region and at least one trench isolation structure with a stable potential on the chip, a multi-layer capacitance structure is formed by the grounding region and the trench isolation structure. Since each layer of the capacitance structure is connected in series, the capacitance value of the multi-layer capacitance structure after series connection is smaller than the capacitance value of the single-layer capacitance structure.
[0019] Compared with the prior art method of forming a single-layer capacitance structure between different grounds, the present invention can form a multi-layer capacitance structure between different grounds, thereby effectively reducing the capacitance coupling between different grounds.
[0020] Moreover, the trench isolation structure provided in the present invention has a stable potential, so that it can reduce the interference of voltage changes between different grounds. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for description will be briefly introduced below. Obviously, the drawings in the following description are an embodiment of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts:
[0022] Figure 1 A schematic diagram of an isolation structure between different grounds in the prior art;
[0023] Figure 2 A schematic diagram of a chip circuit anti-interference structure in an embodiment of the present invention;
[0024] Figure 3 A schematic diagram of a chip circuit anti-interference structure in an embodiment of the present invention in a working state. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a very simplified form and are all drawn using non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention. In order to make the purpose, features, and advantages of the present invention more obvious and understandable, please refer to the accompanying drawings. It should be noted that the structures, scales, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those skilled in this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they do not have technical substance significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present invention.
[0026] As Figure 1 shown, in a first aspect, the present invention provides an anti-interference structure for a chip circuit, including: a multi-layer capacitor structure, including alternately arranged grounding regions and at least one trench isolation structure having a stable potential.
[0027] By alternately arranging grounding regions and at least one trench isolation structure having a stable potential on the chip, the present invention enables the grounding regions and the trench isolation structure to form a multi-layer capacitor structure. Since each layer of the capacitor structure is connected in series, the capacitance value of the multi-layer capacitor structure after series connection is smaller than that of a single-layer capacitor structure. Compared with the prior art method of forming a single-layer capacitor structure between different grounds, the present invention can form a multi-layer capacitor structure between different grounds, thereby effectively reducing the capacitive coupling between different grounds. Moreover, the trench isolation structure provided in the present invention has a stable potential, so it can reduce the interference caused by voltage changes between different grounds.
[0028] As a preferred embodiment, one or more grounding regions are provided between two grounding regions in this embodiment to reduce the capacitance value of the multi-layer capacitor structure.
[0029] As Figure 2As shown, in this embodiment, a second grounding region PW2 is provided between the first grounding region PW1 and the third grounding region PW3, and a first trench isolation structure Ring1 is provided between the first grounding region PW1 and the second grounding region PW2, and a second trench isolation structure Ring2 is provided between the second grounding region PW2 and the third grounding region PW3, such that the first grounding region PW1, the first trench isolation structure Ring1, and the second grounding region PW2 form a first-layer capacitance structure; the second grounding region PW2, the second trench isolation structure Ring2, and the third grounding region PW3 form a second-layer capacitance structure. Since the first-layer capacitance structure and the second-layer capacitance structure are in series, the capacitance value of the double-layer capacitance structure formed after their series connection is smaller than the capacitance value of either the first-layer capacitance structure or the second-layer capacitance structure, thereby reducing the capacitance value between the first grounding region PW1 and the third grounding region PW3.
[0030] Specifically, at least one trench isolation structure in this embodiment forms a series capacitance group with the adjacent grounding region.
[0031] As Figure 3 shown, in this embodiment, a capacitance C11 is formed between the first trench isolation structure Ring1 and the first grounding region PW1, a capacitance C12 is formed between the first trench isolation structure Ring1 and the second grounding region PW2, and the capacitance C11 and the capacitance C12 form a series capacitance group; a capacitance C21 is formed between the second trench isolation structure Ring2 and the second grounding region PW2, a capacitance C22 is formed between the second trench isolation structure Ring2 and the third grounding region PW3, and the capacitance C21 and the capacitance C22 form a series capacitance group.
[0032] As a preferred embodiment, several trench isolation structures in this embodiment have the same or different stable potentials.
[0033] Continuing as Figure 3 shown, the first trench isolation structure Ring1 and the second trench isolation structure Ring2 in this embodiment are externally connected to power supplies VDD1 and VDD2 through switches S1 and S2 respectively, such that the potentials of the first trench isolation structure Ring1 and the second trench isolation structure Ring2 are VP1 and VP2 respectively.
[0034] More specifically, the trench isolation structure in this embodiment is connected to a power supply through a corresponding switch to charge and discharge the capacitance group.
[0035] As Figure 3As shown, in this embodiment, the first trench isolation structure Ring1 is externally connected to the power supply VDD1 through the switch S1 to charge and discharge the capacitor bank formed by the series connection of the capacitors C11 and C12; the second trench isolation structure Ring2 is externally connected to the power supply VDD2 through the switch S2 to charge and discharge the capacitor bank formed by the series connection of the capacitors C21 and C22.
[0036] More specifically, the switches in this embodiment are closed simultaneously or at different times. In this embodiment, the switches S1 and S2 have two working states: the switches S1 and S2 are closed simultaneously to charge and discharge the capacitor bank at the same time; one of the switches S1 and S2 is closed to charge and discharge only one of the capacitor banks.
[0037] As a preferred embodiment, some of the trench isolation structures in this embodiment are floating. Specifically, one or both of the first trench isolation structure Ring1 and the second trench isolation structure Ring2 in this embodiment can be set to be floating.
[0038] More specifically, the trench isolation structure in this embodiment includes an isolation layer for storing charges and a conductive layer connected to the power supply, which are arranged from the outside to the inside. The isolation layers in the first trench isolation structure Ring1 in this embodiment form the capacitors C11 and C12 with the first grounding region PW1 and the second grounding region PW2 respectively, and the conductive layer is connected to the power supply VDD1; the isolation layers in the second trench isolation structure Ring2 form the capacitors C21 and C22 with the second grounding region PW2 and the third grounding region PW3 respectively, and the conductive layer is connected to the power supply VDD2.
[0039] As a preferred embodiment, the grounding regions and the trench isolation structure in this embodiment are arranged on at least one side of the isolated circuit to isolate noise and / or light and / or heat and / or stress from the peripheral circuit region. Such an arrangement enables the grounding regions and the trench isolation structure in this embodiment to play a better role in preventing interference to the chip circuit.
[0040] As Figure 2 and 3 shown, specifically, the grounding regions and the trench isolation structure in this embodiment are concentrically arranged between the isolated circuit and the peripheral circuit region. The grounding regions and the trench isolation structure are in a shape of a rectangle with a hole in the middle, surrounding the isolated circuit to play a better role in preventing interference.
[0041] As a preferred embodiment, the grounding regions and the trench isolation structure in this embodiment are both internally provided in the first conductive type substrate, and the grounding regions have the second conductive type. Specifically, the first conductive type in this embodiment is made of polycrystalline silicon material (poly).
[0042] On the other hand, the present invention also provides a chip having the anti-interference structure of the chip circuit according to any one of the above, so as to reduce the interference between different circuits in the chip.
[0043] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description should not be construed as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and alternatives to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.
Claims
1. An anti-interference structure for a chip circuit, characterized in that, Comprising: A multi-layer capacitor structure including alternately arranged grounding regions and at least one trench isolation structure with a stable potential.
2. The anti-interference structure of the chip circuit according to claim 1, wherein One or more of the grounding regions are arranged between the two grounding regions to reduce the capacitance value of the multi-layer capacitor structure.
3. The anti-interference structure of the chip circuit according to claim 1 or 2, characterized in that, A series capacitor group is formed between at least one of the trench isolation structures and the adjacent grounding region.
4. The anti-interference structure of the chip circuit according to claim 1, characterized in that, The same or different stable potentials exist between several of the trench isolation structures.
5. The anti-interference structure of the chip circuit according to claim 3, characterized in that The trench isolation structure is connected to a power supply through a corresponding switch to charge and discharge the capacitor group.
6. The anti-interference structure of the chip circuit according to claim 5, characterized in that, Each of the switches is closed simultaneously or at different times.
7. The anti-interference structure of the chip circuit according to claim 1, characterized in that Some of the trench isolation structures are floating.
8. The anti-interference structure of the chip circuit according to claim 5, characterized in that, The trench isolation structure includes an isolation layer for storing charges arranged from the outside to the inside and a conductive layer connected to the power supply.
9. The anti-interference structure of the chip circuit according to claim 1, wherein The grounding region and the trench isolation structure are arranged on at least one side of the isolated circuit to isolate noise and / or light and / or heat and / or stress from the peripheral circuit region.
10. The anti-interference structure of the chip circuit according to claim 9, wherein, The grounding region and the trench isolation structure are concentrically arranged between the isolated circuit and the peripheral circuit region.
11. The anti-interference structure of the chip circuit according to claim 1, wherein, The grounding region and the trench isolation structure are both internally provided in a first-conductivity-type substrate, and the grounding region has a second-conductivity type.
12. A chip, characterized in that, There is a chip circuit anti-interference structure as described in any one of claims 1-11.