Capacitor structure and manufacturing method thereof
By introducing alternating dielectric layers and trench designs into the capacitor structure and setting capacitors on the side walls of the dielectric layer, the problems of increasing the capacitance value and reducing process complexity are solved, and the capacitor performance is improved and the manufacturing process is simplified.
Patent Information
- Application Number
- CN202410094760.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-28
- Filing Date
- 2024-01-23
- Publication Date
- 2025-07-01
AI Technical Summary
The prior art is difficult to increase the capacitance value of a capacitor without increasing the process complexity.
An alternately arranged dielectric layers are introduced into the capacitor structure, and trenches are formed on the side walls of the dielectric layer and capacitors are provided on the trench surface, while additional dielectric layers are formed between and around the dielectric layers to reduce process complexity.
Through this structural design, the capacitance value of the capacitor is significantly improved while reducing the complexity of the manufacturing process.
Smart Images
Figure CN120237131A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly to a capacitor structure and a manufacturing method thereof. Background Art
[0002] A capacitor is a semiconductor device widely used in electronic products. However, how to further increase the capacitance value of the capacitor structure and reduce the process complexity of the capacitor structure is an ongoing goal. Summary of the Invention
[0003] The present invention provides a capacitor structure and a manufacturing method thereof, which can further increase the capacitance value of the capacitor structure and reduce the process complexity of the capacitor structure.
[0004] The present invention provides a capacitor structure, including a substrate, a stacked structure, and a capacitor. The stacked structure includes at least one first dielectric layer and at least one second dielectric layer alternately disposed on the substrate. Grooves are formed in at least one first dielectric layer, at least one second dielectric layer, and the substrate. At least one recess is formed on at least one sidewall of the at least one first dielectric layer of the grooves. The capacitor is disposed on the surface of the grooves.
[0005] According to an embodiment of the present invention, in the above capacitor structure, the cross-sectional profile of at least one recess may include a curved surface.
[0006] According to an embodiment of the present invention, in the above capacitor structure, the grooves do not have recesses on the sidewalls of the substrate.
[0007] According to an embodiment of the present invention, in the above capacitor structure, the sidewall of the substrate exposed by the grooves may be a flat surface.
[0008] According to an embodiment of the present invention, in the above capacitor structure, the grooves do not have recesses on at least one sidewall of at least one second dielectric layer.
[0009] According to an embodiment of the present invention, in the above capacitor structure, at least one sidewall of at least one second dielectric layer exposed by the grooves may be a flat surface.
[0010] According to an embodiment of the present invention, in the above capacitor structure, the first dielectric layer closest to the substrate may be located between the second dielectric layer closest to the substrate and the substrate.
[0011] According to an embodiment of the present invention, in the above capacitor structure, the second dielectric layer closest to the substrate may be located between the first dielectric layer closest to the substrate and the substrate.
[0012] According to an embodiment of the present invention, in the above capacitor structure, the capacitor may also be disposed on the top surface of the stacked structure.
[0013] According to an embodiment of the present invention, in the above capacitor structure, a third dielectric layer and a fourth dielectric layer may also be included. The third dielectric layer is disposed between the capacitor and the substrate and between the capacitor and the stacked structure. The fourth dielectric layer is disposed on the capacitor. The fourth dielectric layer may fill the trench.
[0014] The present invention provides a method for manufacturing a capacitor structure, including the following steps. Provide a substrate. Form a stacked structure. The stacked structure includes at least one first dielectric layer and at least one second dielectric layer alternately disposed on the substrate. Form trenches in at least one first dielectric layer, at least one second dielectric layer, and the substrate. The trenches have at least one recess on at least one sidewall of at least one first dielectric layer. Form a capacitor on the surface of the trenches.
[0015] According to an embodiment of the present invention, in the above method for manufacturing a capacitor structure, the method for forming the trenches may include the following steps. Form a patterned photoresist layer on the stacked structure. Using the patterned photoresist layer as a mask, remove a part of the stacked structure and a part of the substrate to form the trenches.
[0016] According to an embodiment of the present invention, in the above method for manufacturing a capacitor structure, the method for removing a part of the stacked structure and a part of the substrate is, for example, a dry etching method.
[0017] According to an embodiment of the present invention, in the above method for manufacturing a capacitor structure, the following steps may also be included. After forming the trenches, remove the patterned photoresist layer.
[0018] According to an embodiment of the present invention, in the above method for manufacturing a capacitor structure, the method for forming at least one recess may include the following steps. Perform an isotropic etching process on at least one first dielectric layer to form at least one recess.
[0019] According to an embodiment of the present invention, in the above method for manufacturing a capacitor structure, the above isotropic etching process is, for example, a dry etching process or a wet etching process.
[0020] According to an embodiment of the present invention, in the above method for manufacturing a capacitor structure, the capacitor may also be formed on the top surface of the stacked structure.
[0021] According to an embodiment of the present invention, in the above method for manufacturing a capacitor structure, the following steps may also be included. Form a third dielectric layer between the capacitor and the substrate and between the capacitor and the stacked structure. Form a fourth dielectric layer on the capacitor. The fourth dielectric layer may fill the trenches.
[0022] According to an embodiment of the present invention, in the manufacturing method of the above capacitor structure, the first dielectric layer closest to the substrate may be located between the second dielectric layer closest to the substrate and the substrate.
[0023] According to an embodiment of the present invention, in the manufacturing method of the above capacitor structure, the second dielectric layer closest to the substrate may be located between the first dielectric layer closest to the substrate and the substrate.
[0024] Based on the above, in the capacitor structure and its manufacturing method proposed by the present invention, the stacked structure includes at least one first dielectric layer and at least one second dielectric layer alternately disposed on the substrate. There are trenches in at least one of the at least one first dielectric layer, at least one second dielectric layer, and the substrate. The trench has at least one recess on at least one sidewall of the at least one first dielectric layer. The capacitor is disposed on the surface of the trench. Therefore, the capacitance value of the capacitor structure can be further increased and the process complexity of the capacitor structure can be reduced.
[0025] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings
[0026] Figures 1A to 1E It is a manufacturing process cross-sectional view of the capacitor structure according to some embodiments of the present invention;
[0027] Figure 2 It is a cross-sectional view of the capacitor structure according to other embodiments of the present invention.
[0028] Description of the Reference Numerals in the Drawings:
[0029] 10, 20: Capacitor structure
[0030] 100: Substrate
[0031] 102: Stacked structure
[0032] 104, 106, 110, 114: Dielectric layer
[0033] 108: Patterned photoresist layer
[0034] 112: Capacitor
[0035] R1: Recess
[0036] S1: Top surface
[0037] SW1, SW2, SW3: Sidewall
[0038] T1: Trench Detailed Description of the Embodiments
[0039] Examples are listed below and described in detail with reference to the accompanying drawings. However, the provided examples are not intended to limit the scope covered by the present invention. For ease of understanding, the same components will be denoted by the same reference numerals in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.
[0040] Figures 1A to 1E It is a cross-sectional view of a manufacturing process of a capacitor structure according to some embodiments of the present invention.
[0041] Please refer to Figure 1A , and a substrate 100 is provided. In some embodiments, the substrate 100 can be a semiconductor substrate, such as a silicon substrate.
[0042] Next, a stacked structure 102 is formed. The stacked structure 102 includes at least one dielectric layer 104 and at least one dielectric layer 106 alternately disposed on the substrate 100. In the present embodiment, the dielectric layer 104 closest to the substrate 100 can be located between the dielectric layer 106 closest to the substrate 100 and the substrate 100, but the present invention is not limited thereto. The materials of the dielectric layer 104 and the dielectric layer 106 can be different materials. In addition, in the same etching process, the dielectric layer 104 and the dielectric layer 106 can have different etching rates. In some embodiments, the material of the dielectric layer 104 is, for example, silicon oxide, silicon nitride, silicon oxynitride (SiON), or silicon carbonitride (SiCN). In some embodiments, the method of forming the dielectric layer 104 is, for example, chemical vapor deposition. In some embodiments, the material of the dielectric layer 106 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. In some embodiments, the method of forming the dielectric layer 106 is, for example, chemical vapor deposition. In the present embodiment, the material of the dielectric layer 104 can be silicon oxide, and the material of the dielectric layer 106 can be silicon nitride, but the present invention is not limited thereto.
[0043] In addition, the number of the dielectric layers 104 and the number of the dielectric layers 106 are not limited to the numbers in the figure. In the present embodiment, the number of the dielectric layers 104 and the number of the dielectric layers 106 are taken as multiple for example, but the present invention is not limited thereto. As long as the stacked structure 102 includes at least one dielectric layer 104 and at least one dielectric layer 106, it falls within the scope covered by the present invention.
[0044] Please refer to Figure 1B , and a patterned photoresist layer 108 can be formed on the stacked structure 102. The patterned photoresist layer 108 can expose a part of the stacked structure 102. In some embodiments, the patterned photoresist layer 108 can be formed by a photolithography process.
[0045] Please refer to Figure 1C, the patterned photoresist layer 108 can be used as a mask to remove a portion of the stacked structure 102 and a portion of the substrate 100, thereby forming a trench T1. Thus, the trench T1 can be formed in the dielectric layer 104, the dielectric layer 106, and the substrate 100. In some embodiments, the trench T1 can be a deep trench. In some embodiments, the method for removing the portion of the stacked structure 102 and the portion of the substrate 100 is, for example, a dry etching method.
[0046] After forming the trench T1, the patterned photoresist layer 108 can be removed. In some embodiments, the method for removing the patterned photoresist layer 108 is, for example, a dry stripping method or a wet stripping method.
[0047] Please refer to Figure 1D , an isotropic etching process can be performed on at least one dielectric layer 104 to form at least one recess R1. Thus, the trench T1 has at least one recess R1 on at least one sidewall SW1 of the at least one dielectric layer 104. In some embodiments, the cross-sectional profile of the at least one recess R1 can include a curved surface. In this embodiment, in this embodiment, an isotropic etching process can be performed on all the dielectric layers 104 to form a plurality of recesses R1, and the cross-sectional profiles of all the recesses R1 can include curved surfaces. In some embodiments, the above isotropic etching process is, for example, a dry etching process or a wet etching process. In the above isotropic etching process, the etching rate of the dielectric layer 104 can be greater than the etching rates of the dielectric layer 106 and the substrate 100.
[0048] In some embodiments, the trench T1 does not have a recess on the sidewall SW2 of the substrate 100. In some embodiments, the sidewall SW2 of the substrate 100 exposed by the trench T1 can be a flat surface. In some embodiments, the trench T1 does not have a recess on at least one sidewall SW3 of the at least one dielectric layer 106. In some embodiments, the at least one sidewall SW3 of the at least one dielectric layer 106 exposed by the trench T1 can be a flat surface. In this embodiment, the trench T1 does not have a recess on all the sidewalls SW3 of all the dielectric layers 106, and all the sidewalls SW3 of all the dielectric layers 106 exposed by the trench T1 can be flat surfaces.
[0049] Please refer to Figure 1E , a dielectric layer 110 can be formed on the surface of the trench T1 and the stacked structure 102. In some embodiments, the material of the dielectric layer 110 is, for example, silicon oxide. In some embodiments, the method for forming the dielectric layer 110 is, for example, a chemical vapor deposition method or a physical vapor deposition method.
[0050] Next, capacitor 112 can be formed on dielectric layer 110. Thus, capacitor 112 can be formed on the surface of trench T1. In addition, capacitor 112 can also be formed on the top surface S1 of stacked structure 102. By the above method, dielectric layer 110 can be formed between capacitor 112 and substrate 100, and between capacitor 112 and stacked structure 102. In some embodiments, capacitor 112 can be a multi-layer structure. In some embodiments, capacitor 112 can include a plurality of electrode layers (not shown) and at least one insulating layer (not shown) stacked alternately. In some embodiments, the material of the electrode layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), cobalt (Co), or a combination thereof. In some embodiments, the method of forming the electrode layer is, for example, chemical vapor deposition. In some embodiments, the material of the insulating layer is, for example, a high dielectric constant (high-k) material, silicon oxide, or silicon nitride. In some embodiments, the method of forming the insulating layer is, for example, chemical vapor deposition or atomic layer deposition (ALD). In some embodiments, capacitor 112 can be a metal layer / insulating layer / metal layer (MIM) capacitor, a metal layer / insulating layer / metal layer / insulating layer / metal layer (MIMIM) capacitor, or a metal layer / insulating layer / metal layer / insulating layer / metal layer / insulating layer / metal layer (MIMIMIM) capacitor, etc.
[0051] Then, dielectric layer 114 can be formed on capacitor 112. Dielectric layer 114 can fill trench T1. In some embodiments, the material of dielectric layer 114 is, for example, silicon oxide. In some embodiments, the method of forming dielectric layer 114 is, for example, chemical vapor deposition.
[0052] Hereinafter, Figure 1E the capacitor structure 10 of the above embodiment will be described. In addition, although the method of forming capacitor structure 10 is described by taking the above method as an example, the present invention is not limited thereto.
[0053] Please refer to Figure 1E , capacitor structure 10 includes substrate 100, stacked structure 102, and capacitor 112. Stacked structure 102 includes at least one dielectric layer 104 and at least one dielectric layer 106 alternately disposed on substrate 100. Trench T1 is formed in at least one dielectric layer 104, at least one dielectric layer 106, and substrate 100. Trench T1 has at least one recess R1 on at least one sidewall SW1 of at least one dielectric layer 104. Capacitor 112 is disposed on the surface of trench T1. In some embodiments, capacitor 112 can also be disposed on the top surface S1 of stacked structure 102.
[0054] The capacitor structure 10 may further include a dielectric layer 110 and a dielectric layer 114. The dielectric layer 110 is disposed between the capacitor 112 and the substrate 100 and between the capacitor 112 and the stack structure 102. The dielectric layer 114 is disposed on the capacitor 112. The dielectric layer 114 may fill the trench T1.
[0055] In addition, the details of each component in the capacitor structure 10 (such as materials and formation methods, etc.) have been described in detail in the above embodiments and will not be described herein again.
[0056] Based on the above embodiments, in the capacitor structure 10 and its manufacturing method, the stack structure 102 includes at least one dielectric layer 104 and at least one dielectric layer 106 alternately disposed on the substrate 100. A trench T1 is formed in at least one of the at least one dielectric layer 104, the at least one dielectric layer 106, and the substrate 100. The trench T1 has at least one recess R1 on at least one sidewall SW1 of the at least one dielectric layer 104. The capacitor 112 is disposed on the surface of the trench T1. Therefore, the capacitance value of the capacitor structure 10 can be further increased and the process complexity of the capacitor structure 10 can be reduced.
[0057] Figure 2 It is a cross-sectional view of a capacitor structure according to other embodiments of the present invention.
[0058] Please refer to Figure 1E and Figure 2 , Figure 2 The differences between the capacitor structure 20 of Figure 1E and the capacitor structure 10 of Figure 2 are as follows. In the capacitor structure 20 of Figure 1E , the dielectric layer 106 closest to the substrate 100 may be located between the dielectric layer 104 closest to the substrate 100 and the substrate 100. In the manufacturing method of the capacitor structure 10 of Figure 2 , the dielectric layer 104 closest to the substrate 100 may be first formed on the substrate 100, and then the dielectric layer 106 closest to the substrate 100 may be formed on the dielectric layer 104 closest to the substrate 100. In the manufacturing method of the capacitor structure 20 of Figure 2 , the dielectric layer 106 closest to the substrate 100 may be first formed on the substrate 100, and then the dielectric layer 104 closest to the substrate 100 may be formed on the dielectric layer 106 closest to the substrate 100. In addition, Figure 2 , the remaining steps of the manufacturing method of the capacitor structure 20 of Figure 1E may refer to the manufacturing method of the capacitor structure 10 of Figure 1E , and the description thereof is omitted herein. In addition, in Figure 1E and Figure 2 , the same or similar components are denoted by the same reference numerals, and the description thereof is omitted.
[0059] As can be seen from the above embodiments, in the capacitor structure 20 and its manufacturing method, the stacked structure 102 includes at least one dielectric layer 104 and at least one dielectric layer 106 alternately disposed on the substrate 100. A trench T1 is formed in at least one of the at least one dielectric layer 104, the at least one dielectric layer 106, and the substrate 100. The trench T1 has at least one recess R1 on at least one sidewall SW1 of the at least one dielectric layer 104. The capacitor 112 is disposed on the surface of the trench T1. Therefore, the capacitance value of the capacitor structure 20 can be further increased and the process complexity of the capacitor structure 20 can be reduced.
[0060] In summary, in the capacitor structure and its manufacturing method of the above embodiments, the stacked structure includes at least one first dielectric layer and at least one second dielectric layer alternately disposed on the substrate. A trench is formed in at least one of the at least one first dielectric layer, the at least one second dielectric layer, and the substrate. The trench has at least one recess on at least one sidewall of the at least one first dielectric layer. The capacitor is disposed on the surface of the trench. Therefore, the capacitance value of the capacitor structure can be further increased and the process complexity of the capacitor structure can be reduced.
[0061] Although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the claims.
Claims
1. A capacitor structure comprising: substrate; A stacked structure, comprising at least one first dielectric layer and at least one second dielectric layer alternately arranged on the substrate, wherein at least one of the first dielectric layer, at least one of the second dielectric layer and the substrate has a groove, and the groove has at least one recess on at least one sidewall of at least one of the first dielectric layers; as well as The capacitor is disposed on the surface of the groove. 2 . The capacitor structure of claim 1 , wherein a cross-sectional profile of at least one of the recesses comprises a curved surface. 3 . The capacitor structure of claim 1 , wherein the trench has no recess on a sidewall of the substrate. 4 . The capacitor structure according to claim 1 , wherein a sidewall of the substrate exposed by the trench is a flat surface. 5 . The capacitor structure of claim 1 , wherein the trench has no recess on at least one sidewall of at least one of the second dielectric layers. 6 . The capacitor structure according to claim 1 , wherein at least one sidewall of at least one of the second dielectric layers exposed by the trench is a flat surface. 7 . The capacitor structure of claim 1 , wherein the first dielectric layer closest to the substrate is located between the second dielectric layer closest to the substrate and the substrate. 8 . The capacitor structure of claim 1 , wherein the second dielectric layer closest to the substrate is located between the first dielectric layer closest to the substrate and the substrate.
9. The capacitor structure of claim 1, wherein the capacitor is further disposed on a top surface of the stacked structure.
10. The capacitor structure of claim 1, further comprising: a third dielectric layer disposed between the capacitor and the substrate and between the capacitor and the stacked structure; as well as The fourth dielectric layer is disposed on the capacitor and fills the trench.
11. A method for manufacturing a capacitor structure, comprising: providing a substrate; forming a stacked structure, wherein the stacked structure comprises at least one first dielectric layer and at least one second dielectric layer alternately disposed on the substrate; forming a trench in at least one of the first dielectric layers, at least one of the second dielectric layers, and the substrate, wherein the trench has at least one recess on at least one sidewall of at least one of the first dielectric layers; as well as A capacitor is formed on the surface of the trench.
12. The method for manufacturing a capacitor structure according to claim 11, wherein the method for forming the trench comprises: forming a patterned photoresist layer on the stacked structure; as well as The patterned photoresist layer is used as a mask to remove a portion of the stacked structure and a portion of the substrate to form the trench. 13 . The method for manufacturing a capacitor structure according to claim 12 , wherein a method for removing a portion of the stacked structure and a portion of the substrate comprises a dry etching method.
14. The method for manufacturing a capacitor structure according to claim 12, further comprising: After forming the trenches, the patterned photoresist layer is removed.
15. The method for manufacturing a capacitor structure according to claim 14, wherein a method for forming at least one of the recesses comprises: An isotropic etching process is performed on at least one of the first dielectric layers to form at least one of the recesses. 16 . The method for manufacturing a capacitor structure according to claim 15 , wherein the isotropic etching process comprises a dry etching process or a wet etching process. 17 . The method for manufacturing a capacitor structure according to claim 11 , wherein the capacitor is also formed on a top surface of the stacked structure.
18. The method for manufacturing a capacitor structure according to claim 11, further comprising: forming a third dielectric layer between the capacitor and the substrate and between the capacitor and the stacked structure; as well as A fourth dielectric layer is formed on the capacitor, wherein the fourth dielectric layer fills the trench. 19 . The method for manufacturing a capacitor structure according to claim 11 , wherein the first dielectric layer closest to the substrate is located between the second dielectric layer closest to the substrate and the substrate. 20 . The method for manufacturing a capacitor structure according to claim 11 , wherein the second dielectric layer closest to the substrate is located between the first dielectric layer closest to the substrate and the substrate.