Parallel-connection carrier wave synchronization method, inversion equipment, system and storage medium

Abstract

The invention relates to the technical field of new energy, in particular to a parallel carrier wave synchronization method, inversion equipment, a system and a storage medium. The parallel carrier wave synchronization method comprises the following steps: sampling the output current of the inversion equipment at a first moment and a second moment of each preset carrier wave adjustment period to obtain a first moment current value and a second moment current value; taking a difference value obtained by subtracting the current value at the second moment from the current value at the first moment as an error value, inputting the error value into a proportional-integral controller, and adjusting a carrier counting period value through the proportional-integral controller; and outputting a corresponding carrier signal based on the adjusted carrier counting period value. According to the method, the slave does not need to communicate with the host, design is simple, cost is low, the method does not depend on hardware precision and communication speed, and flexibility and reliability are high.

Description

Technical Field

[0001] The present application relates to the field of new energy technologies, and particularly to a parallel carrier synchronization method, an inverter device, a system, and a storage medium. Background Art

[0002] With the development of society, electricity has become essential in daily life and work. However, a series of problems such as outdoor power consumption, device power failure, and excessive load are often encountered. Due to its flexibility, portable energy storage power supplies can be configured in parallel or series connections, making them one of the options to solve these problems.

[0003] When multiple inverter devices are connected in parallel, if the PWM (Pulse Width Modulation) carriers of each inverter device are not synchronized, it may cause serious high-frequency circulating current problems inside the multi-inverter parallel system, reducing the efficiency and harmonic characteristics of the multi-inverter parallel system. To prevent high-frequency circulating current between multiple inverter devices, a carrier synchronization technology needs to be introduced to suppress high-frequency circulating current.

[0004] Traditional parallel carrier synchronization technologies are implemented through wired methods. The master device transmits carrier information to the slave device through synchronization signal lines and communication lines for synchronous control. This solution is not only complex in design and high in cost, but also because the clock reference signals of multiple inverter devices are generally independently generated by multiple crystal oscillators, and there are clock errors in the crystal oscillators themselves. Therefore, it is difficult for the clock frequencies of each processor to be exactly the same, and there may still be a situation of carrier asynchronization. Summary of the Invention

[0005] Embodiments of the present application aim to provide a parallel carrier synchronization method, an inverter device, a system, and a storage medium to solve the problems of complex design, high cost, and low reliability of parallel carrier synchronization technologies in the prior art.

[0006] To solve the above technical problems, the embodiments of the present application provide the following technical solutions: In a first aspect, an embodiment of the present application provides a parallel carrier synchronization method applied to an inverter device. The method includes: Sampling the output current of the inverter device at a first moment and a second moment of each preset adjusted carrier period to obtain a first moment current value and a second moment current value; Taking the difference between the first moment current value and the second moment current value as an error value and inputting it into a proportional-integral controller to adjust the carrier counting period value through the proportional-integral controller; Outputting a corresponding carrier signal based on the adjusted carrier counting period value.

[0007] Optionally, the phase difference between the first moment and the second moment is 180 degrees.

[0008] Optionally, the waveform of the carrier signal is a triangular wave. The first moment is the moment when the carrier count value is zero, and the second moment is the moment when the carrier count value is the carrier count period value.

[0009] Optionally, the sampling of the output current of the inverter device at the first moment and the second moment of each preset adjusted carrier period respectively to obtain the first moment current value and the second moment current value includes: When the carrier count value of each preset adjusted carrier period is zero, trigger a first sampling signal, and sample the output current of the inverter device based on the first sampling signal to obtain the first moment current value; When the carrier count value of each preset adjusted carrier period is the carrier count period value, trigger a second sampling signal, and sample the output current of the inverter device based on the second sampling signal to obtain the second moment current value.

[0010] Optionally, the adjusted carrier period is a carrier period selected from all the carrier periods included in one power frequency period according to a preset period interval.

[0011] Optionally, the adjustment of the carrier count period value by the proportional-integral controller includes: When the error value is positive, increase the carrier count period value based on a first adjustment strategy; When the error value is negative, decrease the carrier count period value based on a second adjustment strategy.

[0012] In a second aspect, an embodiment of the present application provides a parallel carrier synchronization method, which is applied to a multi-machine parallel inverter system. The multi-machine parallel inverter system includes a host machine and at least one slave machine. The method includes: controlling each slave machine in the at least one slave machine to execute the method described above.

[0013] In a third aspect, an embodiment of the present application provides an inverter device. The inverter device includes at least one processor and a memory communicatively connected to the at least one processor. The memory stores instructions executable by the at least one processor. The instructions are executed by the at least one processor so that the at least one processor can execute the method described above.

[0014] In a third aspect, an embodiment of the present application provides a multi-machine parallel inverter system. The multi-machine parallel inverter system includes a host machine and at least one slave machine. Control each slave machine in the at least one slave machine to execute the method described above.

[0015] Fourthly, an embodiment of the present application provides a computer storage medium storing instructions or programs, which, when executed by at least one processor, cause the at least one processor to execute the method described in any one of the above.

[0016] The beneficial effects of the embodiments of the present application are as follows: Different from the prior art, in the embodiments of the present application, a parallel machine carrier synchronization method is provided. First, the output current of the inverter device is sampled at the first moment and the second moment of each preset adjusted carrier period respectively to obtain the current value at the first moment and the current value at the second moment. Then, the difference between the current value at the first moment minus the current value at the second moment is used as an error value and input into the proportional-integral controller, and the carrier counting period value is adjusted by the proportional-integral controller. Based on the adjusted carrier counting period value, a corresponding carrier signal is output. In the method of the present application, the slave machine does not need to communicate with the master machine. By using a closed-loop control method to control the current difference between the first moment and the second moment of the carrier period to be zero, high-frequency circulating current can be suppressed and carrier synchronization can be achieved. It is not only simple in design and low in cost, but also does not depend on hardware accuracy and communication speed, and has high flexibility and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are illustrated by way of example in the accompanying drawings, which illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the drawings do not constitute a scale limitation.

[0018] Figure 1 Exemplarily shows a topological structure diagram of a multi-machine parallel inverter system; Figure 2 Exemplarily shows Figure 1 A simplified circuit diagram of the parallel output; Figure 3 Exemplarily shows the high-frequency voltage difference waveform diagrams corresponding to the carrier phase differences of 0 degrees, 90 degrees, and 180 degrees between two inverter devices; Figure 4 Exemplarily shows the structure diagram of the inverter device; Figure 5 Exemplarily shows a flowchart of a parallel machine carrier synchronization method; Figure 6 Exemplarily shows a schematic diagram of the current sampling moment; Figure 7 Exemplarily shows a schematic diagram of the execution process of the PI control algorithm. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Apparently, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the scope of protection of this application.

[0020] In addition, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0021] It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0022] Please refer to Figure 1 , Figure 1 which shows the topological structure diagram of a multi-machine parallel inverter system. As Figure 1 shown, this multi-machine parallel inverter system includes inverter device 10 and inverter device 20. Specifically, inverter device 10 and inverter device 20 are bidirectional PCS (Power Conversion System) power supplies, adopting an LC topology structure (L refers to an inductor, and C refers to a capacitor). After inverter device 10 and inverter device 20 are connected in parallel, the output interface becomes an LCCL structure, and the output voltage of the inverter device is at the capacitor C terminal. Since the PWM signal contains a power frequency signal and a carrier signal, the input of inductor L contains a power frequency voltage and a high-frequency voltage. Among them, through the attenuation of the LC low-pass filter for the high-frequency voltage, there is still a weak high-frequency voltage at the output of capacitor C, and this voltage signal is the high-frequency ripple voltage, usually in the range of a few volts.

[0023] Please refer to Figure 2 , Figure 2 which shows Figure 1 the simplified circuit diagram of the parallel output. Among them, is the output voltage of inverter device 10, is the output voltage of inverter device 20, is the line impedance of inverter device 10, is the line impedance of inverter device 20, is the load impedance. Under steady state, the load power is evenly distributed, or the load impedance of the and The current at both ends and The calculation formula is as follows:

[0024] Since the current is the same as below, only will be analyzed. According to 's calculation formula, it can be known that the output current contains a power frequency current component and a high-frequency circulating current component . Since , the power frequency current component is mainly determined by . In the high-frequency circulating current component, and respectively contain a power frequency voltage signal and a high-frequency voltage signal. When the power frequency signals are already synchronized, 's power frequency signals can cancel each other out, 's high-frequency signals depend on whether the carriers are synchronized. When the carriers are not synchronized, it will inevitably cause 's output voltage not to be zero, and is the line impedance of the two inverter devices, that is, the resistance value on the transmission cable, which is generally only a few tens of milliohms. Therefore, if the high-frequency voltages of the two inverter devices are not synchronized, a large high-frequency circulating current will be generated. As Figure 3 shows, when the carrier phase difference between the two inverter devices is 0 degrees (i.e., the carriers are synchronized), the triangular waves are in a coincident state and the high-frequency voltage difference is zero. When the carrier phase difference between the two inverter devices is 90 degrees or 180 degrees, a high-frequency voltage difference is formed.

[0025] Please refer to Figure 4 , Figure 4 which shows a structure of the inverter device 40. As Figure 4 shows, the inverter device 40 includes at least one processor 41 and a memory 42. Among them, the memory 42 can be built into the inverter device 40 or can be external to the inverter device 40. The memory 42 can also be a remotely set memory, and the inverter device 40 is connected through a network.

[0026] The memory 42 serves as a non-volatile computer-readable storage medium and can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The memory 42 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the terminal, etc. In addition, the memory 42 may include high-speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 42 optionally includes a memory remotely set relative to the processor 41, and these remote memories can be connected to the terminal through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0027] The processor 41 executes various functions of the terminal and processes data by running or executing software programs and / or modules stored in the memory 42 and calling data stored in the memory 42, thereby performing overall monitoring of the terminal, for example, implementing the parallel carrier synchronization method described in any embodiment of the present application.

[0028] The processor 41 can be one or more. Figure 4 Taking one processor 41 as an example. The processor 41 and the memory 42 can be connected through a bus or other means. The processor 41 may include a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a controller, a field programmable gate array (FPGA) device, etc. The processor 41 can also be implemented as a combination of computing devices. For example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0029] Please refer to Figure 5 , Figure 5 which shows a flowchart of a parallel carrier synchronization method applied to an inverter device. The inverter device may include a structure as shown in Figure 1 and Figure 4 shown.

[0030] As Figure 5 shown, the parallel carrier synchronization method applied to the inverter device includes: Step S501, sample the output current of the inverter device at the first moment and the second moment of each preset adjustment carrier period respectively to obtain the current value at the first moment and the current value at the second moment.

[0031] To better suppress high-frequency circulating current and more efficiently achieve carrier synchronization, the phase difference between the first moment and the second moment is about 180 degrees, preferably 180 degrees.

[0032] In one embodiment, the current sampling at the first moment and the second moment is triggered based on a timer. For example, assuming that the starting moment of the carrier period is t0, the first moment is t0 + , the carrier period is T, if the second moment is later than the first moment, the second moment t2 can be t0 + + T / 2. Specifically, the timer is started at the starting moment t0 of the carrier period. When the timing duration is , the current sampling at the first moment is triggered. When the timing duration is + T / 2, the current sampling at the second moment is triggered.

[0033] In a better embodiment, the current sampling at the first moment and the second moment is triggered based on the carrier count value. Taking the waveform of the carrier signal as a triangular wave as an example (the counting method of its carrier counter is to increase from zero to the carrier count period value and then decrease from the carrier count period value to zero), assuming that the carrier count period value is Arr, the carrier count value corresponding to the first moment is A1, if the second moment is later than the first moment, the carrier count value A2 corresponding to the second moment can be Arr - A1.

[0034] Generally, the chip supports triggering the current sampling when the carrier count value is zero and the carrier count period value. To simplify the design, the first moment can be set as the moment when the carrier count value is zero, and the second moment can be set as the moment when the carrier count value is the carrier count period value. Specifically, when the carrier count value of each preset adjusted carrier period is zero, the first sampling signal is triggered, and the output current of the inverter device is sampled based on the first sampling signal to obtain the current value at the first moment; when the carrier count value of each preset adjusted carrier period is the carrier count period value, the second sampling signal is triggered, and the output current of the inverter device is sampled based on the second sampling signal to obtain the current value at the second moment.

[0035] In one embodiment, the adjusted carrier period is each carrier period included in the power frequency period. In other embodiments, the adjusted carrier period is the carrier period selected from all the carrier periods included in one power frequency period according to a preset period interval. Taking a 50Hz sine wave as an example, the power frequency period is 20ms. Assuming that the carrier frequency is 20KHz, the carrier period is 50us, that is, each power frequency period includes 400 carrier periods. In the previous embodiment, all 400 carrier periods are adjusted carrier periods; in the latter embodiment, a certain number of carrier periods are evenly selected from the 400 carrier periods as the adjusted carrier periods. For example, if 10 carrier periods are selected as the adjusted carrier periods, the adjusted carrier periods are the 40th carrier period, the 80th carrier period, the 120th carrier period,..., the 400th carrier period respectively.

[0036] In step S502, the difference between the current value at the first moment and the current value at the second moment is used as the error value and input into the proportional-integral controller, and the carrier count period value is adjusted by the proportional-integral controller.

[0037] Taking the Figure 6 shown current sampling moments as an example, the principle of suppressing high-frequency circulating current by controlling the difference between the current value at the first moment and the current value at the second moment to zero will be discussed. Figure 6 In [the figure], the first moment is the moment when the carrier count value is zero, and the second moment is the moment when the carrier count value is the carrier count period value. Denote the moment when the carrier count value is zero as point a, and the current value at the first moment obtained by sampling the output current is ; denote the moment when the carrier count value is the carrier count period value as point b, and the current value at the second moment obtained by sampling the output current is . Based on the foregoing calculation formula, it can be known that and 's calculation formulas are:

[0038] Based on the foregoing description, it can be known that and also contain the power-frequency current part and the high-frequency circulating current part. By performing a subtraction operation on and , the power-frequency current part can be filtered out and the high-frequency circulating current part can be extracted. Specifically:

[0039] Simplifying the above formula, we can get:

[0040] Among them, is the peak-to-peak voltage of a carrier cycle, is the peak-to-peak value of the power-frequency current part, is the peak-to-peak value of the high-frequency current part.

[0041] Usually, it is a voltage of several volts. Assuming the peak-to-peak voltage is 5V, when the load is unloaded, the load impedance is infinite, and the peak-to-peak value of the power-frequency current approaches zero; when the load is fully loaded, calculated under the full-load condition of 120V / 2400W, the load impedance is 12 ohms, and the peak-to-peak value of the power-frequency current is 0.5A. In summary, the magnitude of the peak-to-peak value of the power-frequency current is 0 to 0.5A.

[0042] The expression for the peak-to-peak value of the high-frequency current is , the numerator is the peak-to-peak voltage error of two inverter devices, and the denominator is the impedance of the output wire (usually in milliohms). Assuming the wire impedance is 50 mΩ, then the peak-to-peak value of the high-frequency current is completely determined by the peak-to-peak voltage error of the two inverter devices. If the peak-to-peak voltage error of the two inverter devices is 5V, then the peak-to-peak value of the high-frequency current will reach 100A. As Figure 3 shown, when the carrier phase difference between the two inverter devices is 90 degrees or 180 degrees, a high-frequency peak-to-peak voltage difference is formed (i.e., ), and at 180 degrees, the high-frequency peak-to-peak voltage difference reaches the maximum value.

[0043] In summary, the peak-to-peak value of the power-frequency current is much smaller than the peak-to-peak value of the high-frequency current. The peak-to-peak value of the power-frequency current can be ignored. The calculation formula of

[0044] can be simplified as: where, represents the difference between the peak current and the valley current within one carrier period. Therefore, by controlling

[0045] to zero, the high-frequency circulating current can be suppressed and carrier synchronization can be achieved.

[0046] In one embodiment, adjusting the carrier counting period value by a proportional-integral controller includes: when the error value is positive, increasing the carrier counting period value based on the first adjustment strategy; when the error value is negative, decreasing the carrier counting period value based on the second adjustment strategy; when the error value is zero, keeping the carrier counting period value unchanged. Specifically, the first adjustment strategy and the second adjustment strategy can be set based on the time interval between adjacent adjusted carrier periods and the magnitude of the error value. For example, when the time interval between adjacent adjusted carrier periods and / or the error value is small, the adjustment amplitude value obtained based on the first adjustment strategy and the second adjustment strategy is small; when the time interval between adjacent adjusted carrier periods and / or the error value is large, the adjustment amplitude value obtained based on the first adjustment strategy and the second adjustment strategy is large.

[0047] Please refer to Figure 7 , Figure 7 which shows the execution process of the PI control algorithm. Among them, and are the sampled currents at the first moment and the second moment of each preset adjusted carrier period respectively. Subtracting - The value is input into an error regulator (i.e., a proportional-integral controller) to obtain an initial value of the adjustment amplitude of the carrier calculation period value. The initial value of the adjustment amplitude is subjected to a clipping process to output a final value of the adjustment amplitude. The final value of the adjustment amplitude is accumulated with the carrier count period value to obtain a new carrier count period value.

[0048] Step S503: Output a corresponding carrier signal based on the adjusted carrier count period value.

[0049] When the carrier count period value of the inverter device is adjusted, the output carrier signal is also adjusted accordingly. By driving the transistors of the inverter device with the drive signal obtained based on the adjusted carrier signal, carrier synchronization can be achieved.

[0050] The embodiment of the present application further provides a parallel carrier synchronization method applied to a multi-machine parallel inverter system. The multi-machine parallel inverter system includes a host machine and at least one slave machine. Among them, the host machine and the slave machine are connected in parallel using the Figure 1 shown topological structure. The parallel carrier synchronization method includes: controlling each of the at least one slave machine to execute the parallel carrier synchronization method applied to the inverter device in any embodiment of the present application.

[0051] From the calculation formula, it can be seen that the high-frequency circulating current component is , and theoretically, it is also possible to suppress the high-frequency circulating current by controlling to zero. However, since the carrier period is very short, for example, the PWM period of 20KHz is 50us. It is required to collect the voltages of two inverter devices and implement communication within 50us, which places too high requirements on the sensitivity of the device and the real-time performance of communication, and it is relatively difficult to implement. And the method of the present application does not require the slave machine to communicate with the host machine. By using a closed-loop control method to control the current difference between the first moment and the second moment of the carrier period to be zero, the high-frequency circulating current can be suppressed and carrier synchronization can be achieved. It is not only simple in design and low in cost, but also does not depend on hardware accuracy and communication speed, and has high flexibility and reliability.

[0052] The embodiment of the present application further provides a computer storage medium. The computer storage medium stores instructions or programs. When the instructions or programs are executed by one or more processors, the one or more processors can execute the parallel carrier synchronization method in any method embodiment described above.

[0053] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution or the part that contributes to the related technology can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0054] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. Therefore, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A parallel carrier synchronization method, characterized in that, Applied to an inverter device, the method includes: Sampling the output current of the inverter device at a first moment and a second moment of each preset carrier adjustment period respectively to obtain a first moment current value and a second moment current value; Taking the difference between the first moment current value and the second moment current value as an error value and inputting it into a proportional-integral controller to adjust the carrier counting period value through the proportional-integral controller; Outputting a corresponding carrier signal based on the adjusted carrier counting period value.

2. The method according to claim 1, wherein The phase difference between the first moment and the second moment is 180 degrees.

3. The method according to claim 1, wherein The waveform of the carrier signal is a triangular wave. The first moment is the moment when the carrier count value is zero, and the second moment is the moment when the carrier count value is the carrier counting period value.

4. The method according to claim 3, wherein The step of sampling the output current of the inverter device at a first moment and a second moment of each preset carrier adjustment period respectively to obtain a first moment current value and a second moment current value includes: Triggering a first sampling signal when the carrier count value of each preset carrier adjustment period is zero, and sampling the output current of the inverter device based on the first sampling signal to obtain the first moment current value; Triggering a second sampling signal when the carrier count value of each preset carrier adjustment period is the carrier counting period value, and sampling the output current of the inverter device based on the second sampling signal to obtain the second moment current value.

5. The method according to claim 1, characterized in that, The adjusted carrier period is a carrier period selected from all the carrier periods included in one power frequency period according to a preset period interval.

6. The method according to any one of claims 1 to 5, characterized in that The step of adjusting the carrier counting period value through the proportional-integral controller includes: When the error value is positive, increasing the carrier counting period value based on a first adjustment strategy; When the error value is negative, decreasing the carrier counting period value based on a second adjustment strategy.

7. A parallel carrier synchronization method, characterized in that, Applied to a multi-machine parallel inverter system, the multi-machine parallel inverter system includes a host machine and at least one slave machine. The method includes: Controlling each slave machine in the at least one slave machine to execute the method according to any one of claims 1 to 6.

8. An inverter device, characterized in that, The inverter device includes at least one processor and a memory communicatively connected to the at least one processor. The memory stores instructions executable by the at least one processor. When the instructions are executed by the at least one processor, the at least one processor is enabled to execute the method according to any one of claims 1 to 6.

9. A multi-machine parallel inverter system, characterized in that, The multi-machine parallel inverter system includes a host machine and at least one slave machine. Controlling each slave machine in the at least one slave machine to execute the method according to any one of claims 1 to 6.

10. A computer storage medium, characterized in that, The computer storage medium stores instructions or programs. When the instructions or programs are executed by at least one processor, the at least one processor is enabled to execute the method according to any one of claims 1 to 7.

Images