Compensating circuit of high-switching-frequency Buck converter and application of compensating circuit

Abstract

The invention provides a compensating circuit of a high-switching-frequency Buck converter and application of the compensating circuit, and belongs to the technical field of Buck converters. According to the compensating circuit, a high gain branch and a low gain branch are designed, wherein the branch including a first transconductance operational amplifier OTA1 has the characteristics of low gain and high bandwidth; the branches including the second transconductance operational amplifier OTA2 have the characteristics of high gain and low bandwidth, and the two branches are provided with corresponding active devices. A feedback voltage signal carrying switching noise is mainly introduced into a subsequent loop through two paths, the first loop passes through the first transconductance operational amplifier OTA1, the high-frequency gain of the path is extremely low, and the high-frequency gain of the switching noise can be effectively suppressed; and the second path passes through an advanced compensation module PD, a second transconductance operational amplifier OTA2 and a divider DIV to form current to charge a second capacitor C2, but the capacitor has an integral effect, so that the high-frequency gain of switching noise is effectively reduced. Compared with traditional three-type compensation, the method has higher noise suppression capability.

Description

Technical Field

[0001] The present invention belongs to the technical field of Buck converters, and particularly relates to a compensation circuit for a high-switching-frequency Buck converter and its application. Background Art

[0002] A Buck converter is a type of DC voltage converter mainly used to reduce the input voltage to the required output voltage. The control methods of Buck converters can be mainly divided into voltage mode and current mode. Among them, the voltage mode has the advantages of simple control and high signal-to-noise ratio. Therefore, voltage-mode control has always been one of the mainstream control methods for Buck converters.

[0003] In the design of voltage-mode Buck converters, since there is a pair of LC double poles in the transfer function of the Buck converter in voltage mode, a Type-III compensation circuit is usually used to optimize the dynamic response performance, and its structure is as Figure 1 shown. The Type-III compensation circuit will generate two zeros to compensate for the LC double poles in the voltage-mode Buck converter. Such a configuration can provide a good phase margin and ensure system stability within a wide frequency range. However, with the traditional Type-III compensation circuit, the high-frequency gain of the switching noise of the Buck converter will be introduced into the loop through the compensation path, affecting the stability of the loop. In addition, the traditional Type-III compensation requires a large number of passive devices and occupies a large area, making chip integration more difficult. Summary of the Invention

[0004] Aiming at the problems existing in the background art, the purpose of the present invention is to provide a compensation circuit for a high-switching-frequency Buck converter and its application. The compensation circuit designs high and low gain branches. The branch including the first transconductance operational amplifier OTA1 has the characteristics of low gain and high bandwidth; the branch including the second transconductance operational amplifier OTA2 has the characteristics of high gain and low bandwidth. The two branches select specific active devices to overcome the problem of poor loop stability of the traditional Type-III compensation circuit while compensating for the LC double poles in the Buck converter.

[0005] To achieve the above object, the technical solution of the present invention is as follows:

[0006] A compensation circuit for a high-switching-frequency Buck converter, including a first bias current I B1 , a second bias current I B2 , a first transconductance operational amplifier OTA1, a second transconductance operational amplifier OTA1, a lead compensation module PD, a divider DIV, a first switch S1, a first resistor R1, a first capacitor C1, a second capacitor C2, and a comparator COMP;

[0007] The output terminal of the first transconductance operational amplifier OTA1 is connected to the first end of the first resistor R1 and the positive input terminal of the comparator COMP. The positive input terminal of the first transconductance operational amplifier OTA1 is connected to the reference voltage V REF , and the negative input terminal is connected to the feedback voltage V FB ; the input terminal of the lead compensation module PD is connected to the feedback voltage V FB , and the output terminal is connected to the positive input terminal of the second transconductance operational amplifier OTA2; the output terminal of the second transconductance operational amplifier OTA2 is connected to the first input terminal of the divider DIV, and the negative input terminal is connected to the reference voltage V REF ; the output terminal of the divider DIV is connected to the first end of the switching device S1, the first end of the second capacitor C2, and the negative input terminal of the comparator COMP. The second input terminal of the divider DIV is connected to the first bias current I B1 , and the third input terminal is connected to the second bias current I B2 ; the second end of the first resistor R1 is connected to the first end of the first capacitor C1; the second end of the switching device S1, the second end of the first capacitor C1, and the second end of the second capacitor C2 are all grounded.

[0008] Preferably, the lead compensation module PD includes an operational amplifier EA, a second resistor R2, a third resistor R3, and a third capacitor C3;

[0009] The positive input terminal of the operational amplifier EA is the input terminal of the lead compensation module PD and is connected to the feedback voltage V FB . The negative input terminal is connected to the first end of the second resistor R2, the first end of the third resistor R3, and the first end of the third capacitor C3. The output terminal is the output terminal of the lead compensation module PD and is connected to the second end of the second resistor R2; the second end of the third resistor R3 and the second end of the third capacitor C3 are both grounded.

[0010] Preferably, the first switch S1 is a triode or a MOSFET.

[0011] Preferably, the magnitudes of the first capacitor, the second capacitor, the second resistor, and the bias current are determined by the output inductor, the output capacitor of the Buck converter, and the required loop bandwidth. The magnitude of the reference voltage V REF is determined by the usage requirements of the Buck converter itself.

[0012] Preferably, the compensation circuit frequency should be selected such that z1 < z2 < p1 and where z1 is the zero point of the branch where the first transconductance operational amplifier OTA1 is located, z2 is the zero point of the lead compensation module PD, and p1 is the pole of the branch where the second transconductance operational amplifier OTA1 is located.

[0013] Preferably, z1 depends on the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1, and z2 depends on the overall resistance value and capacitance value in the lead compensation module.

[0014] The present invention also provides a Buck converter, which includes the above compensation circuit and also includes an input voltage V IN , power switches S2 and S3, an output inductor L, an output resistor C OUT , a parasitic resistance ESR, an output load LOAD, a first feedback resistor R F1 , a second feedback resistor R F2 , a logic module Main Logic and a driver Driver;

[0015] The input end of the logic module Main Logic is connected to the output end of the compensation circuit, and the output end is connected to the input end of the driver Driver; the first output end of the driver Driver controls the turning on and off of the power switch S2, and the second output end controls the turning on and off of the power switch S3; the first end of the power switch S2 is connected to the input voltage V IN , and the second end is respectively connected to the first end of the power switch S3 and the first end of the output inductor L; the second end of the output inductor L is connected to the first end of the output capacitor C OUT , the first end of the load LOAD, and the first end of the first feedback resistor R F1 ; the second end of the output capacitor C OUT is connected to the first end of the parasitic resistance ESR; the second end of the first feedback resistor R F1 is connected to the first end of the second feedback resistor R F2 , and the input end of the compensation circuit; the second ends of the power switch S3, the parasitic resistance ESR, the load LOAD, and the second feedback resistor R F2 are all grounded.

[0016] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention are:

[0017] 1. The present invention reduces the area of passive devices compared with the traditional type III compensation;

[0018] 2. In the present invention, the feedback voltage signal carrying switching noise is mainly introduced into the subsequent loop through two paths. The first branch is through the first transconductance operational amplifier OTA1, and the high-frequency gain of this path is extremely low, and the high-frequency gain of the switching noise can be effectively suppressed; the second branch forms a current to charge the second capacitor C2 after passing through the lead compensation module PD, the second transconductance operational amplifier OTA2, and the divider DIV, but the capacitor itself has an integral effect, which will effectively reduce the high-frequency gain of the switching noise. The present invention has stronger noise suppression ability compared with the traditional type III compensation. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1It is a schematic structural diagram of a traditional type-three compensation circuit.

[0020] Figure 2 It is a schematic structural diagram of the high-switching-frequency Buck converter of the present invention.

[0021] Figure 3 It is a schematic circuit diagram of the lead compensation module PD in the compensation circuit.

[0022] Figure 4 It is a small-signal schematic diagram of the compensation circuit in the high-switching-frequency Buck converter of the present invention.

[0023] Figure 5 It is a schematic diagram of the transfer function of the lead compensation module PD;

[0024] Figure 6 It is a schematic diagram of the relationship between the ramp voltage and the PWM signal;

[0025] Figure 7 It is a schematic diagram of the transfer function of the compensation circuit in the high-switching-frequency Buck converter of the present invention. Specific embodiments

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the embodiments and the accompanying drawings.

[0027] Figure 2 It is a schematic structural diagram of the high-switching-frequency Buck converter of the present invention. The Buck converter includes a compensation circuit and also includes an input voltage V IN , power switches S2 and S3, an output inductor L, an output resistor C OUT , a parasitic resistor ESR, an output load LOAD, a first feedback resistor R F1 , a second feedback resistor R F2 , a logic module Main Logic, and a driver Driver;

[0028] The input end of the logic module Main Logic is connected to the output end of the compensation circuit, and the output end is connected to the input end of the driver Driver; the first output end of the driver Driver controls the turning on and off of the power switch S2, and the second output end controls the turning on and off of the power switch S3; the first end of the power switch S2 is connected to the input voltage V IN , and the second end is respectively connected to the first end of the power switch S3 and the first end of the output inductor L; the second end of the output inductor L is connected to the first end of the output capacitor C OUT , the first end of the load LOAD, and the first end of the first feedback resistor R F1 ; the output capacitor C OUTThe second end of which is connected to the first end of the parasitic resistance ESR; the first feedback resistor R F1 The second end of which is connected to the second feedback resistor R F2 The first end, the input end of the compensation circuit; the second end of the power switch S3, the second end of the parasitic resistance ESR, the second end of the load LOAD, the second end of the second feedback resistor R F2 The second ends are all grounded;

[0029] The compensation circuit includes a first bias current I B1 、a second bias current I B2 、a first transconductance operational amplifier OTA1, a second transconductance operational amplifier OTA1, a lead compensation module PD, a divider DIV, a first switch S1, a first resistor R1, a first capacitor C1, a second capacitor C2 and a comparator COMP;

[0030] The output end of the first transconductance operational amplifier OTA1 is connected to the first end of the first resistor R1 and the positive input end of the comparator COMP. The positive input end of the first transconductance operational amplifier OTA1 is connected to the reference voltage V REF , and the negative input end is connected to the feedback voltage V FB , and the negative input end is also the input end of the compensation circuit; the input end of the lead compensation module PD is connected to the feedback voltage V FB , and the output end is connected to the positive input end of the second transconductance operational amplifier OTA2; the output end of the second transconductance operational amplifier OTA2 is connected to the first input end of the divider DIV, and the negative input end is connected to the reference voltage V REF ; the output end of the divider DIV is connected to the first end of the switching device S1, the first end of the second capacitor C2, and the negative input end of the comparator COMP. The output end of the comparator COMP is also the output end of the compensation circuit; the second input end of the divider DIV is connected to the first bias current I B1 , and the third input end is connected to the second bias current I B2 ; the second end of the first resistor R1 is connected to the first end of the first capacitor C1; the second ends of the switching device S1, the first capacitor C1, and the second capacitor C2 are all grounded.

[0031] A schematic diagram of an implementable circuit structure of the lead compensation module PD is as Figure 3 shown. The lead compensation module PD includes an operational amplifier EA, a second resistor R2, a third resistor R3, and a third capacitor C3. The positive input end of the operational amplifier EA is used as the input end of the lead compensation module PD and is connected to the feedback voltage V FB , and the negative input end is respectively connected to the first end of the second resistor R2, the first end of the third resistor R3, and the first end of the third capacitor C3. The output end is used as the output end of the lead compensation module PD and is connected to the second end of the second resistor R2; the second ends of the third resistor R3 and the third capacitor C3 are both grounded.

[0032] In the steady state, the feedback voltage V FB and the reference voltage V REF form a current after passing through the first transconductance operational amplifier OTA1. This current flows through the first resistor R1 and the first capacitor C1 to form a stable control voltage V C ; meanwhile, the feedback voltage V FB obtains a compensated voltage V PD after passing through the lead compensation module PD. V PD and the reference voltage V REF form an error current I D after passing through the second transconductance operational amplifier OTA2. This current, together with the bias currents I B1 and I B2 , jointly flows into a divider for current division operation to obtain the divider output current I C . The clock signal CLK generated by the logic module controls the switch S1 to turn on and conduct, enabling I C to periodically charge the capacitor C2 and finally generate a ramp voltage V SAW ; V C and V SAW finally output a PWM square wave signal carrying duty cycle information through a comparator. The PWM signal determines the turn-on and turn-off of the power transistor after passing through the logic module and the drive module.

[0033] The derivation process of the transfer function of the high-frequency Buck circuit compensation structure of the present invention is as follows:

[0034] As Figure 4 shown is the small-signal equivalent diagram of the compensation circuit of the present invention, and it can be obtained that:

[0035] T(s) = A(s) + B(s) (1)

[0036] Among them, A(s) is the equivalent transfer function from the first transconductance operational amplifier OTA1 to the comparator output, B(s) is the equivalent transfer function from the lead compensation module PD to the comparator output, and T(s) is the overall transfer function of the compensation circuit.

[0037] The derivation of A(s) is relatively simple. Regarding the feedback voltage as a high-frequency small-signal source, it can be directly obtained that:

[0038]

[0039] Among them, gm1 is the transconductance of the first transconductance operational amplifier OTA1, z1 is the first zero point in A(s), s is the complex frequency variable, C1 is the capacitance value of the first capacitor, R1 is the resistance value of the first resistor, and K1 is the low-frequency gain of the branch where the first transconductance OTA1 is located.

[0040] The lead compensation module PD compensates the feedback voltage V FBFor the clamping, we can obtain:

[0041]

[0042] Among them, v PD (s) is the representation of the output voltage of the lead compensation module PD in the frequency domain, and v FB (s) is the representation of the feedback voltage V FB in the frequency. z2 is the zero point of the lead compensation module, R2 is the resistance value of the second resistor, R3 is the resistance value of the third resistor, C3 is the capacitance value of the third capacitor, and ∥ represents taking the union value.

[0043] In the design, if the second transconductance operational amplifier OTA2 has a pole p1, and z1 < z2 < p1 is set in terms of frequency, then the output I D of the second transconductance operational amplifier to the feedback voltage V FB has the following transfer function:

[0044]

[0045] Among them, gm2 is the transconductance of the second transconductance operational amplifier OTA2, and i D (s) is the representation of the second transconductance operational amplifier OTA2 in the frequency domain, and gm2 is the transconductance of the second transconductance operational amplifier OTA2. As Figure 5 shown, where (a) is the Bode plot of the transfer function from V FB to I D , and (b) is the Bode plot of the transfer function A(s).

[0046] I D and the first bias current I B1 , the second bias current I B2 pass through a divider to obtain the capacitor charging current, and we can obtain:

[0047]

[0048] The relationship between the ramp voltage and the comparator output is as Figure 6 shown. According to the relationship between current and capacitor voltage, we can obtain:

[0049] I C ·D·T SW = C2·V C (6)

[0050] Among them, D is the duty cycle of the Buck converter, T SW is the time of one period, and V C is the representation of the output terminal voltage of the first transconductance operational amplifier OTA1 in the frequency domain.

[0051] Combining formula (4), formula (5) and formula (6), we can obtain:

[0052]

[0053] d(s) is the representation of the duty cycle in the frequency domain in the Buck converter, and K2 is the low-frequency gain of the branch where the second transconductance OTA2 is located.

[0054] Substituting Equation (2) and Equation (7) into Equation (1) gives:

[0055]

[0056] It can be seen from Equation (8) that this structure has two poles and two zeros. The main pole is at the origin, and the secondary pole is at the frequency where p1 is located. The two poles can be written as:

[0057] f p1 = 0; f p2 = p1 (9)

[0058] Using the quadratic formula for the numerator gives:

[0059]

[0060] Given z1 < z2 < p1, if the design and the low-frequency gain of B(s) is very small, that is, K1 is much larger than K2, Equation (10) can be simplified to:

[0061]

[0062] Finally, the solution is:

[0063]

[0064] It can be seen from Equation (12) that the obtained zeros are all zeros in the left half plane, and both zeros are before the secondary pole of the loop. Therefore, the Bode plot of the transfer function of the compensation circuit designed in the present invention is as Figure 7 shown. Among them, the main pole f p1 serves as the main pole of the Buck converter, f z1 and f z2 are used to compensate the LC double-pole pair at the output of the Buck converter to ensure the stability of the loop. The secondary pole f p2 is used to compensate the zero formed by the output capacitor C OUT at the output of the Buck converter and the parasitic resistance ESR.

[0065] So far, in principle, the compensation circuit of the present invention can achieve loop compensation for the voltage-mode Buck converter, where the main pole f p1 at the origin serves as the main pole of the Buck converter; the secondary pole f p2To compensate for the ESR zero at the output of the Buck converter and suppress high-frequency noise; f z1 and f z2 To compensate for the LC double-pole pair at the output of the Buck converter and ensure the stability of the loop.

[0066] As described above, only the specific embodiments of the present invention are concerned. Any feature disclosed in this specification, unless specifically stated, can be replaced by other equivalent or alternative features with similar purposes; all the features disclosed, or all the steps in any method or process, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A compensation circuit for a high switching frequency Buck converter, characterized in that: Including the first bias current I B1 , the second bias current I B2 , a first transconductance amplifier OTA1, a second transconductance amplifier OTA1, a lead compensation module PD, a divider DIV, a first switch S1, a first resistor R1, a first capacitor C1, a second capacitor C2 and a comparator COMP; The output end of the first transconductance amplifier OTA1 is connected to the first end of the first resistor R1 and the positive input end of the comparator COMP, and the positive input end of the first transconductance amplifier OTA1 is connected to the reference voltage V REF , the negative input terminal is connected to the feedback voltage V FB The input terminal of the lead compensation module PD is connected to the feedback voltage V FB , the output end is connected to the positive input end of the second transconductance amplifier OTA2; the output end of the second transconductance amplifier OTA2 is connected to the first input end of the divider DIV, and the negative input end is connected to the reference voltage V REF The output end of the divider DIV is connected to the first end of the switch device S1, the first end of the second capacitor C2, and the negative input end of the comparator COMP, and the second input end of the divider DIV is connected to the first bias current I B1 , the third input terminal is connected to the second bias current I B2 The second end of the first resistor R1 is connected to the first end of the first capacitor C1; the second end of the switch device S1, the second end of the first capacitor C1, and the second end of the second capacitor C2 are all grounded.

2. The compensation circuit according to claim 1, characterized in that: The lead compensation module PD includes an operational amplifier EA, a second resistor R2, a third resistor R3, and a third capacitor C3; The positive input terminal of the operational amplifier EA is the input terminal of the lead compensation module PD, and is connected to the feedback voltage V FB The negative input end is connected to the first end of the second resistor R2, the first end of the third resistor R3, and the first end of the third capacitor C3; the output end is the output end of the lead compensation module PD, connected to the second end of the second resistor R2; the second end of the third resistor R3 and the second end of the third capacitor C3 are both grounded.

3. The compensation circuit according to claim 1, characterized in that: The first switch S1 is a transistor or a MOSFET.

4. The compensation circuit according to claim 1, characterized in that: The first capacitor, the second capacitor, the second resistor, and the bias current are determined by the Bcuk converter output inductor, output capacitor, and required loop bandwidth. The reference voltage V REF The size is determined by the usage requirements of the Buck converter itself.

5. The compensation circuit according to claim 1, characterized in that: The frequency selection of the compensation circuit should satisfy z1 < z2 < p1 and where z1 is the zero point of the branch where the first transconductance operational amplifier OTA1 is located, z2 is the zero point of the lead compensation module PD, and p1 is the pole of the branch where the second transconductance operational amplifier OTA2 is located.

6. The compensation circuit according to claim 1, characterized in that: z1 depends on the resistance of the first resistor R1 and the capacitance of the first capacitor C1, and z2 depends on the overall resistance and capacitance of the lead compensation module.

7. A Buck converter, characterized in that: The Buck converter comprises the compensation circuit according to any one of claims 1 to 6, and also comprises an input voltage V IN , power switches S2 and S3, output inductor L, output resistor C OUT , parasitic resistance ESR, output load LOAD, first feedback resistor R F1 , the second feedback resistor R F2 , logic module Main Logic and driver Driver; The input end of the logic module Main Logic is connected to the output end of the compensation circuit, and the output end is connected to the input end of the driver Driver; the first output end of the driver Driver controls the opening and closing of the power switch S2, and the second output end controls the opening and closing of the power switch S3; the first end of the power switch S2 is connected to the input voltage V IN The second end is connected to the first end of the power switch S3 and the first end of the output inductor L respectively; the second end of the output inductor L is connected to the output capacitor C OUT The first end of the load LOAD, the first feedback resistor R F1 The first end of the output capacitor C OUT The second end of the feedback resistor R F1 The second end of the second feedback resistor R F2 the first end of the power switch S3, the second end of the parasitic resistor ESR, the second end of the load LOAD, the second feedback resistor R F2 The second ends of are grounded.

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