Packaging structure for piezoelectric MEMS resonator and electronic component

Abstract

The invention provides a packaging structure for a piezoelectric MEMS resonator and an electronic component, and belongs to the field of semiconductor devices.The packaging structure comprises a device wafer, a cap wafer, a first insulating layer and a metal layer, and the first insulating layer and the metal layer are arranged on the cap wafer. The substrate layer comprises a substrate area and a first resonance cavity area surrounded by the substrate area; the device silicon layer, the first dielectric layer, the piezoelectric layer and the top electrode layer are arranged on the substrate layer; the cap wafer comprises a cap layer; the first annular isolation groove is formed in the cap layer, and the first annular isolation groove is filled with a second dielectric layer; wherein the surface, bonded with the cap wafer, of the device wafer is the surface, far away from the substrate layer, of the device silicon layer, the surface, bonded with the device wafer, of the cap wafer is the surface, far away from the first insulating layer, of the cap layer, and the cap layer is made of low-resistance monocrystalline silicon. According to the packaging structure, the packaging vacuum degree can be effectively improved, and the working performance of the resonator is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular, to a packaging structure and an electronic component for a piezoelectric MEMS resonator. Background Art

[0002] With the development of piezoelectric thin film materials, compared with electrostatically driven silicon-based MEMS resonators, piezoelectrically driven silicon-based MEMS resonators (abbreviated as "piezoelectrically driven silicon-based MEMS resonators") exhibit excellent performance such as lower motional impedance and higher electromechanical coupling coefficient, which is more conducive to reducing the power consumption and phase noise of oscillators. Since piezoelectrically driven silicon-based MEMS resonators do not require an applied electrostatic bias voltage, the error terms generated by the power supply jitter on the output signal are reduced; in addition, piezoelectrically driven silicon-based MEMS resonators do not require the formation of sub-micron silicon layer slits during processing, reducing the process difficulty, which is beneficial to improving the device yield and further miniaturization of the device.

[0003] Currently, piezoelectrically driven silicon-based MEMS resonators often adopt a wafer-level packaging structure. However, when packaging at the wafer level, a bonding method with a metal layer is generally used, and its vacuum degree is relatively low, usually on the order of 10 Pa, which is difficult to meet the requirements of piezoelectric MEMS resonators for vacuum degree.

[0004] This section aims to provide background or context for the embodiments of the present application stated in the claims. The description herein is not admitted to be prior art because it is included in this section. Summary of the Invention

[0005] Aiming at the problems existing in the prior art, the present application provides a packaging structure and an electronic component for a piezoelectric MEMS resonator, which can effectively improve the packaging vacuum degree and the working performance of the resonator.

[0006] According to the first aspect of the present application, there is provided a packaging structure for a piezoelectric MEMS resonator, the packaging structure including: a device wafer, a capping wafer, and a first insulating layer and a metal layer provided on the capping wafer, wherein:

[0007] The device wafer includes: a substrate layer, wherein the substrate layer includes a substrate region and a first resonant cavity region surrounded by the substrate region; and a device silicon layer, a first dielectric layer, a piezoelectric layer, and a top electrode layer provided on the substrate layer, wherein the material of the top electrode layer is doped polysilicon;

[0008] The capping wafer includes: a capping layer; and a first annular isolation groove formed in the capping layer, wherein the first annular isolation groove is filled with a second dielectric layer;

[0009] Wherein, the surface of the device wafer bonded to the capping wafer is the surface of the device silicon layer away from the substrate layer, the surface of the capping wafer bonded to the device wafer is the surface of the capping layer away from the first insulating layer, and the material of the capping layer is low-resistivity single-crystalline silicon.

[0010] In some alternative embodiments of the present embodiment, the bonding position of the device wafer and the capping wafer is on the same side of the piezoelectric layer in the device silicon layer; at the bonding position, the capping wafer forms an electrical connection and a sealing ring with the surface of the device silicon layer away from the substrate layer through silicon-silicon bonding.

[0011] The capping wafer further includes a second resonant cavity region, wherein the orthographic projection of the first resonant cavity region on the substrate layer and the orthographic projection of the second resonant cavity region on the substrate layer at least partially overlap; the second resonant cavity region is used to accommodate the piezoelectric layer, the top electrode layer, and a part of the first dielectric layer.

[0012] The orthographic projection of the bonding position of the device wafer and the capping wafer on the substrate layer does not overlap with the orthographic projection of the first resonant cavity region on the substrate layer.

[0013] In some alternative embodiments of the present embodiment, the device wafer further includes a second insulating layer located between the device silicon layer and the substrate layer, wherein:

[0014] The part of the second insulating layer corresponding to the first resonant cavity region is located on the surface of the device silicon layer close to the substrate layer; or

[0015] The part of the second insulating layer corresponding to the first resonant cavity region is located on the surface of the substrate region close to the device silicon layer.

[0016] In some alternative embodiments of the present embodiment, the device silicon layer further includes a second annular isolation groove arranged on the same layer, wherein the second annular isolation groove is filled with the first dielectric layer; at least part of the first dielectric layer on the device silicon layer located inside the ring of the second annular isolation groove is removed to expose the device silicon layer.

[0017] In some alternative embodiments of the present embodiment, at least part of the piezoelectric layer is directly disposed on the device silicon layer, and the orthographic projection of the region where the piezoelectric layer contacts the device silicon layer on the substrate layer at least partially overlaps with the orthographic projection of the first resonant cavity region on the substrate layer.

[0018] In some alternative embodiments of the present embodiment, at least part of the piezoelectric layer is located on the first dielectric layer.

[0019] In some alternative embodiments of the present embodiment, the top electrode layer is located above the piezoelectric layer, and the top electrode layer straddles the piezoelectric layer and at least one of the second annular isolation grooves to electrically connect to the exposed device silicon layer within the ring.

[0020] In some alternative embodiments of the present embodiment, the bonding positions include a sealing ring bonding position and a pin bonding position, where:

[0021] The orthographic projection of the sealing ring bonding position on the substrate layer is annular, and the orthographic projection of the sealing ring bonding position on the substrate layer surrounds the orthographic projection of the pin bonding position on the substrate layer;

[0022] At least one of the pin bonding positions is located within the ring portion of the second annular isolation groove.

[0023] In some alternative embodiments of the present embodiment, the device wafer further includes: a first trench penetrating the first stacked structure of the device wafer, where:

[0024] The first trench is used to connect the first resonant cavity region and the second resonant cavity, and to define the shape and boundary region of the resonator.

[0025] In some alternative embodiments of the present embodiment, the first stacked structure includes the device silicon layer and a second stacked structure, where the second stacked structure includes at least one of the first dielectric layer, the second insulating layer, and the piezoelectric layer.

[0026] In some alternative embodiments of the present embodiment, the ring portion within the first annular isolation groove is a conductive via, and the conductive via is electrically connected to the metal layer so that the conductive via leads out the electrical signal in the device wafer to the side of the capping layer close to the first insulating layer.

[0027] In some alternative embodiments of the present embodiment, the material of the second dielectric layer includes silicon dioxide and polysilicon; or the material of the second dielectric layer includes silicon dioxide.

[0028] In some alternative embodiments of the present embodiment, a first raised structure is formed at the bonding position on the side of the capping layer away from the first insulating layer, and the first annular isolation groove is located outside the first raised structure at the pin bonding position;

[0029] Wherein, the height of the first raised structure is at least higher than the thickness of the first dielectric layer; the depth of the second resonant cavity region is greater than or equal to the height of the first raised structure.

[0030] In some alternative embodiments of the present embodiment, the capping wafer further includes a second resonant cavity region formed on a side of the capping layer away from the first insulating layer, and a positive projection of the first resonant cavity region on the substrate layer and a positive projection of the second resonant cavity region on the substrate layer at least partially overlap;

[0031] The bonding position of the device wafer and the capping wafer is on a side of the device silicon layer away from the substrate layer, and the piezoelectric layer is on a side of the device silicon layer close to the substrate layer; at the bonding position, the capping wafer forms an electrical connection and a sealing ring with a side of the device silicon layer away from the substrate layer through silicon-silicon bonding;

[0032] The first resonant cavity region is used to accommodate the piezoelectric layer, the top electrode layer, and a part of the first dielectric layer.

[0033] In some alternative embodiments of the present embodiment, the device wafer further includes a third insulating layer disposed on the device silicon layer and a third annular isolation groove disposed on the same layer as the third insulating layer and the device silicon layer, wherein the third annular isolation groove serves as a lead region on a side of the device silicon layer away from the substrate layer; the third annular isolation groove is filled with a third dielectric layer;

[0034] Wherein, a positive projection of at least one of the third annular isolation grooves and a part of the device silicon layer located inside the ring of the third annular isolation groove on the substrate layer falls within a positive projection of the first resonant cavity region on the substrate layer;

[0035] The top electrode layer is electrically connected to a part of the device silicon layer located inside the ring of the third annular isolation groove.

[0036] In some alternative embodiments of the present embodiment, the device wafer further includes a second trench penetrating through a third stacked structure of the device wafer, wherein:

[0037] The second trench is used to communicate the first resonant cavity region and the second resonant cavity region, and to define the shape and boundary region of the resonator.

[0038] In some alternative embodiments of the present embodiment, the third stacked structure includes the device silicon layer and a fourth stacked structure, wherein the fourth stacked structure includes at least one of the third insulating layer, the third dielectric layer, and the first dielectric layer;

[0039] A positive projection of the bonding position of the device wafer and the capping wafer on the substrate layer does not overlap with a positive projection of the first resonant cavity region on the substrate layer.

[0040] In some alternative embodiments of the present embodiment, the device wafer further includes a fourth insulating layer disposed on the device silicon layer and a fourth annular isolation groove disposed on the same layer as the device silicon layer, wherein the fourth annular isolation groove serves as a lead region on the side of the device silicon layer close to the substrate layer; the fourth annular isolation groove is filled with the first dielectric layer

[0041] Wherein, the positive projection of at least one of the fourth annular isolation grooves and a part of the device silicon layer located inside the ring of the fourth annular isolation groove on the substrate layer falls within the positive projection of the first resonant cavity region on the substrate layer;

[0042] The top electrode layer is electrically connected to a part of the device silicon layer located inside the ring of the fourth annular isolation groove.

[0043] In some alternative embodiments of the present embodiment, the device wafer further includes a third trench penetrating the fifth stacked structure of the device wafer, wherein:

[0044] The third trench is used to communicate the first resonant cavity region and the second resonant cavity region, and to define the shape and boundary region of the resonator.

[0045] In some alternative embodiments of the present embodiment, the fifth stacked structure includes the device silicon layer and a sixth stacked structure, wherein the sixth stacked structure includes at least one of the fourth insulating layer and the first dielectric layer;

[0046] The positive projection of the bonding position between the device wafer and the capping wafer on the substrate layer does not overlap with the positive projection of the first resonant cavity region on the substrate layer.

[0047] In some alternative embodiments of the present embodiment, the bonding position between the device wafer and the capping wafer is on the side of the device silicon layer away from the substrate layer, and the piezoelectric layer is on the side of the device silicon layer close to the substrate layer; at the bonding position, the capping wafer forms an electrical connection and a sealing ring with the side of the device silicon layer away from the substrate layer through silicon-silicon bonding;

[0048] The first resonant cavity region is used to accommodate the piezoelectric layer, the top electrode layer, and a part of the first dielectric layer;

[0049] The device wafer further includes a third resonant cavity region, wherein the third resonant cavity region is formed by locally thinning the side of the device silicon layer away from the substrate layer; the depth of the third resonant cavity region is less than the thickness of the device silicon layer;

[0050] Wherein, the orthographic projection of the third resonant cavity region on the substrate layer and the orthographic projection of the first resonant cavity region on the substrate layer at least partially overlap.

[0051] In some alternative embodiments of the present embodiment, the device wafer further includes a fourth trench penetrating through the seventh stacked structure of the device wafer, wherein:

[0052] The fourth trench is used to connect the first resonant cavity region and the third resonant cavity region, and to define the shape and boundary region of the resonator;

[0053] On one side of the device silicon layer away from the substrate layer, a second convex structure is formed at at least one pin bonding position, and the first annular isolation groove is located outside the second convex structure; the second convex structure is used for electrically connecting the metal layer and the top electrode layer.

[0054] In some alternative embodiments of the present embodiment, the seventh stacked structure includes the device silicon layer and the first dielectric layer;

[0055] The orthographic projection of the bonding position of the device wafer and the capping wafer on the substrate layer does not overlap with the orthographic projection of the first resonant cavity region on the substrate layer.

[0056] In some alternative embodiments of the present embodiment, the device wafer further includes a fifth insulating layer disposed on the device silicon layer and a sixth annular isolation groove disposed on the same layer as the device silicon layer, wherein the depth of the sixth annular isolation groove is less than the thickness of the device silicon layer; the sixth annular isolation groove is correspondingly disposed with the first annular isolation groove; the sixth annular isolation groove is filled with a first dielectric layer, and the surface of the first dielectric layer away from the substrate layer is not higher than the surface of the device silicon layer away from the substrate layer;

[0057] The orthographic projection of the bonding position of the device wafer and the capping wafer on the substrate layer falls within the orthographic projection of the first resonant cavity region on the substrate layer.

[0058] In some alternative embodiments of the present embodiment, the device silicon layer further includes a fifth trench penetrating through the eighth stacked structure of the device wafer, wherein:

[0059] The fifth trench is used to connect the first resonant cavity region and the second resonant cavity region, and to define the shape and boundary region of the resonator;

[0060] The eighth stacked structure includes the device silicon layer and a ninth stacked structure, wherein the ninth stacked structure includes at least one of the first dielectric layer and the piezoelectric layer.

[0061] In some alternative embodiments of the present embodiment, at least a part of the material of the device silicon layer is a doped silicon layer, and the doping concentration of the doped silicon layer is 10 19 cm -3 or more.

[0062] According to the second aspect of the present application, an electronic component is provided, and the electronic component includes the packaging structure described in the above embodiment.

[0063] The packaging structure and the electronic component for a piezoelectric MEMS resonator provided by the present application can discharge the residual gas adsorbed in the material through high-temperature annealing in the bonding step by adopting a silicon-silicon bonding packaging method between the device wafer and the capping wafer, thereby effectively improving the packaging vacuum degree and the working performance of the resonator. Description of the Drawings

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0065] Figure 1 is a schematic diagram of the packaging structure of a piezoelectric MEMS resonator in the prior art;

[0066] Figures 2A to 2B is a schematic diagram of the packaging structure of a piezoelectric MEMS resonator according to an embodiment of the present application;

[0067] Figures 3A to 3I is a schematic diagram of the processing flow of a device wafer according to an embodiment of the present application;

[0068] Figures 4A to 4F is a schematic diagram of the processing flow of a capping wafer according to an embodiment of the present application;

[0069] Figures 5A to 5C is a schematic diagram of the processing flow of a bonding step according to an embodiment of the present application;

[0070] Figure 6 is a schematic diagram of the packaging structure of a piezoelectric MEMS resonator according to another embodiment of the present application;

[0071] Figures 7A to 7J is a schematic diagram of the processing flow of a packaging structure according to another embodiment of the present application;

[0072] Figure 8 is a schematic diagram of the packaging structure of a piezoelectric MEMS resonator according to another embodiment of the present application;

[0073] Figures 9A to 9I is a schematic diagram of the processing flow of a packaging structure according to another embodiment of the present application;

[0074] Figure 10 is a schematic diagram of the packaging structure of a piezoelectric MEMS resonator according to another embodiment of the present application;

[0075] Figure 11 is a schematic diagram of the packaging structure of a piezoelectric MEMS resonator according to another embodiment of the present application;

[0076] Figures 12A to 12N is a schematic diagram of the processing flow of a packaging structure according to another embodiment of the present application. Detailed implementation manners

[0077] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer and more understandable, the following further describes the embodiments of the present application in detail with reference to the accompanying drawings. Herein, the illustrative embodiments of the present application and their descriptions are used to explain the present application, but not to limit the present application.

[0078] The currently common packaging structure of a piezoelectric-driven MEMS resonator is as Figure 1 shown, where 101 is a substrate silicon layer, 102 is a lower cavity close to the device silicon layer 104, 103 is a silicon dioxide bonding layer, 104 is a device silicon layer, 105 is a piezoelectric layer, 106 is a top electrode layer, 107 is a metal bonding layer, 108 is a silicon cap silicon layer, 109 is a conductive via, 110 is an external lead, 111 is an upper cavity close to the piezoelectric layer 105, and 112 is a getter material layer.

[0079] In Figure 1 , the device silicon layer 104 has a lower cavity 102 located in the substrate silicon layer 101, has a bonded silicon cap silicon layer 108 above the piezoelectric layer 105, and has a conductive via 109 for leading out an electrical signal in the silicon cap silicon layer 108. It should be noted that in the piezoelectric-driven MEMS resonator structure as Figure 1 shown, the top electrode layer 106 usually uses a metal material, such as Mo, W, Al, Cu, or Au, etc.; or a bonding method with a metal-containing layer is used during wafer-level packaging, such as gold-gold bonding (106 and 107), aluminum-germanium bonding (106 and 107), or gold-silicon bonding, etc. At this time, it is usually necessary to add a getter material layer 112 (where the getter material is, for example, Ti, titanium alloy, Zr, and zirconium alloy, etc.) in the upper cavity 111 to achieve a high vacuum degree, usually in the order of about 10 Pa, so as to reduce the air damping of the resonator to a certain extent and improve the quality factor Q value of the resonator.

[0080] However, Figure 1The shown packaging structure is difficult to achieve a higher vacuum level. Its vacuum level is usually only around the order of 10 Pa, which obviously does not meet the requirements of the piezoelectric MEMS resonator for the vacuum level and directly affects the working performance of the resonator.

[0081] For this reason, an embodiment of the present application provides a packaging structure for a piezoelectric MEMS resonator. The packaging structure includes:

[0082] A device wafer, a capping wafer, and a first insulating layer and a metal layer disposed on the capping wafer, wherein:

[0083] The device wafer includes: a substrate layer, wherein the substrate layer includes a substrate region and a first resonant cavity region surrounded by the substrate region; and a device silicon layer, a first dielectric layer, a piezoelectric layer, and a top electrode layer disposed on the substrate layer, wherein the material of the top electrode layer is doped polysilicon;

[0084] The capping wafer includes: a capping layer; and a first annular isolation groove formed in the capping layer, wherein the first annular isolation groove is filled with a second dielectric layer;

[0085] Wherein, the surface of the device wafer for bonding with the capping wafer is the surface of the device silicon layer away from the substrate layer, the surface of the capping wafer for bonding with the device wafer is the surface of the capping layer away from the first insulating layer, and the material of the capping layer is low-resistivity single-crystalline silicon.

[0086] Thus, the above-mentioned packaging structure for a piezoelectric MEMS resonator proposed by the present application, by adopting a silicon-silicon bonding packaging method between the device wafer and the capping wafer, can discharge the residual gas adsorbed in the material through high-temperature annealing during the bonding step, thereby effectively improving the packaging vacuum level and the working performance of the resonator.

[0087] It should be noted that the packaging structure of the present application is applicable to piezoelectrically driven silicon-based MEMS resonators. Among them, there are various planar structures of piezoelectrically driven silicon-based MEMS resonators, and the corresponding electrode arrangement structures are also different, and there are also various vibration modes, such as: in-plane flexural mode, out-of-plane flexural mode, width extensional mode (abbreviated as WE mode), length extensional mode (abbreviated as LE mode), Lamé mode, etc., but not limited to the above vibration modes; the resonant frequencies that can be achieved by piezoelectrically driven silicon-based MEMS resonators generally can cover a range from more than a dozen kHz to several hundred MHz, and the present application does not make any limitations in this regard.

[0088] In addition, the packaging structure proposed in this application is also applicable to multi-resonator units or sensors that use piezoelectrically driven silicon-based MEMS resonators as excitation or sensing devices. Among them, the sensors are, for example: accelerometers, gyroscopes, micromirrors, piezoelectric transducers, and pressure sensors, etc. This application does not limit this.

[0089] In this application, according to the bonding position of the device wafer and the capping wafer, the position of the lead region, etc., the packaging structure for piezoelectric MEMS resonators in this application can be divided into the following five embodiments. Specifically:

[0090] Embodiment 1

[0091] As Figure 2A and Figure 2B shown, the packaging structure for piezoelectric MEMS resonators includes:

[0092] A substrate layer 206, where the substrate layer 206 includes a substrate region and a first resonant cavity region 207 surrounded by the substrate region. That is to say, the first resonant cavity region 207 is a cavity formed on the substrate layer 206, which can be a single cavity or multiple sub-cavities. Its depth can be set according to the vibration amplitude of the resonator or the vibration amplitude of the movable components of the sensor. For example, when the first resonant cavity region 207 is used to accommodate the resonator, the depth of the first resonant cavity region is positively correlated with the vibration amplitude of the resonator in the depth direction. In addition, when there are multiple sub-cavities, the depth of each sub-cavity can be the same or different. The cavity depth is, for example: 10um, 20um, or 50um, etc. This application does not limit this.

[0093] A device silicon layer 201 disposed on the substrate layer 206, where the device silicon layer 201 can be single-crystalline silicon or polycrystalline silicon. At the same time, to improve the frequency-temperature characteristics of the device, at least part of the device silicon layer 201 is heavily doped silicon, and the doping element can be boron (B), phosphorus (P), or arsenic (As), etc.; among them, the doping concentration is generally greater than 10 19 cm -3 above, so that the resistivity is lower than 0.01 Ω·cm; further, the doping concentration can also be greater than 10 20 cm -3 above, so that the resistivity is lower than 0.001 Ω·cm. This application does not limit this.

[0094] It should be noted that the device silicon layer 201 also includes a second annular isolation groove (labeled 213 in Figure 3B ), where the second annular isolation groove is filled with the first dielectric layer 203, and at least part of the first dielectric layer on the device silicon layer in the inner part of the ring of the second annular isolation groove is removed, so as to expose the device silicon layer.

[0095] Among them, the material of the first dielectric layer 203 is silicon dioxide; or it is two dielectric materials of silicon dioxide and polysilicon. Among them, the polysilicon is undoped or has a low doping concentration (for example: less than 10 18 cm -3 , or less than 10 15 cm -3 ).

[0096] The second insulating layer 202 located between the device silicon layer 201 and the substrate layer 206 also serves as a bonding layer between the device silicon layer 201 and the substrate layer 206, and the material is generally silicon dioxide formed by thermal oxidation. Among them, when forming a preset cavity-type SOI substrate, according to different manufacturing processes, the formation position of the second insulating layer 202 is different.

[0097] Specifically, as Figure 2A shown, the part of the second insulating layer 202 corresponding to the first resonant cavity region is located on the side of the device silicon layer close to the substrate layer, that is, the second insulating layer 202 is formed under the device silicon layer; or, as Figure 2B shown, the part of the second insulating layer 202 corresponding to the first resonant cavity region is located on the side of the substrate region close to the device silicon layer, that is, the second insulating layer 202 is formed on the substrate layer.

[0098] The piezoelectric layer 204, among which, as Figure 2A or Figure 2B shown, at least part of the piezoelectric layer 204 is directly disposed on the device silicon layer 201, and the projection of the region where the piezoelectric layer 204 contacts the device silicon layer 201 on the substrate layer 206 at least partially overlaps with the projection of the first resonant cavity region 207 on the substrate layer 206; in addition, it should also be noted that, as Figure 2A or Figure 2B shown, at least part of the piezoelectric layer 204 is located on the first dielectric layer 203.

[0099] Among them, the piezoelectric material of the piezoelectric layer 204 can be a single crystal piezoelectric material or a polycrystalline piezoelectric material. For example, the single crystal piezoelectric material is aluminum nitride, and the polycrystalline piezoelectric material is doped aluminum nitride; among them, the doping elements of the doped aluminum nitride can be rare earth elements, II / XII group elements or IV / V group elements. Rare earth elements such as scandium (Sc) element or yttrium (Y) element, etc.; II / XII group elements such as calcium (Ca) element, magnesium (Mg) element, strontium (Sr) element or zinc (Zn) element, etc.; IV / V group elements such as titanium (Ti) element, zirconium (Zr) element or hafnium (Hf) element, etc.

[0100] A top electrode layer 205 disposed above the piezoelectric layer 204, wherein the top electrode layer is located above the piezoelectric layer 204, and the top electrode layer 205 straddles the piezoelectric layer 204 and at least one of the second annular isolation grooves to be electrically connected to the exposed device silicon layer in the inner part of the ring of the second annular isolation groove, that is, to be electrically connected to Figure 3E the device silicon layer exposed at the position of reference numeral 214 in

[0101] wherein, the material of the top electrode layer 205 is doped polysilicon, and the doping element can be boron (B), phosphorus (P), arsenic (As), etc. The doping concentration is generally greater than 10 19 cm -3 above. It should be noted that the higher the doping concentration, the lower the sheet resistance of the electrode made of polysilicon, and the lower the electrical loss. Its resistivity is generally less than 0.05 Ω·cm. For example, it can be 0.01 Ω·cm or 0.005 Ω·cm, etc. This application does not make a limitation on this.

[0102] It should be noted that the above-mentioned substrate layer 206, the first resonant cavity region 207, the device silicon layer 201, the second annular isolation groove, the first dielectric layer 203, the second insulating layer 202, the piezoelectric layer 204, and the top electrode layer 205, etc. constitute the device wafer part in the packaging structure.

[0103] A capping layer 208, wherein the material of the capping layer 208 is low-resistance single-crystal silicon, and its resistivity is lower than 0.05 Ω·cm. For example, it can be 0.01 Ω·cm. This application does not make a limitation on this.

[0104] A first annular isolation groove formed in the capping layer 208 (at the reference numeral 218 in Figure 4A ), and the first annular isolation groove is filled with a second dielectric layer 210. The material of the second dielectric layer 210 includes silicon dioxide and polysilicon; or the material of the second dielectric layer 210 includes silicon dioxide. Among them, the polysilicon is undoped or has a low doping concentration (for example: less than 10 18 cm -3 , or less than 10 15 cm -3 ). The second dielectric layer 210 is generally annular in a top view, so as to isolate a part of the capping layer 208 into a conductive via structure, and this conductive via structure is used to lead out the signals in the device wafer to the outside of the capping wafer.

[0105] The second resonant cavity region 212 is disposed in the capping layer 208, wherein the orthographic projection of the first resonant cavity region 207 on the substrate layer 206 and the orthographic projection of the second resonant cavity region 212 on the substrate layer 206 at least partially overlap; the second resonant cavity region 212 is used to accommodate the piezoelectric layer 204, the top electrode layer 205, and a part of the first dielectric layer 203.

[0106] Wherein, the second resonant cavity region 212 can be a cavity or multiple sub-cavities, and the cavity depth can be set according to the vibration amplitude of the resonator. For example, it can be greater than 10um, greater than 25um, or greater than 50um, etc. The present application does not make any limitation in this regard.

[0107] It should be noted that the above-mentioned capping layer 208, the first annular isolation groove, the second dielectric layer 210, and the second resonant cavity region 212 constitute the capping wafer part in the encapsulation structure.

[0108] According to the foregoing, the device wafer includes a first resonant cavity region, and the capping wafer includes a second resonant cavity region. In order to achieve the connection between the first resonant cavity region and the second resonant cavity pre-drive, as Figure 2A or Figure 2B shown, the device wafer further includes a first trench (labeled 217 in Figure 3I ) that penetrates the first stacked structure of the device wafer. The first trench is used to connect the first resonant cavity region and the second resonant cavity, and to define the shape and boundary region of the resonator.

[0109] In this embodiment, the first stacked structure includes a device silicon layer 201 and a second stacked structure. According to different actual manufacturing processes, the layer structure included in the second stacked structure is also different. Specifically, the second stacked structure includes at least one of the first dielectric layer 203, the second insulating layer 202, and the piezoelectric layer 204.

[0110] The first insulating layer 209 and the metal layer 211 are disposed on the capping wafer. The material of the first insulating layer 209 is generally silicon dioxide and / or polymer, etc.; the metal layer 211 is a device pin, and the number thereof is not limited to two, and there can be multiple. Those skilled in the art can etch the required number of conductive holes and set the corresponding number of device pins according to the actual situation. The material of the metal layer 211 is generally a single-layer or multi-layer material combination such as gold (Au), aluminum (Al), copper (Cu), or aluminum-copper alloy, aluminum-silicon-copper alloy, etc., and can also include adhesion layers such as chromium (Cr), titanium tungsten (TiW), titanium (Ti), and titanium nitride (TiN). The present application does not make any limitation in this regard.

[0111] According to the foregoing, the inner part of the ring of the first annular isolation groove is a conductive through hole (inFigure 4A (label 219), the conductive through-hole is electrically connected to the metal layer 211, so that the conductive through-hole leads out the electrical signal in the device wafer to the side of the capping layer 208 close to the first insulating layer 209.

[0112] Next, the bonding of the device wafer and the capping wafer will be introduced:

[0113] As Figure 2A or Figure 2B shown, the surface of the device wafer for bonding with the capping wafer is the side of the device silicon layer 201 away from the substrate layer 206, and the surface of the capping wafer for bonding with the device wafer is the side of the capping layer 208 away from the first insulating layer 209.

[0114] In the first embodiment, the bonding position of the device wafer and the capping wafer is on the same side of the piezoelectric layer 204 in the device silicon layer 201, and the orthographic projection of the bonding position of the device wafer and the capping wafer on the substrate layer 206 does not overlap with the orthographic projection of the first resonant cavity region 207 on the substrate layer 206. At the bonding position, the capping wafer forms an electrical connection and a sealing ring with the side of the device silicon layer 201 away from the substrate layer 206 through silicon-silicon bonding.

[0115] That is to say, the Si-Si bonding (silicon-silicon bonding) is on the same side of the piezoelectric layer 204 in the device silicon layer 201, that is, the piezoelectric layer 204 faces the cavity side formed by the capping wafer (i.e., the second resonant cavity region); the capping wafer is bonded to the surface of the device silicon layer 201 on the side where the piezoelectric layer 204 is located through Si-Si bonding to form an electrical connection and a sealing ring.

[0116] Thus, in some alternative ways of this embodiment, the bonding position includes a sealing ring bonding position (label 216 in Figure 3H and a pin bonding position (label 215 in Figure 3H ), where:

[0117] The orthographic projection of the sealing ring bonding position on the substrate layer 206 is annular, and the orthographic projection of the sealing ring bonding position on the substrate layer surrounds the orthographic projection of the pin bonding position on the substrate layer 206;

[0118] And at least one of the pin bonding positions is located in the inner part of the ring of the second annular isolation groove.

[0119] In some alternative ways of this embodiment, a first convex structure is formed on the side of the capping layer away from the first insulating layer at the bonding position, and the first annular isolation groove is located at the first convex structure at the pin bonding position (in Figure 4Eoutside the part labeled 220;

[0120] Wherein, the height of the first convex structure is at least higher than the thickness of the first dielectric layer 203; the depth of the second resonant cavity region 212 is greater than or equal to the height of the first convex structure.

[0121] Based on the foregoing description, in the wafer-level packaging structure of the piezoelectric MEMS resonator based on silicon-silicon bonding proposed in this embodiment, only the metal layer on the outside of the capping wafer is made of metal material, and the structures of the remaining parts do not contain any metal material; and the piezoelectric layer is made of aluminum nitride or doped aluminum nitride material that can withstand high temperatures, and the remaining materials are silicon or silicon dioxide materials, all of which can withstand high-temperature treatment above 800 °C. Therefore, the residual gas adsorbed in the material body can be completely discharged through high-temperature annealing in the bonding step, effectively improving the packaging vacuum degree, making the vacuum degree reach below 1 Pa; and a lower vacuum degree is beneficial to further improving the Q value of the resonator, maintaining the resonator frequency, and maintaining the long-term stability of the Q value, effectively improving the working performance of the resonator; in addition, it can also improve the sensitivity, resolution, and reliability of the corresponding sensor.

[0122] Next, in combination with Figures 3A to 3I , Figures 4A to 4F and Figures 5A to 5C shown in the manufacturing method of the packaging structure, the packaging structure of Embodiment 1 shown in Figure 2A or Figure 2B is further described:

[0123] First is the processing flow of the device wafer. A device silicon layer, a first dielectric layer, a piezoelectric layer, and a top electrode layer are sequentially formed on the substrate layer to obtain the fabricated device wafer. Wherein, the substrate layer includes a substrate region and a first resonant cavity region surrounded by the substrate region.

[0124] Secondly is the processing flow of the capping wafer. A first annular isolation groove is formed on the capping layer, and a second dielectric layer is filled in the first annular isolation groove to obtain the fabricated capping wafer.

[0125] Finally is the processing flow of bonding the device wafer and the capping wafer.

[0126] In a specific example, taking Figures 3A to 3I as an example, the processing flow of the device wafer shown in Embodiment 1 is introduced:

[0127] First, as Figure 3A shown, first process a preset cavity-type SOI substrate or CSOI substrate, so as to directly form the substrate layer 206, the first resonant cavity region 207, the second insulating layer 202, and the device silicon layer 201.

[0128] Further, asFigure 3B As shown, at least one annular isolation groove is etched on the device silicon layer 201. The shape of the annular isolation groove is not limited to a circle, and it can be any closed-loop shape. The annular isolation groove etched here is the second annular isolation groove 213. Figure 3C is Figure 3B a top view of. From Figure 3C and Figure 3B it can be seen that the device silicon layer region inside the second annular isolation groove 213 is electrically isolated from the other parts of the device silicon layer region, and is used as a pin connected to the top electrode layer subsequently. It should be noted that if the top electrode layer includes two electrodes connected to different electrical signals, there are at least two annular isolation grooves. That is to say, the number of annular isolation grooves is related to the number of electrical signals of the top electrode layer, and the present application does not limit this.

[0129] Furthermore, as Figure 3D shown, the first dielectric layer 203 is used to fill the device silicon layer 201 and the second annular isolation groove. Among them, the material of the first dielectric layer 203 can be silicon dioxide, and the silicon dioxide can be formed by methods such as thermal oxidation, LPCVD, LPCVD-TEOS or PECVD, etc., and the present application does not limit this. Then at least the silicon dioxide in the effective resonance region of the resonator is removed to expose the device silicon layer, where at least part of the exposed part overlaps with the second resonance cavity region in the vertical direction. That is, then a piezoelectric layer 204 is deposited on the exposed device silicon layer and the piezoelectric layer 204 is etched.

[0130] It should be noted that the edge of the piezoelectric layer 204 covers the unetched silicon dioxide; or part of the edge of the piezoelectric layer can also be located on the surface of the device silicon layer where the silicon dioxide has been removed (which is not shown in the figure), and it satisfies that the orthographic projection of the region where the piezoelectric layer contacts the device silicon layer on the substrate layer at least partially overlaps with the orthographic projection of the first resonance cavity region on the substrate layer.

[0131] Furthermore, as Figure 3E shown, part of the first dielectric layer 203 above the device silicon layer inside the second annular isolation groove is removed to expose the underlying device silicon layer, that is, to expose Figure 3E the device silicon layer at the position numbered 214 in

[0132] Furthermore, as Figure 3F shown, doped polysilicon is deposited as the top electrode layer 205 and patterned to form an electrode. Among them, part of the top electrode layer 205 is located above the piezoelectric layer 204, part straddles the piezoelectric layer 204 and the second annular isolation groove, and is electrically connected to the device silicon layer as a pin (that is, Figure 3E the device silicon layer at the position numbered 214 in

[0133] Furthermore, asFigure 3G As shown, after depositing doped polysilicon as the top electrode layer 205, a chemical mechanical polishing (CMP) step can be further added Figure 3F on this basis to grind its surface flat.

[0134] Furthermore, as Figure 3H shown, the first dielectric layer 203 on the surface of the device silicon layer 201 at the bonding position is etched away to expose the underlying device silicon layer 201, where the exposed positions of the device silicon layer include at least the device silicon layer positions as the seal ring positions and the device silicon layer positions as the pins connected to different electrical signals.

[0135] In some alternative ways of this embodiment, as Figure 3H shown, the bonding positions include a seal ring bonding position 216 and a pin bonding position 215, where:

[0136] The first dielectric layers 203 at both ends of the device silicon layer 201 are removed, and the exposed positions of the device silicon layer are used as the seal ring bonding position 216; the first dielectric layers in the part outside the effective resonance region and inside the ring of the second annular isolation groove are removed, and the exposed positions of the device silicon layer are used as the pin bonding position 215.

[0137] Furthermore, as Figure 3I shown, the stacked structure above the first resonance cavity region 207 is etched to obtain a trench penetrating these stacked structures, that is, the first trench 217. On the one hand, the first trench 217 can connect the first resonance cavity region 207 and the second resonance cavity region 212; on the other hand, it can also define the shape and boundary region of the resonator.

[0138] Among them, the stacked structures penetrated by the first trench include the device silicon layer 201, the second insulating layer 202, and the first dielectric layer 203. According to different manufacturing processes, in the case not shown in other figures, the penetrated stacked structures may further include a piezoelectric layer 204, or the penetrated stacked structures only include the device silicon layer 201 and the second insulating layer 202; or the penetrated stacked structures include the device silicon layer 201, the second insulating layer 202, and the piezoelectric layer 204. This application does not make a limitation on this.

[0139] So far, the processing flow of the device wafer is completed.

[0140] In a specific example, taking Figures 4A to 4F as an example, the processing flow of the Figure 2A or Figure 2B shown capping wafer is introduced:

[0141] First, as Figure 4AAs shown, on the substrate of the capping layer (low-resistivity single-crystalline silicon) 208, an annular isolation groove structure is etched. The shape of the annular isolation groove is not limited to a circle and can be any closed-loop shape. The annular isolation groove etched here is the first annular isolation groove 218. It should be understood that the depth of the first annular isolation groove 218 is at least greater than the thickness of the final device capping wafer. For example, the general depth is greater than 100 um.

[0142] In this embodiment, in order to ensure that the piezoelectric-driven silicon-based MEMS resonator has a small size, a conductive via structure is formed in the capping wafer, and the device wafer signal is led out through this conductive via structure, that is, a conductive via structure for leading out the electrical signal is formed in the capping layer, so as to lead out the electrode in the device silicon layer to the outside of the packaging structure. As Figure 4A shown, the inner part of the ring of the first annular isolation groove 218 is a conductive via 219, which is used to lead out the electrical signal in the device wafer to the outer surface of the capping wafer. For example, the conductive via is electrically connected to the metal layer, so that the conductive via leads out the electrical signal in the device wafer to the side of the capping layer close to the first insulating layer.

[0143] Furthermore, as Figure 4B shown, a silicon dioxide material 210-1 and a polysilicon material 210-2 are continuously deposited on the surface of the capping layer 208, so as to completely fill the first annular isolation groove; or as Figure 4C shown, only the silicon dioxide material 210-1 is deposited on the surface of the capping layer 208, so as to completely fill the first annular isolation groove. That is to say, the silicon dioxide material 210-1 and the polysilicon material 210-2 are the second dielectric layer; or the silicon dioxide material 210-1 is the second dielectric layer 210, and the present application does not make a limitation on this.

[0144] Furthermore, as Figure 4D shown, the second dielectric layer on the side of the capping layer away from the first insulating layer is removed, the side of the capping layer away from the first insulating layer is exposed, and the surface roughness of the side of the capping layer away from the first insulating layer is reduced. That is to say, the second dielectric layer on the surface of the capping layer is removed by a chemical mechanical polishing process, the surface of the low-resistivity single-crystalline silicon is re-exposed, and its surface roughness is small, for example: less than 10 angstroms, or less than 5 angstroms, so as to ensure the subsequent silicon-silicon bonding with the capping wafer.

[0145] Furthermore, as Figure 4EAs shown, at least the surface of the cap layer at the position of the first isolation annular groove and its vicinity is etched to form a sub-cavity 212-1 in a shallower second resonant cavity region. The sub-cavity 212-1 is used to accommodate the remaining first dielectric layer on the surface of the device silicon layer when the cap wafer is bonded to the device wafer. Therefore, the height of the sub-cavity 212-1 is at least greater than the thickness of the first dielectric layer on the surface of the device wafer. For example, the height of the sub-cavity 212-1 is about 1um to 5um, for example, 2.5um.

[0146] It should be noted that, since the material in the first annular isolation groove is different from the material of the cap layer 208, the etching rates of the surface of the first annular isolation groove and the surface of the cap layer are different. Therefore, after etching, the surface of the material in the first annular isolation groove is not necessarily flush with the surface of the cap layer; and when the first annular isolation groove is filled with two materials, the surfaces of the two materials are not necessarily flush. Specifically, the surface of the material in the first annular isolation groove protrudes from the surface of the nearby cap layer or the surface of the material in the first annular isolation groove is lower than the surface of the nearby cap layer.

[0147] In addition, after Figure 4E After etching, a first protruding structure 220 is formed at the bonding position on the side of the cap layer 208 away from the first insulating layer, and it can be seen that the first annular isolation groove is located on the outside of the first protruding structure 220 at the pin bonding position; and the height of the first protruding structure is at least higher than the thickness of the first dielectric layer.

[0148] Further, if Figure 4F As shown, another sub-cavity 212-2 of the second resonant cavity region is etched at a position corresponding to the aforementioned first resonant cavity region, and the sub-cavity 212-2 is used to accommodate the resonator when the device wafer and the cap wafer are bonded. Therefore, the cavity depth of the sub-cavity 212-2 can be selected according to the vibration amplitude of the resonator, for example: 10um, 20um or 50um, which is not limited in the present application.

[0149] It should be noted that if the cavity depth of the aforementioned sub-cavity 212-1 can meet the vibration amplitude selected by the resonator, the etching of the sub-cavity 212-2 may not be performed, thereby simplifying the process flow and saving the production cost of the cap wafer. In other words, the depth of the first resonant cavity region is greater than or equal to the height of the aforementioned first protruding structure.

[0150] At this point, the processing flow of the cap wafer is completed.

[0151] In a specific example, Figures 5A to 5C Taking the bonding process of device wafer and cap wafer as an example, the following is an introduction to the bonding process of device wafer and cap wafer:

[0152] First, if Figure 5AAs shown, the processed device wafer and the capping wafer are bonded, which is also called fusion bonding or direct bonding. It is not difficult to conclude that different from the metal bonding in the prior art, the capping wafer of this application is bonded to the exposed device silicon layer on the device wafer through the aforementioned first protrusion structure. On the basis that the capping layer is a low-resistance single crystal silicon, the bonding method between the device wafer and the capping wafer in this application is silicon-silicon bonding, effectively improving the packaging vacuum degree.

[0153] Further, as Figure 5B shown, after bonding, the side of the capping wafer away from the second resonant cavity region 212 is thinned by grinding or etching until the first annular isolation groove structure is exposed and the target thickness in the manufacturing process is reached. At this time, the capping layer inside the first annular isolation groove ring is electrically isolated from the capping layer outside the first annular isolation groove, so that the inside part of the first annular isolation groove can be used as the conductive via 219.

[0154] Further, as Figure 5C shown, a first insulating layer 209 is deposited on the surface of the capping wafer away from the second resonant cavity region 212. The material of the first insulating layer 209 is generally silicon dioxide and may also include other polymer insulating material layers; and part of the first insulating layer is etched to expose the conductive via, and then a metal layer 211 is deposited, and the metal layer 211 is etched to form device leads as Figure 5C shown.

[0155] So far, the processing flow of bonding the device wafer and the capping wafer in Embodiment 1 is completed.

[0156] Embodiment 2

[0157] As Figure 6 shown, the packaging structure for a piezoelectric MEMS resonator includes:

[0158] A device wafer, a capping wafer, and a first insulating layer 309 and a metal layer 311 provided on the capping wafer, wherein:

[0159] The device wafer includes: a substrate layer 306, wherein the substrate layer 306 includes a substrate region and a first resonant cavity region 307 surrounded by the substrate region; and a device silicon layer 301, a first dielectric layer 302, a piezoelectric layer 304, and a top electrode layer 305 provided on the substrate layer 306, wherein the material of the top electrode layer 305 is doped polysilicon;

[0160] The capping wafer includes: a capping layer 308; and a first annular isolation groove formed in the capping layer, wherein the first annular isolation groove is filled with a second dielectric layer 310;

[0161] Wherein, the surface of the device wafer bonded to the capping wafer is the side of the device silicon layer away from the substrate layer, the surface of the capping wafer bonded to the device wafer is the side of the capping layer away from the first insulating layer, and the material of the capping layer is low-resistivity single-crystalline silicon.

[0162] The capping wafer further includes a second resonant cavity region 312 formed on the side of the capping layer 308 away from the first insulating layer 309. As can be seen from Figure 6 it, the orthographic projection of the first resonant cavity region 307 on the substrate layer 306 and the orthographic projection of the second resonant cavity region 312 on the substrate layer 306 at least partially overlap.

[0163] Different from the foregoing Embodiment 1, in Embodiment 2 of the present application, the silicon-silicon bonding position and the piezoelectric layer are on opposite sides of the device silicon layer. Specifically, as Figure 6 shown, the bonding position of the device wafer and the capping wafer is on the side of the device silicon layer 301 away from the substrate layer 306, while the piezoelectric layer 304 is on the side of the device silicon layer 301 close to the substrate layer 306. The orthographic projection of the bonding position of the device wafer and the capping wafer on the substrate layer does not overlap with the orthographic projection of the first resonant cavity region on the substrate layer.

[0164] Further, at the bonding position, the capping wafer forms an electrical connection and a sealing ring with the side of the device silicon layer away from the substrate layer through silicon-silicon bonding. Thus, the bonding position includes a pin bonding position and a sealing ring bonding position (reference can be made to the foregoing description of Embodiment 1 here).

[0165] Further, different from the foregoing Embodiment 1, the first resonant cavity region 307 is used to accommodate part of the first dielectric layer 302, the piezoelectric layer 304, and the top electrode layer 305; wherein, the depth of the first resonant cavity region 307 is positively correlated with the vibration amplitude of the resonator in the depth direction.

[0166] In some alternative embodiments of the present embodiment, after growing the piezoelectric layer, the lead region in the device silicon layer is defined from the other side of the device silicon layer, that is, the piezoelectric layer and the lead region are not on the same side of the device silicon layer. As Figure 6 shown, the device wafer further includes a third insulating layer 313 provided on the device silicon layer and a third annular isolation groove provided on the same layer as the third insulating layer 313 and the device silicon layer 301. Among them, the third annular isolation groove serves as the lead region on the side of the device silicon layer 301 away from the substrate layer 306; the third annular isolation groove is filled with a third dielectric layer 303;

[0167] Among them, the positive projection of at least one of the third annular isolation grooves and a part of the device silicon layer 301 located in the inner part of the third annular isolation groove on the substrate layer falls within the positive projection of the first resonant cavity region 307 on the substrate layer 306;

[0168] The top electrode layer 305 is electrically connected to a part of the device silicon layer located in the inner part of the third annular isolation groove. Among them, the position where the top electrode layer 305 is electrically connected to the device silicon layer located in the inner part of the third annular isolation groove is Figure 6 the position numbered 314 in the figure.

[0169] As can be seen from the foregoing, the device wafer includes a first resonant cavity region, and the capping wafer includes a second resonant cavity region. In order to realize the communication between the first resonant cavity region and the second resonant cavity region, as Figure 6 shown, the device wafer further includes a second trench 315 penetrating the third stacked structure of the device wafer, where:

[0170] The second trench 315 is used to communicate the first resonant cavity region and the second resonant cavity region, and to define the shape and boundary region of the resonator.

[0171] Among them, the third stacked structure includes the device silicon layer 301 and a fourth stacked structure. According to different actual manufacturing processes, the layer structure included in the fourth stacked structure is also different. Specifically, the fourth stacked structure includes at least one of the third insulating layer 313, the third dielectric layer 303, and the first dielectric layer 302.

[0172] Based on the foregoing description, in the wafer-level packaging structure of a piezoelectric MEMS resonator based on silicon-silicon bonding proposed in this embodiment, only the metal layer on the outer side of the capping wafer is made of metal material, and the structures of the remaining parts do not have any metal materials; and the piezoelectric layer uses aluminum nitride or doped aluminum nitride material that can withstand high temperatures, and the remaining materials are silicon or silicon dioxide materials, all of which can withstand high-temperature treatment above 800 °C. Therefore, the residual gas adsorbed in the material body can be completely discharged through high-temperature annealing in the bonding step, effectively improving the packaging vacuum degree, so that the vacuum degree reaches below 1 Pa; and a lower vacuum degree is beneficial to further improving the Q value of the resonator, maintaining the resonator frequency, and maintaining the long-term stability of the Q value, effectively improving the working performance of the resonator; in addition, it can also improve the sensitivity, resolution, and reliability of the corresponding sensor.

[0173] Next, in combination with Figures 7A to 7J to Figure 6 shown, the manufacturing method of the packaging structure will be further described:

[0174] First, as Figure 7AAs shown, the processing starts from an SOI wafer, where 301 is the device silicon layer and 313 is the third insulating layer. Among them, the device silicon layer 301 is heavily doped silicon, or at least partially heavily doped silicon, with a doping concentration of 10 19 cm -3 or more.

[0175] Furthermore, as Figure 7B shown, a first dielectric layer 302 is first grown on the SOI surface. The material of the first dielectric layer is generally silicon dioxide. Secondly, the first dielectric layer 302 in the area where the piezoelectric layer needs to be deposited is etched away, the piezoelectric layer 304 is deposited, and then etched. At this time, preferably, the edge of the piezoelectric layer 304 covers the unetched first dielectric layer 302. Not shown in the figure, part of the edge of the piezoelectric layer 304 may also be located on the surface of the device silicon layer 301 where the silicon dioxide has been removed. This application does not make any limitations on this.

[0176] Furthermore, as Figure 7C shown, the first dielectric layer above the device silicon layer at the position connected to the top electrode layer 305 is etched away, that is, the first dielectric layer 302 at the position labeled 314 is etched away, and then doped polysilicon is deposited as the top electrode layer, so that the top electrode layer 305 can be electrically connected to the device silicon layer exposed at the position labeled 314.

[0177] Among them, part of the top electrode layer 305 is located above the piezoelectric layer 304, part straddles the piezoelectric layer 304 and the first dielectric layer 302, and is electrically connected to a part of the device silicon layer that will be used as a pin later, that is, electrically connected to the device silicon layer exposed at the position labeled 314.

[0178] Furthermore, as Figure 7D shown, it is bonded to another substrate layer 306 that has been etched to form the first resonant cavity region 307 by means of silicon-silicon dioxide fusion bonding.

[0179] Furthermore, as Figure 7E shown, the layer structure below the third insulating layer 313 is removed by means such as grinding or etching, leaving the buried oxide layer in the SOI. Among them, if the starting SOI is a single crystal silicon substrate, then the single crystal silicon substrate needs to be ground, etched, or mechanically polished, etc., so as to be thinned to the target thickness to form the 301 device silicon layer, and then a third insulating layer 313, generally silicon dioxide, is grown on its surface.

[0180] Furthermore, as Figure 7F shown, the device silicon layer 301 and the third insulating layer 313 are etched to form an annular isolation groove. The shape of the annular isolation groove is not limited to a circle and can be any closed-loop shape. The annular isolation groove etched here is the third annular isolation groove 316.

[0181] Among them, the device silicon layer 301 region inside the third annular isolation groove 316 is electrically isolated from the device silicon layer 301 regions at other positions, and part of the device silicon layer close to the substrate layer side inside the ring has been electrically connected to the top electrode layer 305. Part of the device silicon layer inside the third annular isolation groove 316 is the position marked 314 in the figure, thus leading the top electrode layer to the side of the device silicon layer away from the substrate layer. Refer to Figure 7C Figure 317 is part of the third annular isolation groove, which is the lead region on the side of the device silicon layer away from the substrate layer. Figure 7H In addition, it can be seen that the positive projection of part of the device silicon layer (the position marked 314) inside the third annular isolation groove on the substrate layer falls within the positive projection of the first resonant cavity region on the substrate layer.

[0182] Furthermore, as shown in

[0183] Figure Figure 7G 318, the third annular isolation groove is filled with the third dielectric layer 303, and at the same time, the surface of the third insulating layer 313 is covered. It should be noted that the materials of the third dielectric layer 303 and the third insulating layer 313 can be the same, for example, both are silicon dioxide; they can also be different, and the present application does not limit this.

[0184] Furthermore, as shown in Figure 7H Figure Figure 7I 319, at least the third dielectric layer 303 and the third insulating layer 313 at the position on the surface of the device silicon layer 301 that needs to be bonded to the capping wafer are etched away. As shown in

[0185] Figure Figure 7J 320, it can be further etched away, or partially etched away, or the third dielectric layer 303 and the third insulating layer 313 are etched into a special pattern on the surface of the resonator region of the device silicon layer 301, so as to change the characteristics such as the frequency, temperature drift, and Q value of the resonator. The present application does not limit this. Figure 7J Figure

[0186] After that, as shown in Figure 7J Figure Figure 6The encapsulated structure shown. It should be noted that the manufacturing process of the capping wafer can refer to the description of Figures 4A to 4F in the foregoing Embodiment 1, which will not be elaborated herein in this application.

[0187] It should be noted that for the same structures in Embodiment 1 and Embodiment 2, reference can be made to the description of Embodiment 1 above, and this application will not elaborate herein.

[0188] Embodiment 3

[0189] As Figure 8 shown, the encapsulated structure for a piezoelectric MEMS resonator includes:

[0190] A device wafer, a capping wafer, and a first insulating layer 409 and a metal layer 411 provided on the capping wafer, wherein:

[0191] The device wafer includes: a substrate layer 406, wherein the substrate layer 406 includes a substrate region and a first resonant cavity region 407 surrounded by the substrate region; and a device silicon layer 401, a first dielectric layer 402, a piezoelectric layer 404, and a top electrode layer 405 provided on the substrate layer 406, wherein the material of the top electrode layer 405 is doped polysilicon;

[0192] The capping wafer includes: a capping layer 408; and a first annular isolation groove formed in the capping layer, wherein the first annular isolation groove is filled with a second dielectric layer 410;

[0193] Wherein, the surface of the device wafer for bonding with the capping wafer is the surface of the device silicon layer away from the substrate layer, the surface of the capping wafer for bonding with the device wafer is the surface of the capping layer away from the first insulating layer, and the material of the capping layer is low-resistance single-crystalline silicon.

[0194] The capping wafer further includes a second resonant cavity region 412 formed on the side of the capping layer 408 away from the first insulating layer 409. As can be seen from Figure 8 it, the orthographic projection of the first resonant cavity region 407 on the substrate layer 406 and the orthographic projection of the second resonant cavity region 412 on the substrate layer 406 at least partially overlap.

[0195] Different from the foregoing Embodiment 1, the silicon-silicon bonding position in Embodiment 3 of this application is on the opposite sides of the piezoelectric layer in the device silicon layer. Specifically, as Figure 8As shown, the bonding position between the device wafer and the capping wafer is on the side of the device silicon layer 401 away from the substrate layer 406, while the piezoelectric layer 404 is on the side of the device silicon layer 401 close to the substrate layer 406. The orthographic projection of the bonding position between the device wafer and the capping wafer on the substrate layer does not overlap with the orthographic projection of the first resonant cavity region on the substrate layer.

[0196] Further, at the bonding position, the capping wafer forms an electrical connection and a sealing ring with the side of the device silicon layer away from the substrate layer through silicon-silicon bonding. Thus, the bonding position includes a pin bonding position and a sealing ring bonding position (reference can be made to the description of Embodiment 1 above).

[0197] Further, different from the foregoing Embodiment 1, the first resonant cavity region 407 is used to accommodate part of the first dielectric layer 402, the piezoelectric layer 404, and the top electrode layer 405; wherein, the depth of the first resonant cavity region 407 is positively correlated with the vibration amplitude of the resonator in the depth direction.

[0198] Different from the foregoing Embodiment 2, in this embodiment, the lead region in the device silicon layer is defined from the same side of the device silicon layer before and after growing the piezoelectric, that is, the piezoelectric layer and the lead region are on the same side of the device silicon layer, as Figure 8 shown, the device wafer further includes a third insulating layer 313 disposed on the device silicon layer and a fourth annular isolation groove (labeled 416 in Figure 9B ) provided on the same layer as the fourth insulating layer 413 and the device silicon layer 401. Wherein, the fourth annular isolation groove serves as the lead region on the side of the device silicon layer 401 close to the substrate layer 406; the fourth annular isolation groove is filled with the first dielectric layer 402;

[0199] Wherein, the orthographic projection of at least one of the fourth annular isolation grooves and part of the device silicon layer 401 within the ring of the fourth annular isolation groove on the substrate layer falls within the orthographic projection of the first resonant cavity region 407 on the substrate layer 406;

[0200] The top electrode layer 405 is electrically connected to part of the device silicon layer within the ring of the fourth annular isolation groove. Wherein, the position where the top electrode layer 405 is electrically connected to the device silicon layer within the ring of the fourth annular isolation groove is the position labeled 414 in Figure 8 .

[0201] According to the foregoing, the device wafer includes a first resonant cavity region, and the capping wafer includes a second resonant cavity region. In order to achieve the communication between the first resonant cavity region and the second resonant cavity region, as Figure 8 shown, the device wafer further includes a third trench 415 penetrating the fifth stacked structure of the device wafer, wherein:

[0202] The third groove 415 is used to connect the first resonant cavity region and the second resonant cavity region, and to define the shape and boundary region of the resonator.

[0203] Wherein, the fifth stack structure includes the device silicon layer 401 and the sixth stack structure. According to different actual manufacturing processes, the layer structures included in the sixth stack structure are also different. Specifically, the sixth stack structure includes at least one of the fourth insulating layer and the first dielectric layer.

[0204] Based on the foregoing description, in the wafer-level packaging structure of the piezoelectric MEMS resonator based on silicon-silicon bonding proposed in this embodiment, only the metal layer on the outer side of the capping wafer is made of metal material, and the structures of the remaining parts do not contain any metal material; and the piezoelectric layer is made of aluminum nitride or doped aluminum nitride material that can withstand high temperatures, and the remaining materials are silicon or silicon dioxide materials, all of which can withstand high-temperature treatment above 800 °C. Therefore, the residual gas adsorbed in the material body can be completely discharged through high-temperature annealing in the bonding step, effectively improving the packaging vacuum degree, so that the vacuum degree reaches below 1 Pa; and a lower vacuum degree is beneficial to further improving the Q value of the resonator, maintaining the resonator frequency, and maintaining the long-term stability of the Q value, effectively improving the working performance of the resonator; in addition, it can also improve the sensitivity, resolution, and reliability of the corresponding sensor.

[0205] Next, in combination with Figures 9A to 9I to Figure 6 the manufacturing method of the shown packaging structure will be further described:

[0206] First, as Figure 9A shown, starting from the SOI wafer, where 401 is the device silicon layer and 413 is the fourth insulating layer. Among them, the device silicon layer 301 is heavily doped silicon, or at least part of it is heavily doped silicon, and the doping concentration is 10 19 cm -3 or more.

[0207] Further, as Figure 9B shown, etching the device silicon layer 401 to form an annular isolation groove. The shape of the annular isolation groove is not limited to a circle and can be any closed-loop shape. The annular isolation groove etched here is the fourth annular isolation groove 416.

[0208] Among them, the device silicon layer 401 region inside the fourth annular isolation groove 416 is electrically isolated from the device silicon layer 401 regions at other positions, and part of the device silicon layer near the substrate layer inside the ring has been electrically connected to the top electrode layer 405. Part of the device silicon layer inside the fourth annular isolation groove 416 is Figure 8 and Figure 9D at the position numbered 314 in the figure, so as to lead the top electrode layer to the same side of the device silicon layer close to the substrate layer. Refer toFigure 9H 417 is a partial fourth annular isolation groove, which is the lead area on the side of the device silicon layer close to the substrate layer.

[0209] In addition, it can be seen that the positive projection of the part of the device silicon layer (at the position marked 314) in the inner part of the fourth annular isolation groove on the substrate layer falls within the positive projection of the first resonant cavity region on the substrate layer.

[0210] Furthermore, as Figure 9C shown, the fourth annular isolation groove is filled with the first dielectric layer 402 while covering the surface of the device silicon layer 401; and the first dielectric layer 402 in the area where the piezoelectric layer 404 needs to be deposited is etched open, the piezoelectric layer 404 is deposited, and then etched. At this time, preferably, the edge of the piezoelectric layer 404 covers the unetched first dielectric layer 402. Not shown in the figure, part of the edge of the piezoelectric layer 304 may also be located on the surface of the device silicon layer 401 from which the first dielectric layer has been removed, and the present application does not limit this.

[0211] Furthermore, as Figure 9D and Figure 9E shown, the first dielectric layer 402 above the device silicon layer at the position connected to the top electrode layer 405 is etched open, that is, the first dielectric layer 402 at the position marked 414 is etched open, and then doped polysilicon is deposited as the top electrode layer 405, so that the top electrode layer 405 can be electrically connected to the device silicon layer exposed at the position marked 414.

[0212] Among them, part of the top electrode layer 405 is located above the piezoelectric layer 404, part straddles the piezoelectric layer 404 and the first dielectric layer 402, and is electrically connected to a part of the device silicon layer that will be used as a pin later, that is, electrically connected to the device silicon layer exposed at the position marked 414.

[0213] Furthermore, as Figure 9F shown, it is bonded to another substrate layer 406 on which the first resonant cavity region 407 has been etched out by means of silicon-silicon dioxide fusion bonding.

[0214] Furthermore, as Figure 9G shown, the layer structure below the fourth insulating layer 413 is removed by means of grinding or etching, etc., leaving the buried oxide layer in the SOI. Among them, if the starting SOI is a single-crystal silicon substrate, the single-crystal silicon substrate needs to be ground, etched, or mechanically polished, etc., so as to be thinned to the target thickness to form the 401 device silicon layer, and then a fourth insulating layer 413, generally silicon dioxide, is grown on its surface.

[0215] Furthermore, as Figure 9HAs shown, at least the fourth insulating layer 413 at the position on the surface of the device silicon layer 401 that needs to be bonded to the capping wafer is etched open.

[0216] Further, as Figure 9I shown, trenches penetrating these stacked layers, i.e., the third trenches 415, are etched in the stacked layers above the first resonant cavity region, thereby defining the shape and boundary of the resonator and completing the processing of the device wafer. At this time, as Figure 9I shown, the penetrated stacked structure includes the first dielectric layer 402, the device silicon layer 401, and the fourth insulating layer 413. In the case not shown in other figures, the penetrated stacked layers may also only include the device silicon layer 401 and the first dielectric layer 402, etc., and the present application does not limit this.

[0217] After that, the device wafer as Figure 9I shown is silicon-silicon bonded to the prepared capping wafer, thereby forming the package structure as Figure 8 shown. It should be noted that the manufacturing process of the capping wafer can refer to the description of Figures 4A to 4F in the foregoing Embodiment 1, and the present application will not elaborate here.

[0218] It should be noted that for the same structures in Embodiment 3 and Embodiments 2 and 1, reference can be made to the descriptions of Embodiments 1 and 2 above, and the present application will not elaborate here.

[0219] Embodiment 4

[0220] As Figure 10 shown, the package structure for a piezoelectric MEMS resonator includes:

[0221] a device wafer, a capping wafer, and a first insulating layer 509 and a metal layer 511 provided on the capping wafer, wherein:

[0222] the device wafer includes: a substrate layer 506, wherein the substrate layer 506 includes a substrate region and a first resonant cavity region 507 surrounded by the substrate region; and a device silicon layer 501, a first dielectric layer 502, a piezoelectric layer 504, and a top electrode layer 505 provided on the substrate layer 506, wherein the material of the top electrode layer 505 is doped polysilicon;

[0223] the capping wafer includes: a capping layer 508; and a first annular isolation groove formed in the capping layer, wherein the first annular isolation groove is filled with a second dielectric layer 510;

[0224] wherein, the surface of the device wafer for bonding with the capping wafer is the surface of the device silicon layer away from the substrate layer, the surface of the capping wafer for bonding with the device wafer is the surface of the capping layer away from the first insulating layer, and the material of the capping layer is low-resistance single-crystalline silicon.

[0225] Different from the foregoing First Embodiment, Second Embodiment, and Third Embodiment, in this embodiment, a cavity is not defined on the side of the capping wafer facing the device, that is, the capping wafer in this embodiment does not include a second resonant cavity region.

[0226] Similar to the foregoing Second Embodiment and Third Embodiment, the silicon-silicon bonding position and the piezoelectric layer in this embodiment are also on opposite sides of the device silicon layer. Specifically, as Figure 10 shown, the bonding position of the device wafer and the capping wafer is on the side of the device silicon layer 501 away from the substrate layer 506, while the piezoelectric layer 504 is on the side of the device silicon layer 501 close to the substrate layer 506; the orthographic projection of the bonding position of the device wafer and the capping wafer on the substrate layer does not overlap with the orthographic projection of the first resonant cavity region on the substrate layer, that is, the silicon-silicon bonding position is outside the first resonant cavity region.

[0227] Furthermore, at the bonding position, the capping wafer forms an electrical connection and a sealing ring with the side of the device silicon layer away from the substrate layer through silicon-silicon bonding. Thus, the bonding position includes a pin bonding position and a sealing ring bonding position (reference can be made to the description of the First Embodiment above).

[0228] Furthermore, similar to the foregoing Second Embodiment and Third Embodiment, the first resonant cavity region 507 is used to accommodate part of the first dielectric layer 502, the piezoelectric layer 504, and the top electrode layer 505; wherein, the depth of the first resonant cavity region 507 is positively correlated with the vibration amplitude of the resonator in the depth direction.

[0229] Different from the foregoing First Embodiment, Second Embodiment, and Third Embodiment, as Figure 10 shown, the device wafer in this embodiment further includes a third resonant cavity region 512, wherein the third resonant cavity region 512 is formed after the side of the device silicon layer 501 away from the substrate layer 506 is partially thinned; the depth of the third resonant cavity region 512 is less than the thickness of the device silicon layer;

[0230] wherein, the orthographic projection of the third resonant cavity region 512 on the substrate layer 506 and the orthographic projection of the first resonant cavity region 507 on the substrate layer 506 at least partially overlap.

[0231] According to the foregoing, the device wafer includes a first resonant cavity region and a third resonant cavity region. In order to connect the first resonant cavity region and the third resonant cavity region, as Figure 10 shown, the device wafer further includes a fourth trench 515 penetrating the seventh stacked structure of the device wafer, wherein:

[0232] The fourth groove 515 is used to connect the first resonant cavity region and the third resonant cavity region, and to define the shape and boundary region of the resonator. The seventh stacked structure includes a device silicon layer 501 and a first dielectric layer 502.

[0233] Further, as Figure 10 shown, a second protrusion structure 516 is formed on the side of the device silicon layer 501 away from the substrate layer 506 at at least one pin bonding position, and it can be seen that the first annular isolation groove is located outside the second protrusion structure 516. The second protrusion structure 516 is used for electrically connecting the metal layer 511 and the top electrode layer 505.

[0234] It should be understood that the device silicon layer 501 further includes a fifth annular isolation groove arranged on the same layer, and the positive projection of at least one fifth annular isolation groove and a part of the device silicon layer located inside the ring of the fifth annular isolation groove on the substrate layer falls within the positive projection of the first resonant cavity region 507 on the substrate layer 506.

[0235] The top electrode layer 505 is electrically connected to a part of the device silicon layer located inside the ring of the fifth annular isolation groove. Among them, the position where the top electrode layer 505 is electrically connected to the device silicon layer located inside the ring of the fifth annular isolation groove is Figure 10 the position numbered 514 in the figure, so that the top electrode layer 505 is electrically connected to the second protrusion structure through the device silicon layer at the 514 position.

[0236] It should be noted that Figure 10 The processing flow of the shown packaging structure can refer to the processing flow shown in the foregoing Figures 7A to 7J or the processing flow shown in the foregoing Figures 9A to 9I This application will not elaborate here.

[0237] The difference is that the initial thickness of the device silicon layer is greater than the target thickness of the final thinning region, and the thinning region is the third resonant cavity region. At the same time, as Figure 10 shown, after performing steps similar to Figure 7I or Figure 9H , two types of cavities need to be etched on the side of the device silicon layer facing the capping wafer first. One is a sub-cavity 512-1 with a relatively shallow depth, and it can be seen that the sub-cavity 512-1 straddles part of the fifth annular isolation groove; the other is a sub-cavity 512-2 with a relatively large depth, and the sub-cavity 512-2 is located in the effective region of the resonator. Similar to the steps in Figure 4E and Figure 4F , the sub-cavity 512-1 and the sub-cavity 512-2 together constitute the third resonant cavity region 512; further, perform steps similar to Figure 7J or Figure 9IIn the step of etching a through-groove structure defining the resonator boundary, i.e., the fourth groove, in the sub-cavity 512-2, so as to penetrate the first resonant cavity and the third resonant cavity. It should be understood that the process for implementing the packaging structure as shown in Figure 10 is not limited to the above description, and the present application does not make any limitation thereto.

[0238] It should be noted that for the same structures in Embodiment Four, Embodiment Three, Embodiment Two and Embodiment One, reference may be made to the descriptions of Embodiment One, Embodiment Two and Embodiment Three above, and the present application will not repeat them here.

[0239] Based on the foregoing description, in the wafer-level packaging structure of a piezoelectric MEMS resonator based on silicon-silicon bonding proposed in this embodiment, only the metal layer on the outer side of the capping wafer is made of metal material, and the structures of the remaining parts do not have any metal material; and the piezoelectric layer is made of aluminum nitride or doped aluminum nitride material that can withstand high temperatures, and the remaining materials are silicon or silicon dioxide materials, all of which can withstand high-temperature treatment above 800 °C. Thus, the residual gas adsorbed in the material body can be completely discharged through high-temperature annealing in the bonding step, effectively improving the packaging vacuum degree, so that the vacuum degree reaches below 1 Pa; and a lower vacuum degree is beneficial to further improving the Q value of the resonator, maintaining the resonator frequency and maintaining the long-term stability of the Q value, effectively improving the working performance of the resonator; in addition, it can also improve the sensitivity, resolution and reliability and other characteristics of the corresponding sensor.

[0240] Embodiment Five

[0241] As Figure 11 shown, the packaging structure for a piezoelectric MEMS resonator includes:

[0242] A device wafer, a capping wafer, and a first insulating layer 609 and a metal layer 611 disposed on the capping wafer, wherein:

[0243] The device wafer includes: a substrate layer 606, wherein the substrate layer 606 includes a substrate region and a first resonant cavity region 607 surrounded by the substrate region; and a device silicon layer 601, a first dielectric layer 602, a piezoelectric layer 604 and a top electrode layer 605 disposed on the substrate layer 606, wherein the material of the top electrode layer 605 is doped polysilicon;

[0244] The capping wafer includes: a capping layer 608; and a first annular isolation groove formed in the capping layer, wherein the first annular isolation groove is filled with a second dielectric layer 610;

[0245] Wherein, the surface of the device wafer bonded to the capping wafer is the surface of the device silicon layer away from the substrate layer, the surface of the capping wafer bonded to the device wafer is the surface of the capping layer away from the first insulating layer, and the material of the capping layer is low-resistivity single-crystalline silicon.

[0246] Similar to the foregoing second and third embodiments, the capping wafer of this embodiment further includes a second resonant cavity region 612 formed on the side of the capping layer 608 away from the first insulating layer 609. As can be seen from Figure 11 it, the orthographic projection of the first resonant cavity region 607 on the substrate layer 606 and the orthographic projection of the second resonant cavity region 612 on the substrate layer 406 at least partially overlap.

[0247] Similar to the foregoing second and third embodiments, the silicon-silicon bonding position of this embodiment is on the opposite sides of the piezoelectric layer in the device silicon layer. Specifically, as Figure 11 shown, the bonding position of the device wafer and the capping wafer is on the side of the device silicon layer 601 away from the substrate layer 606, while the piezoelectric layer 604 is on the side of the device silicon layer 601 close to the substrate layer 606. The orthographic projection of the bonding position of the device wafer and the capping wafer on the substrate layer falls within the orthographic projection of the first resonant cavity region on the substrate layer, that is, the silicon-silicon bonding position in this embodiment is located within the first resonant cavity region.

[0248] Further, at the bonding position, the capping wafer forms an electrical connection and a sealing ring with the side of the device silicon layer away from the substrate layer through silicon-silicon bonding. Thus, the bonding position includes a pin bonding position and a sealing ring bonding position (reference can be made to the foregoing description of the first embodiment here).

[0249] Further, different from the foregoing first embodiment, the first resonant cavity region 607 is used to accommodate part of the first dielectric layer 602, the piezoelectric layer 604, and the top electrode layer 605; wherein, the depth of the first resonant cavity region 607 is positively correlated with the vibration amplitude of the resonator in the depth direction.

[0250] Further, the device wafer further includes a fifth insulating layer 613 disposed on the device silicon layer and a sixth annular isolation groove (labeled 616 in Figure 12H ) provided on the same layer as the device silicon layer 601. Wherein, the sixth annular isolation groove is filled with the first dielectric layer 602; wherein, the orthographic projection of at least one of the sixth annular isolation grooves and the device silicon layer 601 within the ring of the sixth annular isolation groove on the substrate layer falls within the orthographic projection of the first resonant cavity region 607 on the substrate layer 606.

[0251] Further, referring to Figure 10, the depth of the sixth annular isolation groove is less than the thickness of the device silicon layer 601; the sixth annular isolation groove is correspondingly arranged with the first annular isolation groove; the sixth annular isolation is filled with the first dielectric layer 602, and the surface of the first dielectric layer 602 away from the substrate layer is not higher than the surface of the device silicon layer 601 away from the substrate layer.

[0252] The top electrode layer 605 is electrically connected to a part of the device silicon layer located inside the ring of the sixth annular isolation groove. Among them, the position where the top electrode layer 605 is electrically connected to the device silicon layer inside the ring of the sixth annular isolation groove is Figure 11 the position marked 614 in the figure.

[0253] As can be seen from the foregoing, the device wafer includes a first resonant cavity region, and the capping wafer includes a second resonant cavity region. In order to realize the communication between the first resonant cavity region and the second resonant cavity region, as Figure 11 shown, the device wafer further includes a fifth trench 615 penetrating the eighth stacked structure of the device wafer, where:

[0254] The fifth trench 615 is used to communicate the first resonant cavity region and the second resonant cavity region, and to define the shape and boundary region of the resonator. Among them, the eighth stacked structure includes the device silicon layer 601 and the ninth stacked structure. According to different manufacturing processes, the ninth stacked structure includes at least one of the first dielectric layer 602 and the piezoelectric layer 604.

[0255] Next, in combination with Figures 12A to 12N to Figure 11 shown, the manufacturing method of the packaging structure will be further described:

[0256] First, as Figure 12A shown, on the substrate of the capping layer (low-resistivity single-crystalline silicon) 608, an annular isolation groove structure is etched, and the second dielectric layer 610 is deposited. Among them, the shape of the annular isolation groove is not limited to a circle, and it can be any closed-loop shape. The annular isolation groove etched here is the first annular isolation groove. It should be understood that the depth of the first annular isolation groove is at least greater than the thickness of the final device capping wafer. For example, the general depth is greater than 100 um.

[0257] Further, as Figure 12B shown, the capping layer 608 of the effective resonant region is etched to form the second resonant cavity region 612.

[0258] So far, the processing of the capping wafer is completed.

[0259] Further, as Figure 12CAs shown, a single-crystalline silicon substrate can be used as the device silicon layer 601. A trench is etched at a position corresponding to the first annular isolation groove structure of the capping wafer. The projected width of the trench on the substrate layer is greater than the projected width of the first annular isolation groove on the corresponding capping wafer on the substrate layer. The fifth insulating layer 613 is filled in the isolation groove. The material of the fifth insulating layer is, for example, silicon dioxide or PSG, etc. Further, CMP is performed to remove the insulating material on the surface of the substrate, and the substrate material is exposed again, that is, the surface of the device silicon layer 601 is exposed; it can also be as Figure 12D shown, starting from an SOI substrate, 601b is the buried oxide layer, and 601c is the support layer. This application does not make any limitations in this regard.

[0260] Further, as Figure 12E shown, the Figure 12B shown capping wafer is silicon-silicon bonded to the Figure 12C shown device silicon layer 601 and the fifth insulating layer 613. Among them, the details of the bonding between the trench at the corresponding position of the fifth insulating layer and the first annular isolation groove are as Figure 12F shown. It can be seen that the insulating material filled in the trench at the corresponding position of the fifth insulating layer has a different hardness from that of the device silicon layer 601. Therefore, in the CMP step, a depression will be formed, that is, the surface of the fifth insulating layer is lower than the surface of the device silicon layer. Therefore, when bonding, the two do not come into contact.

[0261] Further, as Figure 12G shown, the surface of the device silicon layer 601 is thinned, or the support layer 601c and the buried oxide layer 601b of the SOI in Figure 12D are removed, or only the support layer 601c of the SOI is removed, and the buried oxide layer 601b is still retained. The remaining 601a is used as the device silicon layer.

[0262] Further, as Figure 12H shown, an annular trench structure, that is, the sixth annular isolation groove 616, is etched in the device silicon layer 601. The sixth annular isolation groove 616 is correspondingly arranged with the aforementioned first annular isolation groove. Thus, the sixth annular isolation groove 616 is located above the second dielectric layer 610 and uses the second dielectric layer 610 as a barrier layer (etch-stop layer).

[0263] Further, as Figure 12I and Figure 12J shown, the first dielectric layer 602 is used to fill the device silicon layer 601 and the sixth annular isolation groove, and at least the silicon dioxide in the effective resonance region of the resonator is removed, so as to expose the device silicon layer. Among them, at least part of the exposed part overlaps with the second resonance cavity region in the vertical direction. That is, further, a piezoelectric layer 604 is deposited on the exposed device silicon layer, and the piezoelectric layer 604 is etched.

[0264] Further, as Figure 12KAs shown, remove a part of the first dielectric layer 602 above the device silicon layer in the inner part of the sixth annular isolation groove ring to expose the underlying device silicon layer, that is, expose Figure 12K the device silicon layer at the position numbered 614 in

[0265] Further, as Figure 12L shown, deposit doped polysilicon as the top electrode layer 605 and pattern it to form an electrode. Among them, a part of the top electrode layer 605 is located above the piezoelectric layer 604, a part straddles the piezoelectric layer 604 and the sixth annular isolation groove, and is electrically connected to the device silicon layer serving as a pin (that is, Figure 12K the device silicon layer at the position numbered 614 in

[0266] Further, as Figure 12M shown, etch the stacked structure above the second resonant cavity region to obtain a trench penetrating these stacked structures, that is, the fifth trench 615. On the one hand, the fifth trench 615 can connect the first resonant cavity region and the second resonant cavity; on the other hand, it can also define the shape and boundary region of the resonator. Among them, the stacked structure penetrated by the fifth trench 615 includes the device silicon layer 601 and the first dielectric layer 602.

[0267] Further, as Figure 12N shown, bond it to another substrate layer 606 that has been etched to form the first resonant cavity region 607 by means of silicon-silicon dioxide fusion bonding.

[0268] Further, perform an operation similar to Figure 5B to thin the capping wafer. Thin the side of the capping wafer away from the second resonant cavity region by grinding or etching until the first annular isolation groove structure is exposed and the target thickness in the manufacturing process is reached. At this time, the capping layer in the inner part of the first annular isolation groove ring is electrically isolated from the capping layer outside the first annular isolation groove, so that the inner part of the first annular isolation groove can be used as a conductive via.

[0269] Further, perform an operation similar to Figure 5C to deposit a first insulating layer on the surface of the capping wafer away from the second resonant cavity region. The material of the first insulating layer is generally silicon dioxide and may also include other polymer insulating material layers; and etch a part of the first insulating layer to expose the conductive via, and then deposit a metal layer and etch the metal layer to form a device pin. Finally, obtain the packaging structure as Figure 11 shown.

[0270] It should be noted that for the same structures in Embodiment Five, Embodiment Four, Embodiment Three, Embodiment Two, and Embodiment One, reference can be made to the descriptions of Embodiment One, Embodiment Two, Embodiment Three, and Embodiment Four above, and the present application will not repeat them here.

[0271] In summary, the wafer-level packaging structure of the piezoelectric MEMS resonator based on silicon-silicon bonding proposed in the embodiments of the present application can completely discharge the residual gas adsorbed in the material body through high-temperature annealing during the bonding step, effectively improving the packaging vacuum degree to below 1 Pa; and a higher vacuum degree is beneficial to further improving the Q value of the resonator, maintaining the resonator frequency, and maintaining the long-term stability of the Q value, effectively improving the working performance of the resonator; in addition, it can also improve the sensitivity, resolution, reliability and other characteristics of the corresponding sensor.

[0272] The embodiments of the present application also provide an electronic component, which includes the packaging structure described in the foregoing embodiments. Since the structure and characteristics of the packaging structure have been described in detail in the above embodiments, the content is incorporated herein and the description is omitted here.

[0273] In addition, the electronic component of the embodiments of the present application can be applied to a communication device that follows the fifth-generation mobile communication standard or can be included in the communication device. For details, reference can be made to related technologies, and the embodiments of the present application do not limit this.

[0274] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added or deleted. For example, the steps recorded in the present disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present disclosure can be achieved. There is no limitation here.

[0275] In the embodiments of the present application, the singular forms "a", "the", etc. include plural forms and should be broadly understood as "a kind" or "a class" rather than being limited to the meaning of "one"; in addition, the term "the" should be understood to include both singular and plural forms unless the context clearly indicates otherwise. In addition, the term "according to" should be understood as "at least partially according to...", and the term "based on" should be understood as "at least partially based on...", unless the context clearly indicates otherwise.

[0276] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances; relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0277] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0278] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A packaging structure for a piezoelectric MEMS resonator, characterized in that, Comprising: A device wafer, a capping wafer, and a first insulating layer and a metal layer disposed on the capping wafer, wherein: The device wafer includes: a substrate layer, wherein the substrate layer includes a substrate region and a first resonant cavity region surrounded by the substrate region; and a device silicon layer, a first dielectric layer, a piezoelectric layer, and a top electrode layer disposed on the substrate layer, wherein the material of the top electrode layer is doped polysilicon; The capping wafer includes: a capping layer; and a first annular isolation groove formed in the capping layer, wherein the first annular isolation groove is filled with a second dielectric layer; Wherein, the surface of the device wafer for bonding with the capping wafer is the surface of the device silicon layer away from the substrate layer, the surface of the capping wafer for bonding with the device wafer is the surface of the capping layer away from the first insulating layer, and the material of the capping layer is low-resistance single-crystalline silicon.

2. The packaging structure according to claim 1, wherein The bonding position of the device wafer and the capping wafer is on the same side of the piezoelectric layer in the device silicon layer; at the bonding position, the capping wafer forms an electrical connection and a sealing ring with the surface of the device silicon layer away from the substrate layer through silicon-silicon bonding; The capping wafer further includes a second resonant cavity region, wherein the orthographic projection of the first resonant cavity region on the substrate layer and the orthographic projection of the second resonant cavity region on the substrate layer at least partially overlap; the second resonant cavity region is used to accommodate the piezoelectric layer, the top electrode layer, and a part of the first dielectric layer; The orthographic projection of the bonding position of the device wafer and the capping wafer on the substrate layer does not overlap with the orthographic projection of the first resonant cavity region on the substrate layer.

3. The encapsulation structure according to claim 2, characterized in that, The device wafer further includes a second insulating layer located between the device silicon layer and the substrate layer, wherein: The part of the second insulating layer corresponding to the first resonant cavity region is located on the surface of the device silicon layer close to the substrate layer; or The part of the second insulating layer corresponding to the first resonant cavity region is located on the surface of the substrate region close to the device silicon layer.

4. The encapsulation structure according to claim 3, characterized in that, The device silicon layer further includes a second annular isolation groove disposed in the same layer, wherein the second annular isolation groove is filled with the first dielectric layer; at least part of the first dielectric layer on the device silicon layer located inside the ring of the second annular isolation groove is removed to expose the device silicon layer.

5. The packaging structure according to claim 1, wherein At least part of the piezoelectric layer is directly disposed on the device silicon layer, and the orthographic projection of the region where the piezoelectric layer contacts the device silicon layer on the substrate layer at least partially overlaps with the orthographic projection of the first resonant cavity region on the substrate layer.

6. The encapsulation structure according to claim 5, characterized in that At least part of the piezoelectric layer is located on the first dielectric layer.

7. The packaging structure according to claim 4, wherein The top electrode layer is located above the piezoelectric layer, and the top electrode layer straddles the piezoelectric layer and at least one of the second annular isolation grooves to be electrically connected to the exposed device silicon layer inside the ring.

8. The encapsulation structure according to claim 7, wherein The bonding positions include a sealing ring bonding position and a pin bonding position, where: The orthographic projection of the sealing ring bonding position on the substrate layer is annular, and the orthographic projection of the sealing ring bonding position on the substrate layer surrounds the orthographic projection of the pin bonding position on the substrate layer; At least one of the pin bonding positions is located in the inner part of the ring of the second annular isolation groove.

9. The encapsulation structure according to claim 8, wherein The device wafer further includes: a first trench penetrating through the first stacked structure of the device wafer, where: The first trench is used to connect the first resonant cavity region and the second resonant cavity, and to define the shape and boundary region of the resonator.

10. The encapsulation structure according to claim 9, wherein The first stacked structure includes the device silicon layer and a second stacked structure, where the second stacked structure includes at least one of the first dielectric layer, the second insulating layer, and the piezoelectric layer.

11. The packaging structure according to claim 1, wherein The inner part of the ring of the first annular isolation groove is a conductive via, and the conductive via is electrically connected to the metal layer, so that the conductive via leads out the electrical signal in the device wafer to the side of the cap layer close to the first insulating layer.

12. The packaging structure according to claim 1, wherein The material of the second dielectric layer includes silicon dioxide and polysilicon; or the material of the second dielectric layer includes silicon dioxide.

13. The packaging structure according to claim 8, wherein A first raised structure is formed at the bonding position on the side of the cap layer away from the first insulating layer, and the first annular isolation groove is located outside the first raised structure at the pin bonding position; Wherein, the height of the first raised structure is at least higher than the thickness of the first dielectric layer; the depth of the second resonant cavity region is greater than or equal to the height of the first raised structure.

14. The packaging structure according to claim 1, wherein The cap wafer further includes a second resonant cavity region formed on the side of the cap layer away from the first insulating layer, and the orthographic projection of the first resonant cavity region on the substrate layer and the orthographic projection of the second resonant cavity region on the substrate layer at least partially overlap; The bonding position of the device wafer and the cap wafer is on the side of the device silicon layer away from the substrate layer, and the piezoelectric layer is on the side of the device silicon layer close to the substrate layer; at the bonding position, the cap wafer forms an electrical connection and a sealing ring with the side of the device silicon layer away from the substrate layer through silicon-silicon bonding; The first resonant cavity region is used to accommodate the piezoelectric layer, the top electrode layer, and part of the first dielectric layer.

15. The packaging structure according to claim 14, wherein The device wafer further includes a third insulating layer disposed on the device silicon layer and a third annular isolation groove disposed on the same layer as the third insulating layer and the device silicon layer, where the third annular isolation groove serves as a lead region on the side of the device silicon layer away from the substrate layer; the third annular isolation groove is filled with a third dielectric layer. Wherein, the positive projection of at least one of the third annular isolation grooves and a part of the device silicon layer located in the inner part of the ring of the third annular isolation groove on the substrate layer falls within the positive projection of the first resonant cavity region on the substrate layer; The top electrode layer is electrically connected to a part of the device silicon layer located in the inner part of the ring of the third annular isolation groove.

16. The encapsulation structure according to claim 15, wherein The device wafer further includes a second trench penetrating through the third stacked structure of the device wafer, wherein: The second trench is used to communicate the first resonant cavity region and the second resonant cavity region, and to define the shape and boundary region of the resonator.

17. The package structure according to claim 16, wherein The third stacked structure includes the device silicon layer and a fourth stacked structure, wherein the fourth stacked structure includes at least one of the third insulating layer, the third dielectric layer, and the first dielectric layer; The positive projection of the bonding position of the device wafer and the capping wafer on the substrate layer does not overlap with the positive projection of the first resonant cavity region on the substrate layer.

18. The package structure according to claim 14, wherein The device wafer further includes a fourth insulating layer provided on the device silicon layer and a fourth annular isolation groove provided on the same layer as the device silicon layer, wherein the fourth annular isolation groove serves as a lead region on the side of the device silicon layer close to the substrate layer; the fourth annular isolation groove is filled with the first dielectric layer. Wherein, the positive projection of at least one of the fourth annular isolation grooves and a part of the device silicon layer located in the inner part of the ring of the fourth annular isolation groove on the substrate layer falls within the positive projection of the first resonant cavity region on the substrate layer; The top electrode layer is electrically connected to a part of the device silicon layer located in the inner part of the ring of the fourth annular isolation groove.

19. The encapsulation structure according to claim 18, wherein, The device wafer further includes a third trench penetrating through the fifth stacked structure of the device wafer, wherein: The third trench is used to communicate the first resonant cavity region and the second resonant cavity region, and to define the shape and boundary region of the resonator.

20. The package structure according to claim 19, wherein The fifth stacked structure includes the device silicon layer and a sixth stacked structure, wherein the sixth stacked structure includes at least one of the fourth insulating layer and the first dielectric layer; The positive projection of the bonding position of the device wafer and the capping wafer on the substrate layer does not overlap with the positive projection of the first resonant cavity region on the substrate layer.

21. The package structure according to claim 1, wherein The bonding position of the device wafer and the capping wafer is on the side of the device silicon layer away from the substrate layer, and the piezoelectric layer is on the side of the device silicon layer close to the substrate layer; at the bonding position, the capping wafer forms an electrical connection and a sealing ring with the side of the device silicon layer away from the substrate layer through silicon-silicon bonding; The first resonant cavity region is used to accommodate the piezoelectric layer, the top electrode layer, and a part of the first dielectric layer; The device wafer further includes a third resonant cavity region, wherein the third resonant cavity region is formed after the side of the device silicon layer away from the substrate layer is locally thinned; the depth of the third resonant cavity region is less than the thickness of the device silicon layer; wherein, the orthographic projection of the third resonant cavity region on the substrate layer and the orthographic projection of the first resonant cavity region on the substrate layer at least partially overlap.

22. The encapsulation structure according to claim 21, wherein The device wafer further includes a fourth trench penetrating through the seventh stacked structure of the device wafer, wherein: the fourth trench is used to connect the first resonant cavity region and the third resonant cavity region, and to define the shape and boundary region of the resonator; a second raised structure is formed on the side of the device silicon layer away from the substrate layer at at least one pin bonding position, and the first annular isolation groove is located outside the second raised structure; the second raised structure is used to electrically connect the metal layer and the top electrode layer.

23. The package structure according to claim 22, wherein the seventh stacked structure includes the device silicon layer and the first dielectric layer; the orthographic projection of the bonding position between the device wafer and the capping wafer on the substrate layer does not overlap with the orthographic projection of the first resonant cavity region on the substrate layer.

24. The package structure according to claim 14, wherein the device wafer further includes a fifth insulating layer disposed on the device silicon layer and a sixth annular isolation groove disposed on the same layer as the device silicon layer, wherein the depth of the sixth annular isolation groove is less than the thickness of the device silicon layer; the sixth annular isolation groove is correspondingly disposed with the first annular isolation groove; the sixth annular isolation groove is filled with the first dielectric layer, and the surface of the first dielectric layer away from the substrate layer is not higher than the surface of the device silicon layer away from the substrate layer; the orthographic projection of the bonding position between the device wafer and the capping wafer on the substrate layer falls within the orthographic projection of the first resonant cavity region on the substrate layer.

25. The encapsulation structure according to claim 24, wherein The device silicon layer further includes a fifth trench penetrating through the eighth stacked structure of the device wafer, wherein: the fifth trench is used to connect the first resonant cavity region and the second resonant cavity region, and to define the shape and boundary region of the resonator; the eighth stacked structure includes the device silicon layer and a ninth stacked structure, and the ninth stacked structure includes at least one of the first dielectric layer and the piezoelectric layer.

26. The encapsulation structure according to claim 1, wherein At least part of the material of the device silicon layer is a doped silicon layer, and the doping concentration of the doped silicon layer is 10 19 cm -3 or more.

27. An electronic component, characterized in that, The electronic component includes the package structure according to any one of claims 1 to 26.

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