Piezoelectric MEMS resonator, semiconductor device, manufacturing method, and electronic component

Abstract

The invention relates to the field of semiconductor devices, and provides a piezoelectric MEMS resonator, a semiconductor device, a manufacturing method and an electronic element. The resonator comprises a substrate, an insulating layer, a device silicon layer, a piezoelectric layer and an electrode layer which are stacked in the first direction, a cavity is formed in the upper side of the substrate, and a plurality of doped regions with different doping gradients in the first direction are included in the region, corresponding to the cavity, of the device silicon layer. At least one of the plurality of doped regions has a maximum doping concentration of 1020 cm <-3 > or more. Therefore, through local doping, the doping concentration of at least part of the region on the device silicon layer is more than 1020 cm <-3 >, and the equivalent resistivity of the device silicon layer in the effective region of the device is lower than 0.8 m omega.cm, so that the temperature compensation effect is improved, and the frequency temperature stability of the resonator is further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular, to a piezoelectric MEMS resonator, a semiconductor device, a manufacturing method, and an electronic component. Background Art

[0002] A resonator is a core device of an oscillator. Since a silicon-based MEMS resonator driven by electrostatic force has smaller size, lower manufacturing cost, and higher reliability, a MEMS oscillator with a silicon-based MEMS resonator driven by electrostatic force as the core device is expected to become a substitute for traditional quartz oscillators with the increasingly mature technology.

[0003] With the development of piezoelectric thin film materials, compared with a silicon-based MEMS resonator driven by electrostatic force, a silicon-based MEMS resonator driven by piezoelectric force (which can be abbreviated as "piezoelectrically driven silicon-based MEMS resonator") exhibits excellent properties such as lower motional impedance and higher electromechanical coupling coefficient, which is more conducive to reducing the power consumption and phase noise of the oscillator.

[0004] Since a piezoelectrically driven silicon-based MEMS resonator does not require an applied electrostatic bias voltage, the error term generated by the power supply jitter on the output signal is reduced; in addition, a piezoelectrically driven silicon-based MEMS resonator does not require the formation of sub-micron silicon layer slits during processing, reducing the process difficulty, which is conducive to improving the device yield and further miniaturization of the device.

[0005] A typical structure of a piezoelectrically driven silicon-based MEMS resonator includes a stacked substrate silicon layer, a device silicon layer, a piezoelectric layer, an electrode layer, etc. Since the elastic moduli of ordinary silicon layer, piezoelectric layer, and electrode layer have a negative temperature coefficient, the resonator composed of these materials has a negative frequency temperature coefficient. In order to improve the frequency temperature stability, temperature compensation is required for the resonator. One method is to increase the positive temperature coefficient material, and the other method is to use heavily doped silicon (doping concentration of 10 19 cm -3 or higher) as the device silicon layer.

[0006] This section aims to provide background or context for the embodiments of the present application stated in the claims. The description herein is not admitted to be prior art merely because it is included in this section. Summary of the Invention

[0007] The inventors found that the frequency temperature stability of a piezoelectrically driven silicon-based MEMS resonator produced according to the current process is not good. Increasing the positive temperature coefficient material will lead to an increase in interface loss and a decrease in the Q value, and the doping concentration of a silicon wafer manufactured by the Czochralski method is difficult to reach 10 20 cm -3, which is not conducive to further improving the temperature compensation effect. That is to say, the current piezoelectrically driven silicon-based MEMS resonator cannot achieve good temperature compensation to ensure good frequency temperature stability within its operating temperature range (for example: -40°C to 85°C, or even -55°C to 125°C), such as less than ±10 ppm, less than ±1 ppm, less than ±0.1 ppm.

[0008] To solve at least one of the above problems or other similar problems, embodiments of the present application provide a piezoelectric MEMS resonator, a semiconductor device, a manufacturing method, and an electronic component.

[0009] According to a first aspect of embodiments of the present application, there is provided a semiconductor device including a piezoelectric MEMS resonator. The semiconductor device includes a plurality of piezoelectric MEMS resonators. Each piezoelectric MEMS resonator includes a substrate, an insulating layer, a device silicon layer, a piezoelectric layer, and an electrode layer stacked in a first direction. A cavity is provided on the upper side of the substrate. The plurality of piezoelectric MEMS resonators are located on the same substrate.

[0010] The doping concentrations of at least a part of the regions of the device silicon layers of at least two piezoelectric MEMS resonators corresponding to the cavity are different in the first direction, and / or

[0011] The doping elements of at least a part of the regions of the device silicon layers of at least two piezoelectric MEMS resonators corresponding to the cavity are different, and / or

[0012] The distributions of the doping regions included in the regions of the device silicon layers of at least two piezoelectric MEMS resonators corresponding to the cavity are different, and / or

[0013] The equivalent resistivities of the regions of the device silicon layers of at least two piezoelectric MEMS resonators corresponding to the cavity are different.

[0014] According to a second aspect of embodiments of the present application, there is provided a piezoelectric MEMS resonator. The piezoelectric MEMS resonator includes a substrate, an insulating layer, a device silicon layer, a piezoelectric layer, and an electrode layer stacked in a first direction. A cavity is provided on the upper side of the substrate.

[0015] The region of the device silicon layer corresponding to the cavity includes a plurality of doping regions with different doping gradients in the first direction. The highest doping concentration of at least one of the plurality of doping regions is 10 20 cm -3 or more, and / or

[0016] The region of the device silicon layer corresponding to the cavity includes a plurality of doping regions with different doping elements.

[0017] According to a third aspect of an embodiment of the present application, a manufacturing method of a piezoelectric MEMS resonator is provided. The piezoelectric MEMS resonator includes a substrate, a first insulating layer, a device silicon layer, a piezoelectric layer, and an electrode layer stacked in a first direction. A cavity is provided on an upper side of the substrate. The manufacturing method includes performing a first doping operation, and the first doping operation includes:

[0018] Forming a patterned first hard mask on an upper surface of the device silicon layer away from the substrate, and at least a part of a hollowed-out area of the first hard mask coincides with an area of the device silicon layer corresponding to the cavity;

[0019] Growing a first thin film containing a doping element on a side of the first hard mask;

[0020] Diffusing the doping element in the first thin film into the device silicon layer by heating, so that a highest doping concentration of the device silicon layer is 10 20 cm -3 or more;

[0021] Removing the first thin film and the first hard mask.

[0022] According to a fourth aspect of an embodiment of the present application, a manufacturing method of a semiconductor device including a piezoelectric MEMS resonator is provided. The semiconductor device includes a plurality of piezoelectric MEMS resonators. Each piezoelectric MEMS resonator includes a substrate, a first insulating layer, a device silicon layer, a piezoelectric layer, and an electrode layer stacked in a first direction. A cavity is provided on an upper side of the substrate. The manufacturing method includes a third doping operation, and the third doping operation includes:

[0023] Forming a patterned third hard mask on an upper surface of the device silicon layer of the plurality of piezoelectric MEMS resonators away from the substrate, and at least a part of a hollowed-out area of the third hard mask coincides with an area of the device silicon layer of at least one piezoelectric MEMS resonator corresponding to the cavity;

[0024] Growing a third thin film containing a doping element on a side of the third hard mask;

[0025] Diffusing the doping element in the third thin film into the device silicon layer of the at least one piezoelectric MEMS resonator;

[0026] Removing the third thin film and the third hard mask.

[0027] According to a fifth aspect of an embodiment of the present application, an electronic component is provided. The electronic component includes the semiconductor device described in the embodiment of the first aspect.

[0028] According to a sixth aspect of an embodiment of the present application, an electronic component is provided. The electronic component includes the piezoelectric MEMS resonator described in the embodiment of the second aspect.

[0029] One of the beneficial effects of the embodiments of the present application is that through local doping, the doping concentration of at least some regions on the device silicon layer is above 10 20 cm -3 or more, so that the equivalent resistivity of the device silicon layer in the effective region of the device is lower than 0.8 mΩ·cm, which is beneficial to improving the temperature compensation effect and further improving the frequency temperature stability of the resonator. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figure 1 is a schematic diagram of a piezoelectric MEMS resonator according to an embodiment of the present application.

[0032] Figure 2 is along Figure 1 the schematic diagram of the gradient distribution of the doping concentration of the cross-section line A-A' shown.

[0033] Figure 3 is along Figure 1 the schematic diagram of the gradient distribution of the doping concentration of the cross-section line B-B' shown.

[0034] Figure 4 is along Figure 1 the schematic diagram of the gradient distribution of the doping concentration of the cross-section line C-C' shown.

[0035] Figure 5 is a schematic diagram of an embodiment of a semiconductor device including a piezoelectric MEMS resonator according to an embodiment of the present application.

[0036] Figure 6 is a schematic diagram of another embodiment of a semiconductor device including a piezoelectric MEMS resonator according to an embodiment of the present application.

[0037] Figure 7 is a schematic diagram of another embodiment of a semiconductor device including a piezoelectric MEMS resonator according to an embodiment of the present application.

[0038] Figure 8 is a schematic diagram of a manufacturing method of a piezoelectric MEMS resonator according to an embodiment of the present application.

[0039] Figure 9It is a schematic diagram for explaining the first doping operation of the manufacturing method of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0040] Figure 10 It is another schematic diagram for explaining the first doping operation of the manufacturing method of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0041] Figure 11 It is another schematic diagram for explaining the first doping operation of the manufacturing method of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0042] Figure 12 It is another schematic diagram for explaining the first doping operation of the manufacturing method of the piezoelectric MEMS resonator according to the embodiment of the present application.

[0043] Figure 13 It is a schematic diagram for explaining the repeated execution of the first doping operation.

[0044] Figure 14 It is another schematic diagram for explaining the repeated execution of the first doping operation.

[0045] Figure 15 It is a schematic diagram for explaining the double-sided local doping process according to the embodiment of the present application.

[0046] Figure 16 It is another schematic diagram for explaining the double-sided local doping process according to the embodiment of the present application.

[0047] Figure 17 It is another schematic diagram for explaining the double-sided local doping process according to the embodiment of the present application.

[0048] Figure 18 It is another schematic diagram for explaining the double-sided local doping process according to the embodiment of the present application.

[0049] Figure 19 It is a schematic diagram of the manufacturing method of the semiconductor device including the piezoelectric MEMS resonator according to the embodiment of the present application.

[0050] Figure 20 It is a schematic diagram for explaining the manufacturing method of the semiconductor device including the piezoelectric MEMS resonator according to the embodiment of the present application.

[0051] Figure 21 It is another schematic diagram for explaining the manufacturing method of the semiconductor device including the piezoelectric MEMS resonator according to the embodiment of the present application.

[0052] Figure 22 It is another schematic diagram for explaining the manufacturing method of the semiconductor device including the piezoelectric MEMS resonator according to the embodiment of the present application. Detailed implementation manners

[0053] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer and more understandable, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings. Herein, the illustrative embodiments of the present application and their descriptions are used to explain the present application, but are not intended to limit the present application.

[0054] In the embodiments of the present application, terms such as "first", "second", "upper", "lower", etc. are used to distinguish different elements in terms of name, but do not indicate the spatial arrangement or time sequence of these elements, and these elements should not be limited by these terms. The term "and / or" includes any one and all combinations of one or more of the associated listed terms. The terms "comprising", "including", "having", etc. mean the presence of the stated features, elements, components or assemblies, but do not exclude the presence or addition of one or more other features, elements, components or assemblies.

[0055] In the embodiments of the present application, the singular forms "a", "the", etc. include the plural forms and should be broadly understood as "one kind" or "one class" rather than being limited to the meaning of "one"; in addition, the term "the" should be understood to include both the singular form and the plural form unless the context clearly indicates otherwise. In addition, the term "according to" should be understood as "at least partially according to...", and the term "based on" should be understood as "at least partially based on...", unless the context clearly indicates otherwise.

[0056] The embodiments of the present application will be described below with reference to the accompanying drawings.

[0057] The embodiments of the present application provide a piezoelectric MEMS resonator, which may be a silicon-based MEMS resonator based on piezoelectric drive, but the embodiments of the present application do not limit this. Hereinafter, the piezoelectric MEMS resonator of the present application will be described by taking a silicon-based MEMS resonator based on piezoelectric drive as an example.

[0058] Figure 1 is a schematic diagram of the piezoelectric MEMS resonator of the embodiments of the present application.

[0059] As Figure 1 shown, the piezoelectric MEMS resonator (hereinafter referred to as "resonator") 1 includes a substrate 101, an insulating layer 103, a device silicon layer 201, a piezoelectric layer 202, and an electrode layer 203 stacked in the first direction z. A cavity 102 is provided on the upper side of the substrate 101.

[0060] In the embodiments of the present application, the first direction z, the second direction x, and the third direction y are perpendicular to each other. Additionally, when there is no ambiguity, the first direction z is sometimes referred to as the "depth direction", and the second direction x is referred to as the "horizontal direction". Further, for the convenience of description hereinafter, unless otherwise specified, the dimension in the first direction z is referred to as "depth", and the dimension in the second direction x is referred to as "length"; for the first direction z, the direction from the substrate 101 to the device silicon layer 201 is referred to as "up", the direction from the device silicon layer 201 to the substrate 101 is referred to as "down", the surface located in the "up" direction is called the "upper surface", and the surface located in the "down" direction is called the "lower surface".

[0061] In some embodiments, the substrate 101 may be formed of a semiconductor material, or may also be formed by a composite of multiple layers of materials, and the embodiments of the present application do not limit this. For example, the substrate 101 may be formed of single-crystalline silicon, for example, formed of high-resistivity silicon material, and the resistivity of the silicon material is, for example, greater than 1000 Ω·cm, for example, the resistivity > 5000 Ω·cm, and the embodiments of the present application do not limit this. For example, the substrate 101 may also be formed of materials such as lithium niobate, lithium tantalate, silicon carbide (SiC), sapphire, quartz, etc. Additionally, the substrate 101 may also be formed of semiconductor materials such as silicon dioxide, silicon nitride, polysilicon, amorphous silicon, etc., and the embodiments of the present application do not limit this.

[0062] The cavity 102 may be a single cavity or multiple sub-cavities, and its depth may be set according to the vibration amplitude of the resonator. For example, it is greater than 10 μm, greater than 25 μm, or greater than 50 μm.

[0063] The insulating layer 103 may be formed of silicon dioxide and can be used to realize the bonding between the device silicon layer 201 and the substrate 101. Additionally, the structure of the insulating layer 103 is not limited to Figure 1 the structure shown. According to different manufacturing processes, the portion of the insulating layer 103 located above the cavity 102 may also be removed.

[0064] The device silicon layer 201 may be formed of single-crystalline silicon or polysilicon. Additionally, the device silicon layer 201 may be pre-doped, and the doping concentration is, for example, 10 19 cm -3 or above.

[0065] The material of the piezoelectric layer 202 can be: aluminum nitride, doped aluminum nitride, zinc oxide, lead zirconate titanate piezoelectric ceramics (PZT), lithium niobate, lithium tantalate, etc. It can be single-crystal piezoelectric material or polycrystalline piezoelectric material. The doping element of doped aluminum nitride can be rare earth elements, such as scandium (Sc), yttrium (Y), etc.; the doping substance can also be II / XII group elements, such as calcium (Ca), magnesium (Mg), strontium (Sr), zinc (Zn), etc., or IV / V group elements, such as titanium (Ti), zirconium (Zr), hafnium (Hf), etc. The embodiments of the present application do not limit the specific material, and can be selected according to actual needs or performance requirements. For example, a material with a relatively large piezoelectric coupling coefficient corresponding to the lateral electric field excitation is selected. For example, single-crystal piezoelectric materials such as lithium niobate or lithium tantalate are selected. The embodiments of the present application can make lithium niobate or lithium tantalate have relatively large d11 (or e11), d15 (or e15), d16 (or e16) piezoelectric coupling coefficients by selecting a suitable cut type and the angle between the in-plane interdigital electrodes and the crystal axis. Thus, the resonator can respectively excite the zero-order symmetric Lamb Wave mode, abbreviated as the S0 mode, the first-order antisymmetric Lamb Wave mode, abbreviated as the A1 mode, the zero-order shear horizontal mode, abbreviated as the SH0 mode, and the higher-order or lower-order modes of the above modes.

[0066] The forming material of the electrode layer 203 can be metal. For example, elemental metals such as molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), gold (Au), titanium (Ti), chromium (Cr), etc., or their alloys or their composite laminates; the material of the electrode layer 203 can also be doped polysilicon, and the doping elements can be boron (B), phosphorus (P), arsenic (As), etc., and the doping concentration is, for example, 10 19 cm -3 Above, the higher the doping concentration, the lower the sheet resistance of the electrode made of polysilicon, and the lower the electrical loss, and the resistivity is generally lower than 1 mΩ·cm. Which material is selected to form the electrode layer 203 can be determined according to actual needs, and the embodiments of the present application do not limit this.

[0067] In addition, the planar structure of the piezoelectrically driven silicon-based MEMS resonator can have multiple types, and the corresponding electrode arrangement structures are also different. There can also be multiple vibration modes, such as in-plane flexural mode, out-of-plane flexural mode, width extensional mode (abbreviated as WE mode), length extensional mode (abbreviated as LE mode), Lamé mode, etc. The piezoelectric MEMS resonator according to the embodiments of the present application can be applicable to different vibration modes, and the embodiments of the present application do not limit this. In addition, the resonant frequencies that can be achieved by the resonator according to the embodiments of the present application can cover a range from more than a dozen kHz to several hundred MHz, and the embodiments of the present application do not limit this.

[0068] As Figure 1 shown, the region of the device silicon layer 201 corresponding to the cavity 102 contains multiple doping regions with different doping gradients in the first direction z, and the highest doping concentration of at least one of the multiple doping regions is 10 20 cm -3 or higher. For example, the device silicon layer 201 includes a doping region 303 (i.e., doping regions 303-1 and 303-2) and a doping region 304, and the doping concentrations of the doping region 303 and the doping region 304 are different. Or, it can also be said that the doping gradients of the doping region 303 and the doping region 304 are different, and the highest doping concentration of at least one of the doping region 303 and the doping region 304 is 10 20 cm -3 or higher.

[0069] In addition, in some embodiments, the region of the device silicon layer 201 corresponding to the cavity 102 can also contain multiple doping regions with the same doping gradient in the first direction z.

[0070] Figure 2 is a schematic diagram of the gradient distribution of the doping concentration along the Figure 1 A-A' cross-sectional line shown, Figure 3 is a schematic diagram of the gradient distribution of the doping concentration along the Figure 1 B-B' cross-sectional line shown, Figure 4 is a schematic diagram of the gradient distribution of the doping concentration along the Figure 1 C-C' cross-sectional line shown.

[0071] As Figure 2 and Figure 3As shown, the horizontal axis is the thickness (t), the zero point represents the position of the upper surface of the device silicon layer 201, T represents the total thickness of the device silicon layer 201, h1 and h2 respectively represent the depths of the two dopings, and at this position, the doping concentration reaches equilibrium with the doping concentration (N0_bot) of the device silicon layer 201 itself; the vertical axis represents the doping concentration (n), and N1_top and N2_top respectively represent the doping concentrations on the upper surface of the device silicon layer 201. The curve of the change in doping concentration from the upper surface of the device silicon layer 201 to the depth h1 is as Figure 2 shown, and the rate of decrease in its doping concentration gradually becomes smaller, but the way of change in the concentration gradient is not limited to this. For example, the doping concentration can also show a decrease approximately linearly with the increase in thickness. The laws of change in the doping concentration gradient formed during different doping processes can be the same or different.

[0072] As Figure 4 shown, the vertical axis is the doping concentration, the horizontal axis is the dimension in the horizontal direction x, the zero point represents a point outside the local doping, x1 and x2 respectively represent the two edges of the doping region 303-1 in the horizontal direction x, and x3 and x4 respectively represent the two edges of the doping region 304 in the horizontal direction x. N3_top and N4_top are respectively the doping concentrations on the C-C’ cross-sectional line of the doping region 303-1 and the doping region 304, and N3_top and N4_top are respectively less than N1_top and N2_top. In the horizontal direction, in the region outside the edge of the mask (such as silicon nitride), the doping concentration also shows a decreasing trend of change and finally reaches equilibrium with the doping concentration (N0_bot) of the device silicon layer 201 itself.

[0073] In the above example, the doping concentration N0_bot of the device silicon layer 201 itself is, for example, 10 19 cm -3 or more, and at least one of N1_top and N2_top is 10 20 cm -3 or more.

[0074] Thus, through local doping, the doping concentration of at least part of the region on the device silicon layer is 10 20 cm -3 or more, so that the equivalent resistivity of the device silicon layer in the effective region of the device is lower than 0.8 mΩ·cm, which is beneficial to improving the temperature compensation effect and further improving the frequency temperature stability of the resonator.

[0075] In some embodiments, a double-sided local doping process can be used to make the highest doping concentration of the device silicon layer 201 be 10 20 cm -3Above. Thus, the local doping concentration of the device silicon layer 201 is further increased, thereby further improving the temperature compensation effect. The double-sided local doping process will be described in detail in the following manufacturing method.

[0076] In some embodiments, the equivalent resistivity of the region of the device silicon layer 201 corresponding to the cavity 102 is less than 0.8 mΩ·cm.

[0077] In addition, as Figure 1 shown, the electrode layer 203 is a top electrode located on the upper side of the piezoelectric layer 202. However, the embodiments of the present application are not limited thereto, and the piezoelectric MEMS resonator 1 may further include a bottom electrode located on the lower side of the piezoelectric layer 202. In addition, as Figure 1 shown, the insulating layer 103 is located between the substrate 101 and the device silicon layer 201. However, the embodiments of the present application are not limited thereto, and the piezoelectric MEMS resonator 1 may further include a second insulating layer located between the bottom electrode and the device silicon layer. In addition, the piezoelectric MEMS resonator 1 may further include a passivation layer located on the upper side of the top electrode (such as Figure 1 the electrode layer 203 shown). In addition, the piezoelectric MEMS resonator 1 may further include a temperature compensation layer having a positive temperature coefficient and the like arranged in a stacked manner. The structure of the piezoelectric MEMS resonator 1 can be designed according to actual needs, and specific reference can be made to related technologies. The embodiments of the present application do not limit this.

[0078] As can be seen from the above embodiments, through local doping, the doping concentration of at least some regions on the device silicon layer is 10 20 cm -3 or more, so that the equivalent resistivity of the device silicon layer in the effective region of the device is less than 0.8 mΩ·cm, which is beneficial to improving the temperature compensation effect and further improving the frequency temperature stability of the resonator.

[0079] The embodiments of the present application also provide a semiconductor device including a piezoelectric MEMS resonator. Figure 5 is a schematic diagram of an embodiment of a semiconductor device including a piezoelectric MEMS resonator according to the embodiments of the present application.

[0080] As Figure 5 shown, the semiconductor device 5 includes a plurality of piezoelectric MEMS resonators. For example, it includes a piezoelectric MEMS resonator 51 and a piezoelectric MEMS resonator 52. The semiconductor device 5 may include any number of piezoelectric MEMS resonators. The embodiments of the present application do not limit the number of piezoelectric MEMS resonators it includes. Hereinafter, an example of including 2 piezoelectric MEMS resonators will be described, and the case of including other numbers of piezoelectric MEMS resonators can be inferred by analogy.

[0081] As Figure 5As shown, each piezoelectric MEMS resonator includes a substrate 101, an insulating layer 103, a device silicon layer 201, a piezoelectric layer 202, and an electrode layer 203 stacked in the first direction z. A cavity 102 is provided on the upper side of the substrate 10 (i.e., the cavity 102-1 of the piezoelectric MEMS resonator 51 and the cavity 102-2 of the piezoelectric MEMS resonator 52). The structures of the piezoelectric MEMS resonator 51 and the piezoelectric MEMS resonator 52 are similar to the structure of the piezoelectric MEMS resonator 1 shown in Figure 1 The specific implementation can refer to the above embodiments and will not be described one by one here.

[0082] As Figure 5 shown, a doped region 306 is included in the region of the device silicon layer 201 of the piezoelectric MEMS resonator 51 corresponding to the cavity 102-1. The doped region 306 can be the entire region of the device silicon layer 201 corresponding to the cavity 102-1 or a partial region of the device silicon layer 201 corresponding to the cavity 102-1; a doped region 307 is included in the region of the device silicon layer 201 of the piezoelectric MEMS resonator 52 corresponding to the cavity 102-2. The doped region 307 can be the entire region of the device silicon layer 201 corresponding to the cavity 102-2 or a partial region of the device silicon layer 201 corresponding to the cavity 102-2.

[0083] In some embodiments, the doping concentration of the doped region 306 and the doped region 307 in the first direction z is different, and / or the doping elements in the doped region 306 and the doped region 307 are different, and / or the distributions of the doped region 306 and the doped region 307 are different, and / or the equivalent resistivity of the doped region 306 and the doped region 307 is different. In addition, the different distributions of the doped region 306 and the doped region 307 can be that the position of the doped region 306 relative to the cavity 102-1 is different from the position of the doped region 307 relative to the cavity 102-2, or the area size or shape of the doped region 306 and the doped region 307 in the horizontal direction is different.

[0084] Thus, by obtaining a resonator combination with different temperature coefficients on a single wafer, an integration of piezoelectric silicon-based resonators with different temperature coefficients can be obtained on a single chip at low processing cost.

[0085] In some embodiments, the highest doping concentration of at least one of the doped region 306 and the doped region 307 is 10 20 cm -3 or more.

[0086] In some embodiments, the equivalent resistivity of the region of the device silicon layer 201 corresponding to the cavity 102-1 and / or the cavity 102-2 is less than 0.8 mΩ·cm.

[0087] Thus, it is beneficial to improve the temperature compensation effect and further enhance the frequency temperature stability of the resonator.

[0088] In some embodiments, at least two piezoelectric MEMS resonators operate in the same vibration mode. For example, piezoelectric MEMS resonator 51 and piezoelectric MEMS resonator 52 can operate in the same vibration mode. Additionally, not all of the multiple piezoelectric MEMS resonators of semiconductor device 5 need to operate in the same vibration mode. That is to say, at least two of the multiple piezoelectric MEMS resonators can operate in different vibration modes.

[0089] Furthermore, in some embodiments, multiple doped regions are included in the region of the device silicon layer of at least one piezoelectric MEMS resonator corresponding to the cavity. For example, for piezoelectric MEMS resonator 51, multiple doped regions can be included in the region of device silicon layer 201 corresponding to cavity 102-1. For example, the structure of piezoelectric MEMS resonator 51 can be similar to Figure 1 the structure of piezoelectric MEMS resonator 1 shown. Additionally, the doping concentrations or doping concentration gradients of the multiple doped regions of piezoelectric MEMS resonator 51 can be the same or different.

[0090] Figure 6 and Figure 7 are schematic diagrams of another embodiment of a semiconductor device including a piezoelectric MEMS resonator according to an embodiment of the present application.

[0091] Figure 6 The difference between semiconductor device 6 shown and Figure 5 semiconductor device 5 shown is that each resonator further has a trench H penetrating through insulating layer 103, device silicon layer 201, piezoelectric layer 202, and electrode layer 203. Figure 7 The difference between semiconductor device 7 shown and Figure 6 semiconductor device 6 shown is that the electrode layer 203 of each resonator of semiconductor device 6 only includes a top electrode located on the upper side of piezoelectric layer 202, while the electrode layer of each resonator of semiconductor device 7 includes a top electrode 203 and a bottom electrode 204 located on the upper and lower sides of piezoelectric layer 202. The materials of top electrode 203 and bottom electrode 204 can be the same or different, and the specific implementation can refer to electrode layer 203 of piezoelectric MEMS resonator 1.

[0092] In some embodiments, the insulating layer of each resonator can include insulating layer 103 (i.e., the first insulating layer) between substrate 101 and device silicon layer 201, and can also include a second insulating layer located between bottom electrode 204 and device silicon layer 201 ( Figures 5 to 7(not marked in the figure), the material of the second insulating layer is, for example, silicon dioxide, doped silicon dioxide, silicon oxynitride, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, tantalum pentoxide, etc., and can be a single layer or a combination of multiple different dielectric materials. At this time, the bottom electrode 204 is insulated from the device silicon layer 201. Therefore, the bottom electrode layer can be patterned into multiple electrode shapes to connect electrical signals of different polarities.

[0093] In addition, each piezoelectric MEMS resonator may further include a passivation layer located on the upper side of the top electrode 203 ( Figures 5 to 7 (not marked in the figure). The material of the passivation layer is, for example, silicon dioxide, doped silicon dioxide, silicon oxynitride, silicon nitride, aluminum oxide, aluminum nitride, etc., and can be a single layer or a combination of multiple different dielectric materials to protect the electrode from oxidation.

[0094] Moreover, by doping the device silicon layers of multiple resonators with different concentrations, it is possible to integrate piezoelectric silicon-based resonators with different temperature coefficients on a single chip while keeping the thicknesses of the layers other than the device silicon layer (such as the piezoelectric layer, top electrode, passivation layer, etc.) located above the device silicon layer consistent, thereby reducing the processing steps and difficulty and lowering the processing cost.

[0095] In some embodiments, at least one piezoelectric MEMS resonator among multiple piezoelectric MEMS resonators may further include a temperature compensation layer arranged in a stacked manner. The temperature compensation layer can be located between any two layers or at the topmost layer. The material of the temperature compensation layer can be silicon dioxide or a doped silicon dioxide layer (the doping element can be at least one of fluorine, hydrogen, methyl, methylene, chlorine, carbon, nitrogen, phosphorus, sulfur), so as to further achieve temperature compensation. Additionally, optionally, the temperature compensation layer can be located at the topmost layer of the piezoelectric MEMS resonator, thereby further simplifying the processing technology.

[0096] In addition, the thicknesses of the temperature compensation layers of multiple piezoelectric MEMS resonators can be the same or different, and the temperature compensation layers of multiple piezoelectric MEMS resonators can be the same doping element or different doping elements.

[0097] In some embodiments, the thicknesses of the top electrodes of at least two piezoelectric MEMS resonators can be the same or different; the thicknesses of the bottom electrodes of at least two piezoelectric MEMS resonators can be the same or different; the thicknesses of the passivation layers of at least two piezoelectric MEMS resonators can be the same or different; the thicknesses of the temperature compensation layers of at least two piezoelectric MEMS resonators can be the same or different.

[0098] In some embodiments, the first-order frequency temperature coefficient of at least two piezoelectric MEMS resonators can be different, and / or the second-order frequency temperature coefficient can be different, and / or the third-order frequency temperature coefficient can be different.

[0099] In the embodiments of the present application, the characteristic curve of the frequency change rate of the piezoelectric MEMS resonator with respect to temperature can exhibit a linear relationship, a quadratic polynomial function relationship, and a cubic polynomial function relationship within a certain temperature range (e.g., -40°C to 85°C, -55°C to 125°C). Generally, a higher-order polynomial is used to define the relationship between the frequency change rate and temperature. For example, the relationship between the frequency change rate and temperature can be generally defined by a cubic polynomial function:

[0100]

[0101] where α is called the first-order temperature coefficient, β is called the second-order temperature coefficient, γ is called the third-order temperature coefficient, and the temperature coefficient can be positive, negative, or 0.

[0102] By locally doping the device silicon layer, the first-order temperature coefficient of a single resonator can be made 0 or close to 0, or the first-order and second-order temperature coefficients of a single resonator can both be made 0 or close to 0, so that the piezoelectrically driven silicon-based MEMS resonator has good frequency temperature stability within the operating temperature range (e.g., -40°C to 85°C, or even -55°C to 125°C), for example, less than ±10 ppm, less than ±1 ppm, less than ±0.1 ppm.

[0103] For a semiconductor device having multiple resonators, by doping the device silicon layer of at least two piezoelectric MEMS resonators among the multiple resonators with different concentration gradients, and / or different distributions, and / or different elements, and by adjusting the top electrode thickness, and / or bottom electrode thickness, and / or passivation layer thickness, and / or temperature compensation layer thickness of at least two piezoelectric MEMS resonators to be different, the types of frequency-temperature characteristic curves and / or temperature coefficients of at least two resonators can be made different, that is, the first-order frequency temperature coefficients of at least two piezoelectric MEMS resonators are different, and / or the second-order frequency temperature coefficients are different, and / or the third-order frequency temperature coefficients are different. For example: within a specific temperature range, the frequency-temperature characteristic curve of one resonator exhibits a linear relationship, and the other exhibits a quadratic polynomial function relationship (parabolic); or both resonators exhibit a quadratic polynomial function relationship, but the temperature coefficients are different.

[0104] One application scenario of the semiconductor device according to the embodiments of the present application is that for a semiconductor device having resonators with multiple different frequency-temperature characteristics, one of the resonators can be used as a temperature sensor, so as to perform temperature compensation on the output signal of an oscillator composed of another resonator, forming a temperature-compensated oscillator (TCXO), thereby further reducing the frequency-temperature drift amount of the oscillator output signal.

[0105] As can be seen from the above embodiments, by obtaining a combination of resonators with different temperature coefficients on a single wafer, an integration of piezoelectric silicon-based resonators with different temperature coefficients can be obtained on a single chip at a low processing cost.

[0106] The embodiments of the present application also provide a manufacturing method for a piezoelectric MEMS resonator. Figure 8 It is a schematic diagram of the manufacturing method for the piezoelectric MEMS resonator according to the embodiments of the present application.

[0107] As Figure 8 shown, the manufacturing method includes:

[0108] 801: Perform a first doping operation;

[0109] 802: Perform a second doping operation.

[0110] It should be noted that the above Figure 8 only schematically illustrates the embodiments of the present application, but the present application is not limited thereto. For example, the execution order between each operation can be appropriately adjusted. In addition, some other operations can be added or some of the operations can be reduced. Those skilled in the art can make appropriate modifications according to the above content, not limited to the records of the above Figure 8 .

[0111] For the convenience of description, the manufacturing method for the piezoelectric MEMS resonator according to the embodiments of the present application will be described below by taking the piezoelectric MEMS resonator 1 shown in Figure 1 as an example, but the embodiments of the present application are not limited thereto. The manufacturing method for the piezoelectric MEMS resonator according to the embodiments of the present application can also be used to manufacture piezoelectric MEMS resonators with other structures.

[0112] Figures 9 to 12 It is a schematic diagram for explaining the first doping operation of the manufacturing method for the piezoelectric MEMS resonator according to the embodiments of the present application. The following will be combined with Figures 9 to 14 to explain the first doping operation.

[0113] The first doping operation according to the embodiments of the present application includes:

[0114] As Figure 9As shown, a patterned first hard mask 301-1 is formed on the upper surface of the device silicon layer 201 away from the substrate 101, and the etching position (hollowed-out area) of the first hard mask 301-1 at least partially coincides with the area of the device silicon layer 201 corresponding to the cavity 102;

[0115] As Figure 10 shown, a first thin film 302-1 containing a doping element is grown on the side of the first hard mask 301-1;

[0116] As Figure 11 shown, the doping element in the first thin film 302-1 is diffused into the device silicon layer 201 by heating, so that the highest doping concentration of the device silicon layer 201 is 10 20 cm -3 or more;

[0117] As Figure 12 shown, the first thin film 302-1 and the first hard mask 301-1 are removed.

[0118] In some embodiments, the first hard mask 301-1 is, for example, a silicon nitride thin film, but the embodiments of the present application do not limit this, and the first hard mask 301-1 can also be formed of other materials. In addition, the embodiments of the present application do not limit the patterning process, and related technologies can be referred to.

[0119] In addition, the device silicon layer 201 of the present application can be the top silicon layer of a prefabricated CSOI (SOI substrate with a preset cavity). In addition, the device silicon layer 201 can also be a pre-doped silicon layer. For example, the pre-doping concentration of the device silicon layer 201 is 10 19 cm -3 or more, or the initial (i.e., before the first doping operation) equivalent resistivity of the device silicon layer 201 is greater than 0.8 mΩ·cm. The embodiments of the present application do not limit this.

[0120] In some embodiments, the first thin film 302-1 containing a doping element is, for example, phosphosilicate glass 302 (PSG), and a PSG thin film is generally deposited at a high temperature of 900°C to 1100°C. Due to the presence of the patterned first hard mask 301-1 (such as a silicon nitride layer), the first thin film 302-1 only contacts the device silicon layer 201 at the positions etched open by the first hard mask 301-1. For example, after depositing the PSG thin film, the phosphorus element in the PSG thin film is further diffused into the device silicon layer 201 by a thermal driving method. The temperature of the thermal driving is generally 900°C to 1100°C, and the driving time is determined by the required diffusion depth. The longer the time, the greater the diffusion depth. Generally, the driving time is more than 1 hour, as Figure 11As shown, at the edge of the silicon nitride mask, phosphorus not only diffuses along the thickness direction, but also diffuses approximately isotropically along the other directions, forming doping regions 303-1 and 303-2. The highest doping concentration of the doping regions 303-1 and 303-2 is 10 20 cm -3 or higher. The growth of PSG and the thermal driving operation can be carried out in a POCl3-based furnace tube.

[0121] In some embodiments, the first thin film 302-1 and the first hard mask 301-1 can be removed by wet etching. For example, the first thin film 302-1 can be removed using a hydrofluoric acid (HF) solution or a buffer solution containing HF acid, and the first hard mask 301-1 can be removed using hot phosphoric acid. After that, annealing is carried out again at a temperature of 1000°C to 1300°C, so that the phosphorus element on the upper surface of the device silicon layer 201 further diffuses to the bottom of the device silicon layer 201. The concentration distribution gradient of the phosphorus element in the thickness direction can be controlled by controlling the annealing temperature and time. At this time, a rapid annealing method can also be used. By controlling the heating, cooling time and temperature of the rapid annealing, as well as the cycle period, the concentration distribution gradient of the phosphorus element in the thickness direction can also be achieved. In addition, the first thin film 302-1 can be removed first, while the first hard mask 301-1 layer is retained. After the annealing treatment, the first hard mask 301-1 is removed. As Figure 12 shown, doping regions 303-1 and 303-2 are formed on the upper surface of the device silicon layer 201.

[0122] In some embodiments, the first doping operation can be repeatedly executed to form multiple regions with different doping concentrations or doping gradients or equivalent resistivities.

[0123] Figure 13 and Figure 14 are schematic diagrams for explaining the repeated execution of the first doping operation.

[0124] As Figure 13 shown, a patterned first hard mask 301-2 is formed again on the upper surface of the device silicon layer 201 in the state shown in Figure 12 . The etching position (or the hollowed-out position) of the current first hard mask 301-2 can be different from the etching position of the previous first hard mask 301-1 (i.e., the etching position shown in Figure 9 ). That is, the two can be completely non-overlapping or partially overlapping. Then, a first thin film 302-2 containing a doping element is grown on the side of the first hard mask 301-2, so that the doping element in the first thin film 302-2 diffuses into the device silicon layer 201. As Figure 14 shown, the first thin film 302-2 and the first hard mask 301-2 are removed, and a doping region 304 is formed on the upper surface of the device silicon layer 201.

[0125] In addition, as Figure 14 shown, the doping depth of the doping region 304 is smaller than that of the doping regions 303-1 and 303-2. However, the embodiments of the present application are not limited thereto, and the doping depth of each doping region can be set as needed, and the embodiments of the present application do not limit this.

[0126] In addition, when it is necessary to form different doping gradients at more different positions, the above steps can be continued to be repeated.

[0127] In some embodiments, a double-sided local doping process can also be used to dope the upper and lower surfaces of the device silicon layer 201.

[0128] Figures 15 to 18 is a schematic diagram for explaining the double-sided local doping process of the embodiments of the present application.

[0129] For example, as Figure 8 shown, the second doping operation of step 802 can be performed before the first doping operation of step 801. The second doping operation is to dope the lower surface of the device silicon layer 201. The doping process is similar to that of the first doping operation, that is, a patterned second hard mask is formed on the lower surface of the device silicon layer 201. In the region of the device silicon layer 201 corresponding to the cavity, the hollowed-out region of the second hard mask at least partially coincides with the hollowed-out region of the first hard mask; a second thin film containing a doping element is grown on the side of the second hard mask; the doping element in the second thin film is diffused into the device silicon layer 201; the second thin film and the second hard mask are removed. In addition, the second doping operation can also be repeated to form Figure 15 the three doping regions 303-11, 303-22, and 304-1 shown. For example, the doping concentration or doping gradient or doping depth of the doping region 304-1 is different from that of the doping regions 303-11 and 303-22.

[0130] In some embodiments, before performing the second doping operation of step 802, the device silicon layer 201 can be connected to the second substrate, and the lower surface of the device silicon layer 201 is on the outermost side. For example, the upper surface of the device silicon layer 201 can be bonded to the second substrate; between the second doping operation and the first doping operation, the lower surface of the device silicon layer 201 can be bonded to the upper surface of the substrate 101 (i.e., the first substrate) through an insulating layer (such as Figure 1 the insulating layer 103 shown, and the insulating layer 103 can also be referred to as the "first insulating layer"), and the second substrate can be thinned and / or etched to form the upper surface of the device silicon layer 201.

[0131] For example, in the second doping operation, an SOI substrate can be used to replace the device silicon layer 201 for doping. For example, asFigure 16 As shown, the SOI substrate includes a first layer 201-1 (top silicon layer), a second layer 201-2 (buried oxide layer), and a third layer 201-3 (support layer). The second layer 201-2 and the third layer 201-3 can be referred to as the "second substrate". At this time, the thickness of the first layer 201-1 can be consistent with the thickness of the device layer in the CSOI substrate. In the embodiments of the present application, when the thickness of the device layer is less than 20 um, the CSOI can be formed by transferring the top silicon layer of the SOI. When the thickness of the device layer is greater than or equal to 20 um, the CSOI can be formed by bonding a common silicon substrate and then thinning and polishing. The following will be described separately.

[0132] When forming the CSOI by bonding a common silicon substrate and then thinning and polishing, as Figure 17 shown, in the state shown in Figure 15 an insulating layer 103 (such as a silicon dioxide layer) is formed on the lower surface of the device silicon layer 201, and is bonded to another substrate 101 that has been processed with a cavity structure (i.e., the cavity 102 shown in Figure 17 ), and then the device silicon layer 201 is thinned and polished to form a CSOI substrate. In addition, in the above example, the insulating layer 103 can also be formed on one side of the substrate 101, and then bonded to the lower surface of the device silicon layer 201, and then the device silicon layer 201 is thinned and polished to form a CSOI substrate.

[0133] When forming the CSOI by transferring the top silicon layer of the SOI, as Figure 17 shown, in the state shown in Figure 16 an insulating layer 103 is formed on the lower surface of the first layer 201-1 and is bonded to another substrate 101 that has been processed with a cavity structure (i.e., the cavity 102 shown in Figure 17 ), the support layer (i.e., the third layer 201-3) and the buried oxide layer (i.e., the second layer 201-2) in the SOI substrate are removed, so as to expose the upper surface of the device silicon layer, that is, the top silicon layer (i.e., the first layer 201-1) is left as the device silicon layer 201 of the CSOI substrate.

[0134] In addition, the insulating layer 103 can be formed on one side of the substrate 101. Additionally, the insulating layer 103 can be formed on the substrate 101 first, and then the cavity 102 is formed, so that there is no insulating layer 103 in the corresponding part of the cavity 102.

[0135] In addition, the manufacturing method can further include: forming a piezoelectric layer on the upper surface of the device silicon layer, and / or forming a top electrode on the upper side of the piezoelectric layer, and / or forming a bottom electrode on the lower side of the piezoelectric layer, and / or forming a passivation layer on the upper side of the top electrode, and / or forming a second insulating layer between the bottom electrode and the device silicon layer.

[0136] As Figure 18As shown, local doping is performed again on the upper surface of the device silicon layer 201 of CSOI, such as performing the first doping operation described in the above embodiment, so that doping is performed on both the upper and lower surfaces of the device silicon layer 201, that is, double-sided local doping is achieved.

[0137] In some embodiments, the sum of the depths of at least a part of the regions doped from the upper surface of the device silicon layer and the depths of at least a part of the regions doped from the lower surface of the device silicon layer is greater than or equal to the thickness of the device silicon layer. That is to say, the doping regions on the upper and lower surfaces can be fused with each other. For example, the bottom of the doping region 303-22 is in contact with the bottom of the doping region 303-2, and the bottom of the doping region 303-11 is in contact with the bottom of the doping region 303-1.

[0138] In some embodiments, the sum of the depths of at least a part of the regions doped from the upper surface of the device silicon layer and the depths of at least a part of the regions doped from the lower surface of the device silicon layer is less than the thickness of the device silicon layer. That is to say, the doping regions on the upper and lower surfaces may not be in contact with each other. For example, the bottoms of the doping regions 304-1 and 304-2 are not in contact.

[0139] In addition, in the two doping operations performed on the two surfaces of the device silicon layer 201, the doping regions in the two doping operations may completely overlap or only partially overlap; in addition, the doping concentrations and gradients in the two doping operations may be the same or different. In addition, if there is an overlap in the doping regions during the two doping operations above and below, the second doping will further increase the doping concentration in a part of the thickness at the bottom of the previous doping.

[0140] As can be seen from the above embodiments, through local doping, the doping concentration of at least a part of the regions on the device silicon layer is above 10 20 cm -3 or more, so that the equivalent resistivity of the device silicon layer in the effective region of the device is lower than 0.8 mΩ·cm, which is beneficial to improving the temperature compensation effect and further improving the frequency temperature stability of the resonator.

[0141] The embodiments of the present application further provide a manufacturing method of a semiconductor device including a piezoelectric MEMS resonator. Figure 19 It is a schematic diagram of the manufacturing method of the semiconductor device including a piezoelectric MEMS resonator according to the embodiments of the present application.

[0142] As Figure 19 shown, the manufacturing method includes:

[0143] 1901: Perform a third doping operation;

[0144] 1902: Perform a fourth doping operation.

[0145] It should be noted that the above appendix Figure 19 only schematically illustrates the embodiments of the present application, but the present application is not limited thereto. For example, the execution order between various operations can be appropriately adjusted. For example, operation 1901 and operation 1902 can be interchanged. In addition, some other operations can be added or some of the operations can be reduced. For example, it can only include operation 1901 or only include operation 1902. Those skilled in the art can make appropriate modifications according to the above content, not limited to the records in the above appendix Figure 19 .

[0146] For the convenience of description, the manufacturing method of the semiconductor device in the embodiments of the present application will be described below by taking the semiconductor device 5 shown in Figure 5 as an example. However, the embodiments of the present application are not limited thereto. The manufacturing method of the semiconductor device in the embodiments of the present application can also be used to manufacture other semiconductor devices including piezoelectric MEMS resonators.

[0147] Figures 20 to 22 is a schematic diagram for explaining the manufacturing method of the semiconductor device including a piezoelectric MEMS resonator in the embodiments of the present application. Among them, Figure 20 is an explanation of the third doping operation, Figure 21 is an explanation of the fourth doping operation.

[0148] In the embodiments of the present application, the third doping operation is similar to the first doping operation described in the above embodiments. Similar steps can refer to the description of the first doping operation in the above embodiments and will not be repeated here.

[0149] As Figure 20 shown, the third doping operation may include:

[0150] Form a patterned third hard mask 301-3 on the upper surface of the device silicon layer 201. The hollowed-out area of the third hard mask 301-3 at least partially coincides with the area of the device silicon layer 201 corresponding to at least one piezoelectric MEMS resonator (such as the piezoelectric MEMS resonator 51) and corresponding to the cavity (such as the cavity 102-1);

[0151] Grow a third thin film 302-3 containing doping elements on the side of the third hard mask 301-3;

[0152] Diffuse the doping elements in the third thin film 302-3 into the device silicon layer 201 of at least one piezoelectric MEMS resonator (such as the piezoelectric MEMS resonator 51) by heating. For example, as Figure 21 shown, a doped area 306 is formed in the device silicon layer 201 of the piezoelectric MEMS resonator 51;

[0153] Remove the third thin film 302-3 and the third hard mask 301-3.

[0154] Thus, local doping is performed in at least one piezoelectric MEMS resonator through the third doping operation.

[0155] In addition, similar to the first doping operation, the third doping operation can be repeated to achieve further doping of the at least one piezoelectric MEMS resonator. For the specific implementation manner, reference can be made to the description of the first doping operation above.

[0156] In the embodiments of the present application, as Figure 19 shown, the manufacturing method may further include a fourth doping operation. The fourth doping operation may be an operation similar to the third doping operation to achieve doping in different resonators, or may be an operation similar to the second doping operation to achieve double-sided doping of the device silicon layer. The following will be described separately.

[0157] As Figure 21 shown, doping in different resonators can be achieved through the fourth doping operation. For example, the fourth doping operation may include:

[0158] Form a patterned fourth hard mask 301-4 on the upper surface of the device silicon layer 201, and the hollowed-out area of the fourth hard mask 301-4 at least partially coincides with the area of the device silicon layer 201 of at least one piezoelectric MEMS resonator (such as the piezoelectric MEMS resonator 52) corresponding to the cavity (such as the cavity 102-2);

[0159] Grow a fourth thin film 302-4 containing doping elements on the side of the fourth hard mask 301-4;

[0160] Diffuse the doping elements in the fourth thin film 302-4 into the device silicon layer 201 of at least one piezoelectric MEMS resonator (such as the piezoelectric MEMS resonator 52). For example, as Figure 22 shown, a doped region 307 is formed in the device silicon layer 201 of the piezoelectric MEMS resonator 52;

[0161] Remove the fourth thin film 302-4 and the fourth hard mask 301-4.

[0162] In the embodiments of the present application, at least one piezoelectric MEMS resonator among the piezoelectric MEMS resonators doped in the fourth doping operation is different from at least one piezoelectric MEMS resonator among the piezoelectric MEMS resonators doped in the third doping operation.

[0163] For example, in the above example, in the fourth doping operation, only the device silicon layer 201 of the piezoelectric MEMS resonator 52 can be doped, or the device silicon layers 201 of both the piezoelectric MEMS resonator 51 and the piezoelectric MEMS resonator 52 can be doped. Additionally, if in the fourth doping operation, the device silicon layers 201 of both the piezoelectric MEMS resonator 51 and the piezoelectric MEMS resonator 52 are doped, the doping region for doping the piezoelectric MEMS resonator 51 can at least partially overlap with the doping region in the third doping operation, or may not overlap.

[0164] In at least one embodiment, the doping concentration of the device silicon layer of the piezoelectric MEMS resonator doped in the third doping operation is different from the doping concentration of the device silicon layer of the piezoelectric MEMS resonator doped in the fourth doping operation, and / or,

[0165] the doping element of the device silicon layer of the piezoelectric MEMS resonator doped in the third doping operation is different from the doping element of the device silicon layer of the piezoelectric MEMS resonator doped in the fourth doping operation, and / or,

[0166] the distribution of the doping regions included in the region corresponding to the cavity of the device silicon layer of the piezoelectric MEMS resonator doped in the third doping operation is different from the distribution of the doping regions included in the region corresponding to the cavity of the device silicon layer of the piezoelectric MEMS resonator doped in the fourth doping operation, and / or,

[0167] the equivalent resistivity of the region corresponding to the cavity of the device silicon layer of the piezoelectric MEMS resonator doped in the third doping operation is different from the equivalent resistivity of the region corresponding to the cavity of the device silicon layer of the piezoelectric MEMS resonator doped in the fourth doping operation.

[0168] For example, the doping concentration or doping gradient or doping depth of the doping region 306 and the doping region 307 are different. Additionally, the doping elements of the doping region 306 and the doping region 307 can also be different, for example, any two of fluorine, hydrogen, methyl, methylene, chlorine, carbon, nitrogen, phosphorus, sulfur, etc. Additionally, the position of the doping region 306 relative to the cavity 102-1 is different from the position of the doping region 307 relative to the cavity 102-2, or it can also be that the area size or shape of the doping region 306 and the doping region 307 in the horizontal direction are different. Additionally, the equivalent resistivity of the doping region 306 and the doping region 307 can be different.

[0169] Additionally, the fourth doping operation can also be like the second doping operation and be performed before the third doping operation, so as to achieve double-sided doping of the device silicon layer of the semiconductor device. For example, the fourth doping operation can include:

[0170] A patterned fourth hard mask is formed on the lower surface of the device silicon layer of multiple piezoelectric MEMS resonators, and the hollowed-out area of the fourth hard mask at least partially coincides with the area of the device silicon layer of at least one piezoelectric MEMS resonator corresponding to the cavity;

[0171] A fourth thin film containing a doping element is grown on the side of the fourth hard mask;

[0172] The doping element in the fourth thin film is diffused into the device silicon layer of the at least one piezoelectric MEMS resonator by heating;

[0173] The fourth thin film and the fourth hard mask are removed,

[0174] Wherein, at least one piezoelectric MEMS resonator among the piezoelectric MEMS resonators doped in the fourth doping operation is the same piezoelectric MEMS resonator as at least one piezoelectric MEMS resonator among the piezoelectric MEMS resonators doped in the third doping operation.

[0175] In some embodiments, the third doping operation can be repeatedly executed, and the fourth doping operation can also be repeatedly executed, so as to achieve doping in the areas of the device silicon layers of at least two piezoelectric MEMS resonators corresponding to the cavities. For example, by repeatedly executing the third doping operation or the fourth doping operation, multiple regions with different doping concentration gradients are formed on the upper surface of the device silicon layer. Alternatively, by repeatedly executing the third doping operation and the fourth doping operation, double-sided doping of the device silicon layers of multiple piezoelectric MEMS resonators can be performed, or multiple double-sided doped regions can be formed in the device silicon layer of at least one piezoelectric MEMS resonator. Whether to repeatedly execute and the number of repeated executions can be set according to actual needs, and the embodiments of the present application do not limit this.

[0176] In at least one embodiment, the manufacturing method may further include forming Figure 7 The top electrode 203, bottom electrode 204, insulating layer 103, etc. shown. For example, a first insulating layer is formed between the substrate and the device silicon layer; a top electrode is formed on the upper side of the piezoelectric layer, and / or a bottom electrode is formed on the lower side of the piezoelectric layer; a passivation layer is formed on the upper side of the top electrode, and / or a second insulating layer is formed between the bottom electrode and the device silicon layer.

[0177] The manufacturing method of the semiconductor device according to the embodiments of the present application has been described above by taking a semiconductor device including two piezoelectric MEMS resonators as an example, but the embodiments of the present application are not limited thereto. The manufacturing method of the semiconductor device according to the embodiments of the present application can be applied to semiconductor devices including any number of piezoelectric MEMS resonators, and its implementation manner is similar to that of a semiconductor device including two piezoelectric MEMS resonators, and will not be described in detail here.

[0178] As can be seen from the above embodiments, by obtaining a combination of resonators with different temperature coefficients on a single wafer, an integration of piezoelectric silicon-based resonators with different temperature coefficients can be achieved on a single chip at a low processing cost.

[0179] An embodiment of the present application also provides an electronic component, which includes the piezoelectric MEMS resonator described in the foregoing embodiment. Since the structure and characteristics of the piezoelectric MEMS resonator have been described in detail in the above embodiment, the content is incorporated herein and the description is omitted here.

[0180] An embodiment of the present application also provides an electronic component, which includes the semiconductor device including the piezoelectric MEMS resonator described in the foregoing embodiment. Since the structure and characteristics of the semiconductor device have been described in detail in the above embodiment, the content is incorporated herein and the description is omitted here.

[0181] The electronic component of the embodiment of the present application is, for example, a sensor based on a piezoelectric MEMS resonator, such as an accelerometer, a gyroscope, an accelerometer, a pressure sensor, a micromirror, a piezoelectric transducer, etc. The embodiment of the present application does not limit this.

[0182] The specific embodiments described above further elaborate on the purpose, technical solution, and beneficial effects of the present application. It should be understood that the above are only specific embodiments of the present application and are not used to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A semiconductor device comprising a piezoelectric MEMS resonator, the semiconductor device including a plurality of piezoelectric MEMS resonators, each piezoelectric MEMS resonator including a substrate, an insulating layer, a device silicon layer, a piezoelectric layer, and an electrode layer stacked in a first direction, a cavity being provided on an upper side of the substrate, characterized in that, the plurality of piezoelectric MEMS resonators are located on the same substrate, at least a portion of a region of the device silicon layer of at least two piezoelectric MEMS resonators corresponding to the cavity has a different doping concentration in the first direction, and / or, at least a portion of a region of the device silicon layer of at least two piezoelectric MEMS resonators corresponding to the cavity has different doping elements, and / or, the distribution of doping regions included in a region of the device silicon layer of at least two piezoelectric MEMS resonators corresponding to the cavity is different, and / or, the equivalent resistivity of a region of the device silicon layer of at least two piezoelectric MEMS resonators corresponding to the cavity is different.

2. The semiconductor device according to claim 1, characterized in that, a double-sided local doping process is used to make at least a portion of a region of the device silicon layer of at least two piezoelectric MEMS resonators corresponding to the cavity have a different doping concentration in the first direction, and / or, to make at least a portion of a region of the device silicon layer of at least two piezoelectric MEMS resonators corresponding to the cavity have different doping elements.

3. The semiconductor device according to claim 1, characterized in that, The highest doping concentration of the device silicon layer of at least one of the at least two piezoelectric MEMS resonators is 10 20 cm -3 or higher.

4. The semiconductor device according to claim 1, characterized in that, the equivalent resistivity of a region of the device silicon layer of at least one piezoelectric MEMS resonator corresponding to the cavity is less than 0.8 mΩ·cm.

5. The semiconductor device according to claim 1, characterized in that, at least two piezoelectric MEMS resonators operate in the same vibration mode.

6. The semiconductor device according to claim 1, characterized in that, a region of the device silicon layer of at least one piezoelectric MEMS resonator corresponding to the cavity includes a plurality of doping regions.

7. The semiconductor device according to claim 1, wherein, The electrode layer includes a top electrode located on an upper side of the piezoelectric layer; and / or The electrode layer further includes a bottom electrode located on a lower side of the piezoelectric layer; and / or The electrode layer further includes a bottom electrode located on a lower side of the piezoelectric layer, the insulating layer including a first insulating layer between the substrate and the device silicon layer and a second insulating layer between the bottom electrode and the device silicon layer; and / or The electrode layer includes a top electrode located on an upper side of the piezoelectric layer, and each piezoelectric MEMS resonator further includes a passivation layer located on an upper side of the top electrode; and / or At least one piezoelectric MEMS resonator among the plurality of piezoelectric MEMS resonators further includes a temperature compensation layer with a positive temperature coefficient stacked thereon.

8. The semiconductor device according to claim 7, wherein, The thicknesses of the top electrodes of at least two piezoelectric MEMS resonators are different, and / or the thicknesses of the bottom electrodes are different, and / or the thicknesses of the passivation layers are different, and / or the thicknesses of the temperature compensation layers are different.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The first-order frequency temperature coefficients of at least two piezoelectric MEMS resonators are different, and / or the second-order frequency temperature coefficients are different, and / or the third-order frequency temperature coefficients are different.

10. A piezoelectric MEMS resonator, the piezoelectric MEMS resonator includes a substrate, an insulating layer, a device silicon layer, a piezoelectric layer, and an electrode layer stacked in a first direction, a cavity is provided on the upper side of the substrate, and it is characterized in that The region of the device silicon layer corresponding to the cavity contains a plurality of doped regions with different doping gradients in the first direction, and the highest doping concentration of at least one of the plurality of doped regions is 10 20 cm -3 or more.

11. The piezoelectric MEMS resonator according to claim 10, wherein The highest doping concentration of the silicon layer of the device is 10 20 cm -3 or above by using a double-sided local doping process.

12. The piezoelectric MEMS resonator according to claim 10, characterized in that The equivalent resistivity of the region of the device silicon layer corresponding to the cavity is lower than 0.8 mΩ·cm.

13. The piezoelectric MEMS resonator according to claim 10, characterized in that The region of the device silicon layer corresponding to the cavity contains a plurality of doping regions with the same doping gradient in the first direction.

14. The piezoelectric MEMS resonator according to claim 10, wherein The electrode layer includes a top electrode located on the upper side of the piezoelectric layer.

15. The piezoelectric MEMS resonator according to claim 14, characterized in that, The electrode layer further includes a bottom electrode located on the lower side of the piezoelectric layer.

16. The piezoelectric MEMS resonator according to claim 15, wherein, The insulating layer includes a first insulating layer located between the substrate and the device silicon layer and a second insulating layer located between the bottom electrode and the device silicon layer.

17. The piezoelectric MEMS resonator according to claim 14, characterized in that, The piezoelectric MEMS resonator further includes a passivation layer located on the upper side of the top electrode.

18. The piezoelectric MEMS resonator according to claim 10, wherein The piezoelectric MEMS resonator further includes a temperature compensation layer with a positive temperature coefficient arranged in a stacked manner.

19. A manufacturing method of a piezoelectric MEMS resonator, the piezoelectric MEMS resonator comprising a substrate, a first insulating layer, a device silicon layer, a piezoelectric layer, and an electrode layer stacked in a first direction, wherein a cavity is provided on an upper side of the substrate, characterized in that, The manufacturing method includes performing a first doping operation, and the first doping operation includes: Forming a patterned first hard mask on the upper surface of the device silicon layer away from the substrate, and the hollowed-out area of the first hard mask at least partially coincides with the area of the device silicon layer corresponding to the cavity; Growing a first thin film containing doping elements on the side of the first hard mask; Diffuse the doping elements in the first thin film into the device silicon layer by heating, so that the highest doping concentration of the device silicon layer is 10 20 cm -3 or more; Removing the first thin film and the first hard mask.

20. The manufacturing method according to claim 19, characterized in that, The pre-doping concentration of the device silicon layer is 10 19 cm -3 or more, or the initial equivalent resistivity of the device silicon layer is greater than 0.8 mΩ·cm.

21. The manufacturing method according to claim 19, characterized in that, The manufacturing method further includes performing a second doping operation before the first doping operation, and the second doping operation includes: Forming a patterned second hard mask on the lower surface of the device silicon layer opposite to the upper surface, and in the area of the device silicon layer corresponding to the cavity, the hollowed-out area of the second hard mask at least partially coincides with the hollowed-out area of the first hard mask; Growing a second thin film containing doping elements on the side of the second hard mask; Diffusing the doping elements in the second thin film into the device silicon layer by heating; Removing the second thin film and the second hard mask.

22. The manufacturing method according to claim 21, characterized in that, Before the second doping operation, the device silicon layer is connected to a second substrate, and the lower surface of the device silicon layer is on the outermost side. The manufacturing method further includes Between the second doping operation and the first doping operation, bonding the lower surface of the device silicon layer to the upper surface of the substrate through the first insulating layer, and thinning and / or etching the second substrate to form the upper surface of the device silicon layer.

23. The manufacturing method according to claim 21, characterized in that The sum of the depths of at least a part of the regions doped from the upper surface of the device silicon layer and the depths of at least a part of the regions doped from the lower surface of the device silicon layer is greater than or equal to the thickness of the device silicon layer.

24. The manufacturing method according to claim 21, wherein the sum of the depth of at least a part of the region doped from the upper surface of the device silicon layer and the depth of at least a part of the region doped from the lower surface of the device silicon layer is less than the thickness of the device silicon layer.

25. The manufacturing method according to claim 21, characterized in that, The manufacturing method further includes repeating the first doping operation and / or repeating the second doping operation to form a plurality of doped regions with different doping gradients in the first direction in the region of the device silicon layer corresponding to the cavity.

26. The manufacturing method according to any one of claims 19 to 25, characterized in that, The manufacturing method further includes at least one of the following steps: forming the piezoelectric layer on the upper surface of the device silicon layer; forming a top electrode on the upper side of the piezoelectric layer; forming a bottom electrode on the lower side of the piezoelectric layer; forming a passivation layer on the upper side of the top electrode; and forming a second insulating layer between the bottom electrode and the device silicon layer.

27. A method for manufacturing a semiconductor device including a piezoelectric MEMS resonator, the semiconductor device including a plurality of piezoelectric MEMS resonators, each piezoelectric MEMS resonator including a substrate, a first insulating layer, a device silicon layer, a piezoelectric layer, and an electrode layer stacked in a first direction, a cavity being provided on an upper side of the substrate, characterized in that, The manufacturing method includes a third doping operation, and the third doping operation includes: forming a patterned third hard mask on the upper surface of the device silicon layer of the plurality of piezoelectric MEMS resonators away from the substrate, and the hollowed-out area of the third hard mask at least partially coincides with the area of the device silicon layer of at least one piezoelectric MEMS resonator corresponding to the cavity; growing a third thin film containing a doping element on the side of the third hard mask; diffusing the doping element in the third thin film into the device silicon layer of the at least one piezoelectric MEMS resonator by heating; removing the third thin film and the third hard mask.

28. The manufacturing method according to claim 27, wherein The manufacturing method further includes a fourth doping operation, and the fourth doping operation includes: forming a patterned fourth hard mask on the upper surface or the lower surface opposite to the upper surface of the device silicon layer of the plurality of piezoelectric MEMS resonators, and the hollowed-out area of the fourth hard mask at least partially coincides with the area of the device silicon layer of at least one piezoelectric MEMS resonator corresponding to the cavity; growing a fourth thin film containing a doping element on the side of the fourth hard mask; diffusing the doping element in the fourth thin film into the device silicon layer of the at least one piezoelectric MEMS resonator by heating; removing the fourth thin film and the fourth hard mask, wherein, when doping the upper surface of the device silicon layer in the fourth doping operation, at least one piezoelectric MEMS resonator among the piezoelectric MEMS resonators doped in the fourth doping operation is different from at least one piezoelectric MEMS resonator among the piezoelectric MEMS resonators doped in the third doping operation, when doping the lower surface of the device silicon layer in the fourth doping operation, at least one piezoelectric MEMS resonator among the piezoelectric MEMS resonators doped in the fourth doping operation is the same as at least one piezoelectric MEMS resonator among the piezoelectric MEMS resonators doped in the third doping operation.

29. The manufacturing method according to claim 28, wherein The doping concentration of the device silicon layer of the piezoelectric MEMS resonator doped in the third doping operation is different from that of the device silicon layer of the piezoelectric MEMS resonator doped in the fourth doping operation, and / or, the doping element of the device silicon layer of the piezoelectric MEMS resonator doped in the third doping operation is different from that of the device silicon layer of the piezoelectric MEMS resonator doped in the fourth doping operation, and / or, the distribution of the doped regions included in the region corresponding to the cavity of the device silicon layer of the piezoelectric MEMS resonator doped in the third doping operation is different from that of the doped regions included in the region corresponding to the cavity of the device silicon layer of the piezoelectric MEMS resonator doped in the fourth doping operation.

30. The manufacturing method according to claim 28, characterized in that, The manufacturing method further includes repeating the third doping operation and / or repeating the fourth doping operation to dope the region corresponding to the cavity of the device silicon layer of at least two of the plurality of piezoelectric MEMS resonators.

31. The manufacturing method according to any one of claims 27 to 30, characterized in that, The manufacturing method further includes at least one of the following steps: forming the first insulating layer between the substrate and the device silicon layer; forming a top electrode on the upper side of the piezoelectric layer; forming a bottom electrode on the lower side of the piezoelectric layer; forming a passivation layer on the upper side of the top electrode; and forming a second insulating layer between the bottom electrode and the device silicon layer.

32. An electronic component, characterized in that, The electronic component includes the semiconductor device according to any one of claims 1 to 9.

33. An electronic component, characterized in that, The electronic component includes the piezoelectric MEMS resonator according to any one of claims 10 to 18.

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