High-precision multichannel synchronization and delay control system

Abstract

The invention provides a high-precision multichannel synchronization and delay control system, which comprises a DDS pulse generation unit, a pulse width adjustment unit, a ZYNQ control unit and at least one multistage clock distribution buffer unit, and is characterized in that the ZYNQ control unit comprises a ZYNQ chip; the ZYNQ control unit is used for controlling the DDS pulse generation unit to generate a pulse signal, controlling the pulse width adjusting unit, adjusting the width of the pulse signal output by the DDS pulse generation unit so as to output a pulse signal with a fixed width, controlling the multistage clock distribution buffer unit, expanding the pulse signal with the fixed width into multiple paths of pulse signals, and outputting the multiple paths of pulse signals; according to the multi-channel pulse signal generation system, multiple channels of pulse signals are expanded, time difference compensation and synchronous calibration processing are carried out on the multiple channels of pulse signals obtained through expansion so as to output synchronous multiple channels of pulse signals, the system adopts a digital-analog hybrid circuit architecture of a digital integrated chip and an analog gate circuit chip, and the synchronous multiple channels of pulse signals meeting user requirements are generated.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly relates to a high-precision multi-channel synchronization and delay control system. Background Art

[0002] Currently, array synthesis has become the forefront of the development of microwave transmitter technology. The arrayed microwave transmitter system generates radiation microwave element pulses through multiple generating elements, which can avoid the power capacity limitation of a single device and greatly improve the system power limit. At the same time, similar to a phased array radar, the arrayed microwave transmitter can quickly change the shape and direction of the antenna beam by controlling the emission timing of the elements, that is, beamforming and electronic beam scanning can be achieved.

[0003] Compared with a single microwave transmitter, the arrayed microwave transmitter system poses very high requirements on the number of control channels, control accuracy, and control functions of the multi-channel pulse generator. For example, the former only needs to control multiple links of a single device, while the latter needs to control multiple links of multiple devices, so the number of control channels and complexity are greatly increased; the former only needs to ensure the normal working timing of each subsystem, and the accuracy is usually at the ns level, which is relatively conventional, while the latter needs to meet the requirements of coherent synthesis of multiple elements, and the accuracy needs to reach 10p or even ps level, and the delay and jitter of the channels must be precisely controlled; the control function of the former is relatively simple, while the control function of the latter needs to meet requirements such as beamforming and electronic beam scanning. In addition, it is also desirable that the arrayed microwave transmitter has the ability of pulse repetition frequency agility, so that the time for changing the repetition frequency of the transmitted microwave is shortened to within a few microseconds. Due to the above factors, the system complexity and development difficulty of the multi-channel pulse transmitter for the arrayed microwave transmitter exceed the existing devices currently.

[0004] The high-precision multi-channel control system is the control center of the arrayed microwave transmitter system, and its technical performance is directly related to the excellence of the overall system's technical performance. For multi-channel pulse emitters, the existing solution is to use a Microcontroller Unit (MCU) as the main controller, generate pulses in cooperation with a level power converter, and use the internal timer and counter of the MCU to control the pulse precision and delay range. It can only synchronize up to 8 channels at most, and it is impossible to expand more channels, resulting in insufficient expandability of hardware channels and difficulty in meeting the requirements of dynamic changes. At the same time, there is also the problem of low control precision. The traditional pulse control method uses the counter and timer of the MCU, which can only control pulses at the nanosecond (ns) level and is difficult to meet the precision requirements of the arrayed microwave transmitter system. There is also the problem of poor operation convenience. The traditional pulse transmission communication method uses a serial port with a low rate and cannot meet the requirements of high real-time performance. Due to the phase difference in the clocks of different channels, data inconsistency occurs. Since it is impossible to make each channel exactly the same during the circuit board design process, the difference in the signal propagation path may introduce non-negligible delay and jitter, affecting the control precision. Therefore, there is also the problem of poor hardware synchronization. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a high-precision multi-channel synchronization and delay control system, specifically including:

[0006] In a first aspect, the present invention provides a high-precision multi-channel synchronization and delay control system, including:

[0007] A DDS pulse generation unit, a pulse width adjustment unit, a ZYNQ control unit, and at least one multi-stage clock distribution and buffer unit. The ZYNQ control unit includes a ZYNQ chip;

[0008] The ZYNQ control unit is used to control the DDS pulse generation unit to generate a pulse signal;

[0009] The ZYNQ control unit is also used to control the pulse width adjustment unit to adjust the width of the pulse signal output by the DDS pulse generation unit to output a fixed-width pulse signal;

[0010] The ZYNQ control unit is also used to control the multi-stage clock distribution and buffer unit to expand the fixed-width pulse signal into multiple pulse signals, and perform time difference compensation and synchronization calibration processing on the expanded multiple pulse signals to output synchronized multiple pulse signals.

[0011] Advantages of the present invention:

[0012] The high-precision multi-channel synchronization and delay control system provided by the present invention includes a DDS pulse generation unit, a pulse width adjustment unit, a ZYNQ control unit, and at least one multi-stage clock distribution and buffer unit. The ZYNQ control unit includes a ZYNQ chip. Among them, the ZYNQ control unit is used to control the DDS pulse generation unit to generate a pulse signal; the ZYNQ control unit is also used to control the pulse width adjustment unit to adjust the width of the pulse signal output by the DDS pulse generation unit to output a fixed-width pulse signal; the ZYNQ control unit is also used to control the multi-stage clock distribution and buffer unit to expand the fixed-width pulse signal into multiple pulse signals, and perform time difference compensation and synchronization calibration processing on the expanded multiple pulse signals to output synchronized multiple pulse signals. This system adopts a digital-analog hybrid circuit architecture of a digital integrated chip + an analog gate circuit chip, and can modify pulse parameters such as pulse width and the number of pulse outputs according to specific application requirements, and generate synchronized multiple pulse signals that meet the user's needs, solving the problem of fewer pulse channels in the traditional technology.

[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the architecture of a high-precision multi-channel synchronization and delay control system provided by the present invention;

[0015] Figure 2 It is a schematic diagram of the architecture of a DDS pulse generation unit provided by the present invention;

[0016] Figure 3 It is a schematic diagram of the internal principle of a DDS signal generator provided by the present invention;

[0017] Figure 4 It is a schematic diagram of the architecture of a pulse width adjustment unit provided by the present invention;

[0018] Figure 5 It is a schematic diagram of signal timing provided by the present invention;

[0019] Figure 6 It is a schematic diagram of the architecture of a multi-stage clock distribution and buffer unit provided by the present invention;

[0020] Figure 7 It is a schematic diagram of the architecture of a pulse buffer distribution circuit provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The present invention will be further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0022] To solve the problems of poor hardware synchronization, insufficient channel scalability, low control precision, and poor operation convenience existing in the prior art, the present invention provides a high-precision multi-channel synchronization and delay control system. On the basis of the prior art, by using the Zynq-7000 series all-programmable system-on-chip (Zynq-7000 All Programmable SoC, ZYNQ) as the main control chip and matching it with a direct digital frequency synthesis (DDS) signal generator chip, the generation of high-precision pulses is realized; by using a multi-stage topology clock buffer, multi-channel pulse signals are realized; by using a high-precision delay line control chip, high-precision synchronization calibration of multiple channels in the system and picosecond (ps)-level delay control within the channel are realized; by matching an Ethernet physical layer (PHY) network interface chip and an RJ45 network interface connector in the controller, the real-time control of the high-precision multi-channel synchronization and delay control system by the network host computer is completed.

[0023] Figure 1 As shown in the schematic diagram of the architecture of a high-precision multi-channel synchronization and delay control system provided by the present invention, Figure 1 as shown, the system includes:

[0024] A DDS pulse generation unit, a pulse width adjustment unit, a ZYNQ control unit, and at least one multi-stage clock distribution buffer unit.

[0025] Among them, the ZYNQ control unit includes a ZYNQ chip.

[0026] The ZYNQ chip includes two parts: a processing system (PS) and programmable logic (PL).

[0027] The ZYNQ control unit is used to control the DDS pulse generation unit to generate pulse signals.

[0028] The ZYNQ control unit is also used to control the pulse width adjustment unit to adjust the width of the pulse signal output by the DDS pulse generation unit to output a pulse signal with a fixed width.

[0029] The ZYNQ control unit is also used to control the multi-stage clock distribution buffer unit to expand the pulse signal with a fixed width into multi-channel pulse signals, and perform time difference compensation and synchronization calibration processing on the expanded multi-channel pulse signals to output synchronized multi-channel pulse signals.

[0030] The following further details the DDS pulse generation unit:

[0031] Optionally, asFigure 2 As shown in the figure, the DDS pulse generation unit includes a DDS signal generator, a high-precision crystal oscillator circuit, a low-pass filter network, and a duty cycle adjustment circuit.

[0032] The ZYNQ control unit writes a frequency control word and a phase control word to the DDS signal generator, and initializes the DDS signal generator by controlling the reset terminal RESET, the frequency update terminal FQ, and the write clock control terminal WCLK of the DDS signal generator.

[0033] The high-precision crystal oscillator circuit provides a reference frequency for the DDS signal generator.

[0034] The DDS signal generator generates a pulse signal according to the reference frequency, the frequency control word, and the phase control word.

[0035] The duty cycle adjustment circuit adjusts the duty cycle of the pulse signal generated by the DDS signal generator by controlling the voltage on the reference voltage terminal VREF of the DDS signal generator.

[0036] The low-pass filter network filters the pulse signal output by the DDS signal generator to filter out high-frequency signal components and retain low-frequency signal components.

[0037] Figure 3 This is a schematic diagram of the internal principle of a DDS signal generator provided by the present invention. As Figure 3 shown, the basic working process of the DDS signal generator is as follows:

[0038] a. Receive a frequency control word;

[0039] b. The phase accumulator performs cyclic accumulation on the frequency control word;

[0040] c. Add the phase information latched in the phase memory to the initial phase (phase control);

[0041] d. Truncate the high bits of the phase information to be the addressing address of the frequency / phase conversion ROM;

[0042] e. The data output from the frequency / phase conversion ROM forms an analog waveform through a D / A converter;

[0043] f. The DAC outputs a stepped waveform, which passes through a low-pass filter to form an analog waveform, and then is amplified by an amplifier to obtain the final waveform.

[0044] Exemplarily, the ZYNQ chip uses ZYNQ7045, the DDS signal generator is AD9851, the high-precision crystal oscillator circuit includes a 125M high-precision and low-jitter active crystal oscillator, and the duty cycle adjustment circuit includes the digital potentiometer chip TPL0102-100. Selecting a crystal oscillator with a smaller frequency deviation can ensure the low jitter and stability of the output pulse signal.

[0045] ZYNQ7045 writes the frequency control word and phase control word to AD9851 by controlling the data buses D0~D7, and realizes the initialization control of AD9851 by controlling the reset signal terminal RESET, frequency update terminal FQ and write clock control terminal WCLK of AD9851. AD9851 is a highly integrated device that uses advanced DDS technology and incorporates a high-speed and high-performance digital-to-analog converter and comparator, which together constitute a digitally programmable frequency synthesizer and clock generator. When using a precision clock source as a reference, AD9851 can generate a digitally synthesized sinusoidal wave with stable frequency and programmable phase. It can also further convert the sinusoidal wave into a square wave suitable for the application of a frequency agile clock generator through a comparator according to user requirements. TPL0102-100 is a dual-channel 256-bit digital potentiometer chip with a non-volatile memory, and controls the tap position of the digital potentiometer through the Inter-Integrated Circuit (IIC) communication protocol.

[0046] The reference frequency of the DDS signal generator is used for the synchronous operation of each component in the DDS. Therefore, the frequency stability of the signal output by the DDS is the same as that of the reference frequency. Under the control of a standard frequency reference source, the frequency control word K can determine the corresponding phase increment, and the phase accumulator linearly accumulates with a step size M. When the phase accumulator is full, an overflow will occur, thus completing a periodic operation, and this operation period is the period for the DDS to generate a signal. Usually, the minimum value of an N-bit phase accumulator is 0 and the maximum value is 2N-1. Therefore, the frequency of the finally output signal is fc represents the sampling clock, and the size of the frequency resolution is In practical applications, it is very difficult for the calculated step size M to be an integer. Therefore, there will inevitably be a frequency error. If the fractional part of the calculated frequency control word K is discarded, then the frequency error of the finally output signal does not exceed the frequency resolution Δf; if the fractional part of the step size M is rounded, the frequency error will not exceed 0.5Δf.

[0047] The following further details the pulse width adjustment unit:

[0048] Optionally, such as Figure 4As shown, the pulse width adjustment unit includes: a first delay line chip, a second delay line chip, an AND gate chip, and a NAND gate chip.

[0049] Among them, the first delay line chip and the second delay line chip are of the same model.

[0050] The first delay line chip delays the pulse signal output by the DDS pulse generation unit according to the control signal output by the ZYNQ control unit and then outputs it to the NAND gate chip; the NAND gate chip NANDs the signal output by the first delay line chip and the high-level signal and then outputs it to the AND gate chip; the second delay line chip forwards the pulse signal output by the DDS pulse generation unit to the AND gate chip according to the control signal output by the ZYNQ control unit; the AND gate chip ANDs the signal output by the NAND gate chip and the signal output by the second delay line chip and then outputs it to the multi-stage clock distribution buffer unit.

[0051] The pulse width adjustment unit is composed of a delay line chip and a logic gate chip. It splits the pulse signal into two paths. One path is not processed at all, and the other path is delayed by the delay line chip and then inverted by the NAND gate. Then, the two paths of pulse signals are ANDed to obtain a pulse signal with a new pulse width. The advantage of this pulse width adjustment unit is that the adjustment of the pulse width is for the edge of the pulse signal, not affected by the output frequency and pulse repetition time, and no additional jitter is introduced.

[0052] Optionally, both the first delay line chip and the second delay line chip are 0.5 ns-level delay line chips DS1124. DS1124 is an 8-bit digital programmable chip with a delay resolution of 0.25 ns. Under the delay control of DS1124, the pulse signal can achieve a pulse delay of 0.25 ns - 64 ns for the pulse signal. As Figure 5 shown, exemplarily, the pulse signal output by the DDS pulse generation unit is output after passing through the first DS1124 without any delay processing. The pulse signal output by the DDS pulse generation unit is delayed by 20 ns after being processed by the second DS1124 and then enters the NAND gate for NAND operation with the high level, which is equivalent to flipping the high and low levels of the pulse signal. Then, the signal output by the first DS1124 and the signal output by the NAND gate enter the AND gate together, and finally a pulse signal with a pulse width of 20 ns is output.

[0053] The following further details the multi-stage clock distribution buffer unit:

[0054] Optionally, a multi-stage clock distribution buffer unit is arranged on a PCB board. The internal components of the PCB board are symmetrically distributed in the order of the signal from the inside to the outside.

[0055] When the high-precision multi-channel synchronization and delay control system includes multiple multi-stage clock distribution and buffer units, the PCB boards corresponding to the multiple multi-stage clock distribution and buffer units are stacked and connected through the HDM connectors on the boards.

[0056] Adopting a symmetric layout is beneficial for routing each pulse channel and also conducive to the equal-length design of the PCB.

[0057] Optionally, as Figure 6 shown, the multi-stage clock distribution and buffer unit includes: a pulse buffer and distribution circuit, multiple delay line circuits, and multiple amplifier circuits.

[0058] Among them, any one of the delay line circuits includes two stages of serially connected delay line units.

[0059] The ZYNQ control unit initializes each delay line circuit and configures the working mode of each delay line circuit. The pulse buffer and distribution circuit distributes the signal output by the pulse width adjustment unit to each delay line circuit. After each delay line circuit performs two-stage delay processing on the signal sent by the pulse buffer and distribution circuit, it outputs to the corresponding amplifier circuit. The amplifier circuit amplifies the signal sent by the corresponding delay line circuit and then outputs it.

[0060] Exemplarily, the delay line unit includes a delay line chip SY89297U. SY89297U is a dual-channel programmable silicon delay chip. The delay value can be set by programming. The inherent delay of the chip is 2ns, and the rate is as high as 3.2Gbps. The working principle of the chip is: when the enable input terminal is valid, the delay amount is written into the internal register through the serial data interface, and the input pulse signal is delayed by a given number of delays and then output. The delay time is determined by the preset programmable delay number and the inherent delay time of the chip. The relationship is:

[0061] Δt = Date × K + Td,

[0062] where, Δt represents the entire delay time corresponding to the pulse, Date represents the preset programmable delay number, K represents the minimum value of the delay line chip accuracy, Td represents the inherent delay time of the chip, that is, when Date = 0, the delay value between the input and output signals.

[0063] Adopting the architecture of a programmable delay chip + ZYNQ chip can effectively ensure the delay accuracy in digital delay control. At the same time, by using an analog application-specific integrated chip in combination, the delay accuracy of the system is further improved.

[0064] Further optionally, the pulse buffer and distribution circuit includes: a pulse buffer and distribution unit and a voltage matching unit.

[0065] The voltage matching unit is used to convert the level format of the output signal of the pulse buffer and distribution unit into a format suitable for the delay line circuit and output it to each delay line circuit.

[0066] Exemplarily, the voltage matching unit includes a level conversion chip DS90C031TM; the pulse buffer distribution unit includes a buffer distribution chip SN74LV125ATDR. SN74LV125ATDR is a low-jitter clock fan-out buffer suitable for pulse signal applications.

[0067] After the SN74LV125ATDR distributes the pulse signal, the pulse signal remains at single-ended complementary metal oxide semiconductor (CMOS) level. However, since the input signal of the delay line chip SY89297U is current mode logic (CML) level, a level conversion of the pulse link is required. The single-ended level of the pulse is converted into a level signal suitable for the delay line chip. Therefore, DS90C031TM is selected in this module to convert it into low-voltage differential signaling (LVDS) and then connect it to the signal input terminal of the delay chip. DS90C031 is a low-power four-channel level conversion chip that can convert low-voltage transistor-transistor logic (LVTTL) / low-voltage complementary metal-oxide-semiconductor (LVCOMS) input level into LVDS level output. Its maximum supported clock rate is 155 MHz, and the inter-channel error is less than 30 ps. The LVDS level output by DS90C031TM can be directly connected to the signal input pin of SY89297U with a terminating resistor.

[0068] Optionally, as Figure 6 shown, the pulse buffer distribution circuit is composed of cascading multiple buffer chips, where the number of buffers in the subsequent stage is twice the number of buffers in the previous stage.

[0069] Further optionally, the delay line circuit further includes a temperature monitoring unit.

[0070] The ZYNQ control unit controls the temperature monitoring unit to monitor the temperature of the delay line circuit where it is located, and calibrates the phase of the output signal of the corresponding delay line circuit according to the temperature monitoring result feedback by the temperature monitoring unit.

[0071] The DDS signal generator can generate pulse signals with a certain pulse width and adjustable frequency values. Through the matching circuit, it can match and adapt the level signals of the delay line chips in the delay line circuit. The ZYNQ control unit controls the overall system through the delay line circuit to achieve high-precision delay synchronization. Since the phase of the pulse signal output by the delay line chip is affected by temperature, a temperature monitoring unit is set to reflect the temperature change and timely grasp the signal phase change, so as to linearly control the output of the delay line chip.

[0072] Further optionally, the amplifier circuit includes a shaping and amplifying chip THS3091. THS3091 is a current-feedback amplifier with high bandwidth and low distortion, which can work in a wide power supply range of ±5V to ±15V and is suitable for applications that require large linear output signals. This device has characteristics such as high gain bandwidth, low input offset voltage, good gain bandwidth, good slew rate parameters, and high drive current.

[0073] The slew rate refers to the conversion rate of the output voltage of an operational amplifier, and the units are V / s, V / ms, and V / us. It reflects an index of an operational amplifier in terms of speed, indicating the adaptability of the operational amplifier to the signal change speed and is a parameter for measuring the working speed of an operational amplifier when a large-amplitude signal acts. When the absolute value of the slope of the input signal change is less than the slew rate, the output voltage changes linearly. When it is required that the rising edge of the output pulse is within 2 ns, with a 50-ohm load connected externally, the channel output amplitude is 5V, and the output current is 100 mA. The output impedance of the amplifier channel is 50 ohms. It can be calculated that the no-load output amplitude is 10V, and the slew rate of THS3091 is 7300 V / us. It can be calculated that the rising edge time at no-load output is 10V * 1000 ns / 7300V = 1.4 ns, meeting the requirement of a 2-ns rising edge.

[0074] Exemplarily, as Figure 7 shown, the pulse buffer and distribution circuit includes 11 pulse buffer and distribution chips SN74LV125, 64 delay line chips SY89297U (denoted as D in the figure), and 32 shaping and amplifying chips THS3091 (denoted as A in the figure), each having 32 pulse emission channels. Externally, the 32 pulse signals on the board are connected to the backend receiving module through the SMA interface. When 64 pulse signals are required, 64 pulse emission channels are needed. Then, two pulse buffer and distribution circuits as Figure 7 shown can be stacked and connected through the HDM connector to output 64 synchronous pulse signals.

[0075] By expanding the pulse buffer and distribution circuit, synchronous pulse signal multiplication can be achieved, and the implementation process is simple and highly feasible.

[0076] Furthermore, the high-precision multi-channel synchronization and delay control system further includes:

[0077] The ZYNQ control unit responds to the pulse repetition frequency change instruction sent by the host computer, generates a random number, calculates a new pulse repetition frequency according to the random number, obtains a new frequency control word according to the new pulse repetition frequency, and controls the DDS pulse generation unit to generate a pulse signal meeting the requirements of the new pulse repetition frequency through the new frequency control word.

[0078] Optionally, after the high-precision multi-channel synchronization and delay control system completes the pulse repetition frequency update, it sends a signal to the host computer through the ZYNQ control unit to notify the host computer that the pulse repetition frequency of the high-precision multi-channel synchronization and delay control system has been updated.

[0079] Host computers such as computers can perform real-time operation control on the high-precision multi-channel synchronization and delay control system, which can effectively shorten the problem of the long time for the system to update the pulse repetition frequency and has stronger practicability. This system can modify the pulse repetition frequency according to specific application requirements and can meet different needs of users.

[0080] The high-precision multi-channel synchronization and delay control system provided by the present invention includes a DDS pulse generation unit, a pulse width adjustment unit, a ZYNQ control unit, and at least one multi-stage clock distribution buffer unit. The ZYNQ control unit includes a ZYNQ chip; wherein, the ZYNQ control unit is used to control the DDS pulse generation unit to generate a pulse signal; the ZYNQ control unit is also used to control the pulse width adjustment unit to adjust the width of the pulse signal output by the DDS pulse generation unit to output a fixed-width pulse signal; the ZYNQ control unit is also used to control the multi-stage clock distribution buffer unit to expand the fixed-width pulse signal into multiple path pulse signals, and perform time difference compensation and synchronization calibration processing on the expanded multiple path pulse signals to output synchronized multiple path pulse signals. This system adopts a digital integrated chip + analog gate circuit chip digital-analog hybrid circuit architecture, can modify pulse parameters such as pulse width and the number of pulse outputs according to specific application requirements, and generate synchronized multiple path pulse signals meeting the needs of users, solving the problem of fewer pulse channels in the traditional technology.

[0081] The terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0082] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as falling within the protection scope of the present invention.

Claims

1. A high-precision multi-channel synchronization and delay control system, characterized in that: include: A DDS pulse generating unit, a pulse width adjusting unit, a ZYNQ control unit and at least one multi-stage clock distribution buffer unit, wherein the ZYNQ control unit includes a ZYNQ chip; The ZYNQ control unit is used to control the DDS pulse generating unit to generate a pulse signal; The ZYNQ control unit is further used to control the pulse width adjustment unit to adjust the width of the pulse signal output by the DDS pulse generation unit to output a fixed-width pulse signal; The ZYNQ control unit is also used to control the multi-level clock distribution buffer unit to expand the fixed-width pulse signal into a multi-channel pulse signal, and perform time difference compensation and synchronization calibration processing on the expanded multi-channel pulse signal to output a synchronized multi-channel pulse signal.

2. The system according to claim 1, characterized in that The DDS pulse generating unit comprises: DDS signal generator, high-precision crystal oscillator circuit, low-pass filter network and duty cycle adjustment circuit; The ZYNQ control unit writes a frequency control word and a phase control word to the DDS signal generator, and initializes the DDS signal generator by controlling a reset terminal RESET, a frequency update terminal FQ and a write clock control terminal WCLK of the DDS signal generator; The high-precision crystal oscillator circuit provides a reference frequency for the DDS signal generator; The DDS signal generator generates a pulse signal according to the reference frequency, the frequency control word and the phase control word; The duty cycle adjustment circuit adjusts the duty cycle of the pulse signal generated by the DDS signal generator by controlling the voltage on the reference voltage terminal VREF of the DDS signal generator; The low-pass filter network performs filtering processing on the pulse signal output by the DDS signal generator to filter out high-frequency signal components and retain low-frequency signal components.

3. The system according to claim 2, characterized in that The pulse width adjustment unit comprises: A first delay line chip, a second delay line chip, an AND gate chip and an AND-NAND gate chip, wherein the first delay line chip and the second delay line chip are chips of the same model; The first delay line chip delays the pulse signal output by the DDS pulse generating unit and then outputs it to the NAND gate chip according to the control signal output by the ZYNQ control unit; The NAND gate chip performs NAND of the signal output by the first delay line chip and the high level signal and then outputs the NAND signal to the AND gate chip; The second delay line chip forwards the pulse signal output by the DDS pulse generating unit to the AND gate chip according to the control signal output by the ZYNQ control unit; The AND gate chip ANDs the signal output by the NAND gate chip and the signal output by the second delay line chip, and then outputs the result to the multi-stage clock distribution buffer unit.

4. The system according to claim 3, characterized in that The multi-stage clock distribution buffer unit comprises: A pulse buffer distribution circuit, a plurality of delay line circuits and a plurality of amplifier circuits, wherein any of the delay line circuits comprises two stages of delay line units connected in series; The ZYNQ control unit initializes each of the delay line circuits and configures the working mode of each of the delay line circuits; The pulse buffer distribution circuit distributes the signal output by the pulse width adjustment unit to each of the delay line circuits; Each of the delay line circuits performs two-stage delay processing on the signal sent by the pulse buffer distribution circuit and outputs it to the corresponding amplifier circuit; The amplifier circuit amplifies the signal sent by the corresponding delay line circuit and then outputs it.

5. The system according to claim 4, characterized in that The pulse buffer distribution circuit comprises: Pulse buffer distribution unit and voltage matching unit; The voltage matching unit is used to convert the level format of the output signal of the pulse buffer distribution unit into a format suitable for the delay line circuit, and output it to each of the delay line circuits.

6. The system according to claim 5, characterized in that The delay line circuit further includes a temperature monitoring unit; The ZYNQ control unit controls the temperature monitoring unit to monitor the temperature of the delay line circuit, and calibrates the phase of the output signal of the corresponding delay line circuit according to the temperature monitoring result fed back by the temperature monitoring unit.

7. The system according to claim 6, characterized in that The pulse buffer distribution circuit is composed of a plurality of buffer chips cascaded together, wherein the number of buffers in the latter stage is twice the number of buffers in the former stage.

8. The system according to claim 7, characterized in that One of the multi-stage clock distribution buffer units is arranged on a PCB board, and the components inside the PCB board are symmetrically distributed according to the order of the signal from inside to outside; When the high-precision multi-channel synchronization and delay control system includes a plurality of multi-stage clock distribution buffer units, the PCB boards corresponding to the plurality of multi-stage clock distribution buffer units are stacked and connected via HDM connectors on the boards.

9. The system according to claim 8, characterized in that The ZYNQ control unit generates a random number in response to the pulse repetition frequency change instruction sent by the host computer, calculates a new pulse repetition frequency based on the random number, obtains a new frequency control word based on the new pulse repetition frequency, and controls the DDS pulse generating unit to generate a pulse signal that meets the new pulse repetition frequency requirements through the new frequency control word.

10. The system according to claim 9, characterized in that The first delay line chip and the second delay line chip are both DS1124; The DDS signal generator is AD9851; The duty cycle adjustment circuit includes a digital potentiometer chip TPL0102-100; The delay line unit includes a delay line chip SY89297U; The amplifier circuit includes a shaping amplifier chip THS3091; The voltage matching unit includes a level conversion chip DS90C031TM; The pulse buffer distribution unit includes a buffer distribution chip SN74LV125ATDR.

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