Single-channel assembly line analog-to-digital converter suitable for high speed and medium and high precision

Abstract

The invention discloses a single-channel assembly line analog-to-digital converter suitable for high speed and medium and high precision, and solves the problems that an analog-to-digital converter in the prior art is difficult to realize high speed and medium and high precision, and is low in area, power consumption and design complexity. The circuit comprises the following steps: sampling an input analog signal to a capacitor array in a first-stage Loop-Unroll SAR ADC (Synthetic Aperture Radar Analog to Digital Converter) when a sampling clock signal is at a high level; carrying out coarse quantization on the sampling voltage on the capacitor array; the passive residual error transmission module and the inter-stage residual error amplifier module are used for transmission and amplification; the second-stage four-channel partially interleaved SAR ADC module is used for performing fine quantization on residual error amplification voltage; the digital code alignment module is used for carrying out digital code alignment to obtain a complete digital code; the limitation of a traditional inter-stage residual error amplifier on the speed of the first-stage Loop-Unroll SAR ADC is avoided, and the conversion rate of the whole ADC is further increased.

Description

Technical Field

[0001] The present invention relates to the technical field of mixed-signal integrated circuit design, and particularly to a single-channel pipelined analog-to-digital converter applicable to high speed, medium and high precision. Background Art

[0002] The successive approximation analog-to-digital converter (SAR ADC) has become one of the most favored ADC architectures in the current market due to its highly digital structure, excellent compatibility with advanced semiconductor processes, and outstanding stability performance. However, its inherent successive comparison working principle essentially limits the improvement of speed performance, thus constituting a major bottleneck in the performance optimization process. To address the speed limitation of the SAR ADC, the pipelined ADC architecture emerged. By dividing the quantization process into multiple independent and sequential stages, this architecture not only ensures the realization of high-precision quantization but also significantly improves the conversion rate of the ADC. However, this multi-stage pipelined design also brings greater requirements for chip area, increased power consumption, and more stringent requirements for the performance of the inter-stage amplifier. In contrast, the time-interleaved ADC architecture provides a different method to improve the speed of the ADC. Its remarkable feature is that it does not require the use of an inter-stage amplifier, thus effectively avoiding the above challenges in amplifier design. The time-interleaved ADC can achieve a multiple increase in the ADC sampling rate by increasing the interleaving factor, that is, the number of channels processed in parallel.

[0003] However, this method also correspondingly introduces the complexity of the sample-and-hold circuit design and the clock distribution network design, especially the clock skew and jitter problems, which become the key factors restricting the further improvement of the interleaving factor. To effectively overcome the adverse effects brought by clock skew and jitter, an additional digital calibration mechanism needs to be introduced, but this measure increases the complexity and design cost of the system. Obviously, the traditional pipelined and time-interleaved architectures have certain limitations and are difficult to achieve high speed, medium and high precision while maintaining low area, low power consumption, and low design complexity. Summary of the Invention

[0004] The present invention provides a single-channel pipelined analog-to-digital converter applicable to high speed, medium and high precision, solves the problem in the prior art that it is difficult to achieve high speed, medium and high precision while maintaining low area, low power consumption, and low design complexity, avoids the limitation of the speed of the first-stage Loop-Unrolled SAR ADC by the traditional inter-stage residue amplifier, and further accelerates the conversion rate of the overall ADC.

[0005] The present invention provides a single-channel pipelined analog-to-digital converter suitable for high-speed, medium-high precision. The circuit includes: a sample-and-hold circuit, a first-stage Loop-Unrolled SAR ADC, a passive residue transmission module, an inter-stage residue amplifier module, a second-stage four-channel partially interleaved SAR ADC module, and a digital code alignment module;

[0006] The sample-and-hold circuit is used to sample the input analog signal onto the capacitor array in the first-stage Loop-Unrolled SAR ADC at the rising edge of the sampling clock signal; wherein, the capacitor array includes: a P-terminal capacitor array and an N-terminal capacitor array;

[0007] The first-stage Loop-Unrolled SAR ADC is used to roughly quantize the voltage on the capacitor array at the low level of the sampling clock signal to obtain the first 3-bit digital code D[10:8] and the first-stage quantization residue signal;

[0008] The passive residue transmission module is used to passively transmit the first-stage quantization residue signal to the inter-stage residue amplifier module to obtain a passively transmitted residue signal;

[0009] The inter-stage residue amplifier module is used to amplify the passively transmitted residue signal to obtain a residue amplified voltage;

[0010] The second-stage four-channel partially interleaved SAR ADC module is used to finely quantize the residue amplified voltage to obtain an 8-bit digital code D[7:0];

[0011] The digital code alignment module is used to align the first 3-bit digital code D[10:8] and the 8-bit digital code D[7:0] to obtain a complete digital code.

[0012] In a possible implementation, the sample-and-hold circuit is a bootstrap switch type sample-and-hold circuit.

[0013] In a possible implementation, the first-stage Loop-Unrolled SAR ADC is used to roughly quantize the voltage on the capacitor array at the low level of the sampling clock signal to obtain the first 3-bit digital code D[10:8] and the first-stage quantization residue signal, including:

[0014] At the falling edge of the sampling clock signal, the first-stage Loop-Unrolled SAR ADC is triggered to compare the upper plate voltages of the P-terminal capacitor array and the N-terminal capacitor array, and switch the lower plate voltages of the P-terminal capacitor array and the N-terminal capacitor array to obtain the first 3-bit digital code D[10:8] and the first-stage quantization residue signal.

[0015] In a possible implementation, the first-stage Loop-Unrolled SAR ADC includes: a first low kickback noise comparator circuit, a second low kickback noise comparator circuit, a third low kickback noise comparator circuit, a capacitor array circuit, a START.GEN circuit, a first RDY.GEN circuit, a second RDY.GEN circuit, and a RESET.GEN circuit;

[0016] The upper plates of the P-terminal capacitor array are connected to the positive input terminals of the first low kickback noise comparator circuit, the second low kickback noise comparator circuit, and the third low kickback noise comparator circuit; the upper plates of the N-terminal capacitor array are connected to the negative input terminals of the first low kickback noise comparator circuit, the second low kickback noise comparator circuit, and the third low kickback noise comparator circuit;

[0017] The input terminal of the START.GEN circuit is connected to the inverted signal of the sampling clock signal; the output terminal of the START.GEN circuit is connected to the comparison clock CLK of the first low kickback noise comparator circuit;

[0018] The output terminal of the first low kickback noise comparator circuit is connected to the input terminal of the first RDY.GEN circuit;

[0019] The output terminal of the first RDY.GEN circuit is connected to the comparison clock CLK of the second low kickback noise comparator circuit;

[0020] The output terminal of the second low kickback noise comparator circuit is connected to the input terminal of the second RDY.GEN circuit;

[0021] The output terminal of the second RDY.GEN circuit is connected to the comparison clock CLK of the third low kickback noise comparator circuit;

[0022] The output terminal of the third low kickback noise comparator circuit is connected to the input terminal of the RESET.GEN circuit;

[0023] The output terminal of the RESET.GEN circuit is connected to the reset input terminals of the START.GEN circuit, the first RDY.GEN circuit, and the second RDY.GEN circuit.

[0024] In a possible implementation, the first low kickback noise comparator circuit, the second low kickback noise comparator circuit, and the third low kickback noise comparator circuit all include: a low kickback noise preamplification unit, an integration latch unit, and a latch unit connected in series in sequence.

[0025] In a possible implementation, the low back-kick noise pre-amplification unit includes: NMOS transistor M 1a , NMOS transistor M 2a , NMOS transistor M 3a , NMOS transistor M 4a , NMOS transistor M 5a , NMOS transistor M 6a , PMOS transistor M 7a , PMOS transistor M 8a ;

[0026] The integration and latching unit includes: NMOS transistor M 1b , NMOS transistor M 2b , PMOS transistor M 3b , PMOS transistor M 4b and PMOS transistor M 5b ;

[0027] The latching unit includes: PMOS transistor M 1c , PMOS transistor M 2c , PMOS transistor M 3c , PMOS transistor M 4c , NMOS transistor M 5c , NMOS transistor M 6c and NMOS transistor M 7c ;

[0028] The gate terminal of the NMOS transistor M 1a is connected to the upper plate of the P-terminal capacitor array; the source terminal of the NMOS transistor M 1a is connected to the drain terminal of the NMOS transistor M 3a ; the drain terminal of the NMOS transistor M 1a is connected to the source terminal of the NMOS transistor M 5a ;

[0029] The gate terminal of the NMOS transistor M 5a is connected to the gate terminal of the NMOS transistor M 6a , the gate terminal of the PMOS transistor M 7a , the gate terminal of the PMOS transistor M 8a and the comparison clock signal CLK; the drain terminal of the NMOS transistor M 5a is connected to the drain terminal of the PMOS transistor M 7a and the gate terminal of the NMOS transistor M 1b ;

[0030] The source terminal of the PMOS transistor M 7a is connected to the source terminals of the PMOS transistors M 8a , M 5b ​1c The source terminal of, PMOS transistor M 3c The source terminal of, PMOS transistor M 4c The source terminal of, PMOS transistor M 2c The source terminal is connected to the power supply voltage AVDD;

[0031] The PMOS transistor M 8a The drain terminal is connected to the drain terminal of the NMOS transistor M 6a The drain terminal of, and the NMOS transistor M 2b The gate terminal is connected;

[0032] The NMOS transistor M 6a The source terminal is connected to the drain terminal of the NMOS transistor M 2a The drain terminal;

[0033] The NMOS transistor M 2a The gate terminal is connected to the upper plate of the N-terminal capacitor array; The NMOS transistor M 2a The source terminal is connected to the drain terminal of the NMOS transistor M 4a The drain terminal;

[0034] The NMOS transistor M 4a The gate terminal is connected to the gate terminal of the NMOS transistor M 3a The gate terminal and the power supply voltage AVDD; The NMOS transistor M 4a The source terminal is connected to the source terminal of the NMOS transistor M 3a The source terminal of, the NMOS transistor M 1b The source terminal of, the NMOS transistor M 2b The source terminal of, and the NMOS transistor M 7c The source terminal is grounded;

[0035] The NMOS transistor M 1b The drain terminal is connected to the drain terminal of the PMOS transistor M 3b The drain terminal of, the PMOS transistor M 1c The gate terminal and the PMOS transistor M 4b The gate terminal is connected;

[0036] The PMOS transistor M 3b The source terminal is connected to the drain terminal of the PMOS transistor M 5b The source terminal of, the PMOS transistor M 4b The source terminal; The PMOS transistor M 3b The gate terminal is connected to the drain terminal of the PMOS transistor M 4b The drain terminal of, the NMOS transistor M 2b The drain terminal of, the PMOS transistor M 2c The gate terminal is connected;

[0037] The PMOS transistor M 5bThe gate terminal of [it] is connected to the inverted signal CLKB; wherein, the inverted signal CLKB is the inverted signal of the comparison clock signal CLK;

[0038] The PMOS transistor M 1c The drain terminal of [it] is connected to the drain terminal of the PMOS transistor M 3c The drain terminal of [it], the drain terminal of the NMOS transistor M 5c The drain terminal of [it], the gate terminal of the PMOS transistor M 4c The gate terminal of [it] and the gate terminal of the NMOS transistor M 6c are connected;

[0039] The NMOS transistor M 5c The source terminal of [it] is connected to the source terminal of the NMOS transistor M 6c The source terminal of [it], the drain terminal of the NMOS transistor M 7c are connected; The drain terminal of the NMOS transistor M 5c The gate terminal of [it] is connected to the gate terminal of the PMOS transistor M 3c The gate terminal of [it], the drain terminal of the PMOS transistor M 4c The drain terminal of [it], the drain terminal of the NMOS transistor M 6c The drain terminal of [it] and the drain terminal of the PMOS transistor M 2c are connected;

[0040] The NMOS transistor M 7c The gate terminal of [it] is connected to the comparison clock CLK.

[0041] In a possible implementation manner, the capacitance value of the passive residue transfer module is 1 / 2 of the capacitance value on the capacitance array in the first-stage Loop-Unrolled SAR ADC.

[0042] In a possible implementation manner, the digital code alignment module includes a one-bit redundant bit D[7] for calibrating the errors caused by comparator offset, capacitance mismatch, etc. in the first-stage Loop-Unrolled SAR ADC.

[0043] In a possible implementation manner, the inter-stage residue amplifier module is implemented by an open-loop structure.

[0044] In a possible implementation manner, the second-stage four-channel partially interleaved SAR ADC module includes four channel sub-ADCs and works alternately in a round-robin manner.

[0045] One or more technical solutions provided in the present invention have at least the following technical effects or advantages:

[0046] The present invention ingeniously utilizes the loop-unrolled successive approximation technique in the first-stage Loop-Unrolled SAR ADC, successfully eliminating the storage time of the quantization result and the reset time of the comparator, thereby significantly improving the quantization speed. Subsequently, in the second-stage four-channel partially interleaved SAR ADC module, a partially interleaved architecture is adopted. Through the interleaved operation of four sub-channel SAR ADCs, not only is the performance degradation caused by clock skew and jitter in traditional time-interleaved ADCs effectively avoided, but also the overall ADC conversion speed is further accelerated. In addition, during the inter-stage residue transmission and amplification process, a passive residue transmission module and an inter-stage residue amplifier module are introduced. This design not only avoids the limitation of the traditional inter-stage residue amplifier on the speed of the first-stage Loop-Unrolled SAR ADC, but also further accelerates the overall ADC conversion rate. Description of the Drawings

[0047] Figure 1 Schematic diagram of a single-channel pipelined analog-to-digital converter suitable for high-speed, medium-high precision provided by an embodiment of the present invention;

[0048] Figure 2 Timing diagram provided by an embodiment of the present invention;

[0049] Figure 3 Schematic diagram of the first-stage Loop-Unrolled SAR ADC circuit provided by an embodiment of the present invention;

[0050] Figure 4 Circuit diagram of a low kickback noise comparator provided by an embodiment of the present invention. Detailed Description of the Invention

[0051] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0052] The present invention provides a single-channel pipelined analog-to-digital converter suitable for high-speed, medium-high precision. Refer to Figure 1 , the circuit includes: a sample-and-hold circuit, a first-stage Loop-Unrolled SAR ADC, a passive residue transmission module, an inter-stage residue amplifier module, a second-stage four-channel partially interleaved SAR ADC module, and a digital code alignment module.

[0053] The sample-and-hold circuit is used to sample the input analog signal at the sampling clock signal Φ S1Sample the input analog signal onto the capacitor array in the first-stage Loop-Unrolled SAR ADC at the rising edge; wherein, the capacitor array includes: a P-terminal capacitor array and an N-terminal capacitor array;

[0054] Here, the sample-and-hold circuit is a bootstrap switch type sample-and-hold circuit, and the capacitor array uses a split capacitor array. During the sampling phase, a part of the bottom plate voltage is connected to the power supply voltage VDD, and the other part of the bottom plate voltage is grounded to GND. During quantization, switch the voltage value of the upper plate by switching whether the lower plates of these two parts of the capacitors are connected to VDD or GND.

[0055] Exemplarily, refer to Figure 2 , when the sampling clock signal Φ S1 is at a high level, the sample-and-hold circuit (S / H) starts to work and samples VIN / P onto the N / P-terminal capacitor array in the first-stage Loop-Unrolled SAR ADC (the first-stage pipelined module). When the sampling clock signal Φ S1 is at a low level, the sample-and-hold circuit ends its operation, stops sampling the input analog signal VIN / P, and the voltage on the N / P-terminal capacitor array holds the sampled voltage CDAC_VINN / P obtained from the last sampling.

[0056] The first-stage Loop-Unrolled SAR ADC is used to roughly quantize the sampled voltage at the falling edge of the sampling clock signal Φ S1 to obtain the first 3-bit digital code D[10:8] and the first-stage quantization residue signal;

[0057] Here, the first-stage Loop-Unrolled SAR ADC is used to roughly quantize the voltage on the capacitor array at the falling edge of the sampling clock signal Φ S1 to obtain the first 3-bit digital code D[10:8] and the first-stage quantization residue signal, including: triggering the first-stage Loop-Unrolled SAR ADC at the falling edge of the sampling clock signal Φ S1 , then comparing the upper plate voltages of the P-terminal capacitor array and the N-terminal capacitor array, and switching the lower plate voltages of the P-terminal capacitor array and the N-terminal capacitor array to obtain the first 3-bit digital code D[10:8] and the first-stage quantization residue signal.

[0058] Specifically, refer to Figure 3 , the first low kickback noise comparator circuit, the second low kickback noise comparator circuit, the third low kickback noise comparator circuit, the capacitor array circuit, the START.GEN circuit, the first RDY.GEN circuit, the second RDY.GEN circuit, and the RESET.GEN circuit;

[0059] The upper plates of the P-terminal capacitor array (capacitor array CDAC_P) are connected to the positive input terminals of the first low kickback noise comparator circuit, the second low kickback noise comparator circuit, and the third low kickback noise comparator circuit; the upper plates of the N-terminal capacitor array (capacitor array CDAC_N) are connected to the negative input terminals of the first low kickback noise comparator circuit, the second low kickback noise comparator circuit, and the third low kickback noise comparator circuit;

[0060] The input terminal of the START.GEN circuit is connected to the inverted signal of the sampling clock signal; the output terminal of the START.GEN circuit is connected to the comparison clock CLK of the first low kickback noise comparator circuit;

[0061] The output terminal of the first low kickback noise comparator circuit is connected to the input terminal of the first RDY.GEN circuit;

[0062] The output terminal of the first RDY.GEN circuit is connected to the comparison clock CLK of the second low kickback noise comparator circuit;

[0063] The output terminal of the second low kickback noise comparator circuit is connected to the input terminal of the second RDY.GEN circuit;

[0064] The output terminal of the second RDY.GEN circuit is connected to the comparison clock CLK of the third low kickback noise comparator circuit;

[0065] The output terminal of the third low kickback noise comparator circuit is connected to the input terminal of the RESET.GEN circuit;

[0066] The output terminal of the RESET.GEN circuit is connected to the reset input terminals of the START.GEN circuit, the first RDY.GEN circuit, and the second RDY.GEN circuit.

[0067] Here, the upper plates of the capacitor array circuit are connected to the input signal during the sampling phase and are switched to the passive transmission module during the residue transmission phase.

[0068] Exemplarily, when the sampling clock signal Φ S1 is at a low level, it triggers the START.GEN circuit to generate a signal to trigger the first low kickback noise comparator circuit in the first-stage Loop-Unrolled SAR ADC. The first low kickback noise comparator circuit compares the sampled voltages CDAC_VINP / N on the P-terminal capacitor array and the N-terminal capacitor array, generates a digital code D

[10] , and switches the sampled voltages CDAC_VINP / N on the P-terminal capacitor array and the N-terminal capacitor array for the first time. At the same time, the comparison result of the first low kickback noise comparator circuit triggers the first RDY.GEN circuit to generate a start signal for the second low kickback noise comparator circuit;

[0069] The second low kickback noise comparator circuit then compares the sampled voltage CDAC_VINP / N after the first switching, generates the digital code D[9], and switches the sampled voltages CDAC_VINP / N on the P-end capacitor array and the N-end capacitor array for the second time. Meanwhile, the comparison result of the second low kickback noise comparator circuit triggers the second RDY.GEN circuit to generate the start signal for the third low kickback noise comparator circuit;

[0070] The third low kickback noise comparator circuit then compares the sampled voltage CDAC_VINP / N after the second switching, generates the digital code D[8], and switches the sampled voltages CDAC_VINP / N on the P-end capacitor array and the N-end capacitor array for the third time. The voltages on the P-end capacitor array and the N-end capacitor array finally obtained are the first-stage quantization residue signals output by the first-stage Loop-Unrolled SAR ADC. And the first 3-bit digital codes D[10:8] obtained by the first-stage Loop-Unrolled SAR ADC are transmitted to the digital code alignment module (Bit Alignment Logic). Since the Loop-Unrolled SAR ADC is realized by the loop unrolling of multiple comparators, traditionally, the output signal needs to be latched, and then sliced and reset after latching. Therefore, the storage time of the comparator quantization result and the reset time of the comparator can be saved, and the quantization speed of the first-stage ADC is greatly improved.

[0071] Specifically, referring to Figure 4 , the first low kickback noise comparator circuit, the second low kickback noise comparator circuit, and the third low kickback noise comparator circuit all include: a low kickback noise preamplification unit, an integration and latching unit, and a latch unit connected in series in sequence.

[0072] The low kickback noise preamplification unit includes: NMOS transistor M 1a , NMOS transistor M 2a , NMOS transistor M 3a , NMOS transistor M 4a , NMOS transistor M 5a , NMOS transistor M 6a , PMOS transistor M 7a , PMOS transistor M 8a ;

[0073] The integration and latching unit includes: NMOS transistor M 1b , NMOS transistor M 2b , PMOS transistor M 3b , PMOS transistor M 4b and PMOS transistor M 5b ;

[0074] The latch unit includes: PMOS transistor M 1c , PMOS transistor M 2c , PMOS transistor M 3c , PMOS transistor M 4c , NMOS transistor M 5c , NMOS transistor M 6c and NMOS transistor M 7c ;

[0075] The gate terminal of NMOS transistor M 1a is connected to the upper plate of the P-terminal capacitor array; the source terminal of NMOS transistor M 1a is connected to the drain terminal of NMOS transistor M 3a ; the drain terminal of NMOS transistor M 1a is connected to the source terminal of NMOS transistor M 5a ;

[0076] The gate terminal of NMOS transistor M 5a is connected to the gate terminal of NMOS transistor M 6a , the gate terminal of PMOS transistor M 7a , the gate terminal of PMOS transistor M 8a and the comparison clock signal CLK; the drain terminal of NMOS transistor M 5a is connected to the drain terminal of PMOS transistor M 7a and the gate terminal of NMOS transistor M 1b ;

[0077] The source terminal of PMOS transistor M 7a is connected to the source terminal of PMOS transistor M 8a , the source terminal of PMOS transistor M 5b , the source terminal of PMOS transistor M 1c , the source terminal of PMOS transistor M 3c , the source terminal of PMOS transistor M 4c , the source terminal of PMOS transistor M 2c and the power supply voltage AVDD;

[0078] The drain terminal of PMOS transistor M 8a is connected to the drain terminal of NMOS transistor M 6a and the gate terminal of NMOS transistor M 2b ;

[0079] The source terminal of NMOS transistor M 6a is connected to the drain terminal of NMOS transistor M 2a ;

[0080] The gate terminal of NMOS transistor M 2a is connected to the upper plate of the N-terminal capacitor array; the source terminal of NMOS transistor M 2a is connected to the drain terminal of NMOS transistor M 4a ;

[0081] NMOS transistor M 4a has its gate terminal connected to the gate terminal of NMOS transistor M 3a and the power supply voltage AVDD; the source terminal of NMOS transistor M 4a is connected to the source terminal of NMOS transistor M 3a and the source terminal of NMOS transistor M 1b and the source terminal of NMOS transistor M 2b and the source terminal of NMOS transistor M 7c is grounded;

[0082] NMOS transistor M 1b has its drain terminal connected to the drain terminal of PMOS transistor M 3b and the gate terminal of PMOS transistor M 1c and the gate terminal of PMOS transistor M 4b is connected;

[0083] PMOS transistor M 3b has its source terminal connected to the drain terminal of PMOS transistor M 5b and the source terminal of PMOS transistor M 4b is connected; the gate terminal of PMOS transistor M 3b is connected to the drain terminal of PMOS transistor M 4b and the drain terminal of NMOS transistor M 2b and the gate terminal of PMOS transistor M 2c is connected;

[0084] PMOS transistor M 5b has its gate terminal connected to the inverted signal CLKB; where the inverted signal CLKB is the inverted signal of the comparison clock signal CLK;

[0085] PMOS transistor M 1c has its drain terminal connected to the drain terminal of PMOS transistor M 3c and the drain terminal of NMOS transistor M 5c and the gate terminal of PMOS transistor M 4c and the gate terminal of NMOS transistor M 6c is connected;

[0086] NMOS transistor M 5c has its source terminal connected to the source terminal of NMOS transistor M 6c and the drain terminal of NMOS transistor M 7c is connected; the gate terminal of NMOS transistor M 5c is connected to the gate terminal of PMOS transistor M 3c and the drain terminal of PMOS transistor M 4c and the drain terminal of NMOS transistor M 6c and the gate terminal of PMOS transistor M 2c is connected;

[0087] NMOS transistor M 7c has its gate terminal connected to the comparison clock CLK.

[0088] For example, the first-stage tail current tube M 3a / 4a It is implemented in a pseudo-differential manner, and the gate terminal is constantly connected to the power supply voltage AVDD, which can effectively avoid the input tube M from being interrupted when the comparison clock CLK comes. 1a / 2a The source voltage changes, and at the same time, the comparator input tube M 1a / 2a A group of NMOS tubes M controlled by the comparator comparison clock CLK are introduced into the drain end. 5a / 6a Reduce the input tube drain voltage to reduce the comparator comparison clock CLK high level when the input tube M 1a / 2a The above two measures can effectively reduce the input tube M 1a / 2a The decrease in the common mode of the input voltage CDAC_VINN / P further improves the overall ADC operating speed. The second stage circuit acts as an amplifier and latch, and the third stage circuit acts as a latch. The three-stage configuration makes the overall speed faster.

[0089] The present invention proposes a three-stage low kickback noise dynamic comparator, which effectively reduces the jump of the voltage across the source and drain of the input tube when the comparison clock arrives, improves the kickback effect, ensures the stability of the input common-mode voltage of the input tube, and significantly improves the working speed of the Loop-Unrolled SAR ADC by splitting the first-stage tail current tube into a pseudo-differential form controlled by the power supply voltage and introducing an NMOS tube controlled by a comparison clock at the drain end of the input tube.

[0090] The passive residual transmission module is used to passively transmit the first-stage quantized residual signal to the inter-stage residual amplifier module;

[0091] Here, the capacitance value of the passive residual transmission module is 1 / 2 of the capacitance value on the capacitance array in the first-stage Loop-Unrolled SAR ADC.

[0092] Exemplarily, the first-stage quantization residual signal is passively transmitted through a passive residual transmission module. Since the traditional pipeline ADC amplifies the residual voltage through a residual amplifier after the previous stage of quantization, and the residual amplifier has a long working time, it will occupy a large amount of working time of the previous stage ADC. The passive residual transmission speed is faster than the residual amplifier, so the working speed of the previous stage ADC can be greatly improved. After the passive residual transmission, the residual amplifier amplifies the voltage value of the passive transmission.

[0093] The present invention proposes a pipelined inter-stage residue transmission technology combining passive residue transmission and an inter-stage residue amplifier. By using passive transmission instead of a traditional residue amplifier, the operating speed of the previous-stage pipelined module can be significantly improved, and the amplification of the residue voltage starts while the previous-stage pipelined module is reset, compensating for the voltage loss caused by passive transmission amplification and avoiding occupying a large amount of the working time of the second-stage single-channel ADC.

[0094] The inter-stage residue amplifier module is used to amplify the first-stage quantized residue signal to obtain a residue amplified voltage.

[0095] Exemplarily, since the first-stage Loop-Unrolled SAR ADC of the present invention is 3-bit quantization, and the capacitance value used for passive residue transmission is 1 / 2 of the capacitance value of the capacitance array CDAC in the first-stage Loop-Unrolled SAR ADC. At the same time, to introduce redundant bits to calibrate the errors caused by comparator offset, capacitor mismatch, etc. in the first-stage Loop-Unrolled SAR ADC, the amplification factor of the inter-stage residue amplifier of the present invention is 6 times amplification. To further improve the operating speed of the overall ADC, the inter-stage residue amplifier module of the present invention is implemented with an open-loop structure.

[0096] The second-stage four-channel partially interleaved SAR ADC module is used to perform fine quantization on the residue amplified voltage to obtain an 8-bit digital code D[7:0].

[0097] Here, the second-stage four-channel partially interleaved SAR ADC module includes four channel sub-ADCs, which work alternately in turn, improving the operating speed of the ADC.

[0098] Exemplarily, when the inter-stage residue amplifier module performs amplification, the four sub-channel SAR ADCs of the second-stage time-interleaved take turns to sample the residue amplified voltage under the control of the high-level voltages of Φ S2,0， Φ S2,1 、Φ S2,2 and Φ S2,3 .

[0099] For example, when Φ S2,0 is at a high level and Φ S2,1 , Φ S2,2 and Φ S2,3 are all at low levels. At this time, 2 nd CH0.SAR ADC in the second-stage four-channel partially interleaved SAR ADC module starts to sample the residue amplified voltage. When Φ S2,0 is at a low level, 2 ndThe CH0.SAR ADC completes the quantization of the remaining 8-bit digital code to obtain the digital code D[7:0], and transfers it to the Bit Alignment Logic.

[0100] When the first-stage Loop-Unrolled SAR ADC completes the quantization of the first 3 bits and the passive residue transmission module completes the passive residue transmission in the next cycle, when Φ S2,1 is at a high level, Φ S2,0 , Φ S2,2 and Φ S2,3 are all at a low level, the 2 nd CH1.SAR ADC in the second-stage four-channel partially interleaved SAR ADC module starts to sample the residue amplified voltage in the circuit at this time, and then Φ S2,1 is at a low level and 2 nd CH1.SAR ADC starts the quantization of the remaining 8 bits like the 2 nd CH0.SAR ADC.

[0101] The architectures and working modes of the four-channel sub-ADCs in the second stage are the same, and they work alternately in turn, thus doubling the working speed of the ADC and avoiding the performance degradation caused by clock skew and jitter faced by traditional time-interleaved ADCs.

[0102] The digital code alignment module is used to align the first 3-bit digital code D[10:8] and the 8-bit digital code D[7:0] to obtain the complete digital code. Here, the digital code alignment module includes a redundant bit D[7], which is used to calibrate the errors caused by comparator offset, capacitor mismatch, etc. in the first-stage Loop-Unrolled SAR ADC.

[0103] Exemplarily, the Bit Alignment Logic aligns D[10:8] obtained by the first-stage Loop-Unrolled SAR ADC and D[7:0] obtained by the second-stage pipelining module, including a redundant bit D[7], so that the final overall 10-bit digital code DOUT[9:0] can be obtained finally.

[0104] One or more technical solutions provided by the present invention have at least the following technical effects or advantages:

[0105] The present invention cleverly applies the Loop - Unrolled technology in the first - stage Loop - Unrolled SAR ADC, successfully eliminating the storage time of the quantization result and the reset time of the comparator, thus significantly improving the quantization speed. Subsequently, in the second - stage four - channel partially - interleaved SAR ADC module, a partially - interleaved architecture is adopted. Through the interleaved operation of four sub - channel SAR ADCs, it not only effectively avoids the performance deterioration caused by clock skew and jitter in traditional time - interleaved ADCs, but also further accelerates the overall ADC conversion speed. In addition, during the process of inter - stage residue transmission and amplification, a passive residue transmission module and an inter - stage residue amplifier module are introduced. This design not only avoids the limitation of the traditional inter - stage residue amplifier on the speed of the first - stage Loop - Unrolled SAR ADC, but also further accelerates the overall ADC conversion rate.

[0106] The various embodiments in this specification are described in a progressive manner. For the same or similar parts between the various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. All or part of the present invention can be used in many general - purpose or special - purpose computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multi - processor systems, microprocessor - based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and so on.

[0107] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the present invention.

Claims

1. A single-channel pipeline analog-to-digital converter suitable for high-speed, medium-to-high-precision, characterized in that: include: Sample-and-hold circuit, first-stage Loop-Unrolled SAR ADC, passive residual transmission module, inter-stage residual amplifier module, second-stage four-channel partially interleaved SAR ADC module and digital code alignment module; The sample-and-hold circuit is used to sample the input analog signal to the capacitor array in the first-stage Loop-Unrolled SAR ADC at the rising edge of the sampling clock signal; wherein the capacitor array includes: a P-terminal capacitor array and an N-terminal capacitor array; The first-stage Loop-Unrolled SAR ADC is used to coarsely quantize the voltage on the capacitor array when the sampling clock signal is at a low level, to obtain the first 3-bit digital code D[10:8] and the first-stage quantization residual signal; The passive residual transmission module is used to passively transmit the first-stage quantized residual signal to the inter-stage residual amplifier module to obtain a passive transmission residual signal; The inter-stage residual amplifier module is used to amplify the passive transmission residual signal to obtain a residual amplified voltage; The second-stage four-channel partially interleaved SAR ADC module is used to finely quantize the residual amplified voltage to obtain an 8-bit digital code D[7:0]; The digital code alignment module is used to align the first 3-bit digital code D[10:8] and the 8-bit digital code D[7:0] to obtain a complete digital code.

2. The single-channel pipeline analog-to-digital converter suitable for high speed, medium and high precision according to claim 1, characterized in that: The sample-and-hold circuit is a bootstrap switch type sample-and-hold circuit.

3. The single-channel pipeline analog-to-digital converter suitable for high speed, medium and high precision according to claim 1, characterized in that: The first-stage Loop-Unrolled SAR ADC is used to coarsely quantize the voltage on the capacitor array when the sampling clock signal is at a low level, to obtain the first 3-bit digital code D[10:8] and the first-stage quantization residual signal, including: The first-stage Loop-Unrolled SAR ADC is triggered at the falling edge of the sampling clock signal, and then the upper plate voltage of the P-terminal capacitor array and the upper plate voltage of the N-terminal capacitor array are compared, and the lower plate voltage of the P-terminal capacitor array and the lower plate voltage of the N-terminal capacitor array are switched to obtain the first 3-bit digital code D[10:8] and the first-stage quantization residual signal.

4. The single-channel pipeline analog-to-digital converter suitable for high speed, medium and high precision according to claim 1, characterized in that: The first stage Loop-Unrolled SAR ADC includes: a first low kickback noise comparator circuit, a second low kickback noise comparator circuit, a third low kickback noise comparator circuit, a capacitor array circuit, a START.GEN circuit, a first RDY.GEN circuit, a second RDY.GEN circuit and a RESET.GEN circuit; The upper plate of the P-terminal capacitor array is connected to the positive input terminal of the first low kickback noise comparator circuit, the positive input terminal of the second low kickback noise comparator circuit, and the positive input terminal of the third low kickback noise comparator circuit; The upper plate of the N-terminal capacitor array is connected to the negative input terminal of the first low kickback noise comparator circuit, the negative input terminal of the second low kickback noise comparator circuit, and the negative input terminal of the third low kickback noise comparator circuit; The input end of the START.GEN circuit is connected to the inverted signal of the sampling clock signal; the output end of the START.GEN circuit is connected to the comparison clock CLK of the first low kickback noise comparator circuit; The output of the first low kickback noise comparator circuit is connected to the input of the first RDY.GEN circuit; The output terminal of the first RDY.GEN circuit is connected to the comparison clock CLK of the second low kick-back noise comparator circuit; The output terminal of the second low kick-back noise comparator circuit is connected to the input terminal of the second RDY.GEN circuit; The output terminal of the second RDY.GEN circuit is connected to the comparison clock CLK of the third low kick-back noise comparator circuit; The output terminal of the third low kick-back noise comparator circuit is connected to the input terminal of the RESET.GEN circuit; The output end of the RESET.GEN circuit is connected to the reset input ends of the START.GEN circuit, the first RDY.GEN circuit, and the second RDY.GEN circuit.

5. The single-channel pipeline analog-to-digital converter suitable for high speed, medium and high precision according to claim 4, characterized in that: The first low kick-back noise comparator circuit, the second low kick-back noise comparator circuit and the third low kick-back noise comparator circuit all include: a low kick-back noise pre-amplifier unit, an integral latch unit and a latch unit which are connected in series in sequence.

6. The single-channel pipeline analog-to-digital converter suitable for high speed, medium and high precision according to claim 5, characterized in that: The low kick-back noise pre-amplification unit includes: an NMOS tube M 1a 、NMOS tube M 2a 、NMOS tube M 3a 、NMOS tube M 4a 、NMOS tube M 5a 、NMOS tube M 6a 、PMOS tube M 7a 、PMOS tube M 8a ; The integral latch unit includes: an NMOS tube M 1b 、NMOS tube M 2b 、PMOS tube M 3b 、PMOS tube M 4b And PMOS tube M 5b ; The latch unit includes: a PMOS tube M 1c 、PMOS tube M 2c 、PMOS tube M 3c 、PMOS tube M 4c 、NMOS tube M 5c 、NMOS tube M 6c and NMOS tube M 7c ; The NMOS tube M 1a The gate terminal of the NMOS tube M is connected to the upper plate of the P-terminal capacitor array; 1a The source end of the NMOS tube M 3a The drain end is connected; the NMOS tube M 1a The drain end of the NMOS tube M 5a The source connection of The NMOS tube M 5a The gate terminal of the NMOS tube M 6a The gate terminal of the PMOS tube M 7a The gate terminal of the PMOS tube M 8a The gate terminal of the NMOS tube M is connected to the comparison clock signal CLK; 5a The drain end of the PMOS tube M 7a The drain end and the NMOS tube M 1b The gate terminal connection; The PMOS tube M 7a The source end of the PMOS tube M 8a The source end of the PMOS tube M 5b The source end of the PMOS tube M 1c The source end of the PMOS tube M 3c The source end of the PMOS tube M 4c The source end of the PMOS tube M 2c The source terminal is connected to the power supply voltage AVDD; The PMOS tube M 8a The drain end of the NMOS tube M 6a The drain end and the NMOS tube M 2b The gate terminal connection; The NMOS tube M 6a The source end of the NMOS tube M 2a The drain connection of The NMOS tube M 2a The gate terminal of the NMOS tube M is connected to the upper plate of the N-terminal capacitor array; 2a The source end of the NMOS tube M 4a The drain connection of The NMOS tube M 4a The gate terminal of the NMOS tube M 3a The gate terminal of the NMOS tube M is connected to the power supply voltage AVDD; 4a The source end of the NMOS tube M 3a The source end of the NMOS tube M 1b The source end of the NMOS tube M 2b The source end and the NMOS tube M 7c The source end is grounded; The NMOS tube M 1b The drain end of the PMOS tube M 3b The drain end of the PMOS tube M 1c The gate terminal and the PMOS tube M 4b The gate terminal connection; The PMOS tube M 3b The source end of the PMOS tube M 5b The drain end of the PMOS tube M 4b The source end of the PMOS tube M 3b The gate terminal of the PMOS tube M 4b The drain end of the NMOS tube M 2b The drain end of the PMOS tube M 2c The gate terminal connection; The PMOS tube M 5b The gate end is connected to the inverted signal CLKB; wherein the inverted signal CLKB is the inverted signal of the comparison clock signal CLK; The PMOS tube M 1c The drain end of the PMOS tube M 3c The drain end of the NMOS tube M 5c The drain end of the PMOS tube M 4c The gate terminal and the NMOS tube M 6c The gate terminal connection; The NMOS tube M 5c The source end of the NMOS tube M 6c The source end of the NMOS tube M 7c The drain end is connected; the NMOS tube M 5c The gate terminal of the PMOS tube M 3c The gate terminal of the PMOS tube M 4c The drain end of the NMOS tube M 6c The drain end and the PMOS tube M 2c The drain connection of The NMOS tube M 7c The gate terminal is connected to the comparison clock CLK.

7. The single-channel pipeline analog-to-digital converter suitable for high speed, medium and high precision according to claim 1, characterized in that: The capacitance value of the passive residual transmission module is 1 / 2 of the capacitance value on the capacitance array in the first-stage Loop-Unrolled SAR ADC.

8. The single-channel pipeline analog-to-digital converter suitable for high speed, medium and high precision according to claim 1, characterized in that: The digital code alignment module includes a redundant bit D[7], which is used to calibrate the error of the first-stage Loop-Unrolled SAR ADC caused by comparator offset, capacitor mismatch, etc.

9. The single-channel pipeline analog-to-digital converter suitable for high speed, medium and high precision according to claim 1, characterized in that: The inter-stage residual amplifier module is implemented by adopting an open-loop structure.

10. The single-channel pipeline analog-to-digital converter suitable for high speed, medium and high precision according to claim 1, characterized in that: The second-stage four-channel partially interleaved SAR ADC module includes four channel sub-ADCs that work in turn in an alternating method.

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