Method and apparatus for decoding simplified continuous cancellation list for polarization-adjusted convolutional code (PAC)

Abstract

Methods and apparatus are provided for decoding a simplified successive cancellation list of a polarization adjustment convolutional code (PAC). A decoded codeword is generated based at least in part on a simplified successive cancellation list (SSCL) decoding performed on a channel via a decoding tree. The decoding tree includes nodes that generate candidate codeword outputs based on predefined processing using convolutional code (CC) state inputs and channel vector inputs. A sub-tree of the nodes remains unprocessed.

Description

Technical Field

[0001] The present disclosure generally relates to wireless communication systems. More specifically, the subject matter disclosed herein relates to improvements in channel coding schemes in wireless communication systems. Background Art

[0002] Since polar codes have moderate encoding and decoding complexities, the fifth generation (5G) communication systems have adopted polar codes as the channel coding scheme for control channels. Recently, Polar Adjusted Convolution (PAC) codes have been proposed as a new polar coding scheme. Compared with polar codes, PAC codes encode data using a rate-1 convolutional code (CC) before applying the polar transform. The input to the CC encoder includes an information carrier vector, the state of the encoder, and a generator polynomial. The output of the CC encoder may include a CC codeword and an updated state vector.

[0003] Successive Cancellation (SC) is one of the most common polar code decoding algorithms. SC decoding operates on a decoding tree, where each node in the decoding tree corresponds to a component code with a specific information set. SC List (SCL) decoding includes multiple parallel SC decoders that interact at the information bits. Different from SC decoding, two possibilities are considered in SCL decoding. Additionally, in SCL decoding, the list size or number of parallel SC decoders can be expanded and pruned. PAC SCL decoding is similar to polar SCL decoding, except that in PAC SCL decoding, two lists are maintained, and for each list member, the CC state and the encoder state are stored.

[0004] In the Simplified SC / SCL (SSC / SSCL) decoding of polar codes, at special nodes of the decoding tree, the decoding result can be obtained without processing the subtrees of the special nodes. This reduces the decoding delay according to the node type. Special nodes include rate-0 nodes, repetition nodes, rate-1 nodes, and Single Parity Check (SPC) nodes. A rate-0 node is defined as a node having leaf nodes all of which are frozen or zero-valued bits. A repetition node is defined as a node having frozen leaf nodes except for the last leaf node that includes information or one-valued bits. A rate-1 node is defined as a node having leaf nodes all of which include information or one-valued bits. An SPC node is defined as a node having information in leaf nodes except for the first leaf node that is a frozen bit or zero-valued bit.

[0005] One problem with the above method is that due to CC coding, it is impossible to apply special node decoding to PAC codes. For example, if special node decoding is applied to PAC codes, the output of the rate-0 nodes will not all be zero, the output of the repetition nodes will not all be zero or all be 1, the rate-1 nodes will be non-linear codes that require special processing, and the output of the SPS nodes will not come from the SPC codebook. Summary of the Invention

[0006] To overcome these problems, systems and methods for developing an SSCL decoder for PAC codes considering four special node types are described herein.

[0007] Specifically, methods for handling special nodes at the node level considering the impact of CC coding are provided. The output of the rate-0 nodes is a constant codeword for each list member. The output of the repetition nodes is one of two constant codewords for each list member. The output of the rate-1 nodes can be decoded using techniques available for polar codes. A minimum likelihood ratio (LLR) scrambling method for decoding SPC nodes is provided. A method for implementing inverse CC coding with lower complexity over the special node length is also provided.

[0008] In an embodiment, a method is provided in which an electronic device receives a channel encoded with a PAC code. A decoded codeword is generated at least in part based on SSCL decoding performed by the electronic device on the channel via a decoding tree. The decoding tree includes nodes that generate candidate codeword outputs based on predefined processing using CC state inputs and channel vector inputs. The subtrees of the nodes remain unprocessed.

[0009] In an embodiment, an electronic device is provided that includes: a receiver configured to receive a channel encoded with a PAC code. The electronic device further includes a decoder configured to generate a decoded codeword at least in part based on SSCL decoding performed on the channel via a decoding tree. The decoding tree includes nodes that generate candidate codeword outputs based on predefined processing using CC state inputs and channel vector inputs. The subtrees of the nodes remain unprocessed.

[0010] In an embodiment, an electronic device is provided that includes a processor and a non-transitory computer-readable storage medium storing instructions that, when executed, cause the processor to perform the following operations: receive a channel encoded with a PAC code and generate a decoded codeword at least in part based on SSCL decoding performed on the channel via a decoding tree. The decoding tree includes nodes that generate candidate codeword outputs based on predefined processing using convolutional code (CC) state inputs and channel vector inputs. The subtrees of the nodes remain unprocessed. Brief Description of the Drawings

[0011] In the following sections, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings, wherein:

[0012] Figure 1 is a diagram showing a communication system according to an embodiment;

[0013] Figure 2 is a diagram showing a PAC encoder according to an embodiment;

[0014] Figure 3 is a diagram showing a decoding tree of a polar code according to an embodiment;

[0015] Figure 4 is a diagram showing a decoding tree for a PAC code according to an embodiment;

[0016] Figure 5 is a flowchart showing a method for SSCL decoding of a PAC code according to an embodiment; and

[0017] Figure 6 is a block diagram of an electronic device in a network environment according to an embodiment. DETAILED DESCRIPTION

[0018] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, those skilled in the art will understand that the aspects disclosed herein may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the subject matter disclosed herein.

[0019] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment can be included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment," "in an embodiment," or "according to one embodiment" (or other phrases having a similar meaning) that appear throughout this specification may not necessarily all refer to the same embodiment. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other embodiments. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Further, depending on the context discussed herein, singular terms may include their corresponding plural forms and plural terms may include their corresponding singular forms.

[0020] It should also be noted that the various figures (including component diagrams) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Additionally, if deemed appropriate, reference numerals are repeated in the figures to indicate corresponding and / or similar elements.

[0021] The terminology used herein is for the purpose of describing some example embodiments only and is not intended to limit the claimed subject matter. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0022] It should be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. The same reference numerals always refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] As used herein, terms such as "first", "second", etc. are used as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless explicitly defined as such. Additionally, the same reference numerals may be used across two or more figures to refer to components, assemblies, blocks, circuits, units, or modules having the same or similar functionality. However, this usage is for simplicity of illustration and ease of discussion only; it does not mean that the construction or architectural details of such components or units are the same in all embodiments, or that such commonly referenced components / modules are the only way to implement some example embodiments disclosed herein.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] As used herein, the term "module" refers to any combination of software, firmware, and / or hardware configured to provide the functionality described herein in connection with the module. For example, software can be embodied as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any of the embodiments described herein can include, for example, components, hardwired circuitry, programmable circuitry, state machine circuitry, and / or firmware that stores instructions executed by the programmable circuitry, either individually or in any combination. A module can be embodied, jointly or individually, as circuitry that forms part of a larger system, such as, but not limited to, an integrated circuit (IC), a system on a chip (SoC), components, and the like.

[0026] Figure 1 is a diagram showing a communication system according to an embodiment. In Figure 1 the architecture shown, the transmitting device 102 includes a first processor 106 that communicates with an encoder 108. The transmitting device 102 communicates with a receiving device 104, which includes a second processor 110 and a decoder 112. The encoder 108 can encode a message (or message word) into a codeword that is transmitted from the transmitting device 102 to the receiving device 104. The decoder 112 can decode the received codeword into a message (or message word) at the receiving device 104.

[0027] Figure 2 is a diagram showing a PAC encoder according to an embodiment. The message word can be rate profiled at a first block 202 into a word of length N = 2 n (e.g., the vector v in Figure 2 ). Rate profiling refers to determining K indices in the vector v and placing K message bits in those indices of the vector v. Specifically, the vector v has K message bits and N - K frozen bits having a value of zero. The information bit indices are provided by an information set of cardinality K The frozen set is denoted as A rate-1 convolutional encoder having a generator polynomial g = (g0, …, g m ) can be applied to the vector v at a second block 204, the output of which is a vector of length N (e.g., Figure 2 the vector u in m = 1. The parameter m is the number of memory cells of the convolutional code, and m + 1 is the constraint length. This results in the following equation (1).

[0028]

[0029] Equivalently, the following equation (2) is obtained.

[0030]

[0031] Another equivalent description can be provided by the state vector and input bits at a given time. The state vector is a vector of length m that contains the input bits of the convolutional encoder. At time i, when the input to the encoder is v i , the state vector is State i = (v i-1 , …, v i-m ). The output bit u i can be determined from the input bit v i , the current state vector current_State, and the generator polynomial of the code g. This function can be called ConvTrans(.), and it also returns the next state, as shown in equation (3) below.

[0032] (u i , next_State) = ConvTrans(v i , current_State, g) (3)

[0033] The generator matrix of a polar code of length N (N = 2 n ) can be where Then, the vector u can be encoded using a polar code of length N to obtain the final codeword c = (c1, …, c N ) = uG N . The received word at the output of the channel can be represented as y = (y1, …, y N ).

[0034] The SC decoding of the PAC code is similar to the SC decoding of the polar code. Regarding the SC decoding of the polar code, a polar code of length N and message word length K can be associated with an information set of cardinality K that contains the indices of the information bits , the information set of cardinality K which in turn determines the N - K indices of the frozen bits that are always set to zero. The SC polar decoder takes the channel LLR vector (λ1, …, λ N ) and the information set as inputs and outputs the decoded message word which contains the K decoded message bits at the indices given by the information set and the N - K zero-valued bits at the indices given by the frozen set. The SC decoder can be recursively defined as follows.

[0035] To obtain , the input to the SC decoder can be used to decode the upper polar code of length N / 2, as shown in equations (4) and (5) below.

[0036]

[0037] Among them,

[0038]

[0039] The operator is the box-plus operator, also known as the check-node operator, which is defined as The check-node operator can also be defined as an approximation of Equation (6) below.

[0040]

[0041] where Sign(α) is equal to 1 for α > 0 and equal to -1 for α < 0.

[0042] Set can be defined as

[0043] Once the upper polar code is decoded and the decoded message word is obtained then it can be encoded through G N / 2 for the decoded message word to obtain the corresponding codeword, that is Then, the lower polar code of length N / 2 can be decoded using the input of the SC decoder, as shown in Equations (7) and (8) below.

[0044]

[0045] where

[0046]

[0047] Set can be defined as

[0048] This decoder can provide the decoded message word as Then, the final decoded output of the polar code of length N can be obtained, as shown in Equation (9) below.

[0049]

[0050] The above recursive decoder can stop at length N = 1, for which the decoding can be performed using the rule of Equation (10).

[0051]

[0052] Figure 3 is a diagram showing a decoding tree of a polar code according to an embodiment. The above-described SC decoding can also be regarded as operating on the decoding tree. Figure 3 The decoding tree can be a decoding tree of length 8 or a part of a larger decoding tree. For a decoding tree of length 8, a polar code of length 8 can correspond to the first node 302. The second node 304 and the third node 306 immediately to the left of the first node 302 can each correspond to a polar code of length 4. The fourth node 308, the fifth node 310, the sixth node 312, and the seventh node 314 can each correspond to a polar code of length 2. The eighth node 316, the ninth node 318, the tenth node 320, the eleventh node 322, the twelfth node 324, the thirteenth node 326, the fourteenth node 328, and the fifteenth node 330 on the leftmost side of the decoding tree can each correspond to a polar code of length 1 and can be referred to as leaf nodes. SC decoding can be regarded as processing each node in the decoding tree in a specific order starting from the node of length N on the rightmost side. A polar code of length N = 2 n has a decoding tree with n + 1 columns, where there is 1 node of length N at the rightmost column, 2 nodes of length N / 2 at the second rightmost column, and so on. The leftmost column has N nodes corresponding to polar codes of length 1. The channel LLR λ is provided downstream through the nodes (i) , and the candidate decoded codeword β is provided upstream through the nodes (i) .

[0053] The SC decoding of the PAC code is basically the same as the SC decoding of the polar code, but has additional steps considering the CC encoder. In addition, the CC encoder operates at the SC decoder. The CC encoder can be implemented by sequentially calling Equation (3).

[0054] The SC decoder can initialize the state of the CC encoder to all zeros. The decoding continues as with the polar code. Once the LLR λ is calculated according to the bit index i (i) , then v i and u i can be determined according to one of the following cases.

[0055] In the first case, (u i , next_State) = ConvTrans(v i = 0, current_State, g). Then, current_State can be set to next_State.

[0056] In the second case, v can be targeted i= 0 considers two possibilities and calculates v for each as shown in the following equations (11) and (12). i and u i .

[0057]

[0058] Then, v can be determined as shown in the following equation (13). i .

[0059]

[0060] And, if v i = 0, the CC state can also be updated to next_State_0, otherwise, the CC state is updated to _1.

[0061] The SSC decoding of polar codes exploits the special properties of the codes corresponding to the nodes in the decoding tree in order to avoid the necessity of traversing all the way down to the leaf nodes and calculating the LLRs at the information bits. In the case of special nodes, the SC decoding can be temporarily taken over by the decoder of the special node until the special decoding result is passed to the SC decoder, at which point the SC decoder can resume.

[0062] For example, a polar code of length 16 can include four polar codes of length 4, each of length 4 having its corresponding rate. The complete decoding tree for this code has five columns of nodes, with 16 nodes in the leftmost column.

[0063] Generally, at node i, the SC decoder can advance to the leaf nodes (each node #i has more than two branch levels, resulting in Figure 3 eight leaf nodes in). However, if the code corresponding to the node is considered special, traversing to the leaf nodes can be avoided.

[0064] For example, referring to Figure 3, the fourth node 308 can be considered a rate-0 (or all-zero) special node because the information / freeze patterns corresponding to leaf nodes 318 and 320 are each a frozen or zero-valued bit. The second node 304 can be considered a repeat special node because the information / freeze patterns corresponding to leaf nodes 316, 318, 320, and 322 are frozen or zero-valued bits for all leaf nodes except the last leaf node 322, which has information or a one-valued bit. The seventh node 314 can be considered a rate-1 special node because the information / freeze patterns corresponding to leaf nodes 328 and 330 are each information or a one-valued bit. The third node 306 can be considered an SPC special node because the information / freeze patterns corresponding to leaf nodes 324, 326, 328, and 330 are information or one-valued bits for all leaf nodes except the first leaf node 324, which is a frozen or zero-valued bit.

[0065] Since the code at the second node 304 is a repetition code of length 4, the two possible codewords can be decoded at the node level by computing machine learning (ML) metrics only for the codewords (0,0,0,0) and (1,1,1,1). Path metrics can also be computed at the node level. The output of the special decoder can be passed to the SC decoder, and the SC decoder proceeds to the third code corresponding to the third node 306.

[0066] The SCL decoding of polar codes is based on the idea that at each information bit index, no final decision is made, but rather a list of possibilities based on the two values of the bit is considered. In particular, SCL decoding with list size L stores a list of size i after decoding bit index i. The list has L path members, each path member having length i and containing the decoded values of bits u1,…,u i . At frozen bits, the list can be extended by padding zeros to the current list to make it one unit longer. The path metrics can be updated for each member of the new list. At information bits, the current list can be extended to give a list of 2L paths by appending 0 and 1 to each path in the list. Path metrics are computed for each of the 2L new paths. The L paths with the minimum metric can be retained in the list, while the L paths with the maximum metric can be removed from the extended list, resulting in a new list of size L that contains members that are one bit longer than the previous list. This process can continue until the length of the paths in the list reaches N. At this step, the path with the minimum metric is selected as the final candidate (i.e., the decoder output).

[0067] The SCL decoding of polar codes can be improved by appending a cyclic redundancy check (CRC) to the message word u. The resulting decoding scheme can be referred to as CRC-aided SCL (CA-SCL) decoding. Compared with SCL decoding, CA-SCL decoding can select the finally decoded word from the final list given by bit index N as the path with the minimum path metric that satisfies the CRC.

[0068] The SCL decoding of PAC codes is basically the same as that of polar codes, with the modification that L running CC encoders are retained at the decoder. Two lists are stored for v and u. List expansion at the frozen bits for SCL decoding of PAC codes is performed in a manner similar to the SC decoding of PAC codes. Similarly, at the information bits, the list can be expanded by considering two possibilities 0 and 1 of the v list and obtaining the corresponding expanded u list. The path metric can be calculated based on the computed LLR and the u list. The rest of the process is similar to the SCL decoding of polar codes. The CA-SCL decoding of PAC codes is a modification of SCL decoding, where the modification is based on the additional CRC as described in the CA-SCL decoding of polar codes.

[0069] According to an embodiment, an SSCL decoding algorithm is proposed for PAC codes, which defines how to handle the special nodes of PAC codes in SCL decoding. After processing the number of bits i, the SCL decoder can have L (list size) path members of v (referred to as the v list), L path members of u (referred to as the u list), the corresponding path metric (PM), the intermediate LLR, and the encoded message bits of each path member in the decoding graph. The decoder can process special nodes of length M = 2 m whose starting index of the first bit is i. For each path member of size i - 1 bits, simplified processing of the next node can be performed. For each path member before processing the special node, the decoder can have information including the following items: the current state vector Curr_State, the LLR vector (λ0,…,λ M-1 ) at the node output, and the path metric value PM.

[0070] Figure 4 is a diagram showing the decoding tree for PAC codes according to an embodiment. Different from the decoding tree of the polar codes shown in Figure 3 , the input CC state (cState in ) and the output CC state (cState out ) are provided to the nodes of the decoding tree of PAC codes, and the input CC state (cState in ) and the output CC state (cState out ) are received from the nodes of the decoding tree of PAC codes. Figure 4The decoding tree can be part of a decoding tree of length 4 or a larger decoding tree. For a decoding tree of length 4, the PAC code of length 4 can correspond to the first node 402. The second node 404 and the third node 406 immediately to the left of the first node 402 can each correspond to a PAC code of length 2. The fourth node 408, the fifth node 410, the sixth node 412, and the seventh node 414 on the leftmost side of the decoding tree can each correspond to a PAC code of length 1 and can be referred to as leaf nodes. A single node (e.g., the second node 404) can receive the channel LLR λ (i) vector (such as Figure 4 the λ in (v) ) and the current CC state cState in (such as Figure 4 the in (i) ). This node can output a candidate codeword β Figure 4 (such as (v) the β in out ) and the next CC state cState Figure 4 (such as ) (as well as vector u and vector v).

[0071] The input to the CC encoder can be v = [v0,…,v M-1 , and the output of the CC encoder can be u = [u0,…,u M-1 . The codeword at the output of the special node can be represented by .

[0072] If the information / freeze pattern at the node is an all-zero vector of length M, then this node can be considered an all-zero special node. The input to the CC encoder can be a word v = 0 of length M.

[0073] The list can be extended by appending the polarization codeword corresponding to the output of the CC encoder to the list member. The output v of the CC encoder is calculated as shown in the following equation (14).

[0074]

[0075] Subsequently, u can be encoded to obtain c = u.G M . The extended path can be determined by concatenating v and u to the v list and the u list respectively.

[0076] The new path metric PM0 can be calculated as shown in the following equation (15).

[0077]

[0078] If the information / freeze pattern at a node is all zero for the first M - 1 indices and 1 at the last index, then the node can be considered a duplicate special node. The input to the CC encoder can be a word v of length M, resulting in v = [0 1×M-1 , v M-1 .

[0079] For the two possibilities of v M-1 = 0, 1, the v list can be extended by connecting and to the current v list, resulting in two sub - paths. To obtain the u list, the outputs of the CC encoder for the two possibilities can be calculated as set forth in equation (16) below.

[0080]

[0081] As an alternative, u (0) can be calculated according to the above process. u (1) is the same as u (0) , except for the last element, where (GF field or mode 2 operation), because g0 = 1.

[0082] The u list can be extended by connecting u (0) and u (1) to the current u list.

[0083] The path metrics of the two sub - paths represented by PM0 and PM1 can be calculated as shown in equation (17) below.

[0084]

[0085] Where is the codeword at the output of the special node (i.e., after applying the polarization transform).

[0086] It is also possible to perform polarization encoding only once and obtain c (0) , and calculate c (0) from c (1) as follows. Since u(0) and u(1) do not include the last element (where, for the last element, It can thus be shown that c (1) = c (0) + 1, where 1 is the all - one vector of length M.

[0087] If the information / freeze pattern at a node is all 1, then the node can be considered a rate - 1 special node. The input to the CC encoder can be a word v of length M, resulting in v = [v0, …, vM-1 , where all v i are message bits from the message word .

[0088] After polarization transformation, the codeword at the output of the special node can take any arbitrary vector in {0,1} M . That is, a rate-1 code is provided even in the presence of a CC code. u i is a linear combination of v j with j ≤ i and the coefficient of v i equal to 1, due to g0 = 1. Thus, u can be written as the following equation (18).

[0089] u = vG cc + η (18)

[0090] where η = [η0,…,η M-1 is a constant vector whose elements are determined as a linear combination of the elements of the current path members, and G cc is the generator matrix of the CC code, which is invertible and upper triangular. Thus, u can be any vector in {0,1} M . Since c = uG M , the same statement applies to c. Then, the sub-path members can be generated by the word c (0) , c (1) ,…, c (Z-1) with the most likely estimate for Z sub-path extensions.

[0091] The sub-path can be generated at the output of the special node after applying the polarization transformation according to the classical polar code, as shown in the following equation (19).

[0092] c (0) , c (1) ,…, c (Z-1) = Classical_polar_Rate1_dec(λ0,…,λ M-1 ) (19)

[0093] The routine Classical_polar_Rate1 can take M channel LLRs and output the most likely codeword of the rate-1 code. For example, the most likely codeword can be the result of a hard decision on the LLR. The second most likely codeword can be obtained by flipping the sign of the LLR with the smallest absolute value and then making a hard decision. The third most likely codeword can be obtained by flipping the sign of the second smallest absolute value LLR. The fourth most likely codeword can be obtained by flipping the sign of the third smallest absolute value LLR or flipping the signs of both the smallest absolute value LLR and the second smallest absolute value LLR.

[0094] corresponding to c (l) The path metric corresponding to each in can be calculated as shown in Equation (20) below.

[0095]

[0096] For the extension of the u list and the v list, the corresponding u (l) and v (l) vectors mapped to c can be calculated in three steps. (l) vectors.

[0097] In the first step, u (l) can be calculated. Since c (l) = u (l) G M and As a property of the polarization generation matrix, Equation (21) can be implemented by polarization coding of length M.

[0098] u (l) = c (l) G M (21)

[0099] In the second step, the scrambled word η can be calculated. This word η can be called the scrambled word because it scrambles the output of the CC encoder, which is obtained if the encoder starts in the all-zero state. To calculate η, CC can be a linear operator. Thus, for an all-zero input word of length M and an initial encoder state given by Curr_State, η can be equal to the output of the CC encoder, as shown in Equation (22) below.

[0100]

[0101] In the third step, v (l) can be calculated. Equations (23) and (24) are provided below.

[0102] u (l) = v (l) G cc + η (23) or

[0103]

[0104] where solving the equation for v (l) given ~u (l) .

[0105] According to the first solution using the inverse of G cc Since G ccis of size M×M and is full rank, so it can be invertible. The inverse matrix can be computed offline and stored for each special node length M. Then, v (l) can be computed as

[0106] According to the second solution using a shift register, the numerical results can show that has the same structure as G cc . In particular, both are Toeplitz matrices. That is, it can be described by the convolutional code generator polynomial. Examples for g=(1,0,0,1) and M = 8 are shown in the following equations (25) and (26).

[0107]

[0108]

[0109] This corresponds to a CC with the generator polynomial g -1 =(1,0,0,1,0,0,1). If this is always the case, then as described in more detail below, the inverse generator polynomial can be found offline and then used for encoding and obtaining v (l) .

[0110] Once v (l) and u (l) are computed for l = 0,…,Z-1, they can be appended to the current path member to obtain Z sub-path members.

[0111] If the information / freeze pattern at a node is all 1 except for the first index being 0, then the node can be considered an SPC special node. The input to the CC encoder can be a word v of length M, resulting in v = [v0,…,v M-1 , where all v i except v0 = 0 are message bits from the message word .

[0112] Similar to the analysis of rate-1 nodes, equation (27) is provided below.

[0113] u = vG cc + η (27)

[0114] where η = [η0,…,η M-1 is a constant vector whose elements are determined as a linear combination of the elements of the current path member, and G cc is the generator matrix of the CC code, which is invertible and upper triangular. η can be determined as described for rate-1 nodes.

[0115] Encode u with a polar code corresponding to the special nodes to obtain the codeword set forth in Equation (28) below.

[0116] c = uG M = (vG cc + η)G M = vG cc G M + ηG M

[0117] c = v cc G M + η c (28)

[0118] The vector v cc = vG cc has its first element frozen (i.e., it always takes a zero value). The first element is equal to v0g0 = 0. g0 = 0.

[0119] Define such that it is a codeword of an SPC code. Then, the method for classical polar codes can be used to calculate the sub-path membership, where the binary sequence η c is used for additional LLR scrambling. The steps for sub-path membership generation are set forth below.

[0120] In the first step, the encoded scrambling vector η c can be calculated. η can be calculated as described above. η c = (η c,0 ,…,η c,M-1 ) can be calculated as η c = ηG M .

[0121] In the second step, the LLRs can be scrambled. The LLR vector (λ0,…,λ c ) can be scrambled with η M-1 to obtain the scrambled which corresponds to the scrambled codeword The scrambling can be performed as The method for obtaining the sub-members of an SPC code for classical polar codes can be used to obtain Z sub-members as shown in Equation (29) below.

[0122]

[0123] where is a candidate for the list member index l.

[0124] The corresponding path metric PM lIt is a function of PM and scrambling. Calculate the path metric PM corresponding to each as shown in the following equation (30). as of the path metric PM l .

[0125]

[0126] In the third step, v cc can be calculated as where l = 0, …, Z - 1.

[0127] In the fourth step, the v list can be calculated. According to v cc = vG cc , the equation (31) can be calculated as follows.

[0128]

[0129] As described above, this calculation can be performed with low complexity via a shift register without any matrix multiplication. The application of ensures that the first element of and the first element of v (l) are zero for each l.

[0130] For l = 0, … Z - 1, the extended path v list can be obtained by concatenating v (l) to the current v list.

[0131] In the fifth step, the u list can be calculated. To calculate the extended path u list, u (l) can be calculated first as described in the following equation (32).

[0132]

[0133]

[0134] Optionally, for l = 0, …, Z - 1, u (l) can be calculated as

[0135] For l = 0, … Z - 1, the extended path u list can be obtained by concatenating u (l) to the current u list.

[0136] Regarding the inverse operation of the CC encoder, the task of finding the input vector of the rate-1 CC encoder from the encoded output vector can be performed by another CC encoder (i.e., a shift register and linear time). In particular, the inverse of equation (33) takes the form of equation (34) as follows.

[0137]

[0138] This inverse operation can be proven by induction. Note that since G N is full rank, g0 = g m = 1 and α0 = 1.

[0139] This result holds for N = 2. For example, in the case of, equation (35) can be determined.

[0140] where α1 = g1(35)

[0141] It can be assumed that this result holds for N, and it can be shown that this result also holds for N + 1, as shown in equations (36) and (37) below.

[0142]

[0143]

[0144] G N+1 's inverse can be written as equation (38) below.

[0145]

[0146] The goal is to find B N , c, and d. Since this gives equation (39) below.

[0147]

[0148] Assuming g0 = 1 gives equations (40), (41), and (42).

[0149]

[0150] dg0 = 1 → d = 1 = α0 (42) From equations (40)-(42), equation (43) below is obtained.

[0151]

[0152] where α0 = 1. To complete the proof, it suffices to show equation (44) below.

[0153]

[0154] For any α N , for 2 ≤ j ≤ N, c j = α N-j+1 can be determined, giving equation (45) below.

[0155]

[0156] From (considering the first N - 1 lines), equation (46) gives the following equation (47).

[0157]

[0158] Optionally, the following equation (48) is obtained.

[0159] c j +α N-j+1 = 0 → c j = α N-j+1 where 2 ≤ j ≤ N (48)

[0160] The inverse CC generating polynomials for different special node lengths can be nested. Equation (49) is shown below for rate - 1 special nodes of lengths 2, 4, 8, 16.

[0161]

[0162] For a special node of length N = 2 n the CC generating matrix and the inverse generating matrix can take the forms shown in the following equations (50) and (51).

[0163]

[0164] The generating polynomial and the inverse generating polynomial can be (g0,…,g m ) and (α0,…,α N-1 ), respectively. It can be calculated and the first N elements of the first row can be equal to the first row of, as shown in the following equation (52).

[0165]

[0166] It can take the form shown in the following equation (53).

[0167]

[0168] It can be calculated for B and compared with . I n can be set to the identity matrix of size 2 n ×2 n to obtain the following equation (54) or (55).

[0169]

[0170] The following equation (56) is obtained.

[0171] B.G CC,n = I n (56)

[0172] This can optionally be expressed as This means that the first row of B is equal to the first row of, i.e., (α0…, α N-1 ). Thus, the first N elements of the first row of are equal to the first row of, which proves the nested property of the inverse CC generating polynomial.

[0173] Using the above property, an inverse shift register of length N = 2 n may be sufficient for the inverse CC operation of the PAC decoder. When operating on a specific node of a given length M, only the first M storage elements of the shift register can be taken (e.g., the first L elements, where L is the position of the last "1" in the inverse polynomial).

[0174] Figure 5 is a flowchart showing a method for SSCL decoding of a PAC code according to an embodiment.

[0175] At 502, a receiver of an electronic device receives a channel encoded using a PAC code. At 504, a decoder of the electronic device performs SSCL decoding on the channel via a decoding tree to generate a decoded codeword. The decoding tree includes a special node that generates a candidate codeword output based on a predefined process using a CC state input and a channel vector input without processing the subtrees of the special node. The special node can be a rate-0 node, a repetition node, a rate-1 node, and an SPC node, and the predefined process is described in detail above.

[0176] Figure 6 is a block diagram of an electronic device in a network environment 600 according to an embodiment.

[0177] Referring to Figure 6, the electronic device 601 in the network environment 600 may communicate with the electronic device 602 via the first network 698 (e.g., a short-range wireless communication network), or communicate with the electronic device 604 or the server 608 via the second network 699 (e.g., a long-range wireless communication network). The electronic device 601 may communicate with the electronic device 604 via the server 608. The electronic device 601 may include a processor 620, a memory 630, an input device 650, a sound output device 655, a display device 660, an audio module 670, a sensor module 676, an interface 677, a haptic module 679, a camera module 680, a power management module 688, a battery 689, a communication module 690, a subscriber identification module (SIM) card 696, or an antenna module 697. In one embodiment, at least one of the components may be omitted from the electronic device 601 (e.g., the display device 660 or the camera module 680), or one or more other components may be added to the electronic device 601. Some of the components may be implemented as a single integrated circuit (IC). For example, the sensor module 676 (e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) may be embedded in the display device 660 (e.g., a display).

[0178] The processor 620 may execute software (e.g., the program 640) to control at least one other component (e.g., a hardware or software component) of the electronic device 601 coupled to the processor 620, and may perform various data processing or calculations.

[0179] As at least part of the data processing or calculation, the processor 620 may load commands or data received from another component (e.g., the sensor module 676 or the communication module 690) into the volatile memory 632, process the commands or data stored in the volatile memory 632, and store the resulting data in the non-volatile memory 634. The processor 620 may include a main processor 621 (e.g., a central processing unit (CPU) or an application processor (AP)) and an auxiliary processor 623 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that operates independently or in combination with the main processor 621. Additionally or optionally, the auxiliary processor 623 may be adapted to consume less power than the main processor 621, or be adapted to perform a specific function. The auxiliary processor 623 may be implemented separately from the main processor 621 or as part of the main processor 621.

[0180] When the main processor 621 is in an inactive (e.g., sleep) state, the auxiliary processor 623 (instead of the main processor 621) may control at least some of the functions or states related to at least one of the components of the electronic device 601 (e.g., the display module 660, the sensor module 676, or the communication module 690), or when the main processor 621 is in an active state (e.g., running an application), the auxiliary processor 123 may, together with the main processor 621, control at least some of the functions or states related to at least one of the components of the electronic device 601 (e.g., the display module 660, the sensor module 676, or the communication module 690). The auxiliary processor 623 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module 680 or the communication module 690) that is functionally related to the auxiliary processor 623.

[0181] The memory 630 may store various data used by at least one component of the electronic device 601 (e.g., the processor 620 or the sensor module 676). The various data may include, for example, software (e.g., the program 640) and input data or output data for commands related thereto. The memory 630 may include a volatile memory 632 or a non-volatile memory 634. The non-volatile memory 634 may include an internal memory 636 and / or an external memory 638.

[0182] The program 640 may be stored in the memory 630 as software and may include, for example, an operating system (OS) 642, middleware 644, or an application 646.

[0183] The input device 650 may receive commands or data to be used by another component of the electronic device 601 (e.g., the processor 620) from the outside of the electronic device 601 (e.g., a user). The input device 650 may include, for example, a microphone, a mouse, or a keyboard.

[0184] The sound output device 655 may output a sound signal to the outside of the electronic device 601. The sound output device 655 may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as playing multimedia or records, and the receiver may be used for receiving incoming calls. The receiver may be implemented separately from the speaker or as part of the speaker.

[0185] The display device 660 may visually provide information to the outside of the electronic device 601 (e.g., a user). The display device 660 may include, for example, a display, a hologram device, or a projector, and a control circuit for controlling the corresponding one of the display, the hologram device, and the projector. The display device 660 may include a touch circuit suitable for detecting a touch, or a sensor circuit (e.g., a pressure sensor) suitable for measuring the intensity of the force caused by the touch.

[0186] The audio module 670 can convert sound into an electrical signal and vice versa. The audio module 670 can obtain sound via the input device 650, or output sound via the sound output device 655 or the earphone of an external electronic device 602 directly (e.g., wired) or wirelessly coupled to the electronic device 601.

[0187] The sensor module 676 can detect the operating state of the electronic device 601 (e.g., power or temperature) or the environmental state outside the electronic device 601 (e.g., the state of the user), and then generate an electrical signal or data value corresponding to the detected state. The sensor module 676 can include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0188] The interface 677 can support one or more specified protocols used to couple the electronic device 601 to an external electronic device 602 directly (e.g., wired) or wirelessly. The interface 677 can include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0189] The connection end 678 can include a connector through which the electronic device 601 can be physically connected to an external electronic device 602. The connection end 678 can include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0190] The haptic module 679 can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that can be recognized by the user via touch or kinesthesia. The haptic module 679 can include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0191] The camera module 680 can capture a still image or a moving image. The camera module 680 can include one or more lenses, an image sensor, an image signal processor, or a flash. The power management module 688 can manage the power supplied to the electronic device 601. The power management module 688 can be implemented as at least a part of, for example, a power management integrated circuit (PMIC).

[0192] The battery 689 can supply power to at least one component of the electronic device 601. The battery 689 can include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0193] The communication module 690 may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 601 and an external electronic device (e.g., the electronic device 602, the electronic device 604, or the server 608), and perform communication via the established communication channel. The communication module 690 may include one or more communication processors that can operate independently of the processor 620 (e.g., the AP) and support direct (e.g., wired) communication or wireless communication. The communication module 690 may include a wireless communication module 692 (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) or a wired communication module 694 (e.g., a Local Area Network (LAN) communication module or a Power Line Communication (PLC) module). Each of these communication modules may communicate with an external electronic device via a first network 698 (e.g., a short-range communication network, such as a standard of Bluetooth™, Wi-Fi Direct, or Infrared Data Association (IrDA)) or a second network 699 (e.g., a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., a LAN or a Wide Area Network (WAN))). These various types of communication modules may be implemented as a single component (e.g., a single IC), or may be implemented as multiple separate components (e.g., multiple ICs). The wireless communication module 692 may use user information (e.g., an International Mobile Subscriber Identity (IMSI)) stored in the user identification module 696 to identify and authenticate the electronic device 601 in a communication network (such as the first network 698 or the second network 699).

[0194] The antenna module 697 may transmit a signal or power to the outside of the electronic device 601 (e.g., an external electronic device) or receive a signal or power from the outside of the electronic device 601 (e.g., an external electronic device). The antenna module 697 may include one or more antennas, and may, for example, select at least one antenna suitable for a communication scheme to be used in a communication network (such as the first network 698 or the second network 699) by the communication module 690 (e.g., the wireless communication module 692). Then, a signal or power may be transmitted or received between the communication module 690 and an external electronic device via the selected at least one antenna.

[0195] Commands or data can be sent or received between the electronic device 601 and the external electronic device 604 via the server 608 coupled to the second network 699. Each of the electronic devices 602 and 604 can be a device of the same type or a different type from the electronic device 601. All or some of the operations to be run on the electronic device 101 can be run on one or more of the external electronic devices 602, 604, or 608. For example, if the electronic device 601 is to automatically perform a function or service or is to perform a function or service in response to a request from a user or another device, the electronic device 601 can request that one or more of the external electronic devices perform at least part of the function or service, rather than running the function or service, or in addition to running the function or service, the electronic device 601 can also request that one or more of the external electronic devices perform at least part of the function or service. The one or more external electronic devices that receive the request can perform the requested at least part of the function or service, or perform additional functions or additional services related to the request, and transmit the result of the execution to the electronic device 601. The electronic device 601 can provide the result as at least part of a reply to the request, with or without further processing of the result. For this purpose, for example, cloud computing technology, distributed computing technology, or client-server computing technology can be used. Embodiments of the subject matter and operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware (including the structures disclosed in this specification and structural equivalents thereof), or in a combination of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage medium for execution by, or to control the operation of, a data processing apparatus. Optionally or additionally, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by a data processing device. A computer storage medium can be or include a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof. Moreover, although a computer storage medium is not a propagated signal, a computer storage medium can be the source or destination of computer program instructions encoded in an artificially generated propagated signal. A computer storage medium can also be one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices), or be included in one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices).Additionally, the operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0196] Although this specification may include many specific implementation details, the implementation details should not be construed as limiting the scope of any claimed subject matter, but rather as descriptions of features specific to particular embodiments. Certain features described in the context of separate embodiments in this specification can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately or in any suitable sub-combination in multiple embodiments. Additionally, although the features may be described above as acting in certain combinations and even initially claimed as such, in some cases one or more features from the claimed combination can be deleted from the combination, and the claimed combination can be directed to a sub-combination or a variation of the sub-combination.

[0197] Similarly, although the operations are depicted in the drawings in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in sequential order, or that all of the illustrated operations be performed, to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Additionally, the separation of the various system components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0198] Accordingly, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the acts recited in the claims can be performed in a different order and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain implementations, multitasking and parallel processing may be advantageous.

[0199] As those skilled in the art will recognize, the innovative concepts described herein can be modified and varied within a wide range of applications. Accordingly, the scope of the claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but is defined by the appended claims.

Claims

1. A method for decoding a simplified successive cancellation list (SSCL) of a polarization adjusted convolutional PAC code, comprising: receiving, at an electronic device, a channel encoded using a PAC code; as well as Generate a decoded codeword, wherein the decoded codeword is generated at least in part based on SSCL decoding performed by the electronic device on the channel via a decoding tree, wherein the decoding tree includes nodes that generate candidate codeword outputs based on predefined processing using a convolutional code CC state input and a channel vector input, and wherein a subtree of the nodes remains unprocessed.

2. The method according to claim 1, wherein: The node comprises a rate 0 node, and each leaf node of the subtree comprises a zero-valued bit; and The candidate codeword output includes a constant codeword for each member of the list in SSCL decoding.

3. The method according to claim 1, wherein: The node comprises a repeating node, a last leaf node of the subtree comprises a one-valued bit, and remaining leaf nodes of the subtree comprise zero-valued bits; and The candidate codeword output includes one of two constant codewords for each member of the list in SSCL decoding.

4. The method according to claim 1, wherein: The node comprises a rate 1 node, and each leaf node of the subtree comprises a one-value bit; and The candidate codeword output is generated based on determining an information carrier vector from a CC codeword.

5. The method according to claim 4, wherein: The candidate codeword output is based on a non-linear code.

6. The method according to claim 1, wherein: The node comprises a single parity check (SPC) node, a first leaf node of the subtree comprises a zero-valued bit, and remaining leaf nodes of the subtree comprise one-valued bits; and The candidate codeword output is generated based on minimum likelihood ratio LLR scrambling and determining the information carrier vector from the CC codeword.

7. The method according to claim 6, wherein: The candidate codeword output is generated based on the SPC codebook.

8. The method according to claim 1, further comprising: Inverse CC coding is applied for different lengths of the nodes.

9. The method according to claim 1, wherein: The node also generates a CC state output, an information carrier vector, and a CC codeword corresponding to the information carrier vector.

10. The method according to claim 1, wherein: The SSCL decoding is performed using a parallel successive cancellation SC decoder, a first list is maintained for information carrier vectors and a second list is maintained for CC codewords.

11. The method according to claim 1, wherein: The channel vector input comprises an LLR vector.

12. An electronic device for decoding a simplified successive cancellation list (SSCL) of a polarization adjusted convolutional PAC code, comprising: a receiver configured to receive a channel encoded using a PAC code; as well as A decoder configured to generate a decoded codeword, wherein the decoded codeword is generated based at least in part on SSCL decoding performed on the channel via a decoding tree, wherein the decoding tree includes nodes that generate candidate codeword outputs based on predefined processing using a convolutional code CC state input and a channel vector input, and wherein a subtree of the nodes remains unprocessed.

13. The electronic device of claim 12, wherein: The node comprises a rate 0 node, and each leaf node of the subtree comprises a zero-valued bit; and The candidate codeword output remains a constant codeword for each member of the list in SSCL decoding.

14. The electronic device of claim 12, wherein: The node comprises a repeating node, a last leaf node of the subtree comprises a one-valued bit, and remaining leaf nodes of the subtree comprise zero-valued bits; and The candidate codeword output includes one of two constant codewords for each member of the list in SSCL decoding.

15. The electronic device of claim 12, wherein: The node comprises a rate 1 node, and each leaf node of the subtree comprises a one-value bit; and The candidate codeword output is generated based on determining an information carrier vector from a CC codeword.

16. The electronic device as claimed in claim 15, wherein: The candidate codeword output is based on a non-linear code.

17. The electronic device of claim 12, wherein: The node comprises a single parity check (SPC) node, a first leaf node of the subtree comprises a zero-valued bit, and the remaining leaf nodes of the subtree comprise one-valued bits; and The candidate codeword output is generated based on minimum likelihood ratio LLR scrambling and determining the information carrier vector from the CC codeword.

18. The electronic device according to claim 12, wherein: The decoder is further configured to apply inverse CC encoding for different lengths of the nodes.

19. The electronic device according to claim 12, wherein: The node also generates a CC state output, an information carrier vector, and a CC codeword corresponding to the information carrier vector.

20. An electronic device for decoding a simplified successive cancellation list (SSCL) of a polarization adjusted convolutional PAC code, comprising: processor; as well as A non-transitory computer-readable storage medium storing instructions, wherein the instructions, when executed, cause the processor to: receiving a channel encoded using a PAC code; and Generate a decoded codeword, wherein the decoded codeword is generated at least in part based on SSCL decoding performed on the channel via a decoding tree, wherein the decoding tree includes nodes that generate candidate codeword outputs based on predefined processing using a convolutional code CC state input and a channel vector input, and wherein a subtree of the nodes remains unprocessed.

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